Rainbow Electronics MAX3799 User Manual
General Description
The MAX3799 is a highly integrated limiting amplifier
and VCSEL driver that operates up to 14Gbps, making
it suitable for Ethernet and Fibre Channel applications.
By providing a selectable data path with a noise-shaping filter, the MAX3799 enables a module with 10G
optics to be fully compliant with both 1000BASE-SR
and 10GBASE-SR specifications. Operating from a single +3.3V supply, this low-power integrated limiting
amplifier and VCSEL driver IC enables a platform
design for SFP MSA as well as for SFP+ MSA-based
optical transceivers. The high-sensitivity limiting amplifier limits the differential input signal generated by a
transimpedance amplifier into a CML-level differential
output signal. The compact VCSEL driver provides a
modulation and a bias current for a VCSEL diode. The
optical average power is controlled by an average
power control (APC) loop implemented by a controller
that interfaces to the VCSEL driver through a 3-wire
digital interface. All differential I/Os are optimally backterminated for a 50Ω transmission line PCB design.
The use of a 3-wire digital interface reduces the pin
count while enabling advanced Rx (rate selection, LOS
threshold, LOS squelch, LOS polarity, CML output level,
signal path polarity, deemphasis, and fast mode-select
change time) and Tx settings (modulation current, bias
current, polarity, and eye safety control) without the
need for external components. The MAX3799 provides
multiple current and voltage DACs to allow the use of
low-cost controller ICs.
The MAX3799 is packaged in a lead-free, 5mm x 5mm,
32-pin TQFN package.
Applications
1000BASE-SR/10GBASE-SR Multirate SFP+
Optical Transceiver
1x/2x/4x/8x/16x SFF/SFP/SFP+ MSA Fibre
Channel (FC) Optical Transceiver
Features
♦ Enables Single-Module Design Compliance with
1000BASE-SR and 10GBASE-SR Specifications
♦ -21.5dBm Optical Sensitivity at 1.25Gbps Using a
10.32Gbps ROSA (-19.7dBm OMA)
♦ Low Power Dissipation of 320mW at 3.3V Power
Supply
♦ Typical Electrical Performance of 14.025Gbps on
Rx/Tx (Non-Retimed 16x Fibre Channel Solution)
♦ 3mV
P-P
Receiver Sensitivity at 10.32Gbps
♦ 4ps
P-P
DJ at Receiver Output at 8.5Gbps 8B/10B
♦ 4ps
P-P
DJ at Receiver Output at 10.32Gbps
2
31
- 1 PRBS
♦ 26ps Rise and Fall Time at Rx/Tx Output
♦ Rate Select for 1Gbps Mode or 10Gbps Mode
♦ CML Output Squelch
♦ Polarity Select for Rx and Tx
♦ LOS Assert Level Adjustment
♦ LOS Polarity Select
♦ Modulation Current Up to 12mA Into 100Ω
Differential Load
♦ Bias Current Up to 15mA
♦ Integrated Eye Safety Features
♦ 3-Wire Digital Interface
♦ Programmable Deemphasis at Tx Output
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-4695; Rev 0; 8/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE
MAX3799ETJ+ -40°C to +85°C 32 TQFN-EP*
Typical Application Circuit and Pin Configuration appear at
end of data sheet.
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V
CC
= 3.3V, I
BIAS
= 6mA, I
MOD
= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
CCR
, V
CCT
, V
CCD
.................................................-0.3V to +4.0V
Voltage Range at DISABLE, SDA, SCL, CSEL,
RSEL, FAULT, BMON, LOS, CAZ2.........-0.3V to (VCC+ 0.3V)
Voltage Range at ROUT+, ROUT- .....(VCC- 1V) to (VCC+ 0.3V)
Voltage at TIN+, TIN-........................(V
CC
- 2.5V) to (VCC- 0.5V)
Voltage Range at TOUT+, TOUT- ......(VCC- 2V) to (VCC+ 0.3V)
Voltage at BIAS ............................................................0V to V
CC
Voltage at RIN+, RIN-..........................(VCC- 2V) to (VCC- 0.2V)
Current Range into FAULT, LOS...........................-1mA to +5mA
Current Range into SDA........................................-1mA to +1mA
Current into ROUT+, ROUT- ...............................................40mA
Current into TOUT+, TOUT- ................................................60mA
Continuous Power Dissipation (TA= +70°C)
32-Pin TQFN (derate 34.5W/°C above +70°C) ...........2759mW
Operating Junction Temperature Range...........-55°C to +150°C
Storage Temperature Range .............................-65°C to +160°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
Includes the CML output current;
Power-Supply C urrent I
Power-Supply Voltage VCC 2.85 3.63 V
GENERAL
Input Data Rate 1.0625 10.32 Gbps
Input/Output SNR 14.1
BER 10E-12
POWER-ON RESET
High POR Threshold 2.55 2.75 V
Low POR Threshold I
Rx INPUT SPECIFICATIONS
Differentia l Input Resi stance
RIN+/RIN-
Input Sensit ivit y (Note 2) V
Input Overload V
Input Return Loss SDD11
Input Return Loss SCC11
Rx OUTPUT SPECIFICATIONS
Differential Output Resistance R
CC
R
IN_DIFF
INMIN
INMAX
OUTDIFF
excludes I
V
DIFF_R OUT
= I
BIAS
BIASOFF
75 100 125
RATE_SEL = 0 (1.25Gbps) 1 3
RATE_SEL = 1 (10.32Gbps) 3 8
1.2 V
DUT is powered on, f 5GHz 14
DUT is powered on, f 16GHz 7
DUT is powered on, 1GHz < f 5GHz 8
DUT is powered on, 1GHz < f 16GHz 8
75 100 125
= 6mA, I
BIAS
= 400mV
and I
(Note 1)
P-P
MOD
MOD
= I
= 6mA,
MODOFF
2.3 2.45 V
97 150 mA
mV
P-P
P-P
dB
dB
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V
CC
= 3.3V, I
BIAS
= 6mA, I
MOD
= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Return Loss SDD22
Output Return Loss SCC22
CML Differential Output Voltage
High
CML Differential Output Voltage
Medium
CML Differential Output DAC
Limit
Different ia l Output Signal When
Disabled
Data Output Transition Time
(20% to 80%)
t
R/tF
(Notes 2, 3, 4)
DUT is powered on, f 5GHz 11
DUT is powered on, f 16GHz 5
DUT is powered on, 1GHz < f 5GHz 9
DUT is powered on, 1GHz < f 16GHz 7
5mV
10mV
VIN 1200mV
P-P
VIN 1200mV
P-P
, SET_CML[162] 595 800 1005 mV
P-P
, SET_CML[80] 300 400 515 mV
P-P
SET_CML[7:0] 215
Outputs AC-coupled, V
input V
DIFF_ ROUT
= 800mV
INMAX
P-P
applied to
at 8.5Gbps
(Notes 2, 3)
10mV
RATE_SEL = 1, V
5mV
RATE_SEL = 0, V
VIN 1200mV
P-P
VIN 1200mV
P-P
DIFF_R OUT
P-P
DIFF_R OUT
,
P-P
= 400mV
,
= 800mV
Rx TRANSFER CHARACTERISTICS
Determinist ic Jitter
(Notes 2, 3, 5)
DJ
Random Jitter (Notes 2, 3) RJ
Low-Frequency Cutoff
60mV
RATE_SEL = 1, V
10mV
RATE _SEL = 1, V
5mV
RATE _SEL = 0, V
Input = 60mV
RATE_SEL = 0, V
Input = 60mV
RATE _SEL = 1, V
CAZ = 0.1μF 2
C
AZ
VIN 400mV
P-P
VIN 1200mV
P-P
VIN 1200mV
P-P
P-P
P-P
DIFF_R OUT
DIFF_ ROUT
DIFF_ ROUT
at 1.25Gbps
DIFF_R OUT
at 8.5Gbps
DIFF_ ROUT
at 10.32Gbps,
P-P
= 400mV
at 8.5Gbps,
P-P
= 400mV
at 1.25Gbps,
P-P
= 800mV
,
= 800mV
,
= 400mV
= open 500
Rx LOS SPECIFICATIONS
LOS Assert Sensit ivit y Range 14 77 mV
LOS Hysteresis 10 x log(V
DEASSERT/VASSERT
) (Note 6) 1.25 2.1 dB
LOS Assert/Deassert Time (Note 7) 2.3 80 μs
Low As sert Leve l SET_LOS[7] (Notes 2, 6) 8 11 14 mV
Low Deassert Le vel SET_LOS[7] (Notes 2, 6) 14 18 21 mV
Medium Assert Leve l SET_LOS[32] (Notes 2, 6) 39 48 58 mV
Medium Deassert Level SET_LOS[32] (Notes 2, 6) 65 81 95 mV
High Assert Level SET_LOS[63] (Notes 2, 6) 77 94 112 mV
High Deassert Level SET_LOS[63] (Notes 2, 6) 127 158 182 mV
P-P
P-P
P-P
P-P
P-P
P-P
P-P
6 15 mV
26 35
60 100
4 12
4 12
ps
20
1.8 2.5
ps
0.32 0.48
dB
dB
P-P
P-P
P-P
ps
P-P
RMS
kHz
P-P
P-P
P-P
P-P
P-P
P-P
P-P
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V
CC
= 3.3V, I
BIAS
= 6mA, I
MOD
= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Tx INPUT SP ECIFICATIONS
Differentia l Input Voltage V
Common-Mode Input Voltage V
Differentia l Input Re si stance RIN 75 100 125
Input Return Loss SDD11
Input Return Loss SCC11
Tx LASER MODULATOR
Maximum Modulation-On
Current into 100 Differential
Load
Minimum Modulation-On Current
into 100 Differential Load
Modulation Current DAC
Stability
Modulation Current Rise Time/
Fal l Time
Determinist ic Jitter (Notes 2, 9) DJ
Random Jitter
Output Return Loss SDD22
Tx BIAS GENERATOR
Maximum Bias-On Current I
Minimum Bias-On Current I
INCM
I
MODMAX
I
MODMIN
t
R/tF
BIASMAX
BIASMIN
Data rate = 1.0625Gbps 0.2 2.4
IN
Data rate = 10.32Gbps 0.075 0.8
2.75 V
DUT is powered on, f 5GHz 15
DUT is powered on, f 16GHz 6
DUT is powered on, 1GHz < f 5GHz 9
DUT is powered on, 1GHz < f 16GHz 5
Outputs AC-coupled, V
Outputs AC-coupled 2 mA
2mA I
5mA I
SET_TXDE[3:0] = 10 (Notes 2, 4)
5mA I
250mV
SET_TXDE[3:0] = 0
5mA I
250mV
SET_TXDE[3:0] = 10
5mA I
250mV
SET_TXDE[3:0] = 0
5mA I
250mV
SET_TXDE[3:0] = 10
2mA I
2mA I
5mA I
800mV
DUT is powered on, f 5GHz 12
DUT is powered on, f 16GHz 5
Current into BIAS pin 15 mA
Current into BIAS pin 2 mA
12mA (Note 8) 4 %
MOD
10mA, 20% to 80%,
MOD
12mA, at 10.32Gbps,
MOD
VIN 800mV
P-P
12mA, at 10.32Gbps,
MOD
VIN 800mV
P-P
12mA, at 8.5Gbps,
MOD
VIN 800mV
P-P
12mA, at 8.5Gbps,
MOD
VIN 800mV
P-P
12mA, at 4.25Gbps 5
MOD
12mA, at 1.0625Gbps 5
MOD
12mA, 250mV
MOD
P-P
2.95V 12 mA
CCTO
,
P-P
,
P-P
,
P-P
,
P-P
VIN
P-P
26 39 ps
6 12
6 13
6 12
6 12
0.17 0.5 ps
V
dB
dB
ps
dB
P-P
RMS
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V
CC
= 3.3V, I
BIAS
= 6mA, I
MOD
= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
BIAS Current DAC Stability 2mA I
Compliance Voltage at BIAS V
BIAS Current Monitor Current
Gain
Compliance Voltage at BMON V
BIAS Current Monitor Current
Gain Stability
0.9 2.1 V
BIAS
I
BMON
BMON
I
BMON
External resistor to GND defines the
voltage gain
0 1.8 V
2mA I
15mA (Notes 2, 10) 4 %
BIAS
15mA (Note 10) 5 %
BIAS
Tx SAFETY FEATURES
Average voltage, FAULT warning alwa ys
Excessive Voltage at BMON V
BMON
occurs for V
warning never occurs for V
VCC - 0.55V, FAULT
BMON
BMON
0.65V
Average voltage, FAULT always occurs for
0.44V, FAULT never occurs for
Excessive Voltage at BIAS V
Maximum VCSEL Current in Off
State
BIAS
I
OFF
V
BIAS
V
0.65V
BIAS
FAULT or DISABLE, V
= VCC 25 μA
BIAS
SFP TIMING REQUIREMENTS
Time from ri sing edge of DISABLE input
DISABLE Assert Time t_
OFF
signal to I
I
MODOFF
BIAS
= I
BIASOFF
and I
MOD
Time from fall ing edge of DISABLE to I
DISABLE Negate Time t_
ON
and I
at 90% of steady state when
MOD
FAULT = 0 before reset
FAULT Reset Time of Power-On
Time
FAULT Reset Time t_
t_
FAULT
DISABLE to Reset
INIT
Time from power-on or negation of FAULT
using DISABLE
Time from fault to FAULT on,
C
FAULT
20pF, R
FAULT
= 4.7k
Time DISABLE must be held high to reset
FAULT
OUTPUT_LEVEL VOLTAGE DAC (SET_CML)
Ful l-Scale Voltage VFS 100 differential resist ive load 1200 mV
Resolution 5 mV
Integral Nonlinearity INL 5mA I
CML_LEVEL
20mA ±0.9 LSB
LOS THRESHOLD VOLTAGE DAC (SET_LOS)
Ful l-Scale Voltage VFS 94 mV
Resolution 1.5 mV
Integral Nonlinearity INL 11mV
P-P
V
TH_LO S
94mV
±0.7 LSB
P-P
BIAS CURRENT DAC (SET_IBIAS)
Ful l-Scale Current I
FS
VCC -
=
BIAS
16 mA/A
V
-
CC
0.65V
VCC -
0.6V
VCC -
0.55V
0.44 0.48 0.65 V
1 μs
500 μs
100 ms
10 μs
5 μs
21 mA
V
P-P
P-P
P-P
P-P
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V
CC
= 3.3V, I
BIAS
= 6mA, I
MOD
= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Resolution 40 μA
Integral Nonlinearity INL 1mA I
Differentia l Nonlinearity DNL
MODULATION CURRENT DAC (SET_IMOD)
Ful l-Scale Current I
Resolution 40 μA
Integral Nonlinearity INL 2mA I
Differentia l Nonlinearity DNL
CONTROL I/O SPECIFICATIONS
RSEL Input Current IIH, IIL 150 μA
RSEL Input High Voltage VIH 1.8 VCC V
RSEL Input Low Voltage VIL 0 0.8 V
RSEL Input Impedance R
DISABLE Input Current
DISABLE Input High Voltage VIH 1.8 VCC V
DISABLE Input Low Voltage VIL 0 0.8 V
DISABLE Input Impedance R
LOS, FAULT Output High Voltage V
LOS, FAULT Output Low Voltage V
3-WIRE DIGITAL I/O SPECIFICATIONS (SDA, CSEL, SCL)
Input High Voltage VIH 2.0 VCC V
Input Low Voltage VIL 0.8 V
Input Hystere sis V
Input Leakage Current IIL, I
Output High Voltage V
Output Low Voltage V
3-WIRE DIGITAL INTERFACE TIMING CHARACTERISTICS (See Figure 4)
SCL Clock Frequency f
SCL Pulse-Width High tCH 0.5 μs
SCL Pulse-Width Low tCL 0.5 μs
FS
PULL
IIH 12
I
PULL
OH
HYST
OH
SCL
1mA I
tonic at 8-bit resolution (SET_IBIAS[8:1])
2mA I
tonic at 8-bit resolution (SET_IMOD[8:1])
Internal pulldown resistor 40 75 110 k
Dependency on pullup resistance 420 800
IL
Internal pullup resistor 4.7 8 10 k
R
LOS
R
FAULT
R
OL
OL
LOS
R
FAULT
0.082 V
VIN = 0V or VCC; internal pullup or pulldown
IH
(75k typ)
External pullup of 4.7k to V
External pullup of 4.7k to VCC 0.4 V
400 1000 kH z
15mA ±1 LSB
BIAS
15mA, guaranteed mono-
BIAS
12mA ±1 LSB
MOD
12mA, guaranteed mono-
MOD
= 4.7k - 10k to VCC,
= 4.7k - 10k to V
= 4.7k - 10k to VCC,
= 4.7k - 10k to V
CC
CC
CC
±1
21 mA
±1
VCC -
0.5
0 0.4 V
150 μA
VCC -
0.5
V
V
CC
V
LSB
LSB
μA
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V
CC
= 3.3V, I
BIAS
= 6mA, I
MOD
= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
Note 1: Supply current is measured with unterminated receiver CML output or with AC-coupled Rx output termination. The Tx out-
put and the bias current output must be connected to a separate supply to remove the modulation/bias current portion from
the supply current. BIAS must be connected to 2.0V. TOUT+/- must be connected through 50Ω load resistors to a separate
supply voltage.
Note 2: Guaranteed by design and characterization, T
A
= -40°C to +95°C.
Note 3: The data input transition time is controlled by a 4th-order Bessel filter with -3dB frequency = 0.75 x data rate. The determin-
istic jitter caused by this filter is not included in the DJ generation specifications.
Note 4: Test pattern is 00001111 at 1.25Gbps for RATE_SEL = 0. Test pattern is 00001111 at 8.5Gbps for RATE_SEL = 1.
Note 5: Receiver deterministic jitter is measured with a repeating 2
31
- 1 PRBS equivalent pattern at 10.32Gbps. For 1.25Gbps to
8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is defined as the arithmetic sum
of pulse-width distortion (PWD) and pattern-dependent jitter (PDJ).
Note 6: Measured with a k28.5 pattern from 1.0625Gbps to 8.5Gbps. Measured with 2
31
- 1 PRBS at 10.32Gbps.
Note 7: Measurement includes an input AC-coupling capacitor of 100nF and C
CAZ
of 100nF. The signal at the input is switched
between two amplitudes: Signal_ON and Signal_OFF.
1) Receiver operates at sensitivity level plus 1dB power penalty.
a) Signal_OFF = 0
Signal_ON = (+8dB) + 10log(min_assert_level)
b) Signal_ON = (+1dB) + 10log(max_deassert_level)
Signal_OFF = 0
2) Receiver operates at overload.
Signal_OFF = 0
Signal_ON = 1.2V
P-P
max_deassert_level and the min_assert_level are measured for one LOS_THRESHOLD setting.
Note 8: Gain stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and V
CC
from +2.95V to +3.63V. Reference current measured at VCC= +3.2V, TA= +25°C.
Note 9: Transmitter deterministic jitter is measured with a repeating 2
7
- 1 PRBS, 72 0s, 27- 1 PRBS, and 72 1s pattern at
10.32Gbps. For 1.0625Gbps to 8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is
defined as the arithmetic sum of PWD and PDJ.
Note 10: Gain stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and V
CC
from +2.85V to +3.63V. Reference current measured at VCC= +3.3V, TA= +25°C.
SDA Setup Time tDS 100 ns
SDA Hold Time tDH 100 ns
SCL Rise to SDA Propagation
Time
CSEL Pulse-Width Low t
CSEL Leading Time Before the
First SCL Edge
CSEL Trailing Time After the
Last SCL Edge
SDA, SCL External Load C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
5ns
t
D
500 ns
CSW
t
L
t
T
Total bus capacitance on one line with
B
4.7k pullup to V
CC
500 ns
500 ns
20 pF
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
8 _______________________________________________________________________________________
Figure 1. Test Circuit for VCSEL Driver Characterization
V
CCR
1000pF
1nF
50Ω
50Ω
4.7kΩ
CONTROLLER
50Ω
OSCILLOSCOPE
50Ω
V
CC
0.1μF 0.1μF
1μH
V
CCR
50Ω
50Ω
CONTROLLER
V
1000pF
0.1μF
0.1μF
CCD
V
CCR
V
CCT
V
CCD
V
CCR
LOS
RSEL
ROUT+
ROUT-
DISABLE
V
CCD
CAZ1
SCL
SDA
CONTROLLER
CSEL
CAZ2
MAX3799
RIN+
TIN+
50Ω
0.1μF
0.1μF
RIN-
TIN-
50Ω
0.1μF
0.1μF
FAULT
TOUT+
TOUT-
BMON
1kΩ
V
V
BIAS
V
CCT
EER
EET
0.1μF
0.1μF
V
CCT
V
CONTROLLER
50Ω
50Ω
1000pF
CCT
4.7kΩ
50Ω
OSCILLOSCOPE
50Ω
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
_______________________________________________________________________________________
9
Typical Operating Characteristics—Limiting Amplifier
(VCC= 3.3V, TA= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was
used and the RSEL pin was left open.)
RANDOM JITTER
vs. INPUT AMPLITUDE
MAX3799 toc01
INPUT AMPLITUDE (mV
P-P
)
RANDOM JITTER (ps)
1000800600400200
310
320
330
340
350
360
370
300
0 1200
RATE_SEL = 1
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE
MAX3799 toc03
INPUT AMPLITUDE (mV
P-P
)
DETERMINISTIC JITTER (ps)
1000800600400200
2
3
4
5
6
7
1
0 1200
PATTERN = PRBS, RATE_SEL = 1
AT 8.5Gbps
AT 10.32Gbps
OUTPUT EYE DIAGRAM AT 1.25Gbps
MAX3799 toc06
200ps/div
150mV/div
RATE_SEL = 0
OUTPUT EYE DIAGRAM AT 4.25Gbps
MAX3799 toc07
50ps/div
50mV/div
RATE_SEL = 1
OUTPUT EYE DIAGRAM AT 8.5Gbps
MAX3799 toc08
20ps/div
50mV/div
OUTPUT EYE DIAGRAM AT 10.32Gbps
MAX3799 toc09
20ps/div
50mV/div
DETERMINISTIC JITTER vs.
INPUT AMPLITUDE AT 1.25Gbps
25
PATTERN = k28.5, RATE_SEL = 0
23
21
19
17
15
13
11
9
DETERMINISTIC JITTER (ps)
7
5
3
0 1200
DETERMINISTIC JITTER
vs. DATA RATE
MAX3799 toc04
BER
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E-05
1.0E-06
1.0E-07
1.0E-08
1.0E-09
1.0E-10
1.0E-11
1.0E-12
1.0E-13
10
PATTERN = k28.5
9
8
7
6
5
DETERMINISTIC JITTER (ps)
4
3
2
014
RATE_SEL = 1
12102 4 6 8
DATA RATE (Gbps)
BER vs. INPUT AMPLITUDE
RATE_SEL = 0
0.5 3.0
INPUT AMPLITUDE (mV
RATE_SEL = 1
INPUT AMPLITUDE (mV
1000800600400200
)
P-P
2.52.01.0 1.5
)
P-P
MAX3799 toc02
MAX3799 toc05
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
10 ______________________________________________________________________________________
Typical Operating Characteristics—Limiting Amplifier (continued)
(VCC= 3.3V, TA= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was
used and the RSEL pin was left open.)
LOS THRESHOLD vs. DAC SETTING
MAX3799 toc12
SET_LOS[5:0]
LOS THRESHOLD (mV)
564935 4214 21 287
20
40
60
80
100
120
140
160
180
0
063
DEASSERT
ASSERT
Rx INPUT RETURN LOSS
MAX3799 toc14
FREQUENCY (Hz)
SDD11 (dB)
10G1G
-50
-40
-30
-20
-10
0
-60
100M 100G
Rx OUTPUT RETURN LOSS
MAX3799 toc15
FREQUENCY (Hz)
SDD22 (dB)
10G1G
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
-50
100M 100G
CML OUTPUT AMPLITUDE
vs. DAC SETTING
MAX3799 toc16
SET_CML[7:0]
CML OUTPUT AMPLITUDE (mV
P-P
)
25020015010050
200
400
600
800
1000
1200
1400
0
0 300
TOTAL SUPPLY CURRENT
vs. TEMPERATURE
MAX3799 toc17
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
806535 50-10 5 20-25
50
60
70
80
90
100
110
120
130
140
40
-40 95
I
BIAS
= 12mA
I
BIAS
= 9mA
I
BIAS
= 2mA
I
MOD
= 2mA; RECEIVER OUTPUT = 400mV
P-P
;
TOTAL SUPPLY MEASURED USING THE SETUP
IN FIGURE 1
TOTAL SUPPLY CURRENT
vs. TEMPERATURE
MAX3799 toc18
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
806535 50-10 5 20-25
50
60
70
80
90
100
110
120
130
140
150
160
40
-40 95
I
MOD
= 12mA
I
MOD
= 9mA
I
MOD
= 2mA
I
BIAS
= 2mA; RECEIVER OUTPUT = 400mV
P-P
;
TOTAL SUPPLY MEASURED USING THE SETUP
IN FIGURE 1
OUTPUT EYE DIAGRAM AT 14.025Gbps
RATE_SEL = 1, RXDE_EN = 1
MAX3799 toc10
70
60
50
TRANSITION TIME
vs. INPUT AMPLITUDE
RATE_SEL = 0, RXDE_EN = 0
MAX3799 toc11
50mV/div
-12
USING FINISAR ROSA
-13
-14
-15
-16
-17
-18
-19
SENSITIVITY OMA (dBm)
-20
-21
RATE_SEL = 0
-22
111
20ps/div
SENSITIVITY vs. DATA RATE
RATE_SEL = 1
9753
DATA RATE (Gbps)
TRANSITION TIME (ps)
MAAX3799 toc13
40
RATE_SEL = 1, RXDE_EN = 0
30
20
RATE_SEL = 1, RXDE_EN = 1
10
0
0 1200
INPUT AMPLITUDE (mV
PATTERN = 00001111
20% TO 80%
1000800600400200
)
P-P
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
______________________________________________________________________________________
11
Typical Operating Characteristics—VCSEL Driver (continued)
(VCC= 3.3V, TA= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was
used and the RSEL pin was left open.)
OPTICAL EYE DIAGRAM
MAX3799 toc19
68ps/div
2.125Gbps, SET_IMOD = 60, 27 - 1 PRBS,
850nm VCSEL, MASK WITH 50%
OPTICAL EYE DIAGRAM
MAX3799 toc20
34ps/div
4.25Gbps, SET_IMOD = 60, 27 - 1 PRBS,
850nm VCSEL, MASK WITH 46%
OPTICAL EYE DIAGRAM
MAX3799 toc21
17ps/div
8.5Gbps, SET_IMOD = 60, 27 - 1 PRBS,
850nm VCSEL, MASK WITH 54%
OPTICAL EYE DIAGRAM
MAX3799 toc22
14ps/div
10.3Gbps, SET_IMOD = 60, 27 - 1 PRBS,
850nm VCSEL, MASK WITH 44%
DETERMINISTIC JITTER
vs. MODULATION CURRENT
MAX3799 toc24
MODULATION CURRENT (mA
P-P
)
DETERMINISTIC JITTER (ps)
10864
5.0
5.5
6.0
6.5
7.0
7.5
8.0
4.5
212
PATTERN = PRBS, DATA RATE = 10.32Gbps
TRANSITION TIME
vs. MODULATION CURRENT
MAX3799 toc25
MODULATION CURRENT (mA
P-P
)
TRANSITION TIME (ps)
10864
8
13
18
23
28
33
38
3
212
FALL TIME
RISE TIME
PATTERN = 11110000,
DATA RATE = 8.5Gbps
TRANSITION TIME
vs. DEEMPHASIS SETTING
MAX3799 toc26
SET_TXDE[3:0]
TRANSITION TIME (ps)
1091 2 3 5 6 74 8
27
29
31
33
35
37
39
41
25
011
FALL TIME
RISE TIME
PATTERN = 11110000,
DATA RATE = 8.5Gbps,
I
MOD
= 10mA
P-P
MODULATION CURRENT
vs. DAC SETTING
MAX3799 toc27
SET_IMOD[8:0]
MODULATION CURRENT (mA)
25020015010050
2
4
6
8
10
12
14
0
0 300
R
LOAD
= 50Ω
R
LOAD
= 75Ω
R
LOAD
= 100Ω
ELECTRICAL EYE DIAGRAM
14.025Gbps, SET_IMOD = 60, 231 - 1 PRBS
MAX3799 toc23
EYE WIDTH
62.8ps
14ps/div
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