The MAX3799 is a highly integrated limiting amplifier
and VCSEL driver that operates up to 14Gbps, making
it suitable for Ethernet and Fibre Channel applications.
By providing a selectable data path with a noise-shaping filter, the MAX3799 enables a module with 10G
optics to be fully compliant with both 1000BASE-SR
and 10GBASE-SR specifications. Operating from a single +3.3V supply, this low-power integrated limiting
amplifier and VCSEL driver IC enables a platform
design for SFP MSA as well as for SFP+ MSA-based
optical transceivers. The high-sensitivity limiting amplifier limits the differential input signal generated by a
transimpedance amplifier into a CML-level differential
output signal. The compact VCSEL driver provides a
modulation and a bias current for a VCSEL diode. The
optical average power is controlled by an average
power control (APC) loop implemented by a controller
that interfaces to the VCSEL driver through a 3-wire
digital interface. All differential I/Os are optimally backterminated for a 50Ω transmission line PCB design.
The use of a 3-wire digital interface reduces the pin
count while enabling advanced Rx (rate selection, LOS
threshold, LOS squelch, LOS polarity, CML output level,
signal path polarity, deemphasis, and fast mode-select
change time) and Tx settings (modulation current, bias
current, polarity, and eye safety control) without the
need for external components. The MAX3799 provides
multiple current and voltage DACs to allow the use of
low-cost controller ICs.
The MAX3799 is packaged in a lead-free, 5mm x 5mm,
32-pin TQFN package.
(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V
CC
= 3.3V, I
BIAS
= 6mA, I
MOD
= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
CCR
, V
CCT
, V
CCD
.................................................-0.3V to +4.0V
Voltage Range at DISABLE, SDA, SCL, CSEL,
RSEL, FAULT, BMON, LOS, CAZ2.........-0.3V to (VCC+ 0.3V)
Voltage Range at ROUT+, ROUT- .....(VCC- 1V) to (VCC+ 0.3V)
Voltage at TIN+, TIN-........................(V
CC
- 2.5V) to (VCC- 0.5V)
Voltage Range at TOUT+, TOUT- ......(VCC- 2V) to (VCC+ 0.3V)
Voltage at BIAS ............................................................0V to V
CC
Voltage at RIN+, RIN-..........................(VCC- 2V) to (VCC- 0.2V)
Current Range into FAULT, LOS...........................-1mA to +5mA
Current Range into SDA........................................-1mA to +1mA
Current into ROUT+, ROUT- ...............................................40mA
Current into TOUT+, TOUT- ................................................60mA
(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V
CC
= 3.3V, I
BIAS
= 6mA, I
MOD
= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Return Loss SDD22
Output Return Loss SCC22
CML Differential Output Voltage
High
CML Differential Output Voltage
Medium
CML Differential Output DAC
Limit
Different ia l Output Signal When
Disabled
Data Output Transition Time
(20% to 80%)
t
R/tF
(Notes 2, 3, 4)
DUT is powered on, f 5GHz 11
DUT is powered on, f 16GHz 5
DUT is powered on, 1GHz < f 5GHz 9
DUT is powered on, 1GHz < f 16GHz 7
5mV
10mV
VIN 1200mV
P-P
VIN 1200mV
P-P
, SET_CML[162] 595 800 1005 mV
P-P
, SET_CML[80] 300 400 515 mV
P-P
SET_CML[7:0] 215
Outputs AC-coupled, V
input V
DIFF_ ROUT
= 800mV
INMAX
P-P
applied to
at 8.5Gbps
(Notes 2, 3)
10mV
RATE_SEL = 1, V
5mV
RATE_SEL = 0, V
VIN 1200mV
P-P
VIN 1200mV
P-P
DIFF_R OUT
P-P
DIFF_R OUT
,
P-P
= 400mV
,
= 800mV
Rx TRANSFER CHARACTERISTICS
Determinist ic Jitter
(Notes 2, 3, 5)
DJ
Random Jitter (Notes 2, 3) RJ
Low-Frequency Cutoff
60mV
RATE_SEL = 1, V
10mV
RATE _SEL = 1, V
5mV
RATE _SEL = 0, V
Input = 60mV
RATE_SEL = 0, V
Input = 60mV
RATE _SEL = 1, V
CAZ = 0.1μF 2
C
AZ
VIN 400mV
P-P
VIN 1200mV
P-P
VIN 1200mV
P-P
P-P
P-P
DIFF_R OUT
DIFF_ ROUT
DIFF_ ROUT
at 1.25Gbps
DIFF_R OUT
at 8.5Gbps
DIFF_ ROUT
at 10.32Gbps,
P-P
= 400mV
at 8.5Gbps,
P-P
= 400mV
at 1.25Gbps,
P-P
= 800mV
,
= 800mV
,
= 400mV
= open 500
Rx LOS SPECIFICATIONS
LOS Assert Sensit ivit y Range 14 77 mV
LOS Hysteresis 10 x log(V
DEASSERT/VASSERT
) (Note 6) 1.25 2.1dB
LOS Assert/Deassert Time (Note 7) 2.3 80 μs
Low As sert Leve l SET_LOS[7] (Notes 2, 6) 8 1114 mV
Low Deassert Le vel SET_LOS[7] (Notes 2, 6) 14 18 21mV
Medium Assert Leve l SET_LOS[32] (Notes 2, 6) 39 48 58mV
Medium Deassert Level SET_LOS[32] (Notes 2, 6) 65 81 95mV
High Assert Level SET_LOS[63] (Notes 2, 6) 77 94 112mV
High Deassert Level SET_LOS[63] (Notes 2, 6) 127 158 182mV
P-P
P-P
P-P
P-P
P-P
P-P
P-P
6 15 mV
26 35
60 100
4 12
4 12
ps
20
1.82.5
ps
0.320.48
dB
dB
P-P
P-P
P-P
ps
P-P
RMS
kHz
P-P
P-P
P-P
P-P
P-P
P-P
P-P
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V
CC
= 3.3V, I
BIAS
= 6mA, I
MOD
= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Tx INPUT SP ECIFICATIONS
Differentia l Input Voltage V
Common-Mode Input Voltage V
Differentia l Input Re si stance RIN 75100 125
Input Return Loss SDD11
Input Return Loss SCC11
Tx LASER MODULATOR
Maximum Modulation-On
Current into 100 Differential
Load
Minimum Modulation-On Current
into 100 Differential Load
(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V
CC
= 3.3V, I
BIAS
= 6mA, I
MOD
= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
BIAS Current DAC Stability 2mA I
Compliance Voltage at BIAS V
BIAS Current Monitor Current
Gain
Compliance Voltage at BMON V
BIAS Current Monitor Current
Gain Stability
0.9 2.1 V
BIAS
I
BMON
BMON
I
BMON
External resistor to GND defines the
voltage gain
0 1.8 V
2mA I
15mA (Notes 2, 10) 4 %
BIAS
15mA (Note 10) 5 %
BIAS
Tx SAFETY FEATURES
Average voltage, FAULT warning alwa ys
Excessive Voltage at BMON V
BMON
occurs for V
warning never occurs for V
VCC - 0.55V, FAULT
BMON
BMON
0.65V
Average voltage, FAULT always occurs for
0.44V, FAULT never occurs for
Excessive Voltage at BIAS V
Maximum VCSEL Current in Off
State
BIAS
I
OFF
V
BIAS
V
0.65V
BIAS
FAULT or DISABLE, V
= VCC 25 μA
BIAS
SFP TIMING REQUIREMENTS
Time from ri sing edge of DISABLE input
DISABLE Assert Time t_
OFF
signal to I
I
MODOFF
BIAS
= I
BIASOFF
and I
MOD
Time from fall ing edge of DISABLE to I
DISABLE Negate Time t_
ON
and I
at 90% of steady state when
MOD
FAULT = 0 before reset
FAULT Reset Time of Power-On
Time
FAULT Reset Time t_
t_
FAULT
DISABLE to Reset
INIT
Time from power-on or negation of FAULT
using DISABLE
(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V
CC
= 3.3V, I
BIAS
= 6mA, I
MOD
= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Resolution 40 μA
Integral Nonlinearity INL 1mA I
Differentia l Nonlinearity DNL
MODULATION CURRENT DAC (SET_IMOD)
Ful l-Scale Current I
Resolution 40 μA
Integral Nonlinearity INL 2mA I
Differentia l Nonlinearity DNL
CONTROL I/O SPECIFICATIONS
RSEL Input Current IIH, IIL 150 μA
RSEL Input High Voltage VIH 1.8 VCC V
RSEL Input Low Voltage VIL 0 0.8 V
RSEL Input Impedance R
DISABLE Input Current
DISABLE Input High Voltage VIH 1.8 VCC V
DISABLE Input Low Voltage VIL 0 0.8 V
DISABLE Input Impedance R
LOS, FAULT Output High Voltage V
LOS, FAULT Output Low Voltage V
3-WIRE DIGITAL I/O SPECIFICATIONS (SDA, CSEL, SCL)
Input High Voltage VIH 2.0 VCC V
Input Low Voltage VIL 0.8 V
Input Hystere sis V
Input Leakage Current IIL, I
Output High Voltage V
Output Low Voltage V
3-WIRE DIGITAL INTERFACE TIMING CHARACTERISTICS (See Figure 4)
SCL Clock Frequency f
SCL Pulse-Width High tCH 0.5 μs
SCL Pulse-Width Low tCL 0.5 μs
FS
PULL
IIH 12
I
PULL
OH
HYST
OH
SCL
1mA I
tonic at 8-bit resolution (SET_IBIAS[8:1])
(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter output load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V
CC
= 3.3V, I
BIAS
= 6mA, I
MOD
= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
Note 1: Supply current is measured with unterminated receiver CML output or with AC-coupled Rx output termination. The Tx out-
put and the bias current output must be connected to a separate supply to remove the modulation/bias current portion from
the supply current. BIAS must be connected to 2.0V. TOUT+/- must be connected through 50Ω load resistors to a separate
supply voltage.
Note 2: Guaranteed by design and characterization, T
A
= -40°C to +95°C.
Note 3: The data input transition time is controlled by a 4th-order Bessel filter with -3dB frequency = 0.75 x data rate. The determin-
istic jitter caused by this filter is not included in the DJ generation specifications.
Note 4: Test pattern is 00001111 at 1.25Gbps for RATE_SEL = 0. Test pattern is 00001111 at 8.5Gbps for RATE_SEL = 1.
Note 5: Receiver deterministic jitter is measured with a repeating 2
31
- 1 PRBS equivalent pattern at 10.32Gbps. For 1.25Gbps to
8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is defined as the arithmetic sum
of pulse-width distortion (PWD) and pattern-dependent jitter (PDJ).
Note 6: Measured with a k28.5 pattern from 1.0625Gbps to 8.5Gbps. Measured with 2
31
- 1 PRBS at 10.32Gbps.
Note 7: Measurement includes an input AC-coupling capacitor of 100nF and C
CAZ
of 100nF. The signal at the input is switched
between two amplitudes: Signal_ON and Signal_OFF.
1) Receiver operates at sensitivity level plus 1dB power penalty.
a) Signal_OFF = 0
(VCC= 3.3V, TA= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was
used and the RSEL pin was left open.)
RANDOM JITTER
vs. INPUT AMPLITUDE
MAX3799 toc01
INPUT AMPLITUDE (mV
P-P
)
RANDOM JITTER (ps)
1000800600400200
310
320
330
340
350
360
370
300
01200
RATE_SEL = 1
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE
MAX3799 toc03
INPUT AMPLITUDE (mV
P-P
)
DETERMINISTIC JITTER (ps)
1000800600400200
2
3
4
5
6
7
1
01200
PATTERN = PRBS, RATE_SEL = 1
AT 8.5Gbps
AT 10.32Gbps
OUTPUT EYE DIAGRAM AT 1.25Gbps
MAX3799 toc06
200ps/div
150mV/div
RATE_SEL = 0
OUTPUT EYE DIAGRAM AT 4.25Gbps
MAX3799 toc07
50ps/div
50mV/div
RATE_SEL = 1
OUTPUT EYE DIAGRAM AT 8.5Gbps
MAX3799 toc08
20ps/div
50mV/div
OUTPUT EYE DIAGRAM AT 10.32Gbps
MAX3799 toc09
20ps/div
50mV/div
DETERMINISTIC JITTER vs.
INPUT AMPLITUDE AT 1.25Gbps
25
PATTERN = k28.5, RATE_SEL = 0
23
21
19
17
15
13
11
9
DETERMINISTIC JITTER (ps)
7
5
3
01200
DETERMINISTIC JITTER
vs. DATA RATE
MAX3799 toc04
BER
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E-05
1.0E-06
1.0E-07
1.0E-08
1.0E-09
1.0E-10
1.0E-11
1.0E-12
1.0E-13
10
PATTERN = k28.5
9
8
7
6
5
DETERMINISTIC JITTER (ps)
4
3
2
014
RATE_SEL = 1
12102468
DATA RATE (Gbps)
BER vs. INPUT AMPLITUDE
RATE_SEL = 0
0.53.0
INPUT AMPLITUDE (mV
RATE_SEL = 1
INPUT AMPLITUDE (mV
1000800600400200
)
P-P
2.52.01.01.5
)
P-P
MAX3799 toc02
MAX3799 toc05
MAX3799
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
(VCC= 3.3V, TA= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was
used and the RSEL pin was left open.)
LOS THRESHOLD vs. DAC SETTING
MAX3799 toc12
SET_LOS[5:0]
LOS THRESHOLD (mV)
564935 4214 21 287
20
40
60
80
100
120
140
160
180
0
063
DEASSERT
ASSERT
Rx INPUT RETURN LOSS
MAX3799 toc14
FREQUENCY (Hz)
SDD11 (dB)
10G1G
-50
-40
-30
-20
-10
0
-60
100M100G
Rx OUTPUT RETURN LOSS
MAX3799 toc15
FREQUENCY (Hz)
SDD22 (dB)
10G1G
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
-50
100M100G
CML OUTPUT AMPLITUDE
vs. DAC SETTING
MAX3799 toc16
SET_CML[7:0]
CML OUTPUT AMPLITUDE (mV
P-P
)
25020015010050
200
400
600
800
1000
1200
1400
0
0300
TOTAL SUPPLY CURRENT
vs. TEMPERATURE
MAX3799 toc17
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
806535 50-10 5 20-25
50
60
70
80
90
100
110
120
130
140
40
-4095
I
BIAS
= 12mA
I
BIAS
= 9mA
I
BIAS
= 2mA
I
MOD
= 2mA; RECEIVER OUTPUT = 400mV
P-P
;
TOTAL SUPPLY MEASURED USING THE SETUP
IN FIGURE 1
TOTAL SUPPLY CURRENT
vs. TEMPERATURE
MAX3799 toc18
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
806535 50-10 5 20-25
50
60
70
80
90
100
110
120
130
140
150
160
40
-4095
I
MOD
= 12mA
I
MOD
= 9mA
I
MOD
= 2mA
I
BIAS
= 2mA; RECEIVER OUTPUT = 400mV
P-P
;
TOTAL SUPPLY MEASURED USING THE SETUP
IN FIGURE 1
(VCC= 3.3V, TA= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was
used and the RSEL pin was left open.)
(VCC= 3.3V, TA= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was
used and the RSEL pin was left open.)
(VCC= 3.3V, TA= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was
used and the RSEL pin was left open.)
DETERMINISTIC JITTER
vs. PULSE-WIDTH SETTING
MAX3799 toc36
SET_PWCTRL[3:0]
DETERMINISTIC JITTER (ps)
53-5-3-11
3
4
5
6
7
8
9
10
2
-77
PATTERN = PRBS, DATA RATE = 10.32Gbps
EYE CROSSING
DOWNUP
BIAS MONITOR CURRENT
vs. TEMPERATURE
MAX3799 toc37
TEMPERATURE (°C)
MONITOR CURRENT (μA)
8065-25 -10 5352050
100
200
300
400
500
600
700
800
0
-4095
I
BIAS
= 12mA
I
BIAS
= 8mA
I
BIAS
= 2mA
PINNAMEFUNCTION
Loss-of-Signal Output, Open Drain. The default polarity of LOS is high when the level of the input
1 LOS
signal is below the preset threshold set by the SET_LOS DAC. Polarity of the LOS function can be
inverted by sett ing LOS_POL = 0. The LOS circuitry can be disabled by setting the bit LOS_EN = 0.
2 RSEL
3, 6, 27, 30 V
4 ROUT+ Noninverted Receive Data Output, CML. Back-terminated for 50 load.
5 ROUT- In verted Receive Data Output, CML. Back-terminated for 50 load.
7 V
8 DISABLE
9 SCL Serial-Clock Input, TTL/CMOS. This pin has a 75k internal pul ldown.
10 SDA
11 CSEL
12, 15, 18,
21, 24, 25
13 TIN+ Noninverted Transmit Data Input, CML
Mode-Select Input, TTL/CMOS. Set the RSEL pin or RATE_SEL bit (set by the 3-wire digital interface)
to logic-high for high-bandwidth mode. Setting RSEL and RATE_SEL logic-low for high-gain mode.
The RSEL pin is internally pulled down by a 75k resistor to ground.
Power Supply. Provides supply voltage to the receiver block.
CCR
Power Supply. Provides supply voltage for the digital block.
CCD
Transm itter Disable Input, TTL/CMOS. Set to logic-low for normal operation. Logic-high or open
disables both the modulation and bias current. Internal ly pul led up by an 8k resistor to V
CCT
.
Serial-Data Bidirectional Input, TTL/CMOS. Open-drain output. This pin has a 75k internal pullup,
but it requires an external 4.7k pullup resistor to meet the 3-wire digital timing specification. (Data
line collision protection is implemented.)
Chip-Select Input, TTL/CMOS. Setting CSEL to logic-high starts a cycle. Setting CSEL to logic-low
ends the cycle and resets the control state machine. Internall y pulled down by a 75k resi stor to
ground.
V
Power Supply. Provides supply voltage to the transmitter block.
CCT
MAX3799
Detailed Description
The MAX3799 SFP+ transceiver combines a limiting
amplifier receiver with loss-of-signal detection and a
VCSEL laser driver transmitter with fault protection.
Configuration of the advanced Rx and Tx settings of the
MAX3799 is performed by a controller through the
3-wire interface. The MAX3799 provides multiple current and voltage DACs to allow the use of low-cost controller ICs.
Limiting Amplifier Receiver
The limiting amplifier receiver inside the MAX3799 is
designed to operate from 1.0625Gbps to 10.32Gbps.
The receiver includes a dual path limiter, offset correction circuitry, CML output stage with deemphasis, and
loss-of-signal circuitry. The functions of the receiver can
be controlled through the on-chip 3-wire interface. The
registers that control the receiver functionality are
RXCTRL1, RXCTRL2, RXSTAT, MODECTRL, SET_CML,
and SET_LOS.
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
19 TOUT- Inverted Modulation Current Output. Back-termination of 50 to V
20 TOUT+ Noninverted Modulation Current Output. Back-termination of 50 to V
22 BIAS VCSEL Bias Current Output
23 FAULT
26 V
28 RIN- Inverted Receive Data Input, CML
29 RIN+ Noninverted Receive Data Input, CML
31 CAZ2
32 CAZ1 Offset Correction Loop Capacitor. Counterpart to CAZ2, internally connected to V
— EP
EET
EER
Bias Current Mon itor Output. Current out of this pin develops a ground-referenced voltage across an
external resistor that is proportional to the laser bias current.
Ground. Provides ground for the tran sm itter block.
.
CCT
.
CCT
Transm itter Fault Output, Open Drain. Logic-high indicates a fault condition. FAULT remain s h igh
even after the fault condition has been removed. A logic-low occurs when the fault condition has
been removed and the fault latch has been cleared by the DISABLE signal.
Ground. Provides ground for the receiver b lock.
Offset Correction Loop Capacitor. A capacitor connected between this pin and CAZ1 sets the time
constant of the offset correction loop. The offset correction can be disabled through the digita l
interface by setting the bit AZ_EN = 0.
Exposed Pad. Ground. Must be soldered to circuit board ground for proper thermal and electrical
performance (see the Exposed-Pad Package section).
The limiting amplifier features a low data-rate mode
(1.25Gbps) and a high data-rate mode (up to
10.32Gbps), allowing for overall system optimization.
Either the RSEL pin or the RATE_SEL bit can perform
the rate selection. For operating up to 1.25Gbps, the
low data-rate mode (RATE_SEL = 0) is recommended.
For operation up to 14.025Gbps, the high data-rate
mode (RATE_SEL = 1) is recommended. The polarity of
the ROUT+/ROUT- relative to RIN+/RIN- is programmed by the RX_POL bit.
Offset Correction Circuitry
The offset correction circuit is enabled to remove pulsewidth distortion caused by intrinsic offset voltages within the differential amplifier stages. An external capacitor
(CAZ) connected between the CAZ1 and CAZ2 pins is
used to set the offset correction loop cutoff frequency.
The offset loop can be disabled using the AZ_EN bit.
CML Output Stage with Deemphasis
and Slew-Rate Control
The CML output stage is optimized for differential 100Ω
loads. The RXDE_EN bit adds analog deemphasis
compensation to the limited differential output signal for
SFP connector losses. The output stage is controlled by
a combination of the RX_EN and SQ_EN bits and the
LOS pin. See Table 1.
Amplitude of the CML output stage is controlled by an
8-bit DAC register (SET_CML). The differential output
amplitude range is from 40mV
P-P
up to 1200mV
P-P
with
4.6mV
P-P
resolution (assuming an ideal 100Ω differen-
tial load).
Loss-of-Signal (LOS) Circuitry
The input data amplitude is compared to a preset
threshold controlled by the 6-bit DAC register
SET_LOS. The LOS assert level can be programmed
from 14mV
P-P
up to 77mV
P-P
with 1.5mV
P-P
resolution
(assuming an ideal 100Ω differential source). LOS is
enabled through the LOS_EN bit and the polarity of the
LOS is controlled with the LOS_POL bit.
VCSEL Driver
The VCSEL driver inside the MAX3799 is designed to
operate from 1.0625Gbps to 10.32Gbps. The transmitter contains a differential data path with pulse-width
adjustment, bias current and modulation current DACs,
output driver with programmable deemphasis, poweron reset circuitry, BIAS monitor, VCSEL current limiter,
and eye safety circuitry. A 3-wire digital interface is
used to control the transmitter functions. The registers
that control the transmitter functionality are TXCTRL,
TXSTAT1, TXSTAT2, SET_IBIAS, SET_IMOD, IMODMAX, IBIASMAX, MODINC, BIASINC, MODECTRL,
SET_PWCTRL, and SET_TXDE.
Differential Data Path
The CML input buffer is optimized for AC-coupled signals and is internally terminated with a differential
100Ω. Differential input data is equalized for high-frequency losses due to SFP connectors. The TX_POL bit
in the TXCTRL register controls the polarity of TOUT+
and TOUT- vs. TIN+ and TIN-. The SET_PWCTRL register controls the output eye-crossing adjustment. A status indicator bit (TXED) monitors the presence of an AC
input signal.
Table 1. CML Output Stage Operation Mode
Table 2. Slew-Rate Control for CML
Output Stage
RX_ENSQ_ENLOS
0 X X CML output disabled.
1 0 X CML output enabled.
1 1 0 CML output enabled.
1 1 1 CML output disabled.
OPERATION MODE
DESCRIPTION
RATE_SELOPERATION MODE DESCRIPTION
0
1 Up to 10.32Gbps operation.
1.25Gbps operation with reduced output
edge speed.
Bias Current DAC
The bias current from the MAX3799 is optimized to provide up to 15mA of bias current into a 50Ω to 75Ω
VCSEL load with 40μA resolution. The bias current is
controlled through the 3-wire digital interface using the
SET_IBIAS, IBIASMAX, and BIASINC registers.
For VCSEL operation, the IBIASMAX register is first programmed to a desired maximum bias current value (up
to 15mA). The bias current to the VCSEL then can
range from zero to the value programmed into the
IBIASMAX register. The bias current level is stored in
the 9-bit SET_IBIAS register. Only bits 1 to 8 are written
to. The LSB (bit 0) of SET_IBIAS is initialized to zero
and is updated through the BIASINC register.
The value of the SET_IBIAS DAC register is updated
when the BIASINC register is addressed through the
3-wire interface. The BIASINC register is an 8-bit register where the first 5 bits contain the increment information in two’s complement notation. Increment values
range from -8 to +7 LSBs. If the updated value of
SET_IBIAS[8:1] exceeds IBIASMAX[7:0], the IBIASERR
warning flag is set and SET_IBIAS[8:0] remains
unchanged.
Modulation Current DAC
The modulation current from the MAX3799 is optimized
to provide up to 12mA of modulation current into a
100Ω differential load with 40μA resolution. The modulation current is controlled through the 3-wire digital
interface using the SET_IMOD, IMODMAX, MODINC,
and SET_TXDE registers.
For VCSEL operation, the IMODMAX register is first programmed to a desired maximum modulation current
value (up to 12mA into a 100Ω differential load). The
modulation current to the VCSEL then can range from
zero to the value programmed into the IMODMAX register. The modulation current level is stored in the 9-bit
SET_IMOD register. Only bits 1 to 8 are written to. The
LSB (bit 0) of SET_IMOD is initialized to zero and is
updated through the MODINC register.
The value of the SET_IMOD DAC register is updated
when the MODINC register is addressed through the
3-wire interface. The MODINC register is an 8-bit register where the first 5 bits contain the increment information in two’s complement notation. Increment values
range from -8 to +7 LSBs. If the updated value of
SET_IMOD[8:1] exceeds IMODMAX[7:0], the IMODERR
warning flag is set and SET_IMOD[8:0] remains
unchanged.
Output Driver
The output driver is optimized for an AC-coupled 100Ω
differential load. The output stage also features programmable deemphasis that allows the deemphasis amplitude to be set as a percentage of the modulation current.
The deemphasis function is enabled by the TXDE_EN
bit. At initial setup, the required amount of deemphasis
can be set using the SET_TXDE register. During the
system operation, it is advised to use the incremental
mode that updates the deemphasis (SET_TXDE) and
the modulation current DAC (SET_IMOD) simultaneously through the MODINC register.
Power-On Reset (POR)
Power-on reset ensures that the laser is off until the
supply voltage has reached a specified threshold
(2.55V). After power-on reset, bias current and modulation current ramp up slowly to avoid an overshoot. In
the case of a POR, all registers are reset to their default
values.
Bias Current Monitor
Current out of the BMON pin is typically 1/16th the
value of I
BIAS
. A resistor to ground at BMON sets the
voltage gain. An internal comparator latches a SOFT
FAULT if the voltage on BMON exceeds the value of
VCC- 0.55V.
Eye Safety and Output Control Circuitry
The safety and output control circuitry contains a disable pin (DISABLE) and disable bit (TX_EN), along with
a FAULT indicator and fault detectors (Figure 3). The
MAX3799 has two types of faults, HARD FAULT and
SOFT FAULT. A HARD FAULT triggers the FAULT pin
and the output to the VCSEL is disabled. A SOFT
FAULT operates more like a warning and the outputs
are not disabled. Both types of faults are stored in the
TXSTAT1 and TXSTAT2 registers.
The FAULT pin is a latched output that can be cleared
by toggling the DISABLE pin. Toggling the DISABLE
pin also clears the TXSTAT1 and TXSTAT2 registers. A
single-point fault can be a short to V
CC
or GND. Table
3 shows the circuit response to various single-point
failures.
The MAX3799 implements a proprietary 3-wire digital
interface. An external controller generates the clock. The
3-wire interface consists of an SDA bidirectional data
line, an SCL clock signal input, and a CSEL chip-select
input (active high). The external master initiates a data
transfer by asserting the CSEL pin. The master starts to
generate a clock signal after the CSEL pin has been set
to 1. All data transfers are most significant bit (MSB) first.
Protocol
Each operation consists of 16-bit transfers (15-bit
address/data, 1-bit RWN). The bus master generates
16 clock cycles to SCL. All operations transfer 8 bits to
the MAX3799. The RWN bit determines if the cycle is
read or write. See Table 4.
Register Addresses
The MAX3799 contains 17 registers available for programming. Table 5 shows the registers and addresses.
Write Mode (RWN = 0)
The master generates 16 clock cycles at SCL in total.
The master outputs a total of 16 bits (MSB first) to the
SDA line at the falling edge of the clock. The master
closes the transmission by setting CSEL to 0. Figure 4
shows the interface timing.
Read Mode (RWN = 1)
The master generates 16 clock cycles at SCL in total.
The master outputs a total of 8 bits (MSB first) to the
SDA line at the falling edge of the clock. The SDA line is
released after the RWN bit has been transmitted. The
slave outputs 8 bits of data (MSB first) at the rising edge
of the clock. The master closes the transmission by setting CSEL to 0. Figure 4 shows the interface timing.
Mode Control
Normal mode allows read-only instruction for all registers except MODINC and BIASINC. The MODINC and
BIASINC registers can be updated during normal
mode. Doing so speeds up the laser control update
through the 3-wire interface by a factor of two. The normal mode is the default mode.
Setup mode allows the master to write unrestricted data
into any register except the status (TXSTAT1, TXSTAT2,
and RXSTAT) registers. To enter the setup mode, the
MODECTRL register (address = H0x0E) must be set to
H0x12. After the MODECTRL register has been set to
H0x12, the next operation is unrestricted. The setup
mode is automatically exited after the next operation is
finished. This sequence must be repeated if further
unrestricted settings are necessary.
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
Table 3. Circuit Response to Single-Point Faults (continued)
Table 4. Digital Communication Word Structure
Note 1: Normal—Does not affect laser power.
Note 2: Supply-shorted current is assumed to be primarily on the circuit board (outside this device) and the main supply is
collapsed by the short.
Note 3: Normal in functionality, but performance could be affected.
Warning: Shorted to V
CC
or shorted to ground on some pins can violate the
Absolute Maximum Ratings
.
PIN NAME SHORT TO VCC SHORT TO GND OPEN
30 V
31 CAZ2 Normal (Note 1) Normal (Note 1) Normal (Note 1)
32
Normal
CCR
CAZ1
)
(V
EER
Disabled—Fault (external supply
shorted) (Note 2)
Disabled—Fault (external supply
shorted) (Note 2)
Normal (Note 3)—Redundant path Normal (Note 3)—Redundant path
Normal (Note 3)—Redundant path
BIT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Regi ster Address RWN Data that is written or read.
Bit 2: IBIASERR. When the bias incremented result is greater than IBIASMAX, then a SOFT FAULT is reported. See
the
Programming Bias Current
section.
Bit 1: TXED. This only indicates the absence of an AC signal at the transmit input. This is not an LOS indicator.
Bias Current Setting Register (SET_IBIAS)
Bits 7 to 0: SET_IBIAS[8:1]. The bias current DAC is controlled by a total of 9 bits. The SET_IBIAS[8:1] bits are
used to set the bias current with even denominations from 0 to 510 bits. The LSB (SET_IBIAS[0]) bit is controlled by
the BIASINC register and is used to set the odd denominations in the SET_IBIAS[8:0].
Modulation Current Setting Register (SET_IMOD)
Bits 7 to 0: SET_IMOD[8:1]. The modulation current DAC is controlled by a total of 9 bits. The SET_IMOD[8:1] bits
are used to set the modulation current with even denominations from 0 to 510 bits. The LSB (SET_IMOD[0]) bit is
controlled by the MODINC register and is used to set the odd denominations in the SET_IMOD[8:0].
Maximum Modulation Current Setting Register (IMODMAX)
Bits 7 to 0: IMODMAX[7:0]. The IMODMAX register is an 8-bit register that can be used to limit the maximum modu-
lation current. IMODMAX[7:0] is continuously compared to the SET_IMOD[8:1].
Maximum Bias Current Setting Register (IBIASMAX)
Bits 7 to 0: IBIASMAX[7:0]. The IBIASMAX register is an 8-bit register that can be used to limit the maximum bias
current. IBIASMAX[7:0] is continuously compared to the SET_IBAS[8:1].
Modulation Current Increment Setting Register (MODINC)
Bit 7: SET_IMOD[0]. This is the LSB of the SET_IMOD[8:0] bits. This bit can only be updated by the use of
MODINC[4:0].
Bit 5: DE_INC. When this bit is set to 1 and the deemphasis on the transmit output is enabled, the SET_TXDE[3:0] is
incremented or decremented by 1 LSB. The increment or decrement is determined by the sign bit of the MODINC[4:0]
string of bits.
Bits 4 to 0: MODINC[4:0]. This string of bits is used to increment or decrement the modulation current. When written
to, the SET_IMOD[8:0] bits are updated. MODINC[4:0] are a two’s complement string.
Bias Current Increment Setting Register (BIASINC)
Bit 7: SET_IBIAS[0]. This is the LSB of the SET_IBIAS[8:0] bits. This bit can only be updated by the use of BIASINC[4:0].
Bits 4 to 0: BIASINC[4:0]. This string of bits is used to increment or decrement the bias current. When written to, the
SET_IBIAS[8:0] bits are updated. BIASINC[4:0] are a two’s complement string.
Mode Control Register (MODECTRL)
Bits 7 to 0: MODECTRL[7:0]. The MODECTRL register enables a switch between normal and setup modes. The
setup mode is achieved by setting this register to H0x12. MODECTRL must be updated before each write operation.
Exceptions are MODINC and BIASINC, which can be updated in normal mode.
Transmitter Pulse-Width Control Register (SET_PWCTRL)
Bits 3 to 0: SET_PWCTRL[3:0]. This is a 4-bit register used to control the eye crossing by adjusting the pulse width.
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
Note: The total bias current value is calculated using
the SET_IBIAS[8:0] register. SET_IBIAS[8:1] are the bits
that can be manually written. SET_IBIAS[0] can only be
updated using the BIASINC[4:0] register.
When implementing an APC loop, it is recommended to
use the BIASINC[4:0] register, which guarantees the
fastest bias current update.
3) BIASINCi[4:0] = New_Increment_Value
4) If (SET_IBIASi[8:1] ≤ IBIASMAX[7:0]),
then (SET_IBIASi[8:0] = SET_IBIAS
i-1
[8:0] + BIASINCi[4:0])
5) Else (SET_IBIASi[8:0] = SET_IBIAS
i-1
[8:0])
The total bias current can be calculated as follows:
Note: The total modulation current value is calculated
using the SET_IMOD[8:0] register. SET_IMOD[8:1] are
the bits that can be manually written. SET_IMOD[0] can
only be updated using the MODINC[4:0] register.
When implementing modulation compensation, it is recommended to use the MODINC[4:0] register, which
guarantees the fastest modulation current update.
3) MODINC
i
[4:0] = New_Increment_Value
4) If (SET_IMODi[8:1] ≤ IMODMAX[7:0]),
then (SET_IMODi[8:0] = SET_IMOD
i-1
[8:0] + MODINCi[4:0])
5) Else (SET_IMOD
i
[8:0] = SET_IMOD
i-1
[8:0])
The following equation is valid with assumption of 100Ω
on-chip and 100Ω external differential load (Rextd). The
maximum value that can be set for SET_TXDE[3:0] = 11.
6)I
MOD(Rextd=100Ω)
= [(20 + SET_IMODi[8:0]) x 40μA]
For general Rextd, the modulation current that is
achieved using the same setting of SET_IMODi[8:0] as
for Rextd = 100Ω is shown below. It can be written as a
function of I
MOD(Rextd=100Ω)
, still assuming a 100Ω on-
chip load.
7)
Programming LOS Threshold
LOSTH= (SET_LOS[5:0] x 1.5mV
P-P
)
Programming Transmit Output
Deemphasis
The TXDE_EN bit must be set to 1 to enable the deemphasis function. The SET_TXDE register value is used
to set the amount of deemphasis, which is a percentage of the modulation current. Deemphasis percentage
is determined as:
where the maximum SET_TXDE[3:0] = 11.
For an I
MOD
value of 10mA, the maximum achievable
deemphasis value is approximately 20%. Maximum
deemphasis achievable for full I
MOD
range of 12mA is
limited to 15%.
With deemphasis enabled, the value of the modulation
current amplitude is reduced by the calculated deemphasis percentage. To maintain the modulation current
amplitude constant, the SET_IMOD[8:0] register must
be increased by the deemphasis percentage. If the system conditions like temperature, required I
MOD
value,
etc., change during the transmit operation, the deemphasis setting might need to be readjusted. For such an
Transmitter Deemphasis Control Register (SET_TXDE)
Bits 3 to 0: SET_TXDE[3:0]. This is a 4-bit register used to control the amount of deemphasis on the transmitter out-
put. When calculating the total modulation current, the amount of deemphasis must be taken into account. The
deemphasis is set as a percentage of modulation current.
impromptu deemphasis adjustment, it is recommended
that the DE_INC (MODINC[5]) bit is used. Use of this bit
increments or decrements the deemphasis code setting
by 1 LSB based on the sign of increment in the
MODINC[4:0] and, hence, the SET_IMOD[8:0] setting.
This helps maintain the BER while having the flexibility to
improve signal quality by adjusting deemphasis while
the transmit operation continues. This feature enables
glitchless deemphasis adjustment while maintaining
excellent BER performance.
Activating Receiver Output Deemphasis
The RXDE_EN bit must be set to 1 to enable the deemphasis function. Deemphasis decreases the output
amplitude at ROUT+/ROUT- by 25%. To maintain the
same output amplitude as before the activation of
deemphasis, the SET_CML register value needs to be
increased by 25%. When deemphasis is enabled, the
limiting amplifier AC performance is guaranteed up to
800mV
P-P
typical output amplitude. The SET_CML register can be set from 0 to 255 bits, but it is important to
note that performance is guaranteed up to 215 bits.
Programming Pulse-Width Control
The eye crossing at the Tx output can be adjusted using
the SET_PWCTRL register. Table 6 shows these settings.
The sign of the number specifies the direction of pulsewidth distortion. The code of 1111 corresponds to a
balanced state for differential output. The pulse-width
distortion is bidirectional around the balanced state
(see the
Typical Operating Characteristics
section).
Programming CML Output Settings
Amplitude of the CML output stage is controlled by an
8-bit DAC register (SET_CML). The differential output
amplitude is up to 1000mV
P-P
with 4.6mV
P-P
resolution
(assuming an ideal 100Ω differential load). The guaranteed output CML DAC range is up to 215.
Output Voltage R
OUT
(mV
P-P
) = 40 + 4.55 (SET_CML)
Select the Coupling Capacitor
For AC-coupling, the coupling capacitors CINand
C
OUT
should be selected to minimize the receiver’s
deterministic jitter. Jitter is decreased as the input lowfrequency cutoff (fIN) is decreased.
fIN= 1/[2π(50)(CIN)]
The recommended CINand C
OUT
is 0.1μF for the
MAX3799.
Select the Offset-Correction Capacitor
The capacitor between CAZ1 and CAZ2 determines the
time constant of the signal path DC-offset cancellation
loop. To maintain stability, it is important to keep at
least a one-decade separation between fINand the
low-frequency cutoff (fOC) associated with the DC-offset cancellation circuit. A 1nF capacitor between CAZ1
and CAZ2 is recommended for the MAX3799.
Applications Information
Layout Considerations
To minimize inductance, keep the connections between
the MAX3799 output pins and laser diode as close as
possible. Optimize the laser diode performance by
placing a bypass capacitor as close as possible to the
laser anode. Use good high-frequency layout techniques and multiple-layer boards with uninterrupted
ground planes to minimize EMI and crosstalk.
Exposed-Pad Package
The exposed pad on the 32-pin TQFN provides a very
low-thermal resistance path for heat removal from the IC.
The pad is also electrical ground on the MAX3799 and
must be soldered to the circuit board ground for proper
thermal and electrical performance. Refer to Application
Note 862:
HFAN-08.1: Thermal Considerations of QFN
and Other Exposed-Paddle Packages
for additional
information.
Laser Safety and IEC 825
Using the MAX3799 laser driver alone does not ensure
that a transmitter design is compliant with IEC 825. The
entire transmitter circuit and component selections
must be considered. Each user must determine the
level of fault tolerance required by the application, recognizing that Maxim products are neither designed nor
authorized for use as components in systems intended
for surgical implant into the body, for applications
intended to support or sustain life, or for any other
application in which the failure of a Maxim product
could create a situation where personal injury or death
could occur.
1Gbps to 14Gbps, SFP+ Multirate Limiting
Amplifier and VCSEL Driver
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________