Rainbow Electronics MAX3798 User Manual

General Description

The MAX3798 is a highly integrated limiting amplifier
and VCSEL driver designed for 1x/2x/4x/8x Fibre
Channel transmission systems at data rates up to

8.5Gbps as well as for 10GBASE-SR transmission sys­tems at a data rate of 10.3125Gbps. Operating from a
single +3.3V supply, this low-power integrated limiting
amplifier and VCSEL driver IC enables a platform
design for SFP MSA as well as for SFP+ MSA-based
optical transceivers. The high-sensitivity limiting ampli­fier limits the differential input signal generated by a
transimpedance amplifier into a CML-level differential
output signal. The compact VCSEL driver provides a
modulation and a bias current for a VCSEL diode. The
optical average power is controlled by an average
power control (APC) loop implemented by a controller
that interfaces to the VCSEL driver through a 3-wire
digital interface. All differential I/Os are optimally back­terminated for a 50Ω transmission line PCB design.

The use of a 3-wire digital interface reduces the pin
count while enabling advanced Rx (mode selection,
LOS threshold, LOS squelch, LOS polarity, CML output
level, signal path polarity, slew-rate control, deempha­sis, and fast mode-select change time) and Tx settings
(modulation current, bias current, polarity, programma­ble deemphasis, eye-crossing adjustment, and eye
safety control) without the need for external compo­nents. The MAX3798 provides multiple current and volt­age DACs to allow the use of low-cost controller ICs.

The MAX3798 is packaged in a lead-free, 5mm x 5mm,
32-pin TQFN package.

Applications

10GBASE-SR SFP+ Optical Transceiver

1x/2x/4x/8x SFF/SFP/SFP+ MSA Fibre Channel
(FC) Optical Transceiver

10GBASE-LR SFP+ Optical Transceiver (1310nm
VCSEL)

10GBASE-LRM SFP+ Optical Transceiver
(1310nm VCSEL)

Features

♦ Low Power Dissipation of 320mW at 3.3V Power

Supply

♦ Up to 10.32Gbps (NRZ) Operation

♦ 3mV

P-P

Receiver Sensitivity at 10.32Gbps

♦ 4ps

P-P

DJ at Receiver Output at 8.5Gbps 8B/10B

♦ 4ps

P-P

DJ at Receiver Output at 10.32Gbps

2

31

- 1 PRBS

♦ 26ps Rise and Fall Time at Rx/Tx Output

♦ Mode Select for High-Gain Mode and High-

Bandwidth Mode

♦ CML Output Slew-Rate Adjustment for High-Gain

Mode

♦ CML Output with Continuous Level Adjustment

♦ CML Output Squelch

♦ Polarity Select for Rx and Tx

♦ LOS Assert Level Adjustment

♦ LOS Polarity Select

♦ Modulation Current Up to 12mA Into 100Ω

Differential Load

♦ Bias Current Up to 15mA

♦ Integrated Eye Safety Features

♦ Selectable Deemphasis at Rx Output

♦ 3-Wire Digital Interface

♦ Eye-Crossing Adjustment of Modulation Output

♦ Programmable Deemphasis at Tx Output

♦ Fast Mode-Select Change Time of 10µs

MAX3798

1.0625Gbps to 10.32Gbps, Integrated, Low-

Power SFP+ Limiting Amplifier and VCSEL Driver

________________________________________________________________

Maxim Integrated Products

1

Ordering Information

19-4360; Rev 0; 10/08

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

+

Denotes a lead-free/RoHS-compliant package.

*

EP = Exposed pad.

PART TEMP RANGE PIN-PACKAGE

MAX3798ETJ+ -40°C to +85°C 32 TQFN-EP*

Typical Application Circuit and Pin Configuration appear at
end of data sheet.

MAX3798

1.0625Gbps to 10.32Gbps, Integrated, Low­Power SFP+ Limiting Amplifier and VCSEL Driver

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter out­put load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V

CC

= 3.3V, I

BIAS

= 6mA, I

MOD

= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure­ments. For testing, the MODE_SEL bit was used and the MSEL pin was left open.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

V

CCR

, V

CCT

, V

CCD

.................................................-0.3V to +4.0V

Voltage Range at DISABLE, SDA, SCL,

CSEL, MSEL, FAULT, BMON, LOS,

BMAX, MMAX, CAZ2...............................-0.3V to (VCC+ 0.3V)

Voltage Range at ROUT+, ROUT- .....(V

CC

- 1V) to (VCC+ 0.3V)

Voltage at TIN+, TIN-........................(VCC- 2.5V) to (VCC- 0.5V)

Voltage Range at TOUT+, TOUT- ......(VCC- 2V) to (VCC+ 0.3V)

Voltage at BIAS...............................................................0 to V

CC

Voltage at RIN+, RIN-..........................(VCC- 2V) to (VCC- 0.2V)

Current Range into FAULT, LOS...........................-1mA to +5mA

Current Range into SDA........................................-1mA to +1mA

Current into ROUT+, ROUT- ...............................................40mA

Current into TOUT+, TOUT- ................................................60mA

Continuous Power Dissipation (TA= +70°C)

32-Pin TQFN (derate 34.5W/°C above +70°C) ...........2759mW

Operating Junction Temperature Range...........-55°C to +150°C

Storage Temperature Range .............................-65°C to +160°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLY

Power-Supply C urrent

Power-Supply Voltage VCC 2.85 3.63 V

GENERAL

Input Data Rate 1.0625 10.32 Gbps

Input/Output SNR 14.1

BER 10E-12

POWER-ON RESET

High POR Threshold 2.55 2.75 V

Low POR Threshold I

Rx INPUT SPECIFICATIONS

Differentia l Input Resi stance
RIN+/RIN-

Input Sensit ivit y (Note 2) V

Input Overload V

Input Return Loss SDD11

Input Return Loss SCC11

Rx OUTPUT SPECIFICATIONS

Differential Output Resistance R

Output Return Loss SDD22

I

CC

R

IN_DIFF

INMIN

INMAX

OUTDIFF

Includes the CML output current;
excludes I
V

DIFF_R OUT

= I

BIAS

BIASOFF

75 100 125 

MODE_SEL = 0 at 4.25Gbps 2 4

MODE_SEL = 1 at 8.5Gbps 3 8

1.2 V

DUT is powered on, f  5GHz 14

DUT is powered on, f  16GHz 7

DUT is powered on, 1GHz < f  5GHz 8

DUT is powered on, 1GHz < f  16GHz 8

75 100 125 

DUT is powered on, f  5GHz 11

DUT is powered on, f  16GHz 5

= 6mA, I

BIAS

= 400mV

and I

(Note 1)

P-P

MOD

MOD

= I

= 6mA,

MODOFF

2.3 2.45 V

97 150 mA

mV

P-P

P-P

dB

dB

dB

MAX3798

1.0625Gbps to 10.32Gbps, Integrated, Low-

Power SFP+ Limiting Amplifier and VCSEL Driver

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter out­put load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V

CC

= 3.3V, I

BIAS

= 6mA, I

MOD

= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure­ments. For testing, the MODE_SEL bit was used and the MSEL pin was left open.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Return Loss SCC22

CML Differential Output Voltage
High

CML Differential Output Voltage
Medium

Different ia l Output Signal When
Disabled

Data Output Transition Time
(20% to 80%)

t

R/tF

(Notes 2, 3, 4)

DUT is powered on, 1GHz < f  5GHz 9

DUT is powered on, 1GHz < f  16GHz 7

5mV

10mV

Outputs AC-coupled, V
input V

 VIN 1200mV

P-P

 VIN 1200mV

P-P

DIFF_ ROUT

P-P

INMAX

= 800mV

, SET_CML[162] 595 800 1005 mV

, SET_CML[80] 300 400 515 mV

P-P

applied to

at 8.5Gbps

P-P

(Notes 2, 3)

10mV
MODE_SEL = 1, V

5mV

 VIN 1200mV

P-P

 VIN 1200mV

P-P

P-P

DIFF_ ROUT

P-P

,

= 400mV

,
MODE_SEL = 0, SLEW_RATE = 1,
V

DIFF_R OUT

5mV

= 800mV

 VIN 1200mV

P-P

P-P

P-P

,
MODE_SEL = 0, SLEW_RATE = 0,
V

DIFF_R OUT

= 800mV

P-P

Rx TRANSFER CHARACTERISTICS

Determinist ic Jitter
(Notes 2, 3, 5)

DJ

60mV
MODE_SEL = 1, V

10mV
MODE _SEL = 1, V

10mV
MODE _SEL = 1, V

10mV
MODE _SEL = 0, V

5mV

 VIN 400mV

P-P

 VIN 1200mV

P-P

 VIN 1200mV

P-P

 VIN 1200mV

P-P

 VIN 1200mV

P-P

P-P

DIFF_ ROUT

P-P

DIFF_ ROUT

P-P

DIFF_ ROUT

P-P

DIFF_ ROUT

P-P

at 10.32Gbps,

= 400mV

at 8.5Gbps,

= 400mV

at 4.25Gbps,

= 400mV

at 8.5Gbps,

= 400mV

at 4.25Gbps,
MODE _SEL = 0, SLEW_RATE = 1,
V

DIFF_R OUT

5mV

= 800mV

 VIN 1200mV

P-P

P-P

at 4.25Gbps,

P-P

MODE _SEL = 0, SLEW_RATE = 0,

Random Jitter (Notes 2, 3) RJ

Low-Frequency Cutoff

V

DIFF_R OUT

Input = 60mV
MODE_SEL = 0, V

Input = 60mV
MODE _SEL = 1, V

CAZ = 0.1μF 2

C

AZ

= 800mV

P-P

at 4.25Gbps

P-P

DIFF_ ROUT

at 8.5Gbps

P-P

DIFF_ ROUT

,

= 800mV

,

= 400mV

= open 500

Rx LOS SPECIFICATIONS

LOS Assert Sensit ivit y Range 14 77 mV

LOS Hysteresis 10 x log (V

DEASSERT/VASSERT

) (Note 6) 1.25 2.1 dB

P-P

P-P

P-P

P-P

P-P

P-P

P-P

6 15 mV

26 35

28 50

45

4 12

4 12

5

5 10

ps

6 20

7

0.36 0.51

ps

0.32 0.48

dB

P-P

P-P

P-P

ps

P-P

RMS

kHz

P-P

MAX3798

1.0625Gbps to 10.32Gbps, Integrated, Low­Power SFP+ Limiting Amplifier and VCSEL Driver

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter out­put load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V

CC

= 3.3V, I

BIAS

= 6mA, I

MOD

= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure­ments. For testing, the MODE_SEL bit was used and the MSEL pin was left open.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

LOS Assert/Deassert Time (Note 7) 2.3 80 μs

Low As sert Leve l SET_LOS[7] (Notes 2, 6) 8 11 14 mV

Low Deassert Le vel SET_LOS[7] (Notes 2, 6) 14 18 21 mV

Medium Assert Leve l SET_LOS[32] (Notes 2, 6) 39 48 58 mV

Medium Deassert Level SET_LOS[32] (Notes 2, 6) 65 81 95 mV

High Assert Level SET_LOS[63] (Notes 2, 6) 77 94 112 mV

High Deassert Level SET_LOS[63] (Notes 2, 6) 127 158 182 mV

Tx INPUT SP ECIFICATIONS

Differentia l Input Voltage V

Common-Mode Input Voltage V

Differentia l Input Re si stance RIN 75 100 125 

Input Return Loss SDD11

Input Return Loss SCC11

Tx LASER MODULATOR

Maximum Modulation-On
Current into 100 Differential
Load

Minimum Modulation-On Current
into 100 Differential Load

Modulation Current DAC
Stability

Modulation Current Rise Time/
Fal l Time

Determinist ic Jitter (Notes 2, 9) DJ

INCM

I

MODMAX

I

MODMIN

t

R/tF

Data rate = 1.0625Gbps to 4.25Gbps 0.2 2.4

IN

Data rate = 4.25Gbps to 10.32Gbps 0.075 0.8

2.75 V

DUT is powered on, f  5GHz 15

DUT is powered on, f  16GHz 6

DUT is powered on, 1GHz < f  5GHz 9

DUT is powered on, 1GHz < f  16GHz 5

Outputs AC-coupled, V

Outputs AC-coupled 2 mA

2mA  I

5mA  I
SET_TXDE[3:0] = 10 (Notes 2, 4)

5mA  I
250mV
SET_TXDE[4:1] = 0

5mA  I
250mV
SET_TXDE[4:1] = 10

5mA  I
250mV
SET_TXDE[4:1] = 0

5mA  I
250mV
SET_TXDE[4:1] = 10

2mA  I

2mA  I

 12mA (Note 8) 4 %

MOD

 10mA, 20% to 80%,

MOD

 12mA, at 10.32Gbps,

MOD

 VIN 800mV

P-P

 12mA, at 10.32Gbps,

MOD

 VIN 800mV

P-P

 12mA, at 8.5Gbps,

MOD

 VIN 800mV

P-P

 12mA, at 8.5Gbps,

MOD

 VIN 800mV

P-P

 12mA, at 4.25Gbps 5

MOD

 12mA, at 1.0625Gbps 5

MOD

 2.95V 12 mA

CCTO

,

P-P

,

P-P

,

P-P

,

P-P

26 39 ps

6 12

6 13

6 12

6 12

V

P-P

P-P

P-P

P-P

P-P

P-P

P-P

dB

dB

ps

MAX3798

1.0625Gbps to 10.32Gbps, Integrated, Low-

Power SFP+ Limiting Amplifier and VCSEL Driver

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter out­put load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V

CC

= 3.3V, I

BIAS

= 6mA, I

MOD

= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure­ments. For testing, the MODE_SEL bit was used and the MSEL pin was left open.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Random Jitter

Output Return Loss SDD22

5mA  I
800mV

DUT is powered on, f  5GHz 12

DUT is powered on, f  16GHz 5

 12mA, 250mV

MOD

P-P

P-P

 VIN

Tx BIAS GENERATOR

Maximum Bias-On Current I

Minimum Bias-On Current I

BIASMAX

BIASMIN

BIAS Current DAC Stability 2mA  I

Compliance Voltage at BIAS V

BIAS Current Monitor Current
Gain

Compliance Voltage at BMON V

BIAS Current Monitor Current
Gain Stability

Current into BIAS pin 15 mA

Current into BIAS pin 2 mA

 15mA (Notes 2, 10) 4 %

BIAS

0.9 2.1 V

BIAS

I

BMON

BMON

I

BMON

External resistor to GND defines the
voltage gain

0 1.8 V

2mA  I

 15mA (Note 10) 5 %

BIAS

Tx SAFETY FEATURES

Average voltage, FAULT always occurs for

 VCC - 0.65V, FAULT never occurs

Excessive Voltage at BMAX V

BMAX

V

BMAX

for V

 VCC - 0.55V

BMAX

V

0.65V

0.17 0.5 ps

RMS

dB

16 mA/A

-

CC

VCC -

0.6V

VCC -

0.55V

V

Excessive Voltage at MMAX V

Excessive Voltage at BMON V

Excessive Voltage at BIAS V

Maximum VCSEL Current in Off
State

SFP TIMING REQUIREMENTS

Mode-Select Change Time t_

MODESEL

DISABLE Assert Time t_

Average voltage, FAULT always occurs for
V

MMAX

 VCC - 0.65V, FAULT never occurs

MMAX

for V

MMAX

 VCC - 0.55V

Average voltage, FAULT warning alwa ys

BMON

occurs for V
warning never occurs for V

0.65V

Average voltage, FAULT always occurs for

 0.44V, FAULT never occurs for

V

BIAS

I

OFF

BIAS

V

 0.65V

BIAS

FAULT or DISABLE, V

Time from ri sing or falling edge at MSEL
until Rx output PWD falls below 10ps

Time from ri sing edge of DISABLE input

OFF

signal to I
I

MODOFF

BIAS

 VCC - 0.55V, FAULT

BMON

BIAS

= I

BIASOFF

-

BMON

 VCC -

V

CC

0.65V

-

V

CC

0.65V

VCC -

0.6V

VCC -

0.6V

VCC -

0.55V

VCC -

0.55V

V

V

0.44 0.48 0.65 V

= VCC 25 μA

10 μs

and I

MOD

=

1 μs

MAX3798

1.0625Gbps to 10.32Gbps, Integrated, Low­Power SFP+ Limiting Amplifier and VCSEL Driver

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter out­put load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V

CC

= 3.3V, I

BIAS

= 6mA, I

MOD

= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure­ments. For testing, the MODE_SEL bit was used and the MSEL pin was left open.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Time from fall ing edge of DISABLE to I

DISABLE Negate Time t_

FAULT Reset Time of Power-On
Time

FAULT Reset Time t_

DISABLE to Reset

OUTPUT LEVEL VOLTAGE DAC (SET_CML)

Ful l-Scale Voltage VFS 100 differential resist ive load 1200 mV

Resolution 5 mV

Integral Nonlinearity INL 5mA  I

LOS THRESHOLD VOLTAGE DAC (SET_LOS)

Ful l-Scale Voltage VFS 94 mV

Resolution 1.5 mV

Integral Nonlinearity INL 11mV

BIAS CURRENT DAC (SET_IBIAS)

Ful l-Scale Current I

Resolution 40 μA

Integral Nonlinearity INL 1mA  I

Differentia l Nonlinearity DNL

MODULATION CURRENT DAC (SET_IMOD)

Ful l-Scale Current I

Resolution 40 μA

Integral Nonlinearity INL 2mA  I

Differentia l Nonlinearity DNL

CONTROL I/O SPECIFICATIONS

MSEL Input Current IIH, IIL 150 μA

MSEL Input High Voltage VIH 1.8 VCC V

MSEL Input Low Voltage VIL 0 0.8 V

MSEL Input Impedance R

DISABLE Input Current

DISABLE Input High Voltage VIH 1.8 VCC V

t_

INIT

FAULT

FS

FS

PULL

IIH 12

I

and I

ON

FAULT = 0 before reset

Time from power-on or negation of FAULT
using DISABLE

Time from fault to FAULT on,
C

FAULT

Time DISABLE must be held high to reset
FAULT

1mA  I
tonic at 8-bit resolution (SET_IBIAS[8:1])

2mA  I
tonic at 8-bit resolution (SET_IMOD[8:1])

Internal pulldown resistor 40 75 110 k

Dependency on pullup resistance 420 800

IL

at 90% of steady state when

MOD

 20pF, R

CML_LEVEL

 V

P-P

TH_LO S

 15mA ±1 LSB

BIAS

 15mA, guaranteed mono-

BIAS

 12mA ±1 LSB

MOD

 12mA, guaranteed mono-

MOD

= 4.7k

FAULT

 20mA ±0.9 LSB

 94mV

±0.7 LSB

P-P

BIAS

500 μs

100 ms

10 μs

5 μs

21 mA

±1

21 mA

±1

P-P

P-P

P-P

P-P

LSB

LSB

μA

MAX3798

1.0625Gbps to 10.32Gbps, Integrated, Low-

Power SFP+ Limiting Amplifier and VCSEL Driver

_______________________________________________________________________________________ 7

ELECTRICAL CHARACTERISTICS (continued)

(VCC= 2.85V to 3.63V, TA= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, CAZ= 1nF, transmitter out­put load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V

CC

= 3.3V, I

BIAS

= 6mA, I

MOD

= 6mA, unless
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure­ments. For testing, the MODE_SEL bit was used and the MSEL pin was left open.)

Note 1: Supply current is measured with unterminated receiver CML output or with AC-coupled Rx output termination. The Tx out-

put and the bias current output must be connected to a separate supply in order to remove the modulation/bias current
portion from the supply current. BIAS must be connected to 2.0V. TOUT+/- must be connected through 50Ω load resistors
to a separate supply voltage.

Note 2: Guaranteed by design and characterization, T

A

= -40°C to +95°C.

Note 3: The data input transition time is controlled by a 4th-order Bessel filter with -3dB frequency = 0.75 x data rate. The determin-

istic jitter caused by this filter is not included in the DJ generation specifications.

Note 4: Test pattern is 00001111 at 4.25Gbps for MODE_SEL = 0. Test pattern is 00001111 at 8.5Gbps for MODE_SEL = 1.

DISABLE Input Low Voltage VIL 0 0.8 V

DISABLE Input Impedance R

LOS, FAULT Output High Voltage V

LOS, FAULT Output Low Voltage V

3-WIRE DIGITAL I/O SPECIFICATIONS (SDA, CSEL, SCL)

Input High Voltage VIH 2.0 VCC V

Input Low Voltage VIL 0.8 V

Input Hystere sis V

Input Leakage Current IIL, I

Output High Voltage V

Output Low Voltage V

3-WIRE DIGITAL INTERFACE TIMING CHARACTERISTICS (see Figure 4)

SCL Clock Frequency f

SCL Pulse-Width High tCH 0.5 μs

SCL Pulse-Width Low tCL 0.5 μs

SDA Setup Time tDS 100 ns

SDA Hold Time tDH 100 ns

SCL Rise to SDA Propagation
Time

CSEL Pulse-Width Low t

CSEL Leading Time Before the
First SCL Edge

CSEL Trailing Time After the
Last SCL Edge

SDA, SCL External Load C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Internal pullup resistor 5.5 8 10.5 k

PULL

R

= 4.7k - 10k to VCC,

OH

OL

HYST

OH

OL

SCL

t

D

CSW

t

L

t

T

B

LOS

= 4.7k - 10k to V

R

FAULT

R

= 4.7k - 10k to VCC,

LOS

= 4.7k - 10k to V

R

FAULT

0.082 V

VIN = 0V or VCC; internal pullup or pulldown

IH

(75k typical)

External pullup of 4.7k to V

External pullup of 4.7k to VCC 0.4 V

400 1000 kH z

5ns

500 ns

Total bus capacitance on one line with

4.7k pullup to V

CC

CC

CC

CC

VCC -

VCC -

0.5

0 0.4 V

150 μA

0.5

20 pF

V

V

500 ns

500 ns

CC

V

MAX3798

1.0625Gbps to 10.32Gbps, Integrated, Low­Power SFP+ Limiting Amplifier and VCSEL Driver

8 _______________________________________________________________________________________

Figure 1. Test Circuit for VCSEL Driver Characterization

Note 5: Receiver deterministic jitter is measured with a repeating 231- 1 PRBS equivalent pattern at 10.32Gbps. For 1.0625Gbps to

8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is defined as the arithmetic sum
of pulse-width distortion (PWD) and pattern-dependent jitter (PDJ).

Note 6: Measured with a k28.5 pattern from 1.0625Gbps to 8.5Gbps. Measured with 2

31

- 1 PRBS at 10.32Gbps.

Note 7: Measurement includes an input AC-coupling capacitor of 100nF and C

CAZ

of 100nF. The signal at the input is switched

between two amplitudes: Signal_ON and Signal_OFF.

1) Receiver operates at sensitivity level plus 1dB power penalty.
a) Signal_OFF = 0

Signal_ON = (+8dB) + 10log(min_assert_level)

b) Signal_ON = (+1dB) + 10log(max_deassert_level)

Signal_OFF = 0

2) Receiver operates at overload.
Signal_OFF = 0
Signal_ON = 1.2V

P-P

max_deassert_level and the min_assert_level are measured for one LOS_THRESHOLD setting.

Note 8: Gain stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and V

CC

from +2.95V to +3.63V. Reference current measured at VCC= +3.2V, TA= +25°C.

Note 9: Transmitter deterministic jitter is measured with a repeating 2

7

- 1 PRBS, 72 0s, 27- 1 PRBS, and 72 1s pattern at

10.32Gbps. For 1.0625Gbps to 8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is

defined as the arithmetic sum of PWD and PDJ.

Note 10: Gain stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and V

CC

from +2.85V to +3.63V. Reference current measured at VCC= +3.3V, TA= +25°C.

CONTROLLER

V

50Ω

OSCILLOSCOPE

50Ω

V

CC

0.1μF 0.1μF

CONTROLLER

1μH

4.7kΩ

CCR

50Ω

50Ω

1000pF

V

V

CCR

0.1μF

0.1μF

CCD

1000pF

V

CCR

V

CCT

V

CCD

V

CCR

LOS

MSEL

ROUT+

ROUT-

DISABLE

V

CCD

1nF

CAZ1

SCL

SDA

CONTROLLER

CSEL

CAZ2

MAX3798

TIN+

50Ω

50Ω

RIN+

0.1μF

0.1μF

50Ω

RIN-

TIN-

50Ω

0.1μF

0.1μF

V

CCT

MMAX

BMON

1kΩ

400Ω

V

V

BMAX

FAULT

BIAS

TOUT+

TOUT-

V

CCT

V

CCT

EER

EET

0.1μF

0.1μF

V

CCT

400Ω

CONTROLLER

50Ω

50Ω

1000pF

4.7kΩ

50Ω

OSCILLOSCOPE

50Ω

MAX3798

1.0625Gbps to 10.32Gbps, Integrated, Low-

Power SFP+ Limiting Amplifier and VCSEL Driver

_______________________________________________________________________________________

9

Typical Operating Characteristics—Limiting Amplifier

(VCC= 3.3V, TA= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the MODE_SEL bit was
used and the MSEL pin was left open.)

RANDOM JITTER

vs. INPUT AMPLITUDE

370

360

350

340

330

RANDOM JITTER (ps)

320

310

300

AT 4.25Gbps MODE_SEL = 0

AT 8.5Gbps MODE_SEL = 1

0 1200

INPUT AMPLITUDE (mV

12

MAX3798 toc01

1000800600400200

)

P-P

11

10

9

8

7

6

DETERMINISTIC JITTER (ps)

5

4

3

DETERMINISTIC JITTER

vs. INPUT AMPLITUDE AT 4.25Gbps

PATTERN = k28.5, MODE_SELECT = 0

0 1200

DETERMINISTIC JITTER

vs. DATA RATE

MAX3798 toc04

BER

1.0E-01

1.0E-02

1.0E-03

1.0E-04

1.0E-05

1.0E-06

1.0E-07

1.0E-08

1.0E-09

1.0E-10

1.0E-11

10

PATTERN = k28.5

9

8

7

6

5

DETERMINISTIC JITTER (ps)

4

3

2

012

MODE_SEL = 0, SLEW_RATE = 1

MODE_SEL = 1

1082 4 6

DATA RATE (Gbps)

vs. INPUT AMPLITUDE

MODE_SEL = 0

0.5 2.5

SLEW_RATE = 0

SLEW_RATE = 1

INPUT AMPLITUDE (mV

BER

AT 8.5Gbps

AT 8.5Gbps

MODE_SEL = 1

INPUT AMPLITUDE (mV

7

MAX3798 toc02

1000800600400200

)

P-P

MAX3798 toc05

2.01.51.0
)

P-P

6

5

4

3

DETERMINISTIC JITTER (ps)

2

1

50mV/div

DETERMINISTIC JITTER

vs. INPUT AMPLITUDE

PATTERN = PRBS, MODE_SEL = 1

AT 8.5Gbps

AT 10.32Gbps

0 1200

INPUT AMPLITUDE (mV

OUTPUT EYE DIAGRAM AT 10.32Gbps

20ps/div

P-P

1000800600400200

)

MAX3798 toc06

MAX3798 toc03

50mV/div

OUTPUT EYE DIAGRAM AT 8.5Gbps

20ps/div

MAX3798 toc07

50mV/div

OUTPUT EYE DIAGRAM AT 4.25Gbps

50ps/div

MAX3798 toc08

MODE_SEL = 1

100mV/div

OUTPUT EYE DIAGRAM AT 4.25Gbps

MODE_SEL = 0, SLEW_RATE = 1

50ps/div

MAX3798 toc09

MAX3798

1.0625Gbps to 10.32Gbps, Integrated, Low­Power SFP+ Limiting Amplifier and VCSEL Driver

10 ______________________________________________________________________________________

Typical Operating Characteristics—Limiting Amplifier (continued)

(VCC= 3.3V, TA= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the MODE_SEL bit was
used and the MSEL pin was left open.)

OUTPUT EYE DIAGRAM AT 4.25Gbps

MODE_SEL = 0, SLEW_RATE = 0

100mV/div

MAX3798 toc10

50ps/div

TRANSITION TIME vs. INPUT AMPLITUDE

50

45

MODE_SEL = 0, SLEW_RATE = 0, RXDE_EN = 0

40

35

MODE_SEL = 0, SLEW_RATE = 0, RXDE_EN = 1

30

MODE_SEL = X, SLEW_RATE = 1, RXDE_EN = 0

25

20

MODE_SEL = X, SLEW_RATE = 1, RXDE_EN = 1

TRANSITION TIME (ps)

15

10

5

0

0 1200

INPUT AMPLITUDE (mV

PATTERN = 00001111,
DATA RATE = 8.5Gbps,
20% TO 80%

LOS THRESHOLD vs. DAC SETTING

180

160

MAX3798 toc11

140

120

100

80

60

LOS THRESHOLD (mV)

40

20

1000800600400200

)

P-P

0

063

DEASSERT

ASSERT

SET_LOS[5:0]

MAX3798 toc12

564935 4214 21 287

-12
USING FINISAR ROSA

-13

-14

-15

-16

SENSITIVITY OMA (dBm)

-17

-18

MODE_SEL = 1

MODE_SEL = 0

212

DATA RATE (Gbps)

10864

MAX3798 toc13

0

-10

-20

-30

SDD11 (dB)

-40

-50

-60
100M 100G

SENSITIVITY vs. DATA RATE

Rx INPUT RETURN LOSS

CML OUTPUT AMPLITUDE

1400

)

1200

P-P

1000

800

600

400

CML OUTPUT AMPLITUDE (mV

200

10G1G

FREQUENCY (Hz)

vs. DAC SETTING

MAX3798 toc14

MAX3798 toc16

Rx OUTPUT RETURN LOSS

0

-5

-10

-15

-20

-25

SDD22 (dB)

-30

-35

-40

-45

-50
100M 100G

FREQUENCY (Hz)

10G1G

MAX3798 toc15

0

0 300

SET_CML[7:0]

25020015010050

MAX3798

1.0625Gbps to 10.32Gbps, Integrated, Low-

Power SFP+ Limiting Amplifier and VCSEL Driver

______________________________________________________________________________________

11

Typical Operating Characteristics—VCSEL Driver

(VCC= 3.3V, TA= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the MODE_SEL bit was
used and the MSEL pin was left open.)

TOTAL SUPPLY CURRENT

vs. TEMPERATURE

MAX3798 toc17

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

806535 50-10 5 20-25

50

60

70

80

90

100

110

120

130

140

40

-40 95

I

BIAS

= 12mA

I

BIAS

= 9mA

I

BIAS

= 2mA

I

MOD

= 2mA; RECEIVER OUTPUT = 400mV

P-P

;
TOTAL SUPPLY MEASURED USING THE SETUP
IN FIGURE 1.

TOTAL SUPPLY CURRENT

vs. TEMPERATURE

MAX3798 toc18

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

806535 50-10 5 20-25

50

60

70

80

90

100

110

120

130

140

150

160

40

-40 95

I

MOD

= 12mA

I

MOD

= 9mA

I

MOD

= 2mA

I

BIAS

= 2mA; RECEIVER OUTPUT = 400mV

P-P

;
TOTAL SUPPLY MEASURED USING THE SETUP
IN FIGURE 1.

OPTICAL EYE DIAGRAM

MAX3798 toc19

14ps/div

10.3Gbps, SET_IMOD = 60, 27 - 1 PRBS,
850nm VCSEL, MASK WITH 44%

OPTICAL EYE DIAGRAM

MAX3798 toc20

17ps/div

8.5Gbps, SET_IMOD = 60, 27 - 1 PRBS,
850nm VCSEL, MASK WITH 54%

OPTICAL EYE DIAGRAM

MAX3798 toc21

34ps/div

4.25Gbps, SET_IMOD = 60, 27 - 1 PRBS,
850nm VCSEL, MASK WITH 46%

OPTICAL EYE DIAGRAM

MAX3798 toc22

68ps/div

2.125Gbps, SET_IMOD = 60, 27 - 1 PRBS,
850nm VCSEL, MASK WITH 50%

DETERMINISTIC JITTER

vs. MODULATION CURRENT

MAX3798 toc23

MODULATION CURRENT (mA

P-P

)

DETERMINISTIC JITTER (ps)

10864

5.0

5.5

6.0

6.5

7.0

7.5

8.0

4.5
212

PATTERN = PRBS, DATA RATE = 10.32Gbps

TRANSITION TIME

vs. MODULATION CURRENT

MAX3798 toc24

MODULATION CURRENT (mA

P-P

)

TRANSITION TIME (ps)

10864

8

13

18

23

28

33

38

3

212

FALL TIME

RISE TIME

PATTERN = 11110000,
DATA RATE = 8.5Gbps

TRANSITION TIME

vs. DEEMPHASIS SETTING

MAX3798 toc25

SET_TXDE[3:0]

TRANSITION TIME (ps)

1091 2 3 5 6 74 8

27

29

31

33

35

37

39

41

25

011

FALL TIME

RISE TIME

PATTERN = 11110000,
DATA RATE = 8.5Gbps,
I

MOD

= 10mA

P-P