General Description
The MAX3746 multirate limiting amplifier functions as a
data quantizer for SONET, Fibre-Channel, and Gigabit
Ethernet optical receivers. The amplifier accepts a wide
range of input voltages and provides selectable-level,
current-mode logic (CML) output voltages with controlled edge speeds. A received-signal-strength indicator (RSSI) is available when the MAX3746 is
DC-coupled to the MAX3744/MAX3724 SFP transimpedance amplifier (TIA). A receiver consisting of the
MAX3744/MAX3724 and the MAX3746 can provide up
to 19dB RSSI dynamic range. Additional features
include a programmable loss-of-signal (LOS) detect, an
optional disable function (DISABLE), and an
output-signal polarity reversal (OUTPOL). Output disable can be used to implement squelch.
The combination of the MAX3746 and the MAX3744/
MAX3724 allows for the implementation of all the smallform-factor SFF-8472 digital diagnostic specifications
using a standard 4-pin TO-46 header.
The MAX3746 is pin-for-pin compatible with the
MAX3748A limiting amplifier and consumes 30% less
power. The MAX3746 is packaged in a 3mm x 3mm,
16-pin QFN package.
Applications
Gigabit Ethernet SFF/SFP Transceiver Modules
Fibre-Channel SFF/SFP Transceiver Modules
Multirate OC-12 to OC48-FEC SFF/SFP
Transceiver Modules
Features
♦ SFP Reference Design Available
♦ Low 115mW Power Consumption
♦ 16-Pin QFN Package with 3mm x 3mm Footprint
♦ 70ps Rise and Fall Time
♦ Loss-of-Signal with Programmable Threshold
♦ RSSI Interface (with MAX3744/MAX3724 TIA)
♦ Output Disable
♦ Polarity Select
♦ 8.4ps
P-P
Deterministic Jitter (3.2Gbps)
♦ Improved EMI Performance
♦ Selectable CML Output levels
♦ Pin Compatible with MAX3748A
MAX3746
Low-Power, 622Mbps to 3.2Gbps
Limiting Amplifier
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3386; Rev 0; 8/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Typical Operating Circuits continued at end of data sheet.
Pin Configuration appears at end of data sheet.
MAX3746
MAX3744 TIA
DS1859
3-INPUT DIAGNOSTIC
MONITOR
R1
3kΩ
C1
0.1µF
IN+
IN-
RSSI TH DISABLE LOS
OUTPOL V
CC
GND
4.7kΩ TO 10kΩ
LOS
2.97V TO 3.6V
OUT+
50Ω
0.1µF
OUT-
50Ω
0.1µF
SERDES
RTH = 14kΩ
SUPPLY FILTER HOST FILTER
V
CC
_RX
4-PIN TO HEADER
HOST BOARDSFP OPTICAL RECEIVER
Typical Operating Circuits
PART TEMP RANGE PIN-PACKAGE PKG CODE
MAX3746ETE -40°C to +85°C 16 QFN T1633F-3
MAX3746
Low-Power, 622Mbps to 3.2Gbps
Limiting Amplifier
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Power-Supply Voltage (VCC).................................-0.5V to +4.5V
Voltage at IN+, IN- ..........................(V
CC
- 2.4V) to (VCC+ 0.5V)
Voltage at DISABLE, OUTPOL, RSSI,
LOS, TH...................................................-0.5V to (V
CC
+ 0.5V)
Current into LOS.....................................................1mA to +9mA
Differential Input Voltage (IN+ - IN-) .....................................2.5V
Continuous Current at CML Outputs
(OUT+, OUT-) ................................................-25mA to +25mA
Continuous Power Dissipation (T
A
= + 70°C)
16-Pin QFN (derate 17.7mW above +70°C) .....................1.4W
Operating Junction Temperature Range (T
J
)....-55°C to +150°C
Storage Ambient Temperature Range (Ts) .......-55°C to +150°C
ELECTRICAL CHARACTERISTICS
(VCC= +2.97V to +3.63V, CML output load is 50Ω to VCC, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC=
+3.3V, T
A
= +25°C, unless otherwise specified. The data input transition time is controlled by 4th-order Bessel filter with f
-3dB
= 0.75 x
2.667GHz for all data rates of 2.667Gbps and below, and with f
-3dB
= 0.75 x 3.2GHz for a data rate of 3.2Gbps.)
Single-Ended Input Resistance R
Input Return Loss
Input Sensitivity V
Input Overload V
Single-Ended Output Resistance R
Output Return Loss diff S
CML Differential Output Voltage
Differential Output Signal when
Disabled
Deterministic Jitter
(Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Single ended to V
IN
se S
diff S
IN-MIN
IN-MAX
OUT
S i ng l e end ed , f < 3GH z, D U T i s p ow er ed on 14
11
Differential, f < 3GHz, DUT is powered on 15
11
(Note 1) 2 4 mV
(Note 1) 1200 mV
Single ended to V
Differential, f < 3GHz, DUT is powered on 20 dB
22
4mV
< V
P-P
OUTPOL connected to V
4mV
< V
P-P
OUTPOL open or connected to 30kΩ
CC
CC
< 1200mV
IN
< 1200mV
IN
P-P
CC
P-P
,
or GND
,
42 50 58 Ω
42 50 58 Ω
600 800 1000
400 500 600
Outputs AC-coupled,
V
applied to input (Note 2)
IN-MAX
10 mV
K28.5 pattern at 3.2Gbps (Note 2) 8.4 18
K28.5 pattern at 3.2Gbps at TA = +100°C 10.2
23
2
- 1 PRBS equivalent at 2.7Gbps (Note 2) 11.6 23
23
2
DJ
- 1 PRBS equivalent pattern at 2.7Gbps
= +100°C
at T
A
K28.5 pattern at 2.1Gbps 8 20
13.1
K28.5 pattern at 2.1Gbps at TA = +100°C 9.7
223 - 1 PRBS equivalent pattern at 622Mbps
(Note 2)
23
2
- 1 PRBS equivalent pattern at 622Mbps
at T
= +100°C
A
42.5 69
47.8
dB
P-P
P-P
mV
P-P
P-P
ps
P-P
MAX3746
Low-Power, 622Mbps to 3.2Gbps
Limiting Amplifier
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +2.97V to +3.63V, CML output load is 50Ω to VCC, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC=
3.3V, T
A
= +25°C, unless otherwise specified. The data input transition time is controlled by 4th-order Bessel filter with f
-3dB
= 0.75 x
2.667GHz for all data rates of 2.667Gbps and below, and with f
-3dB
= 0.75 x 3.2GHz for a data rate of 3.2Gbps.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Random Jitter Input = 4mV
P-P
(Notes 2, 4) 3 7
ps
RMS
Data Output Transition
Time
4mV
P-P
< V
INP-P
< 1200mV
P-P
,
20% to 80% (Note 2)
70 114 ps
Input-ReferredNoise (Note 2) 150
µV
RMS
Low-Frequency Cutoff 20 kHz
Includes the CML output current; OUTPOL
connected to V
CC
or GND
35
Includes the CML output current; OUTPOL
open or connected to 30kΩ to GND
29 35
Power-Supply Current I
CC
Excludes the CML output current and the
CM_RSSI circuitry; OUTPOL connected to
V
CC
or GND (Note 5)
20 25
mA
Power-Supply Noise Rejection PSNR f < 2MHz 40 dB
LOSS-OF-SIGNAL (Notes 2, 6)
LOS Hysteresis 10 log (V
DEASSERT
/ V
ASSERT
)
2.2 dB
LOS Assert/Deassert Time (Note 7) 2.3 50 µs
Low LOS Assert Level RTH = 2kΩ 2.6 4 6.4
mV
P-P
Low LOS Deassert Level RTH = 2kΩ 6 9.6
mV
P-P
Medium LOS Assert Level RTH = 14kΩ
28
mV
P-P
Medium LOS Deassert Level RTH = 14kΩ 42
mV
P-P
High LOS Assert Level RTH = 25kΩ 36 50
mV
P-P
High LOS Deassert Level RTH = 25kΩ 84
mV
P-P
CM_RSSI SPECIFICATION
RSSI Current Gain A
RSSIIRSSI
/ I
CM_RSSI
(Note 8)
V
CM
to I
RSSI
3dB Bandwidth 40 kHz
Input-Referred RSSI Current
Stability
I
RSS
I
ARSS
I
Input < 6.6mA, 0V ≤ V
RSSI
≤ 2.5V (Note 9) -40
µA
RSSI Output Compliance Voltage
V
RSSI
0 2.0 V
TTL/CMOS I/O
LOS Output High Voltage V
OH
R
LOS
= 4.7kΩ to 10kΩ to Vcc_host (3V) 2.4 V
LOS Output Low Voltage V
OL
R
LOS
= 4.7kΩ to 10kΩ to Vcc_host (3.6V) 0.4 V
1.25
19.6
0.031
41.5
31.8
54.7
54.3
114
+36
Typical Operating Characteristics
(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
MAX3746
Low-Power, 622Mbps to 3.2Gbps
Limiting Amplifier
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +2.97V to +3.63V, CML output load is 50Ω to VCC, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC=
+3.3V, T
A
= +25°C, unless otherwise specified. The data input transition time is controlled by 4th-order Bessel filter with f
-3dB
= 0.75 x
2.667GHz for all data rates of 2.667Gbps and below, and with f
-3dB
= 0.75 x 3.2GHz for a data rate of 3.2Gbps.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DISABLE Input High V
IH
2.0 V
DISABLE Input Low V
IL
0.8 V
DISABLE Input Current R
LOS
= 4.7kΩ to 10kΩ to Vcc_host 10 µA
Note 1: Between sensitivity and overload, all AC specifications are met.
Note 2: Guaranteed by design and characterization.
Note 3: The deterministic jitter caused by the filter is not included in the DJ generation specification.
Note 4: Random jitter was measured without using a filter at the input.
Note 5: The supply current measurement excludes the CML output currents by connecting the CML outputs to a separate V
CC
. (See
Figure 1.)
Note 6: Hysteresis is calculated as 10 log (V
DEASSERT
/ V
ASSERT
). Unless otherwise specified, the data rate for all LOS detect speci-
fications varies from 622Mbps up to 3.2Gbps, and the patterns are 1010 or 2
23
- 1 PRBS.
Note 7: The signal is switched between two amplitudes, Signal_On and Signal _Off as shown in Figure 2.
Note 8: I
CM_RSSI
is the input common-mode current. I
RSSI
is the current at the RSSI output.
Note 9: Stability is defined as the variation over temperature and power supply with respect to the typical gain of the part.
SUPPLY CURRENT
vs. TEMPERATURE
MAX3746 toc01
TEMPERATURE (°C)
CURRENT (mA)
908060 70-10 0 10 20 30 40 50-30-20
10
20
30
40
50
60
70
80
90
100
0
-40 100
CML OUTPUTS INCLUDED
CML OUTPUTS NOT INCLUDED
OUTPOL = V
CC
TRANSFER FUNCTION
MAX3746 toc02
DIFFERENTIAL INPUT (mV
P-P
)
DIFFERENTIAL OUTPUT (mV
P-P
)
54321
100
200
300
400
500
600
700
800
900
0
06
OUTPOL = V
CC
RANDOM JITTER vs. TEMPERATURE
(INPUT LEVEL 10mV
P-P
)
MAX3746 toc03
TEMPERATURE (°C)
RANDOM JITTER (ps
RMS
)
908060 70-10 0 10 20 30 40 50-30-20
1
2
3
4
5
6
7
8
9
10
0
-40 100
MAX3746
Low-Power, 622Mbps to 3.2Gbps
Limiting Amplifier
_______________________________________________________________________________________ 5
Typical Operating Characteristics (continued)
(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
RANDOM JITTER
10
9
8
)
7
RMS
6
5
4
3
RANDOM JITTER (ps
2
1
0
vs. INPUT AMPLITUDE
1200
1000
MAX3746 toc04
)
-12
800
600
400
BIT-ERROR RATIO (10
200
040
DIFFERENTIAL INPUT (mV
353020 2510 155
)
P-P
0
0 5.0
OUTPUT EYE DIAGRAM
(MINIMUM INPUT)
3.2Gbps, K28.5, 4mV
P-P
MAX3746 toc07
3.2Gbps, K28.5, 1200mV
BIT-ERROR RATIO
vs. INPUT VOLTAGE
INPUT VOLTAGE (mV
P-P
OUTPUT EYE DIAGRAM
(MAXIMUM INPUT)
P-P
)
4.54.03.53.02.52.01.51.00.5
MAX3746 toc08
24
)
MAX3746 toc05
22
P-P
20
18
16
14
DETERMINISTIC JITTER (ps
12
10
-1.0 0
DETERMINISTIC JITTER
vs. INPUT COMMON-MODE VOLTAGE
(2.7Gbps, K28.5)
-0.1-0.2-0.9 -0.8 -0.7 -0.5 -0.4-0.6 -0.3
COMMON-MODE VOLTAGE (V
+ X)
CC
OUTPUT EYE DIAGRAM
2.7Gbps, 2
(MINIMUM INPUT)
23
- 1 PRBS, 4mV
MAX3746 toc09
P-P
MAX3746 toc06
100mV/div
2.7Gbps, 2
100mV/div
50ps/div
OUTPUT EYE DIAGRAM
(MAXIMUM INPUT)
23
- 1 PRBS, 1200mV
P-P
50ps/div
MAX3746 toc10
100mV/div
50ps/div
OUTPUT EYE DIAGRAM AT +100°C
(MINIMUM INPUT)
23
2.7Gbps, 2
100mV/div
- 1 PRBS, 4mV
50ps/div
P-P
MAX3746 toc11
100mV/div
100ps/div
ASSERT/DEASSERT LEVELS vs. R
120
)
100
P-P
80
60
40
LOS ASSERT/DEASSERT (mV
20
0
030
DEASSERT
RTH (kΩ)
TH
MAX3726 toc12
ASSERT
2010
MAX3746
Low-Power, 622Mbps to 3.2Gbps
Limiting Amplifier
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
GAIN (dB)
-10
-20
-30
-40
INPUT RETURN GAIN (SDD11)
(INPUT SIGNAL LEVEL = -50dBm)
(OUTPUT DISABLED)
30
20
10
0
100M 10G
1G
FREQUENCY (Hz)
MAX3746 toc13
OUTPUT RETURN GAIN (SDD22)
(INPUT SIGNAL LEVEL = -50dBm)
(WITH INPUT DC OFFSET)
30
20
10
0
GAIN (dB)
-10
-20
-30
-40
100M 10G
1G
FREQUENCY (MHz)
20
18
)
MAX3746 toc14
16
P-P
14
12
10
8
6
DETERMINISTIC JITTER (ps
4
2
0
DETERMINISTIC JITTER
vs. INPUT OFFSET VOLTAGE
(2.667Gbps, K28.5)
-6 6
INPUT OFFSET VOLTAGE (mV
542 3-4 -3 -2 -1 0 1-5
)
P-P
MAX3746 toc15
LOS HYSTERESIS
vs. TEMPERATURE
(2.667Gbps, 2
6
5
4
RTH = 25kΩ
3
2
10 log (DEASSERT/ASSERT) (dB)
1
0
-40
RTH = 2.00kΩ
TEMPERATURE (°C)
SINGLE-ENDED
OUTPUT SIGNAL
2.7Gbps, 27 - 1, 1000mV
50mV/div
23
- 1 PRBS)
RTH = 14kΩ
P-P
MAX3746 toc18
9080706050403020100-10-20-30
MAX3746 toc16
RSSI CURRENT vs. INPUT TIA CURRENT
(MAX3744 and MAX3746)
700
600
500
400
300
200
OUTPUT RSSI CURRENT (µA)
100
0
0 1000
INPUT TIA CURRENT (µA)
RSSI CURRENT vs. OPTICAL POWER
(MAX3744 and MAX3746)
700
600
500
400
300
MAX3746 toc17
900800700600500400300200100
MAX3746 toc19
200
OUTPUT RSSI CURRENT (µA)
100
0
200ps/div
-30 0
OPTICAL POWER (dBm)
-5-10-15-20-25
MAX3746
Low-Power, 622Mbps to 3.2Gbps
Limiting Amplifier
_______________________________________________________________________________________ 7
Pin Description
Detailed Description
The MAX3746 limiting amplifier consists of an input
buffer, a multistage amplifier, offset-correction circuitry,
an output buffer, power-detection circuitry, and signaldetect circuitry (see the Functional Diagram).
Input Buffer
The input buffer is shown in Figure 3. It provides 50Ω termination for each input signal IN+ and IN-. The MAX3746
can be DC- or AC-coupled to a TIA (TIA output offset
degrades receiver performance if DC-coupled). The
CML input buffer is optimized for the MAX3744/
MAX3724 TIA.
Gain Stage
The high-bandwidth multistage amplifier provides
approximately 60dB of gain.
Offset Correction Loop
The MAX3746 is susceptible to DC offsets in the signal
path because it has high gain. In communication systems using NRZ data with a 50% duty cycle, pulsewidth distortion present in the signal, or generated in
the transimpedance amplifier, appears as an input offset and is reduced by the offset correction loop.
CML Output Buffer
The MAX3746 limiting amplifier’s CML output provides
high tolerance to impedance mismatches and inductive
connectors. The OUTPOL setting programs the output
current. Connecting the DISABLE pin to V
CC
disables
the output. If the LOS pin is connected to the DISABLE
pin, the outputs OUT+ and OUT- are at a static voltage
(squelch) whenever the input signal level drops below
the LOS threshold. The output common mode remains
constant when the part is disabled. The output buffer
can be AC- or DC-coupled to the load (Figure 4).
PIN NAME FUNCTION
1, 4 V
2 IN+ Noninverted Input Signal, CML
3 IN- Inverted Input Signal, CML
5TH
6 DISABLE
7 LOS
8, 16 GND Supply Ground
9 OUTPOL
10 OUT- Inverted Data Output, CML
11 OUT+ Noninverted Data Output, CML
12 V
13 RSSI
14,15 N.C. No Connection. Leave open.
EP
CC1
CC2
EXPOSED
PAD
Supply Voltage
Loss-of-Signal Threshold Pin. Resistor to ground (R
Connecting this pin to V
Disable Input, CMOS/TTL. The data outputs are held static when this pin is asserted high. The LOS
function remains active when the outputs are disabled.
Noninverted Loss-of-Signal Output. LOS is asserted high when the signal drops below the assert
threshold set by the TH input. The output is open collector.
Output Polarity Control. Connect to GND for an inversion of polarity through the limiting amplifier and
connect to V
Output Supply
Received-Signal-Strength Indicator. This current output can be used to obtain a ground-referenced
voltage proportional to the photodiode current with the MAX3744 by connecting an external resistor
between this pin and GND.
Connect the exposed pad to board ground for optimal electrical and thermal performance.
for normal operation. See Table 1 for all settings.
CC
disables the LOS circuitry and reduces power consumption.
CC
TH
) sets the LOS threshold.
MAX3746
Power Detect and Loss-of-Signal Indicator
The MAX3746 is equipped with multirate LOS circuitry
that indicates when the input signal is below a programmable threshold, set by resistor RTHat the TH pin
(see the Typical Operating Characteristics for appropriate resistor sizing). An averaging RMS power detector
compares the input signal amplitude with this threshold
and feeds the signal-detect information to the open-collector LOS output.
To prevent LOS chatter in the region of the programmed threshold, approximately 2dB of hysteresis is
built into the LOS assert/deassert function. Once
asserted, the LOS is not deasserted until the input
amplitude rises to the required level (V
DEASSERT
). (See
Figures 2 and 5.)
Design Procedure
Program the LOS Assert Threshold
External resistor, R
TH,
programs the loss-of-signal
threshold. See the LOS Threshold vs. RTHgraph in the
Typical Operating Characteristics to select the appropriate resistor.
Low-Power, 622Mbps to 3.2Gbps
Limiting Amplifier
8 _______________________________________________________________________________________
Figure 1. Power-Supply Current Measurement
Figure 2. LOS Assert Threshold Set 1dB Below the Minimum by
Receiver Sensitivity for Selected R
TH
Figure 3. CML Input Buffer
Figure 4. CML Output Buffer
V
CC
I
(SUPPLY CURRENT)
CC
I
(CML
OUT
OUTPUT CURRENT)
V
IN
1dB
MAX DEASSERT LEVEL
SIGNAL ON
50Ω
MAX3746
0.25pF
IN+
IN-
0.25pF
50Ω 50Ω
50Ω
6dB
R
TH
0V
POWER-DETECT WINDOW
MIN ASSERT LEVEL
SIGNAL OFF
TIME
V
CC
Q3 Q4 Q1
DISABLE
V
CC
50Ω50Ω
OUT+
OUT-
Q2
ESD
STRUCTURES
DATA
ESD
STRUCTURES
I2 = f (OUTPOL, DISABLE)I1 = f (OUTPOL, DISABLE)
Select the Coupling Capacitor
When AC coupling is desired, coupling capacitors C
IN
and C
OUT
should be selected to minimize the receiver’s deterministic jitter. Jitter is decreased as the input
low-frequency cutoff (fIN) is decreased.
fIN= 1 / [2π(50)(CIN)]
For ATM/SONET or other applications using scrambled
NRZ data, select (CIN, C
OUT
) ≥ 0.1µF, which provides
fIN< 32kHz. For Fibre Channel, Gigabit Ethernet, or
other applications using 8B/10B data coding, select
(CIN, C
OUT
) ≥ 0.01µF, which provides fIN< 320kHz.
Refer to Application Note HFAN-1.1, Choosing AC-
Coupling Capacitors.
RSSI Implementation
The SFF-8472 Digital Diagnostic specification requires
monitoring of input receive power. The MAX3746 and
MAX3744 receiver chipset allows for the monitoring of
the average receive power by measuring the average
DC current of the photodiode.
The MAX3744/MAX3724 preamp measures the average photodiode current and provides the information to
the output common mode. The MAX3746 RSSI detect
block senses the common-mode DC level of input signals. IN+ and IN- provide a ground-referenced output
signal (RSSI) proportional to the photodiode current.
The advantage of this implementation is that it allows
the TIA to be packaged in a low-cost, conventional 4pin TO-46 header.
The MAX3746 RSSI output is connected to an analog
input channel of the DS1858/DS1859 SFP controller to
convert the analog information into a 16-bit word. The
DS1858/DS1859 provide the receive-power information
to the host board of the optical receiver through a 2wire interface. The DS1859 allows for internal calibration of the receive power monitor.
The MAX3744/MAX3724 and the MAX3746 have been
optimized to achieve RSSI stability of 2.5dB within the
6µA to 500µA range of average input photodiode current. To achieve the best accuracy, MAXIM recommends receive-power calibration at the low end (6µA)
and the high end (500µA) of the required range. See
the RSSI Current Gain graph in the Typical Operating
Characteristics.
Connecting to the Dallas DS1858/DS1859
For best use of the RSSI monitor, capacitor C1 and
resistor R1 shown in the first Typical Application Circuit
need to be placed as close as possible to the Dallas
diagnostic monitor with the ground of C1 and R1 the
same as the DS1858/DS1859 ground. Capacitor C1
suppresses system noise on the RSSI signal. R1 = 3kΩ
and C1 = 0.1µF is recommended.
EMI Performance
The MAX3746 has been designed for better EMI performance. To help reduce EMI, special care has been
taken to produce symmetrical signal outputs. See the
eye diagram of the single-ended output in the Typical
Operating Characteristics.
MAX3746
Low-Power, 622Mbps to 3.2Gbps
Limiting Amplifier
_______________________________________________________________________________________ 9
V
Figure 5. LOS Output Circuit
Table 1. Logic Table for Polarity and CML
Output-Level Settings
Chip Information
TRANSISTOR COUNT: 1385
PROCESS: SiGe Bipolar
CC
GND
LOS
ESD
STRUCTURE
OUTPOL DESCRIPTION
V
CC
Open
30kΩ to GND
GND Inverting output with full CML output level
N oni nver ti ng outp ut w i th ful l C M L outp ut l evel
N oni nver ti ng outp ut w i th r ed uced C M L outp ut
l evel
Inverting output with reduced CML output
level
MAX3746
Low-Power, 622Mbps to 3.2Gbps
Limiting Amplifier
10 ______________________________________________________________________________________
Functional Diagram
Typical Operating Circuits (continued)
IN+
IN-
V
CC
50Ω 50Ω
RSSI
DETECT
OFFSET
CORRECTION
RSSI
V
CC
MAX3746
POWER
DETECT
TH LOS OUTPOL
50Ω 50Ω
OUTPOL
DECODE
OUTOUT+
DISABLE
HOST BOARDSFP OPTICAL RECEIVER
V
(+3.3V OR APD
CC
REFERENCE VOLTAGE)
PIN OR
APD
DS1859
3-INPUT DIAGNOSTIC
MONITOR
MAX3744 TIA
3.01kΩ
VCC (+3.3V)
5-PIN TO HEADER
R1
OUTPOL V
IN+
IN-
MAX3746
RSSI TH DISABLE LOS
RTH = 14kΩ
C1
0.1µF
CC
GND
SUPPLY FILTER HOST FILTER
OUT+
OUT-
0.1µF
50Ω
0.1µF
50Ω
4.7kΩ TO 10kΩ
V
CC_RX
SERDES
2.97V TO 3.6V
LOS
MAX3746
Low-Power, 622Mbps to 3.2Gbps
Limiting Amplifier
______________________________________________________________________________________ 11
Typical Operating Circuits (continued)
MAX3744 TIA
IN+
IN-
RSSI TH DISABLE LOS
OUTPOL V
CC
GND
4.7kΩ TO 10kΩ
LOS
2.97V TO 3.6V
OUT+
50Ω
OUT-
50Ω
C
IN
0.1µF
C
OUT
0.1µF
C
OUT
0.1µF
C
IN
0.1µF
SERDES
SUPPLY FILTER HOST FILTER
V
CC_RX
5-PIN TO HEADER
HOST BOARDSFP OPTICAL RECEIVER
PIN OR
APD
V
CC
(+3.3V OR APD
REFERENCE VOLTAGE)
VCC (+3.3V)
MAX4004
MAX3746
DS1859
3-INPUT DIAGNOSTIC
MONITOR
RTH = 14kΩ
16
1
2
3
4
GND
V
CC1
IN+
IN-
V
CC1
V
CC2
OUT+
OUT-
OUTPOL
15
N.C.14N.C.
13
5 6 7 8
12
11
10
9
RSSI
TH DISABLE LOS GND
3mm x 3mm QFN
MAX3746
Pin Configuration
MAX3746
Low-Power, 622Mbps to 3.2Gbps
Limiting Amplifier
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
D2
D
D/2
D2/2
b
0.10 M C A B
C
L
0.10 C 0.08 C
E/2
E
C
L
A
A2
A1
(NE - 1) X e
C
L
L
e
EXPOSED PAD VARIATIONS
e
PACKAGE OUTLINE
12, 16L, THIN QFN, 3x3x0.8mm
k
(ND - 1) X e
C
L
e
21-0136
E2/2
E2
L
L
DOWN
BONDS
ALLOWED
12x16L QFN THIN.EPS
1
E
2
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
PACKAGE OUTLINE
12, 16L, THIN QFN, 3x3x0.8mm
21-0136
2
E
2
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