Rainbow Electronics MAX3679A User Manual

General Description

The MAX3679A is a low-jitter precision clock generator with the integration of three LVPECL and one LVCMOS outputs optimized for Ethernet applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) clock multiplier to generate high-frequency clock outputs for Ethernet applications.

Maxim’s proprietary PLL design features ultra-low jitter (0.36ps

RMS

) and excellent power-supply noise rejection,

minimizing design risk for network equipment.

Applications

Ethernet Networking Equipment

Features

♦ Crystal Oscillator Interface: 25MHz

♦ CMOS Input: 25MHz ♦ Output Frequencies for Ethernet

62.5MHz, 125MHz, 156.25MHz, 312.5MHz

♦ Low Jitter

0.14ps

RMS

(1.875MHz to 20MHz)

0.36ps

RMS

(12kHz to 20MHz)

♦ Excellent Power-Supply Noise Rejection ♦ No External Loop Filter Capacitor Required

MAX3679A

+3.3V, Low-Jitter Crystal to LVPECL

Clock Generator

________________________________________________________________

Maxim Integrated Products

1

Ordering Information

Typical Application Circuit

19-4858; Rev 0; 8/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

+

Denotes a lead(Pb)-free/RoHS-compliant package.

*

EP = Exposed pad.

EVALUATION KIT

AVAILABLE

Pin Configuration appears at end of data sheet.

10.5Ω

PART TEMP RANGE PIN-PACKAGE

MAX3679AETJ+ -40°C to +85°C 32 TQFN-EP*

+3.3V ±5%

0.01μF0.1μF 0.1μF 0.1μF 0.1μF

10μF

0.1μF

V

CC

(C

25MHz

= 18pF)

L

V

CCO_A

MAX3679A

X_IN GNDO_AGND

V

CC

V

CCA

MR REF_IN

IN_SEL QAC_OE QA_OE QB0_OE QB1_OE

BYPASS SELA1 SELA0 SELB1 SELB0 RES1 RES0

X_OUT

33pF 27pF

V

CCO_B

V

DDO_A

QA_C

QB0

QB1

QA

125MHz

312.5MHz

36Ω

Z

= 50Ω

0

Z0 = 50Ω

= 50Ω

Z

0

Z0 = 50Ω

Z

= 50Ω

0

Z0 = 50Ω

50Ω

(V

ASIC

CC

ASIC

CC

ASIC

CC

- 2V)

MAX3679A

+3.3V, Low-Jitter Crystal to LVPECL Clock Generator

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VCC= +3.0V to +3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise noted.) (Notes 1, 2, and 3)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage Range VCC, V

CCA

,

V

DDO_A

, V

CCO_A

, V

CCO_B

................................-0.3V to +4.0V

Voltage Range at REF_IN, IN_SEL,

SELA[1:0], SELB[1:0], RES[1:0], QAC_OE, QA_OE, QB0_OE, QB1_OE,

MR, BYPASS ..........................................-0.3V to (V

CC

+ 0.3V)

Voltage Range at X_IN Pin ...................................-0.3V to +1.2V

Voltage Range at GNDO_A...................................-0.3V to +0.3V

Voltage Range at X_OUT ............................-0.3V to (V

CC

- 0.6V)

Current into QA_C ...........................................................±50mA

Current into QA, QA, QB0, QB0, QB1, QB1 .....................-56mA

Continuous Power Dissipation (T

A

= +70°C)

32-Pin TQFN (derate 34.5mW/°C above +70°C) .......2759mW

Operating Junction Temperature Range...........-55°C to +150°C

Storage Temperature Range .............................-65°C to +160°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Power-Supply C urrent ICC (Note 4) 77 100 mA

CONTROL INPUT CHARACTERISTICS (SELA[1:0], SELB[1:0], IN_SEL, QAC_OE, QA_OE, QB1_OE, QB0_OE, MR, BYPASS Pins)

Input Capacitance C

Input Pulldown Resistor R

Input Logic Bia s Resistor R

Input Pullup Resistor R

LVPECL OUTPUT SPECIFICATIONS (QA, QA, QB0, QB0, QB1, QB1 Pins)

Output High Voltage V

Output Low Voltage V

Peak-to-Peak Output-Voltage Swing (Single-Ended)

Cloc k Output Ris e/Fall Time 20% to 80% (Note 2) 200 350 600 ps

Output Duty-Cycle Distortion

LVCMOS/LVTTL INPUT SPECIFICATIONS (SELA[1:0], SELB[1:0], IN_SEL, QAC_OE, QA_OE, QB1_OE, QB0_OE, MR, BYPASS Pins)

Input-Voltage High VIH 2.0 V

Input-Voltage Low V

2 pF

IN

PULLDOWN

BIAS

PULLUP

OH

OL

Pin MR 75 k

Pins SELA[1:0], SELB[1:0], QB0_OE 50 k

Pins QAC_OE, QA_OE, QB1_OE, IN_SEL,

BYPASS

TA = 0°C to +85°C

TA = -40°C to 0°C

TA = 0°C to +85°C

TA = -40°C to 0°C

(Note 2) 0.6 0.72 0.9 V

PLL enabled 48 50 52

PLL bypassed (Note 5) 40 50 60

0.8 V

IL

75 k

V

-

CC

1.13

V

CC

1.18

V

CC

1.85

V

CC

1.90

-

VCC -

0.98

VCC -

1.7

VCC -

0.83

VCC -

0.83

VCC -

1.55

VCC -

1.55

V

P-P

%

MAX3679A

+3.3V, Low-Jitter Crystal to LVPECL

Clock Generator

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VCC= +3.0V to +3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise noted.) (Notes 1, 2, and 3)

Note 1: A series resistor of up to 10.5Ω is allowed between VCCand V

CCA

for filtering supply noise when system power-supply

tolerance is V

CC

= 3.3V ±5%. See Figure 2.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input High Current I

Input Low Current I

REF_IN SPECIFICATIONS (Input DC- or AC-Coupled)

Reference Clock Frequenc y

Input-Voltage High VIH 2.0 V

Input-Voltage Low V

Input High Current I

Input Low Current I

Reference Clock Duty Cycle PLL enab led 30 70 %

Input Capacitance 2.5 pF

QA_C SPECIFICATIONS

Output High Voltage VOH QA_C sourcing 12mA 2.6 V

Output Low Voltage V

Output Rise/Fall Time (Notes 3, 6) 250 500 1000 ps

Output Duty-Cycle Distortion

Output Impedance 14 

CLOCK OUTPUT AC SPECIFICATIONS

VCO Frequency Range 625 MHz

Random Jitter (Note 7) RJ

Deterministic Jitter Due to Supply Noise

Spurs Induced by Power-Supply Noise (Note s 7, 9, 10)

Nonharmonic and Subharmonic Spurs

Output Skew

Clock Output SSB Phase Noise at 125MH z (Note 11)

IH

IL

IH

IL

OL

RMS

VIN = V

CC

VIN = 0V -80 μA

PLL enabled 25

PLL bypassed 320

0.8 V

IL

VIN = V

CC

VIN = 0V -240 μA

QA_C sink ing 12mA 0.4 V

PLL enabled 42 50 58

PLL bypassed (Note 5) 40 60

12kHz to 20MHz 0.36 1.0

1.875MHz to 20MHz 0.14

LVPECL o utput (Notes 7, 8, 9) 5.0 ps

LVPECL o utput -59

LVCMOS output -47

-70 dBc

Between QB0 and QB1 15

Between QA and QB0 or QB1, PECL outputs

f = 1kHz -124

f = 10kHz -125

f = 100kHz -130

f = 1MHz -145

f > 10MH z -153

80 μA

MHz

240 μA

%

ps

RMS

P-P

dBc

20

ps

dBc/Hz

MAX3679A

+3.3V, Low-Jitter Crystal to LVPECL Clock Generator

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VCC= +3.0V to +3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise noted.) (Notes 1, 2, and 3)

Figure 1. LVCMOS Output Measurement Setup

Note 2: Guaranteed up to 320MHz for LVPECL output. Note 3: Guaranteed up to 160MHz for LVCMOS output. Note 4: All outputs enabled and unloaded. IN_SEL set high. Note 5: Measured with crystal or AC-coupled, 50% duty-cycle signal on REF_IN. Note 6: Measured using setup shown in Figure 1 with V

CC

= 3.3V ±5%.

Note 7: Measured with crystal source. Note 8: Total TIE including random and deterministic jitter. Measured with Agilent DSO81304A 40GS/s real-time oscilloscope

using 2M sample record length.

Note 9: Measured with 40mV

P-P

, 100kHz sinusoidal signal on the supply.

Note 10: Measured at 156.25MHz output. Note 11: Measured with 25MHz crystal or 25MHz reference clock at LVCMOS input with a slew rate of 0.5V/ns or greater.

MAX3679A

QA_C

36Ω 499Ω

4.7pF

0.1μF

OSCILLOSCOPE

Z0 = 50Ω

50Ω