Rainbow Electronics MAX3673 User Manual
MAX3673
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
________________________________________________________________
Maxim Integrated Products
1
19-4442; Rev 0; 2/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
General Description
The MAX3673 is a low-jitter frequency synthesizer that
accepts two reference clock inputs and generates nine
phase-aligned outputs. The device features 40kHz jitter
transfer bandwidth, 0.3ps
RMS
(12kHz to 20MHz) integrated phase jitter, and best-in-class power-supply
noise rejection (PSNR), making it ideal for jitter cleanup, frequency translation, and clock distribution in wireless base-station applications.
The MAX3673 operates from a single +3.3V supply and
typically consumes 400mW. The IC is available in an
8mm x 8mm, 56-pin TQFN package, and operates from
-40°C to +85°C.
Applications
3G Wireless Base Stations
Frequency Translation
Jitter Cleanup
Clock Distribution
Features
♦ Two Reference Clock Inputs: LVPECL
♦ Nine Phase-Aligned Clock Outputs: LVPECL
♦ Input Frequencies: 61.44MHz,122.88MHz,
245.76MHz, 307.2MHz
♦ Output Frequencies: 61.44MHz, 122.88MHz,
153.6MHz, 245.76MHz, 307.2MHz
♦ Low-Jitter Generation: 0.3ps
RMS
(12kHz to 20MHz)
♦ Clock Failure Indicator for Both Reference Clocks
♦ External Feedback Provides Zero-Delay Capability
♦ Low Output Skew: 20ps Typical
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX3673ETN+ -40°C to +85°C 56 TQFN-EP*
SIGNAL QUALIFIER
AND
LOCK DETECT
POWER-ON
RESET
(POR)
IN0FAIL
IN1FAIL
LOCK
REFCLK0
REFCLK0
FB_INFB_SEL FB_IN
REFCLK1
REFCLK1
MR
0
1
1
0
DIV M
DMSEL_CLK
DA
DB
PFD CP
DIV N
DIV A
DIV B
VCO
2.457GHz61.44MHz
OUTA2
OUTA2
OUTA1
OUTA1
OUTA3
OUTA3
OUTA0
OUTB_EN
OUTA0
OUTA_ENPLL_BYPASS
1
0
10
OUTB3
OUTB3
OUTB2
OUTB2
OUTB4
OUTB4
OUTB1
OUTB1
OUTB0
OUTB0
C
PLL
0.1μF
C
REG
0.22μF
MAX3673
Functional Diagram
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
Pin Configuration and Typical Application Circuits appear at
end of data sheet.
MAX3673
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, TA= -40°C to +85°C, C
PLL
= 0.1µF, C
REG
= 0.22µF. Typical values are at VCC= +3.3V, TA= +25°C, unless
otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage Range (VCC, VCC_VCO)..............-0.3V to +4.0V
LVPECL Output Current (OUTA[3:0],
, OUTB[4:0], ) .............................-56mA
All Other Pins..............................................-0.3V to (V
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
56-Pin TQFN (derate 47.6mW/°C above 70°C)..........3808mW
Operating Junction Temperature (T
J
)................-55°C to +150°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
O
UTA[ : ]30
OUTB[ : ]40
Supply Current ICC LVPECL outputs unt ermin ated 120 175 mA
POWER-ON RESET
VCC Rising (Note 1) 2.55 V
VCC Falling (Note 1) 2.45 V
LVCMOS/LVTTL INPUTS (MR, SEL_CLK, PLL_BYPAS S, FB_SEL)
Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V
Input High Current IIH VIN = VCC 75 μA
Input Low Current IIL VIN = GND -75 μA
LVCMOS/LVTTL OUTPUTS (IN0FAIL, IN1FAIL, LOCK)
Output High Voltage VOH IOH = -8mA 2.4 V
Output Low Voltage VOL IOL = +8mA 0.4 V
LVPECL INPUTS (REFCLK0, REFCLK0, REFCLK1, REFCLK1, FB_IN, FB_IN) (Note 2)
Input High Voltage VIH
Input Low Voltage V
Input Bias Voltage V
Differentia l-Input Swing 0.15 1.9 V
Differentia l-Input Impedance > 40 k
Common-Mode Input Impedance > 14 k
Input Capacitance 1.5 pF
Input Current VIH = VCC - 0.7V, VIL = VCC - 2.0V -100 +100 μA
Input Inrush Current When Power
is Off (Steady State)
Input Inrush Current Over shoot
When Power i s Off
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IL
CMI
I
DC
I
OVERSHOOT
(Notes 3, 4) 8 mA
(Notes 3, 4) 6 mA
VCC -
2.0
VCC -
1.8
V
VCC -
1.34
V
-
CC
0.7
V
V
P-P
MAX3673
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +3.0V to +3.6V, TA= -40°C to +85°C, C
PLL
= 0.1µF, C
REG
= 0.22µF. Typical values are at VCC= +3.3V, TA= +25°C, unless
otherwise noted.)
REFERENCE CLOCK INPUTS (REFCLK0, REFCLK0, REFCLK1, REFCLK1)
Reference Clock Frequenc y f
Reference Clock Frequenc y
Tolerance
Reference Clock Duty Cycle 40 60 %
Reference Clock Amplitude
Detection Assert Threshold
LVPECL OUTPUTS (OUTA[3:0],
Output High Voltage V
Output Low Voltage V
Differentia l-Output Swing 1.1 1.45 1.8 V
Output Current When Disabled VO = VCC - 2.0V to VCC - 0.7V 130 μA
Output Frequency f
Output Rise/Fall Time tR, tF 20% to 80% (Note 8) 150 500 ps
Output Duty Cycle
Output-to-Output Skew t
OTHER AC ELECTRICAL SPECIFICATIONS
PLL Jitter Transfer Bandwidth 40 kH z
Jitter Peaking 0.1 dB
PFD Compare Frequency 61.44 MHz
VCO Center Frequency 2.457 GHz
Random Jitter Generation Integrated 12kH z to 20MH z (Notes 5, 8) 0.3 1.0 ps
Determinisitic Jitter Caused by
Power-Supply Noise
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REF
-200 +200 ppm
V
DT
OUTA[3:0],
OH
OL
OUT
SKEW
(Note 10) 5 ps
Table 1 MHz
Differentia l swing (Notes 5, 6) 200 mV
OUTB[4:0],
OUTB[4:0])
PLL_BYP ASS = 0 48 52
PLL_BYP ASS = 1 (Note 9) 45 55
Within output bank 20
All outputs 40
(Note 7)
VCC -
1.13
VCC -
1.85
VCC -
0.98
VCC -
1.70
Table s
2, 3
VCC -
0.83
VCC -
1.55
MHz
P-P
V
V
P-P
%
ps
RMS
P-P
Frequency Difference Between
Reference Clock and VCO
Within Which the PLL i s
Considered in Lock
Frequency Difference Between
Reference Clock and VCO at
Which the PLL is Con sidered
Out-of-Lock
PLL Lock Time t
500 ppm
800 ppm
Figure 2 600 μs
LOCK
MAX3673
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +3.0V to +3.6V, TA= -40°C to +85°C, C
PLL
= 0.1µF, C
REG
= 0.22µF. Typical values are at VCC= +3.3V, TA= +25°C, unless
otherwise noted.)
Note 1: During the power-on-reset time, the LVPECL outputs are held to logic-low (OUTxx = low, OUTxx = high). See the
Power-
On-Reset (POR)
section for more information.
Note 2: LVPECL inputs can be AC- or DC-coupled.
Note 3: For hot-pluggable purposes, the device can receive LVPECL inputs when no supply voltage is applied. Measured with
V
CC
pins connected to GND. See Figure 1.
Note 4: Measured with LVPECL input (V
IH
, VIL) as specified.
Note 5: Measured using reference clock input with 550ps rise/fall time (20% to 80%).
Note 6: When input differential swing is below the specified threshold, a clock failure is declared. See Figure 4.
Note 7: LVPECL outputs terminated 50Ω to V
TT
= VCC- 2V.
Note 8: Guaranteed by design and characterization.
Note 9: Measured with 50% duty cycle at reference clock input.
Note 10: Measured with 50mV
P-P
sinusoidal noise on the power supply, f
NOISE
= 100kHz.
Note 11: Measured with f
REFCLKx
= f
FB_IN
and matched slew rates.
Master Reset (MR) Minimum
Pulse Width
Propagation Delay from Input to
FB_IN
Propagation Delay from Input to
Any Output
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
100 ns
FB_SEL = 1 (Notes 8, 11) -120 +120 ps
PLL_BYP ASS = 1 1.0 ns
MAX3673
Low-Jitter Frequency Synthesizer
with Selectable Input Reference
_______________________________________________________________________________________ 5
Figure 1. LVPECL Input Inrush Current
REFCLK0
REFCLK1
OUTxx
IN0FAIL
IN1FAIL
LOCK
HIGH
SEL_CLK
LOW
V
CC
POWER-ON-RESET (~ 20μs)
HIGH
t
LOCK
(~ 600μs)
PLL LOCKED TO REFCLK0
Figure 2. Power-Up, PLL Locks to REFCLK0
INRUSH CURRENT
(mA)
I
OVERSHOOT
I
DC
t
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