Rainbow Electronics MAX3627 User Manual

MAX3627

+3.3V, Low-Jitter, Precision Clock

Generator with Multiple Outputs

________________________________________________________________

Maxim Integrated Products

1

19-4567; Rev 0; 4/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

General Description

The MAX3627 is a low-jitter, precision clock generator optimized for network applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) to generate high-frequency clock outputs for Ethernet applications.

Maxim’s proprietary PLL design features ultra-low jitter (0.4ps

RMS

) and excellent power-supply noise rejection

(PSNR), minimizing design risk for network equipment.

The MAX3627 contains seven LVDS outputs and one LVCMOS output. The output frequencies are selectable among 125MHz, 156.25MHz, and 312.5MHz.

Applications

Ethernet Networking Equipment

Features

♦ Crystal Oscillator Interface: 25MHz ♦ OSC_IN Interface

PLL Enabled: 25MHz PLL Disabled: 20MHz to 320MHz

♦ Outputs

One LVDS Output at 125MHz/156.25MHz/

312.5MHz (Selectable with FSELA)

Six LVDS Outputs at 125MHz/156.25MHz/

312.5MHz (Selectable with FSELB)

One LVCMOS Output at 125MHz/156.25MHz

(Selectable with FSELB)

♦ Low Phase Jitter

0.4ps

RMS

(12kHz to 20MHz)

0.2ps

RMS

(1.875MHz to 20MHz)

♦ Excellent PSNR: -64dBc at 156.25MHz with

40mV

P-P

Supply Noise at 100kHz

♦ Operating Temperature Range: 0°C to +70°C

THIN QFN

(5mm × 5mm)

TOP VIEW

29

30

28

27

12

11

13

Q0

Q1

V

DDO_DIFF

Q2

14

Q0

Q7

Q6

GND

V

DDO_DIFF

Q5

12

FSELA

4567

2324 22 20 19 18

OSC_IN

X_IN

Q4

V

DDO_DIFF

Q3

GND

V

DDO_SE

3

21

31

10

X_OUT

Q3

32

9

GND

V

DDA

26

15

FSELB

PLL_BP

25

16

OE

Q2

8

17

V

DD

+

Q5

*EP

*EXPOSED PAD CONNECTED TO GROUND.

MAX3627

Pin Configuration

Ordering Information

Typical Operating Circuit

+

Denotes a lead(Pb)-free/RoHS-compliant package.

*

EP = Exposed pad.

10.5Ω

10μF

0.01μF

33pF

25MHz

= 18pF)

(C

L

27pF

V

DDA

OPEN

OSC_IN

OEOPEN

X_OUT

X_IN

V

DD

PLL_BP

FSELAGND, OPEN, OR V

DD

FSELBGND, OPEN, OR V

DD

GND

+3.3V ±5%

0.1μF

0.1μF0.1μF

V

DDO_DIFF

DD

MAX3627

V

DDO_SE

125MHz/156MHz/312.5MHz

Q0

125MHz/156MHz/312.5MHz

Q1

125MHz/156MHz/312.5MHz

Q2

125MHz/156MHz/312.5MHz

Q3

125MHz/156MHz/312.5MHz

Q4

125MHz/156MHz/312.5MHz

Q5

125MHz/156MHz/312.5MHz

Q6

Q7

33Ω

Z0 = 50Ω

Z

= 50Ω

0

Z0 = 50Ω

Z

= 50Ω

0

Z0 = 50Ω

= 50Ω

Z

0

Z0 = 50Ω

Z

= 50Ω

0

Z0 = 50Ω

Z

= 50Ω

0

Z0 = 50Ω

125MHz/156.25MHz

Z0 = 50Ω

100Ω

ASIC

PART TEMP RANGE PIN-PACKAGE

MAX3627CTJ + 0°C to +70°C 32 TQFN-EP*

MAX3627

+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD= +3.0V to +3.6V, TA= 0°C to +70°C, unless otherwise noted. Typical values are at VDD= +3.3V, TA= +25°C, unless otherwise noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is bypassed, PLL_BP = low.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Supply Voltage Range at VDD, V

DDA

,

V

DDO_SE

, V

DDO_DIFF

................................................

-0.3V to +4.0V

Voltage Range at Q0, Q0, Q1, Q1, Q2, Q2,

Q3, Q3, Q4, Q4, Q5, Q5, Q6, Q6, Q7, PLL_BP, FSELA, FSELB, OE, OSC_IN ...-0.3V to (V

DD

+ 0.3V)

Voltage Range at X_IN ..........................................-0.3V to +1.2V

Voltage Range at X_OUT

.................................

-0.3V to (VDD- 0.6V)

Continuous Power Dissipation (T

A

= +70°C)

32-Pin TQFN-EP (derate 34.5mW/°C above +70°C)..2759mW

Operating Junction Temperature Range...........-55°C to +150°C

Storage Temperature Range .............................-65°C to +160°C

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Power-Supply Current (Note 2) I

LVDS OUTPUTS (Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4, Q5, Q5, Q6, Q6)

Output High Voltage V

Output Low Voltage V

Differentia l Output Voltage Ampl itude

Change in Magnitude of Differentia l Output for Complementar y State s

Output Offset Voltage VOS 1.125 1.275 V

Change in Magnitude of Output Offset Voltage for Complementar y State s

Differentia l Output Impedance 80 105 140 

Output Current

Cloc k Output Ri se/Fall Time tr, tf 20% to 80%, RL = 100 100 200 330 ps

Output Duty-Cycle Distortion

LVCMOS/LVTTL OUTPUT (Q7)

Output Frequency 160 MHz

Output High Voltage VOH IOH = -12mA 2.6 VDD V

Output Low Voltage VOL IOL = 12mA 0.4 V

Output Rise/Fall Time tr, tf 20% to 80% at 125MHz (Note 5) 0.15 0.4 0.8 ns

Output Duty-Cycle Distortion

Output Impedance R

PLL enabled 190 256

PLL bypassed 175

1.475 V

0.925 V

OL

| Figure 1 250 400 mV

| 25 mV

OD

| 25 mV

OS

Shorted together 5

Short to ground (Note 3) 8

PLL enabled 48 50 52

PLL bypassed (Note 4) 46 50 54

PLL enabled 46 50 54

PLL bypassed (Note 4) 45 50 55

15 

|V

|V

DD

OH

OD

OUT

mA

%

MAX3627

+3.3V, Low-Jitter, Precision Clock

Generator with Multiple Outputs

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +3.0V to +3.6V, TA= 0°C to +70°C, unless otherwise noted. Typical values are at VDD= +3.3V, TA= +25°C, unless otherwise noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is bypassed, PLL_BP = low.) (Note 1)

INPUT SPECIFICATIONS (FSELA, FSELB, PLL_BP, OE)

Input-Voltage High VIH 2.0 VDD V

Input-Voltage Low V

Input High Current I

Input Low Current I

LVCMOS/LVTTL INPUT SPECIFICATIONS (OSC_IN) (Note 6)

Input Clock Frequenc y

Input Amplitude Range (Note 7) 1.2 3.6 V

Input High Current IIH VIN = VDD 80 μA

Input Low Current IIL VIN = 0 -80 μA

Reference Clock Dut y Cycle 40 50 60 %

Input Capacitance CIN 1.5 pF

CLOCK OUTPUT AC SPECIFICATIONS

VCO Center Frequency 625 MHz

Output Frequency with PLL Enabled (Q0)

Output Frequency with PLL Enabled (Q1 to Q7)

Output Frequency with PLL Disabled

Integrated Phase Jitter RJ

Power-Supply Noise Rejection (Note 11)

Deterministic Jitter Due to Supply Noise (Note 12)

Nonharmonic and Subharmonic Spurs

LVDS Clock Output SSB Phase Noise at 125MHz (Note 14)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

0 0.8 V

IL

IH

IL

RMS

PSNR

VIN = V

DD

VIN = 0 -80 μA

PLL enabled 25

PLL bypassed 20 320

FSELA = GND 125

FSELA = VDD 156.25

FSELA = high-Z 312.5

FSELB = GND 125

FSELB = VDD 156.25

FSELB = high-Z (Note 8) 312.5

LVDS outputs 20 320

LVCMOS output 20 160 12kHz to 20MHz, PLL_BP = high (Note 9) 0.4 1.0 12kHz to 20MHz, PLL_BP = high-Z

(Note 10)

LVDS outputs -64

LVCMOS output -49

LVDS outputs 2.5

LVCMOS output 18

(Note 13) -70 dBc

f = 100Hz -115 f = 1kHz -124 f = 10kHz -126 f = 100kHz -130 f = 1MHz -143 f > 10MH z -149

80 μA

MHz

ps

0.4

RMS

dBc

ps

P-P

dBc/Hz

MAX3627

+3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +3.0V to +3.6V, TA= 0°C to +70°C, unless otherwise noted. Typical values are at VDD= +3.3V, TA= +25°C, unless otherwise noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled, PLL_BP = high-Z or high. When PLL is bypassed, PLL_BP = low.) (Note 1)

Note 1: A series resistor of up to 10.5Ω is allowed between V

DD

and V

DDA

for filtering supply noise when system power-supply tol-

erance is V

DD

= 3.3V ±5%. See Figure 4.

Note 2: All outputs unloaded. Note 3: The current when an LVDS output is shorted to ground is the steady-state current after the detection circuitry has settled. It

is expected that the LVDS output short to ground condition is short-term only.

Note 4: Measured with OSC_IN input with 50% duty cycle. Note 5: Measured with a series resistor of 33Ω to a load capacitance of 3.0pF. See Figure 2. Note 6: The OSC_IN input can be DC- or AC-coupled. Note 7: Must be within the absolute maximum rating of V

DD

+ 0.3V.

Note 8: AC characteristics of LVCMOS output (Q7) are only guaranteed up to 160MHz. Note 9: Measured with 25MHz crystal (with OSC_IN left open). Note 10: Measured with 25MHz reference clock applied to OSC_IN. Note 11: Measured with 40mV

P-P

sinusoidal signal on the supply at 100kHz. For LVDS the output frequency is 156.25MHz; for

LVCMOS the output frequency is 125MHz. Measured with a 10.5Ω resistor between V

DD

and V

DDA

.

Note 12: Parameter calculated based on PSNR. Note 13: Measurement includes XTAL oscillator feedthrough, crosstalk, intermodulation spurs, etc. Note 14: Measured with 25MHz XTAL oscillator.

Figure 1. Driver Output Levels

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

f = 100Hz -113

LVCMOS Clock Output SSB Phase Noise at 125MHz (Note 14)

f = 1kHz -123 f = 10kHz -126 f = 100kHz -130 f = 1MHz -144

f > 10MH z -151

dBc/Hz

Qx

= 100Ω

Qx

SINGLE-ENDED OUTPUT

Qx

R

L

Qx

IV

I

OD

V

OD

V

OH

V

OS

V

OL

Qx - Qx

V

= 2IVODI

OD

DIFFERENTIAL OUTPUT

P-P

0