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MAX3625В
User Manual
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Rainbow Electronics MAX3625В User Manual

MAX3625B
Low-Jitter, Precision Clock
Generator with Three Outputs
________________________________________________________________
Maxim Integrated Products
1
19-4978; Rev 0; 10/09
EVALUATION KIT
AVAILABLE
General Description
The MAX3625B is a low-jitter, precision clock generator optimized for networking applications. The device inte­grates a crystal oscillator and a phase-locked loop (PLL) clock multiplier to generate high-frequency clock outputs for Ethernet, 10G Fibre Channel, and other net­working applications.
Maxim’s proprietary PLL design features ultra-low jitter and excellent power-supply noise rejection, minimizing design risk for network equipment.
The MAX3625B has three LVPECL outputs. Selectable output dividers and a selectable feedback divider allow a range of output frequencies.
Applications
Ethernet Networking Equipment
Fibre Channel Storage Area Network
Features
♦ Crystal Oscillator Interface: 24.8MHz to 27MHz
♦ CMOS Input: Up to 320MHz
♦ Output Frequencies
Ethernet: 62.5MHz, 125MHz, 156.25MHz, 312.5MHz 10G Fibre Channel: 159.375MHz, 318.75MHz
♦ Low Jitter
0.14ps
RMS
(1.875MHz to 20MHz)
0.36ps
RMS
(12kHz to 20MHz)
♦ Excellent Power-Supply Noise Rejection
♦ No External Loop Filter Capacitor Required
Ordering Information
CRYSTAL
OSCILLATOR
LVCMOS
DIVIDERS:
M = 24, 25 NA = 10, 2, 4, 5 NB = 10, 2, 4, 5
REF_IN
X_IN
X_OUT
0
1
0
1
PFD FILTER
RESET
RESET
RESET LOGIC/POR
DIVIDER
M
RESET
DIVIDER
NB
DIVIDER
NA
VCO
620MHz TO 648MHz
LVPECL BUFFER
QA
QA_OE
QA
LVPECL BUFFER
QB1
QB1
LVPECL BUFFER
QB0
FB_SEL
QB_OE
QB0
SELB[1:0]
SELA[1:0]IN_SEL
BYPASSMR
MAX3625B
SELA[1:0]
RESET
SELB[1:0]
FB_SEL
BYPASS
33pF
27pF
Block Diagram
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
Typical Application Circuit appears at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX3625BEUG+ -40°C to +85°C 24 TSSOP-EP*
MAX3625B
Low-Jitter, Precision Clock Generator with Three Outputs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC= +3.0V to +3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C, unless other­wise noted.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Supply Voltage Range VCC, V
CCA
,
V
CCO_A
, V
CCO_B
..............................................-0.3V to +4.0V
Voltage Range at REF_IN, IN_SEL,
FB_SEL, SELA[1:0], SELB[1:0],
QA_OE, QB_OE, MR, BYPASS ..............-0.3V to (V
CC
+ 0.3V)
Voltage Range at X_IN ..........................................-0.3V to +1.2V
Voltage Range at X_OUT ............................-0.3V to (V
CC
- 0.6V)
Current into QA, QA, QB0, QB0, QB1, QB1 .....................-56mA
Continuous Power Dissipation (T
A
= +70°C)
24-Pin TSSOP (derate 26.7mW/°C above +70°C) ..2133.3mW
Operating Junction Temperature Range...........-55°C to +150°C
Storage Temperature Range .............................-65°C to +160°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Power-Supply Current (Note 3) I
CONTROL INPUT CHARACTERISTICS (SELA[1:0], SELB[1:0], FB_SEL, IN _SEL, QA_OE, QB_OE, MR, B Y PA SS Pins)
Input Capacitance C
Input Pulldown Resistor R
Input Logic Bia s Resistor R
Input Pullup Resistor R
LVPECL OUTPUTS (QA, QA, QB0, QB0, QB1, QB1 Pins)
Output High Voltage V
Output Low Voltage V
Peak-to-Peak Output-Voltage Swing (Single-Ended)
Cloc k Output Rise/Fall Time 20% to 80% (Note 2) 200 350 600 ps
Output Duty-Cycle Distortion
LVCMOS/LVTTL INPUTS (SELA[1:0], SELB[1:0], FB_SEL, IN _SEL, QA_OE, QB_OE, MR, B Y PA SS Pins)
Input-Voltage High VIH 2.0 V
Input-Voltage Low V
Input High Current I
Input Low Current I
CC
PULLDOWN
BIAS
PULLUP
OH
OL
IH
IN_SEL = high 72 98
IN_SEL = low 74
2 pF
IN
Pins MR, FB_SEL 75 k
Pins SELA[1:0], SELB[1:0] 50 k
Pins QA_OE, QB_OE, IN_SEL, BYPASS 75 k
(Note 2) 0.6 0.72 0.9 V
PLL enabled 48 50 52
PLL bypassed (Note 4) 45 50 55
0.8 V
IL
VIN = V
CC
VIN = 0V -80 μA
IL
VCC -
1.18
VCC -
1.90
VCC -
0.98
VCC -
1.7
80 μA
VCC -
0.83
VCC -
1.55
mA
V
V
P-P
%
MAX3625B
Low-Jitter, Precision Clock
Generator with Three Outputs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC= +3.0V to +3.6V, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C, unless other­wise noted.) (Notes 1, 2)
Note 1: A series resistor of up to 10.5Ω is allowed between VCCand V
CCA
for filtering supply noise when system power-supply
tolerance is V
CC
= 3.3V ±5%. See Figure 1.
Note 2: LVPECL outputs guaranteed up to 320MHz. Note 3: All outputs enabled and unloaded. Note 4: Measured with a crystal (see Table 4) or an AC-coupled, 50% duty-cycle signal on REF_IN. Note 5: Measured with crystal source, see Table 4. Note 6: Measured using setup shown in Figure 1. Note 7: Measured with 40mV
P-P
, 100kHz sinusoidal signal on the supply.
Note 8: Measured at 156.25MHz output. Note 9: Calculated based on measured spurs induced by power-supply noise (refer to Application Note 4461:
HFAN-04.5.5:
Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers
).
Note 10: Measured with 25MHz crystal or 25MHz reference clock at REF_IN with a slew rate of 0.5V/ns or greater.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REF_IN SPECIFICATIONS (Input DC- or AC-Coupled)
Reference Clock Frequenc y
Input-Voltage High VIH 2.0 V
Input-Voltage Low V
Input High Current I
Input Low Current I
Reference Clock Duty Cycle PLL enabled 30 70 %
Input Capacitance 2.5 pF
CLOCK OUTPUT AC SPECIFICATIONS
VCO Frequency Range 620 648 MHz
Random Jitter (Note 5) RJ
Spurs Induced by Power-Supply Noise
Determin istic Jitter Induced by Power-Supply Noise
Nonharmonic and Subharmonic Spurs
Output Skew Between any output pair 5 ps
Clock Output SSB Phase Noise at 125MH z (Note 10)
IH
RMS
PLL enabled 24.8 27.0
PLL bypassed 320
0.8 V
IL
VIN = V
CC
VIN = 0V -240 μA
IL
12kHz to 20MHz 0.36 1.0
1.875MHz to 20MHz 0.14
(Notes 6, 7, 8) -60 dBc
(Note 9) 5.6 ps
-70 dBc
f = 1kHz -124
f = 10kHz -127
f = 100kHz -131
f = 1MHz -145
f > 10MH z -153
240 μA
MHz
ps
RMS
P-P
dBc/Hz
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