The MAX3580 fully integrated, direct-conversion TV tuner
is designed for Digital Video Broadcasting-Terrestrial
(DVB-T) applications. The integrated tuner covers a
170MHz to 230MHz input frequency range for the VHF-III
band and 470MHz to 878MHz for the UHF band.
The MAX3580 direct-conversion tuner integrates an RF
input switch and a multiband tracking filter, allowing
low-power tuner-on-board applications without the cost
and power-dissipation issues of dual-conversion tuner
solutions. The zero-IF architecture eliminates the need
for SAW filters by providing baseband I and Q outputs
directly to the demodulator. In addition, DC-offset cancellation is implemented on-chip using a mixed-signal
architecture to improve the second-order distortion performance and the dynamic range of the downstream
digitizer and demodulator.
The MAX3580 features dynamic gain control of more
than 76dB and a typical midband noise figure of 4.7dB
referred to the LNA input. The VCO architecture optimizes both in-band and wideband phase noise for
OFDM applications where sensitivity to both 1kHz
phase noise and wideband phase noise related to
strong adjacents can be a problem.
The MAX3580 communicates using a 2-wire serial bus.
The device operates from a typical +3.3V power supply
and dissipates 650mW. The MAX3580 is available in a
small 32-pin thin QFN package (5mm x 5mm) with an
exposed paddle. Electrical performance is guaranteed
over the extended -40°C to +85°C temperature range.
(MAX3580 EV kit, VCC= +3.1V to +3.5V, GND = 0V, BB_AGC = RF_AGC = +2.85V, RF input terminated into a 75Ω load, BBI_ and
BBQ_ are open, no input signal, VCO active, registers set according to the specified default register conditions, T
A
= -40°C to
+85°C, unless otherwise specified. Typical values are at V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCCto GND...........................................................-0.3V to +3.6V
SDA, SCL, ADDR2, MUX, REF_BUFF,
BB_AGC, RF_AGC to GND ................................-0.3V to +3.6V
All Other Pins to GND ..............................-0.3V to (+V
CC
+ 0.3V)
RF Input Power ...............................................................+10dBm
Operating Temperature Range ...........................-40°C to +85°C
(MAX3580 EV kit, VCC= +3.1V to +3.5V, GND = 0V. RF_AGC = BB_AGC = +2.85V, RF input terminated into a 75Ω load, BBI_ and
BBQ_ loaded by R
L
greater than 2kΩ and CLless than 10pF, VCO active, registers are set according to the recommended default
register conditions, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at VCC= +3.3V, TA= +25°C, unless otherwise
noted.) (Note 1)
Note 1: Min and Max limits are guaranteed by test above TA= +25°C and are guaranteed by design and characterization at
T
A
= -40°C. The default register settings are not production tested. Load registers no sooner than 100µs after power-up.
Note 2: The specified overall voltage gain is suitable to amplify -93dBm to -20dBm to 1V
P-P
at the baseband output.
Note 3: Guaranteed by design characterization over the specified operating conditions. Not production tested.
Note 4: BB_AGC adjusted for gain = 72dB with RF_AGC at 2.85V.
Note 5: Two tones at a) 230MHz and 431MHz with IM measured at 201MHz and b) 230MHz and 701MHz with IM measured at
471MHz.
Note 6: Two tones at 499MHz and 689MHz with IM measured at 879MHz.
Note 7: IM3 measured with two tones within the adjacent channel. Production tested at 72dB of gain with two tones at a)
205.75MHz and 210.5MHz with IM measured at 201MHz and b) 475.25MHz and 479.5MHz with IM measured at
471MHz. Production tested at 49dB of gain with two tones at 475.25MHz and 479.5MHz with IM measured at 471MHz.
Note 8: Measured at RF = 171MHz with harmonics at 511MHz (3rd harmonic) and 851MHz (5th harmonic).
Note 9: Delay of 2ns equal 2.74° phase error.
Note 10: UHF rolloff of 4dB in addition to gain flatness specification.
Note 11: Production tested at V
CC
= +3.5V to limits of 1.7V ±0.1V.
Rejection Ratio
DC Output VoltageV
Output DC OffsetBB_AGC = 2.85V -70 +70 mV
Baseband Highpass CutoffProgrammable 20 to 200 Hz
AGC Gain SlopeBB_AGC = 0.5V to 2.85V 14 35 dB/V
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Ratio of Passband to Stopband
Noise
At 5.25MHz (UHF mode) 23
At 4.75MHz (VHF mode) 23
At 13.25MHz (UHF mode) 63
At 11.75MHz (VHF mode) 62
At > 16.2MHz
CM
Common mode (Note 11) 0.485 x V
BB_AGC = 2.85V, 10kHz to 3.8MHz vs.
16.2MHz to 23.8MHz
84
V
CC
15dB
dB
DC
MIXER OVERLOAD DETECTOR (RSSI)Attack-Point Accuracy5.25MHz test tone±1dBAttack-Point Increment3-bit DAC1.5dB
The following is selected overall performance data for the
MAX3580 + digital demodulator.
Table 1 shows the typical overall performance as measured using the MAX3580 and one current production
DVB-T demodulator. This reference design is available
in NIM card form factor upon request.
MBRAI refers to standard MBRAI 04-102 IEC 62002-1
available from www.ansi.org.
NorDig refers to standard Unified 1.0.2 available from
www.nordig.org.
Modulation of wanted and interfering channel(s) is 8k
mode, 16 QAM, C/R = 3/4, GI = 1/4, sensitivity or
immunity Reference Bit Error Rate is 2 x 10e-4, unless
stated otherwise.
Table 1. Selected Typical MBRAI and NorDig Performance
TEST SCENARIOCOMMENTSSPEC MINIMUMMAX3580 TYPICAL
MBRAI S2Immunity/ACPR for N ±1 adjacent ch.29dB40dB
MBRAI S2Immunity/ACPR N ±2 alternate ch.40dB43dB
MBRAI L3Li near ity/c r ossm od . w i th N +2 and N +4 ch.40dB47dB
NorDig 16 QAM 2/3S ensi ti vi ty at channel 21 ( 470 M H z) -84.1dBm-85.1dBm
NorDig QPSK 1/2Sensitivity at channel 42 (642 MHz)-92.1dBm-94.8dBm
NorDig 64 QAM 7/8Sensitivity at channel 59 (778 MHz)-74.7dBm-76dBm
The MAX3580 includes thirteen write/read registers and
three read-only registers. See Table 2 for register configuration and the
Register Description
section. The
register configuration of Table 2 shows each bit name
and the bit usage information for all registers. “U”
labeled under each bit name indicates that the bit
value is user defined to meet specific application
requirements. A “0” or “1” indicates that the bit must be
set to the defined “0” or “1” value for proper operation.
Operation is not tested or guaranteed if these bits are
programmed to other values and is only for
factory/bench evaluation. For field use, always program
to the defined operational state. Note that all registers
must be written after and no earlier than 100µs after
device power-up.
The main bandgap can and will be shut down
once all other blocks are shut down (i.e., all bits in this
shutdown register and bits VCO_ in the VCO
Control Register and bits DC_MO_ in the DC
Offset Control Register are shut down).
SHDN_PD: Baseband Power Detector
0 = Enabled
1 = Disabled
SHDN_RF: RF LNA/VGA:
0 = Enabled
1 = Disabled
SHDN_MIX: I/Q Mixer and LO Drivers
0 = Enabled
1 = Disabled
SHDN_BB: Baseband Filters and VGA
0 = Enabled
1 = Disabled
SHDN_SYN: Fractional PLL
0 = Enabled
1 = Disabled
SHDN_REF: Controls the Crystal Oscillator Buffered
Output
0 = Enabled
1 = Disabled
The XTAL oscillator activation results from the
SHDN_SYN, SHDN_REF bits: If either one is on,
the XTAL oscillator runs. The XTAL oscillator is
shut down only if both bits are off.
VCO Control (Register Address 0x09)
VCO<1:0>: Selects 1 of 3 VCO Bands. 00 turns off
VCO block completely.
BS<2:0>: Selects 1 of 8 VCO Sub-Bands
VAS: VCO Band Autoselect
0 = VCO band select controlled by bits VCO<1:0>
1 = Controlled by autotuner
ADL: VCO ADC Latch Enable Bit
1 = Latches ADC value
0 = Default
ADE: Enable VCO Tune Voltage DAC Read
1 = Enables ADC read
0 = Default
Baseband Control (Register Address 0x0A)
PD_TH<2:0>: Detection Threshold for Baseband
Power Detector
BB_BW<3:0>: Baseband Filter Bandwidth. Optimum
values for 7MHz and 8MHz wide RF channels can
be taken from the ROM table.
DC Offset Control (Register Address 0x0B)
DC_TH<1:0>: DC Offset Correction Thresholds.
Keeps output within:
00 = Output within ±0.55V of balanced state
11 = Output within ±0.75V of balanced state
DC_SP<1:0>: DC Offset Correction Speed (or Highpass
Corner Frequency).
11 = Fast (~500Hz)
01 = Slow (~20Hz)
00 = Off/hold DAC values
DC_MO<1:0>: Mode of Operation
00 = Off
10/01 = Sets I/Q channel DACs direct from register
than 8’h00 (the system trim bits), it is possible that the
data going to the bias cells will be disturbed due to the
architecture of the fuse bank. This means the bias current could change while reading back fuse data.
1) Write 8’hXX to TFA. XX is the address of the fuse column you want to read.
2) Read 8’hXX from TFR. TFR is the Tracking Filter
Read Register.
3) Repeat steps 1 and 2 for other addresses.
2-Wire Serial Interface
The MAX3580 uses a 2-wire I2C*-compatible serial
interface consisting of a serial-data line (SDA) and a
serial-clock line (SCL). The serial interface allows communication between the MAX3580 and the master at
clock frequencies up to 400kHz. The master initiates a
data transfer on the bus and generates the SCL signal
to permit data transfer. The MAX3580 behaves as slave
devices that transfer and receive data to and from the
master. Pull SDA and SCL high with external pullup
resistors (1kΩ or greater) for proper bus operation.
One bit is transferred during each SCL clock cycle. A
minimum of nine clock cycles are required to transfer a
byte in or out of the MAX3580 (8 bits and an ACK/NACK).
The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is
high and stable are considered control signals (see the
START and STOP Conditions
section). Both SDA and
SCL remain high when the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condition (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high.
Acknowledge and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the master and the MAX3580 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccessful data transfer, the bus master must reattempt
communication at a later time.
Slave Address
The MAX3580 has a 7-bit slave address that must be
sent to the device following a START condition to initiate communication. The slave address is determined
by the state of the ADDR2 pin and is equal to
11000[ADDR2]0 (see Table 4). The eighth bit (R/W) following the 7-bit address determines whether a read or
write operation will occur.
The MAX3580 continuously awaits a START condition
followed by its slave address. When the device recognizes its slave address, it acknowledges by pulling the
SDA line low for one clock period; it is ready to accept
or send data depending on the R/W bit (Figure 1).
*Purchase of I2C components of Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a
license under the Philips I
2
C Patent rights to use these components in an I2C system, provided that the system conforms to the I2C
When addressed with a write command, the MAX3580
allows the master to write to a single register or to multiple successive registers.
A write cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/W = 0). The MAX3580 issues an
ACK if the slave address byte is successfully received.
The bus master must then send to the slave the
address of the first register it wishes to write to. If the
slave acknowledges the address, the master can then
write one byte to the register at the specified address.
Data is written beginning with the most significant bit.
The MAX3580 again issues an ACK if the data is successfully written to the register. The master can continue to write data to the successive internal registers with
the MAX3580 acknowledging each successful transfer,
or it can terminate transmission by issuing a STOP condition. The write cycle does not terminate until the master issues a STOP condition.
Figure 2 illustrates an example in which Registers 0
through 2 are written with 0x0E, 0xD8, and 0xE1,
respectively.
Read Cycle
When addressed with a read command, the MAX3580
allows the master to read back a single register or multiple successive registers.
A read cycle begins with the bus master issuing a
START condition followed by the 7 slave address bits
and a write bit (R/W = 0). The MAX3580 issues an ACK if
the slave address byte is successfully received. The bus
master must then send the address of the first register it
wishes to read. The slave acknowledges the address.
Then a START condition is issued by the master, followed by the 7 slave address bits and a read bit (R/W =
1). The MAX3580 issues an ACK if the slave address
byte is successfully received. The MAX3580 starts sending data MSB first with each SCL clock cycle. At the 9th
clock cycle, the master can issue an ACK, and continue
to read successive registers, or the master terminate the
transmission by issuing a NACK. The read cycle does
not terminate until the master issues a STOP condition.
Figure 3 illustrates an example in which Registers 0
through 2 are read back.
Figure 2. Example: Write Registers 0 through 2 with 0x0E, 0xD8 and 0xE1, respectively.
Figure 3. Example: Receive data from read registers.
The MAX3580 is designed to be suitable for operation
in the 170MHz to 230MHz VHF-III band and in the
470MHz to 878MHz UHF band.
RF Inputs
A switch selects either RFIN or RFIN2 as the input to the
single-ended broadband matched LNA. This switch is
programmed through the RFS bit (bit 5) of register 0x05.
The LNA provides a continuous gain control range of
typically 50dB before the signal is downconverted.
For optimal matching above 600MHz, add a 5nH to
6nH inductor in series with a capacitor at either of the
RF input. Application Note:
Front End Diplexer Filter for
MAX3580
is available, detailing the implementation of a
UHF and VHF simple diplexer. This simple diplexerl
improves strong-signal-handling capabilities of the
MAX3580.
DC-Offset Cancellation
The MAX3580 features an on-chip fast-settling, DC-offset cancellation circuitry that requires no off-chip components. Note that the offset correction circuit is not
enabled when the device is powered up. To enable the
offset correction circuit, program the DC-Offset Control
Register to the recommended default setting.
When active, the offset correction circuit creates a
highpass characteristic in the signal path with a typical
corner frequency of 200Hz, and the residual DC offset
can be as high as ±70mV.
Gain Control
The MAX3580 features two VGA circuits that can be
used to achieve the optimum SNR. The two circuits can
be driven independently by the baseband controller,
which allows balancing the gain based on SNR measurements in the digital demodulator. If only one gain control
voltage can be provided by the digital demodulator, the
RF VGA is controlled by the baseband power detector of
the MAX3580. See the
Baseband Power Detector
section. In this operation mode, the baseband gain is set by
an amplitude detector in the digital demodulator.
Baseband Power Detector
The MAX3580 baseband power detector compares the
total weighted receive input signal within approximately
2 channels of the wanted channel to a programmable
threshold. This threshold can be programmed to different values with the PD_TH<2:0> bits in the Baseband
Control Register.
To close the RF gain control loop, connect the 300µA
control current sink of the power detector (pin
OVLD_DET) to VCCwith a 10kΩ pullup resistor. The
resulting voltage is fed with an RC lowpass to the
RF_AGC input.
Synthesizer Loop Filters
A second-order lowpass loop filter is used to connect
the PLL to the RF local oscillator. A loop filter bandwidth
of 30kHz is optimal for fractional PLL spurs and integrated LO phase noise. Refer to the EV kit data sheet for the
recommended loop-filter component values.
Crystal-Oscillator Interface
The MAX3580 reference oscillator circuitry can be used
either as a high-impedance reference input driven by
an external source, or be configured as a crystal oscillator. In the latter case, the resulting frequency can be
used to drive the digital demodulator chip through the
buffered reference output of the MAX3580. When using
an external reference oscillator, drive the XB input
through an AC-coupling capacitor with amplitude of
approximately 1.5V
P-P
, and leave XE unconnected.
Note that the phase noise of the external reference
needs to exceed -140dBc/Hz at offsets of 1kHz to
100kHz. When connecting directly to a crystal, see the
Typical Application Circuit
for the required topology.
For particular capacitor values, possible changes to
accommodate for different crystal frequencies, crystal
load-capacitance requirements, and crystal power-dissipation requirements, refer to the EV kit data sheet.
The MAX3580 utilizes two narrowband RF tracking filters,
one for VHF and one for UHF. Each filter is comprised of
a fixed inductor and three digitally controlled variable
capacitors named series, shunt, and parallel capacitors.
The integrated RF tracking filters uses an external inductor between IND1 and IND2 pins to set the filter’s center
frequency. The inductor value must be 68nH ±2% in
order to achieve the corner frequency response. The variable capacitors are factory calibrated to this particular
inductor value. The value of each capacitor is also set to
compensate for process variation of each individual part
and to receive the desired RF channel.
The process variation is factory calibrated by determining the best capacitor values for three discrete frequencies, which are stored in the on-chip ROM table. Upon
power-up these values (6 bytes total) have to be read
out of the MAX3580 ROM table and stored in the microprocessor local memory.
When tuning the MAX3580 to a given Rx frequency, the
correct capacitor value has to be calculated using the
following linear formulas and written to the appropriate
registers. This is in addition to programming the PLL
with the desired frequency.
The formulas differ for VHF and UHF bands but are the
same for all three capacitor values. Since the factory
calibration coefficients stored on the MAX3580 can differ for each capacitor, the calculations have to be executed for all three capacitor values separately.
This means the capacitor values stored in the UHF_lo
entries of the MAX3580 ROM table are the correct values
for 470MHz reception and the UHF_hi values for 860MHz
reception. For any frequency in between, the capacitor
values are obtained by a simple linear interpolation.
Note: When tuning to frequencies above 860MHz
channel center frequency, do not use the formula
above, but rather keep programming the tracking filter
with the coefficients obtained for 860MHz.
Examples: Assuming the MAX3580 ROM table entries
are C
SERIES
VHF = 8, C
SERIES
UHF_lo = 15, C
SERIES
UHF_hi = 3
208MHz: C
SERIES
= 8 - round ( ( 208-200 ) / 10 ) = 7
(floating point division, round to nearest
integer after division)
8 - floor ( ( 208 - 200 + 5) / 10 ) = 7
(all calculations using signed integer values,
truncate result of division)
677MHz: C
SERIES
= 15 - round ( (15-3) x (677 - 470) /
390 ) = 9 (floating point division, round to
nearest integer after division) 15 - floor
( ( ( 15-3) x (677-470) + 195 ) / 390 ) = 9
(all calculations using signed integer values,
truncate result of division)
Power-Supply Layout
To minimize coupling between different sections of the
IC, the ideal power-supply layout is a star configuration,
which has a large decoupling capacitor at the central
VCCnode. The VCCtraces branch out from this node,
with each trace going to separate VCCpins of the
MAX3580. Next to each VCCpin is a bypass capacitor
with a low impedance to ground at the frequency of
interest. Use at least one via per bypass capacitor for a
low-inductance ground connection.
The three ground pins (GND_PLL, GND_CP,
GND_TUNE) must be connected to the ground plane
by separate via holes and must not be directly connected to the exposed paddle.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
QFN THIN.EPS
MAX3580
Direct-Conversion TV Tuner
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
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