Rainbow Electronics MAX3420E User Manual

General Description

The MAX3420E contains the digital logic and analog circuitry necessary to implement a full-speed USB peripheral compliant to USB specification rev 2.0. A built-in full-speed transceiver features ±15kV ESD protection and programmable USB connect and disconnect. An internal SIE (serial-interface engine) handles low-level USB protocol details such as error checking and bus retries. The MAX3420E operates using a register set accessed by an SPI interface that operates up to 26MHz. Any SPI master (microprocessor, ASIC, DSP, etc.) can add USB functionality using the simple 3- or 4-wire SPI interface.

Internal level translators allow the SPI interface to run at a system voltage between 1.71V and 3.6V. USB timed operations are done inside the MAX3420E with interrupts provided at completion so an SPI master does not need timers to meet USB timing requirements. The MAX3420E includes four general-purpose inputs and outputs so any microprocessor that uses I/O pins to implement the SPI interface can reclaim the I/O pins and gain additional ones.

The MAX3420E operates over the extended -40°C to +85°C temperature range and is available in a 32-pin TQFP package (7mm x 7mm) and a space-saving 24pin TQFN package (4mm x 4mm).

Applications

Features

♦ Microprocessor-Independent USB Solution

♦ Complies with USB Specification Revision 2.0

(Full-Speed Operation)

♦ Integrated Full-Speed USB Transceiver

♦ Firmware/Hardware Control of an Internal D+

Pullup Resistor

♦ Programmable 3- or 4-Wire 26MHz SPI Interface

♦ Level Translators and V

Input Allow Independent

System Interface Voltage

♦ Internal Comparator Detects V

BUS

for

Self-Powered Applications

♦ ESD Protection on D+, D-, and VBCOMP ♦ Interrupt Output Pin (Level or Programmable

Edge) Allows Polled or Interrupt-Driven SPI Interface

♦ Intelligent USB Serial Interface Engine (SIE)

Automatically Handles USB Flow Control and Double Buffering

Handles Low-Level USB Signaling Details

Contains Timers for USB Time-Sensitive Operations So SPI Master Does Not Need to Time Events

♦ Built-In Endpoint FIFOs:

EP0: CONTROL (64 Bytes)

EP1: OUT, Bulk or Interrupt, 2 x 64 Bytes (Double-Buffered)

EP2: IN, Bulk or Interrupt, 2 x 64 Bytes (Double-Buffered)

EP3: IN, Bulk or Interrupt (64 Bytes)

♦ Double-Buffered Data Endpoints Increase

Throughput by Allowing the SPI Master to Transfer Data Concurrently with USB Transfers Over the Same Endpoint

♦ SETUP Data Has Its Own 8-Byte FIFO, Simplifying

Firmware

♦ Four General-Purpose Inputs and Four General-

Purpose Outputs

♦ Space-Saving TQFP and TQFN Packages

MAX3420E

USB Peripheral Controller

with SPI Interface

________________________________________________________________ Maxim Integrated Products 1

19-3781; Rev 0; 8/05

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

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PART

TEMP RANGE

PINPACKAGE

PACKAGE

CODE

M AX 3420E E C J

32 TQFP

1.4m m

C 32- 1

M AX 3420E E TG*

24 TQFN

0.8m m

T2444- 4

Ordering Information

*Future product—contact factory for availability.

- 40°C to + 85°C

7m m x 7m m x

4m m x 4m m x

The MAX3420E connects to any microprocessor using 3 or 4 interface pins (Figure 1). On a simple microprocessor without SPI hardware, these can be bitbanged general-purpose I/O pins. Four GPIN and four GPOUT pins on the MAX3420E more than replace the µP pins necessary to implement the interface. Although the MAX3420E SPI hardware includes separate data-in (MOSI, (Master-Out, Slave-In)) and data-out (MISO, (Master-In, Slave-Out)) pins, the SPI interface can also be configured for the MOSI pin to carry bidirectional data, saving an interface pin. This is referred to as halfduplex mode.

Two MAX3420E features make it easy to connect to large, fast chips such as ASICs and DSPs (see Figure

2). First, the SPI interface can be clocked up to 26MHz. Second, a VLpin and internal level translators allow running the system interface at a lower voltage than the

3.3V required for VCC.

The MAX3420E provides an ideal method for electrically isolating a USB interface (Figure 3). USB employs flow control in which the MAX3420E automatically answers host requests with a NAK handshake, until the microprocessor completes its data-transfer operations over the SPI port. This means that the SPI interface can run at any frequency up to 26MHz. Therefore, the designer is free to choose the interface operating frequency and to make opto-isolator choices optimized for cost or performance.

MAX3420E

USB Peripheral Controller with SPI Interface

2 _______________________________________________________________________________________

Typical Application Circuits

3.3V

REGULATOR

SPI 3, 4

INT

USB

MAX3420E

Figure 2. The MAX3420E Connected to a Large Chip

3.3V

REGULATOR

MISO

LOCAL GND

LOCAL POWER

INT

MAX3420E

SCLK MOSI

MICRO

ASIC

DSP

I S O L A T O R S

USB

Figure 3. Optical Isolation of USB Using the MAX3420E

Figure 1. The MAX3420E connects to any microprocessor using 3 or 4 interface pins.

3.3V

REGULATOR

SPI

USB

MAX3420E

3, 4

INT

ASIC,

DSP, ETC.

POWER RAIL

MAX3420E

USB Peripheral Controller

with SPI Interface

_______________________________________________________________________________________ 3

Functional Diagram

GPIN3

GPIN

1V–3V

VBCOMP

D-

D+

GPIN2 GPIN1 GPIN0 GPOUT3

GPOUT2

GPOUT1

GPOUT0

VBUS

COMP

MISO

SCLK

INT

SPI SLAVE

INTERFACE

USB SIE

(SERIAL-INTERFACE ENGINE)

FULL-SPEED

USB

TRANSCEIVER

RESET LOGIC

1.5kΩ

INTERNAL

POR

RES

XIV

POWER

DOWN

OSC AND

PLL 4X

48MHZ

ESD

PROTECTION

ESD

PROTECTION

GPX

VBUS_DET

OPERATE

SOF

BUSACT

MUX

0123

MOSI

VBUS_DET

ENDPOINT

BUFFERS

MAX3420E

GND

MAX3420E

USB Peripheral Controller with SPI Interface

4 _______________________________________________________________________________________

Pin Description

TQFN TQFP

NAME

INPUT/

FUNCTION

G ener al - P ur p ose P ush- P ul l O utp uts. G P OU T3–G P OU T0 l og i c l evel s ar e r efer enced to the vol tag e on V

. The S P I m aster contr ol s the G P OU T3–GP OU T0 states b y

w r i ti ng to b i t 3 thr oug h b i t 0 of the IOP IN S ( R20) r eg i ster .

3 3, 4 V

Input

Level-Translator Reference Voltage. Connect V

to the system’s 1.71V to 3.6V

logic-level power supply. Bypass V

to ground with a 0.1µF capacitor as close to

the V

pin as possible.

4, 14

GND Input Ground

Gener al - P ur p ose P ush- P ul l O utp uts. GP OU T3–GP O U T0 l og i c l evel s ar e r efer enced to the vol tag e on V

. The S P I m aster contr ol s the GP O U T3–GP OU T0 states b y w r i ti ng to

b i t 3 thr oug h b i t 0 of the IOP IN S ( R20) r eg i ster .

710RES Input

Device Reset. Drive RES low to clear all of the internal registers except for PINCTL (R17), USBCTL (R15), and SPI logic. See the Device Reset section for a description of resets available on the MAX3420E.

811SCLK Input

SPI Serial-Clock Input. An external SPI master supplies this clock with frequencies up to 26MHz. The logic level is referenced to the voltage on V

. Data is clocked into the SPI slave interface on the positive edge of SCLK. Data is clocked out of the SPI slave interface on the falling edge of SCLK.

912SS Input

SPI Slave-Select Input. The SS logic level is referenced to the voltage on V

When SS is driven high, the SPI slave interface is not selected and SCLK transitions are ignored. An SPI transfer begins with a high-to-low SS transition and ends with a low-to-high SS transition. The MAX3420E SS pin is sensitive to undershoot. A 33pF capacitor should be connected from SS to ground to prevent any noise spikes.*

10 13 MISO

SPI Serial-Data Output (Master-In, Slave-Out). MISO is a push-pull output. MISO is tri-stated in half-duplex mode or when SS = 1. The MISO logic level is referenced to the voltage on V

11 14 MOSI

Input or

Input/

SPI Serial-Data Input (Master-Out, Slave-In). The logic level on MOSI is referenced to the voltage on V

. MOSI can also be configured as a bidirectional

MOSI/MISO input and output.

12 15 GPX

General-Purpose Multiplexed Output. The internal MAX3420E signal that appears on GPX is programmable by writing to the GPXB and GPXA bits of the PINCTL (R17) register. GPX indicates one of four signals: OPERATE (00, Default), VBUS_DET (01), BUSACT (10), and SOF (11).

13 17 INT

Inter r up t Outp ut. In ed g e m od e, the l og i c l evel on IN T i s r efer enced to the vol tag e on V L. In ed g e m od e , IN T i s a p ush- p ul l outp ut w i th p r og r am m ab l e p ol ar i ty. In l evel m od e, IN T i s op en d r ai n and acti ve l ow . S et the IE b i t i n the C P U C TL ( R16) r eg i ster to enab l e IN T.

15 20 D-

Input/

U S B D - S i g nal . C onnect D - to a U S B “B” connector thr ough a 33Ω ( ±1%) ser ies re si stor .

*33pF capacitor will not be required after redesign.

OUTPUT

GPOUT0

Output

GPOUT1

5, 6, 18, 19

GPOUT2

GPOUT3

Output

The SPI master controls the MAX3420E by reading and writing 21 registers (Table 1). For a complete description of register contents, please refer to the “MAX3420E Programming Guide.” A register access consists of the SPI master first writing an SPI command byte, followed by reading or writing the contents of the addressed register. All SPI transfers are MSB (most significant bit) first. The command byte contains the register address, a direction bit (Read = 0, Write = 1), and the ACKSTAT bit (Figure 4). The SPI master addresses the MAX3420E registers by writing the binary value of the register number in the Reg4 through Reg0 bits of the command byte. For example, to access the IOPINS

(R20) register, the Reg4 through Reg0 bits would be as follows: Reg4 = 1, Reg3 = 0, Reg2 = 1, Reg1 = 0, Reg0 = 0. The DIR (direction) bit determines the direction for the data transfer. DIR = 1 means the data byte(s) will be written to the register, and DIR = 0 means the data byte(s) will be read from the register. The ACKSTAT bit sets the ACKSTAT bit in the EPSTALLS (R9) register. The SPI master sets this bit to indicate that it has finished servicing a CONTROL transfer. Since the bit is frequently used, having it in the SPI command byte improves firmware efficiency. In SPI full-duplex mode, the MAX3420E clocks out eight USB status bits as the command byte is clocked in (Figure 5). In half-duplex

MAX3420E

USB Peripheral Controller

with SPI Interface

_______________________________________________________________________________________ 5

Pin Description (continued)

TQFN TQFP

NAME

INPUT/

FUNCTION

16 21 D+

Input/

USB D+ Signal. Connect D+ to a USB “B” connector through a 33Ω (±1%) series resistor. The 1.5kΩ D+ pullup resistor is internal to the device.

17 22, 23 V

Input

USB Transceiver Power-Supply Input. Connect V

to a positive 3.3V power

supply. Bypass V

to ground with a 1.0µF ceramic capacitor as close to the

pin as possible.

18 24

Input

BUS

Comparator Input. VBCOMP is internally connected to a voltage comparator to allow the SPI master to detect (through an interrupt or checking a register bit) the presence or loss of power on V

BUS

. Bypass VBCOMP to

ground with a 1.0µF ceramic capacitor.

19 26 XI Input

Crystal Oscillator Input. Connect XI to one side of a parallel resonant 12MHz (±0.25%) crystal and a capacitor to GND. XI can also be driven by an external clock referenced to V

20 27 XO

Crystal Oscillator Output. Connect XO to the other side of a parallel resonant 12MHz (±0.25%) crystal and a capacitor to GND. Leave XO unconnected if XI is driven with an external source.

21 29 GPIN0

22 30 GPIN1

23 31 GPIN2

24 32 GPIN3

Input

General-Purpose Inputs. GPIN3–GPIN0 are connected to V

with internal

pullup resistors. GPIN3–GPIN0 logic levels are referenced to the voltage on V

. The SPI master samples GPIN3–GPIN0 states by reading bit 7 through bit 4 of the IOPINS (R20) register. Writing to these bits has no effect.

—

N.C. — No Internal Connection

EP — GND Input Exposed Paddle on the Bottom of the TQFN Package. Connect EP to GND.

Figure 4. SPI Command Byte

b7 b6 b5 b4 b3 b2 b1 b0

Reg4 Reg3 Reg2 Reg1 Reg0 0 DIR ACKSTAT

Figure 5. USB Status Bits Clocked Out as First Byte of Every Transfer (Full-Duplex Mode Only)

b7 b6 b5 b4 b3 b2 b1 b0

SUSPIRQ URESIRQ

IN0BAVIRQ

9, 16, 25, 28

VBCOMP

OUTPUT

Output

SUDAVIRQ IN3BAVIRQ IN2BAVIRQ OUT1DAVIRQ OUT0DAVIRQ

MAX3420E

mode, these status bits are accessed in the normal way, as register bits.

The first five registers (R0–R4) access endpoint FIFOs. To access a FIFO, an initial command byte sets the register address and then consecutive reads or writes keep the same register address to access subsequent FIFO bytes.

The remaining registers (R5–R20) control the operation of the MAX3420E. Once a register address above R4 is set in the command byte, successive byte reads or writes in the same SPI access cycle (SS low) increment the register address after every byte read or written. This incrementing operation continues until R20 is accessed. Subsequent byte reads or writes continue to access R20. Note that this auto-incrementing action stops with the next SPI cycle, which establishes a new register address. Addressing beyond R20 is ignored.

USB Peripheral Controller with SPI Interface

6 _______________________________________________________________________________________

Table 1. MAX3420E Register Map

R EG

NAME b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0

a c c

EP0 F IF O b 7b 6b 5b 4b 3b 2b 1b 0

RS C

b 7b 6b 5b 4b 3b 2b 1b 0

RS C

EP2 IN F IF O b 7b 6b 5b 4b 3b 2b 1b 0

RS C

EP3 IN F IF O b 7b 6b 5b 4b 3b 2b 1b 0

RS C

SU D F IF O b 7b 6b 5b 4b 3b 2b 1b 0

RS C

EP0 B C 0b 6b 5b 4b 3b 2b 1b 0

RS C

EP1 O U T B C 0b 6b 5b 4b 3b 2b 1b 0

RS C

EP2 IN B C 0b 6b 5b 4b 3b 2b 1b 0

RS C

EP3 IN B C 0b 6b 5b 4b 3b 2b 1b 0

RS C

EPST A L L S 0

RS C

R10

C L R T O G S

RS C

R11

EPI R Q 00

R12

EPI EN 00

RS C

R13

U SB IR Q

R14

U SB IEN

RS C

R15

U SB C T L

S IG RWU 0 0

RS C

R16

C PU C T L 000 00 0 0 IE

RS C

R17

PIN C T L

P OS IN TGP X BGP X A

RS C

R18

R EVISIO N 000 00 0 1 0

R19

F N A D D R 0b 6b 5b 4b 3b 2b 1b 0

R20

IO PIN S GP IN 3

GP IN 1GP IN 0

GP O U T2 GP O U T1

RS C

Note: The acc (access) column indicates how the SPI Master can access the register.

R = Read, RC = Read or Clear, RSC = Read, Set, or Clear. Writing to an R register (Read-Only) has no effect. Writing a 1 to an RC bit (Read or Clear) clears the bit. Writing a zero to an RC bit has no effect.

EP1 O U T F IF O

AC KS TAT S TLS TAT S TLE P 3IN S TLE P 2IN S TLE P 1OU TS TLE P 0OU TS TLE P 0IN

E P 3D IS AB E P 2D IS AB E P 1D IS AB C TG E P 3IN C TG E P 2IN C TG E P 1OU T

S U D AV IRQ IN 3BAV IRQ IN 2BAV IRQ OU T1D AV IRQ OU T0D AV IRQ IN 0BAV IRQ

S U D AV IE IN 3BAV IE IN 2BAV IE OU T1D AV IE OU T0D AV IE IN 0BAV IE

U RE S D N IRQ V BU S IRQ N OV BU S IRQ S U S P IRQ U RE S IRQ BU S AC TIRQ RWU D N IRQ OS C OKIRQ

U RE S D N IE V BU S IE N OV BU S IE S U S P IE U RE S IE BU S AC TIE RWU D N IE OS C OKIE

H OS C S TE N V BG ATE C H IP RE S P WRD OWN C ON N E C T

E P 3IN AK E P 2IN AK E P 0IN AK FD U P S P IIN TLE V E L

GP IN 2

GP O U T3

GP O U T0

MAX3420E

USB Peripheral Controller

with SPI Interface

_______________________________________________________________________________________ 7

TQFN

MAX3420E

*EP

1234

* EXPOSED PADDLE CONNECTED TO GROUND

18 17 16 15 14 13

GPOUT0

GPOUT1

GPOUT3

SCLK

RES

MISO

MOSI

GPX

GPIN3

GPIN2

GPIN0

GPOUT2

GND

VBCOMP

D+

D-

INT

GND

GPIN1

TOP VIEW

MAX3420E

TQFP

TOP VIEW

GPIN2

GPIN1

GPIN0

N.C.

GPIN3

N.C.

SCLK

RES

MISO

GPX

MOSI

N.C.

17181920212223

VBCOMP

D+

D-

GND

INT

GPOUT3

GPOUT2

GND

LVL

GPOUT1

GPOUT0

Pin Configurations

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