Rainbow Electronics MAX3107 User Manual
19-5014; Rev 0; 10/09
SPI/I2C UART with 128-Word FIFOs
General Description
The MAX3107 is an advanced universal asynchronous
receiver-transmitter (UART) with 128 words each of
receive and transmit first-in/first-out (FIFO) that can be
controlled through I2C or high-speed SPI™. An internal
oscillator reduces the need for an external crystal or
clock source. The 2x and 4x rate modes allow a maximum of 24Mbps data rates. A phase-locked loop (PLL),
prescaler, and fractional baud-rate generator allow for
high-resolution baud-rate programming and minimize
the dependency of baud rate on reference clock frequency.
Autosleep and shutdown modes help reduce power
consumption during periods of inactivity. A low 640µA
(typ) supply current and tiny 24-pin TQFN (3.5mm x
3.5mm) package make the MAX3107 ideal for low-power
portable devices.
Integrated logic-level translation on the controller and
transceiver (RX/TX and RTS/CTS) interfaces enable use
with a wide selection of RS-232/RS-485 transceivers.
Automatic hardware and software flow control with
selectable FIFO interrupt triggering offloads low-level
activity from the host controller. Automatic half-duplex
transceiver control with programmable setup and hold
times allow the MAX3107 to be used in high-speed applications, for example Profibus-DP.
The MAX3107 is ideal for use in portable devices,
industrial applications, and automotive applications. The
MAX3107 is available in a 24-pin SSOP package and a
24-pin TQFN package. It is specified over the -40NC to
+85NC extended ambient temperature range.
Applications
Portable Devices
Industrial Control Systems
Fieldbus Networks
Automotive Infotainment Systems
Medical Systems
Point-of-Sale Systems
HVAC or Building Control
and Internal Oscillator
Features
S Tiny 24-Pin, Lead-Free TQFN (3.5mm x 3.5mm)
and 24-Pin, Lead-Free SSOP Packages
S Integrated Internal Oscillator
S 24Mbps (max) Data Rate
S Integrated PLL and Divider
S Fractional Baud-Rate Generator
S SPI Up to 26MHz Clock Rate
S Autotransceiver Direction Control
S Half-Duplex Echo Suppression
S Automatic RTS/CTS and XON/XOFF Flow Control
S Special Character Detection
S GPIO-Based Character Detection
S 9-Bit Multidrop-Mode Data Filtering
S SIR- and MIR-Compliant IrDA Encoder/Decoder
S +2.35V to +3.6V Supply Range
S Logic-Level Translation on the Controller and
Transceiver Interfaces (Down to 1.7V)
S Four Flexible GPIOs
S Line Noise Indication
S Shutdown and Autosleep Modes
S Low 640µA (typ) Supply Current at 1Mbaud and
20MHz Clock
S Low 20µA (typ) Shutdown Power
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX3107EAG+
MAX3107ETG+
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Functional Diagram appears at end of data sheet.
-40NC to +85NC
-40NC to +85NC
24 SSOP
24 TQFN-EP*
MAX3107
SPI is a trademark of Motorola, Inc.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
SPI/I2C UART with 128-Word FIFOs
and Internal Oscillator
TABLE OF CONTENTS
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Test Circuits/Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MAX3107
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Receive and Transmit FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Transmitter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Receiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Line Noise Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clocking and Baud-Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PLL and Predivider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Fractional Baud-Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2x and 4x Rate Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Multidrop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Autodata Filtering in Multidrop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Autotransceiver Direction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Echo Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Automatic Hardware Flow Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AutoRTS Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AutoCTS Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Automatic Software (XON/XOFF) Flow Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Transmitter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Receiver Overflow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
FIFO Interrupt Triggering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Low-Power Standby Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Forced Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Autosleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Shutdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2 ______________________________________________________________________________________
SPI/I2C UART with 128-Word FIFOs
and Internal Oscillator
TABLE OF CONTENTS (continued)
Power-Up and IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Interrupt Enabling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Interrupt Clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Serial Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SPI Single-Cycle Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SPI Burst Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
START, STOP, and Repeated START Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Single-Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Single-Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Startup and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Interrupts and Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Logic-Level Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Connector Pin Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
RS-232 5x3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
MAX3107
_______________________________________________________________________________________ 3
SPI/I2C UART with 128-Word FIFOs
and Internal Oscillator
LIST OF FIGURES
Figure 1. I2C Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2. SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. Transmit FIFO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. Receive Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. Midbit Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MAX3107
Figure 6. Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Clock Selection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. 2x and 4x Baud Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Autotransceiver Direction Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Setup and Hold Times in Autotransceiver Direction Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Half-Duplex with Echo Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Echo Suppression Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. Simplified Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. PLL Signal Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 15. SPI Single-Cycle Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 16. SPI Single-Cycle Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 17. I2C START, STOP, and Repeated START Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 18. Write Byte Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 19. Burst Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 20. Read Byte Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 21. Burst Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 22. Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 23. Startup and Initialization Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 24. Logic-Level Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 25. Connector Sharing with a USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 26. RS-232 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 27. RS-485 Half-Duplex Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
LIST OF TABLES
Table 1. StopBits Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 2. Length[1:0] Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 3. SwFlow[3:0] Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 4. PLLFactor[1:0] Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 5. I2C Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4 ______________________________________________________________________________________
SPI/I2C UART with 128-Word FIFOs
and Internal Oscillator
LIST OF REGISTERS
RHR—Receiver Hold Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
THR—Transmit Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
IRQEn—IRQ Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ISR—Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
LSRIntEn—Line Status Register Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LSR—Line Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SpclChrIntEn—Special Character Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SpclCharInt—Special Character Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STSIntEn—STS Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
STSInt—Status Interrupt Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MODE1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
MODE2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LCR—Line Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
RxTimeOut—Receiver Timeout Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
HDplxDelay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
IrDA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FlowLvl—Flow Level Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FIFOTrgLvl—FIFO Interrupt Trigger Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
TxFIFOLvl—Transmit FIFO Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
RxFIFOLvl—Receive FIFO Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
FlowCtrl—Flow Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
XON1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
XON2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
XOFF1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
XOFF2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
GPIOConfg—GPIO Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
GPIOData—GPIO Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
PLLConfig—PLL Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
BRGConfig—Baud-Rate Generator Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DIVLSB—Baud-Rate Generator LSB Divisor Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DIVMSB—Baud-Rate Generator MSB Divisor Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
CLKSource—Clock Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
RevID—Revision Identification Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
MAX3107
_______________________________________________________________________________________ 5
SPI/I2C UART with 128-Word FIFOs
and Internal Oscillator
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to AGND.)
VL, VA, V
V18, XOUT .................................................. -0.3V to (VA + 0.3V)
RST, IRQ, DIN/A1, CS/A0, SCLK/SCL,
DOUT/SDA, LDOEN, I2C/SPI .................. -0.3V to (VL + 0.3V)
TX, RX, RTS/CLKOUT, CTS, GPIO_ ....... -0.3V to (V
DGND .................................................................. -0.3V to +0.3V
Continuous Power Dissipation (TA = +70NC)
MAX3107
24-Pin TQFN (derate 15.4mW/NC above +70NC) ...... 1229mW
24-Pin SSOP (derate 12.3mW/NC above +70NC) ........ 988mW
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
, XIN ................................................ -0.3V to +4.0V
EXT
+ 0.3V)
EXT
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
DC ELECTRICAL CHARACTERISTICS
(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, V
are at VA = +2.8V, VL = +1.8V, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Digital Interface Supply Voltage V
Analog Supply Voltage V
UART Interface Logic Supply
Voltage
Logic Supply Voltage V
CURRENT CONSUMPTION
VA Supply Current I
VA Shutdown Supply Current I
VA Sleep Supply Current I
VL Supply Current I
V
Supply Current I
EXT
V18 Input Power-Supply Current
in Shutdown Mode
= +2.5V, TA = +25NC.) (Note 2)
EXT
L
A
V
EXT
18
A
A, SHDN
A, SLEEP
L
EXT
I
18SHDN
= +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values
EXT
1.8MHz crystal oscillator active, PLL disabled, V
LDOEN
Baud rate = 1Mbps, external clock, SPI
frequency is 8MHz, external loopback PLL
disabled, V
Internal oscillator enabled, PLL = 6X,
TX-RX loopback, continuous data transmission at 115kbps, V
Shutdown mode, V
all inputs and outputs are idle
Sleep mode, V
inputs and outputs are idle
All logic inputs are at VL or V
All logic inputs are at VL or V
V
LDOEN
nal 1.85V voltage source), static power
consumption
LDOEN
= 0V (V18 is powered by an exter-
Junction-to-Ambient Thermal Resistance (BJA) (Note 1)
24-Pin TQFN ............................................................. +65NC/W
24-Pin SSOP ............................................................. +81NC/W
Junction-to-Case Thermal Resistance (BJC) (Note 1)
24-Pin TQFN .............................................................. +15NC/W
24-Pin SSOP ............................................................. +32NC/W
Operating Temperature Range ........................ -40NC to +85NC
Junction Temperature ................................................... +150NC
Storage Temperature Range ........................... -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
1.71 3.6 V
2.35 3.6 V
1.71 3.6 V
1.65 1.80 1.95 V
= VL, SPI/I2C interface idle
= VL (Note 3)
= VL (Note 3)
LDOEN
LDOEN
LDOEN
= 0V, V
= VL, V
EXT
EXT
= 0V,
RST
= VL, all
RST
or 0V 4 15
or 0V 5 10
220 500
0.65 1.3
4 8
20 35
45 100
7 50
FA
mA
FA
FA
FA
FA
FA
6 ______________________________________________________________________________________
SPI/I2C UART with 128-Word FIFOs
and Internal Oscillator
DC ELECTRICAL CHARACTERISTICS (continued)
(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, V
are at VA = +2.8V, VL = +1.8V, V
= +2.5V, TA = +25NC.) (Note 2)
EXT
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK/SCL, DOUT/SDA
DOUT/SDA Output Low Voltage
in I2C Mode
DOUT/SDA Output Low Voltage
in SPI Mode
DOUT/SDA Output High Voltage
in SPI Mode
Input Low Voltage V
Input High Voltage V
Input Hysteresis V
Input Leakage Current I
Input Capacitance C
V
OL,I2C
V
OL,SPIILOAD
V
OH,SPIILOAD
IL
IH
HYST
IL
IN_I2C_SPI
I2C/SPI, CS/A0, DIN/A1 INPUTS
Input Low Voltage V
Input High Voltage V
Input Hysteresis V
Input Leakage Current I
Input Capacitance C
IL
IH
HYST
IL
IN_I2C_SPI
IRQ OUTPUT (OPEN DRAIN)
Output Low Voltage V
Output Leakage I
OL
LK
LDOEN AND RST INPUTS
Input Low Voltage V
Input High Voltage V
Input Hysteresis V
Input Leakage Current I
IL
IH
HYST
IN
RTS/CLKOUT AND TX OUTPUTS
Output Low Voltage V
Output High Voltage V
Input Leakage Current I
Input Capacitance C
OL
OH
IN
IN_IRSTB
RX, CTS INPUTS
Input Low Voltage V
Input High Voltage V
Input Hysteresis V
CTS Input Leakage Current
RX Pullup Current I
Input Capacitance C
IL
IH
HYST
I
IN_CTS
IN_RX
IN_IUART
GPIO_ OUTPUTS AND INPUTS
Output Low Voltage V
Output High Voltage V
OL
OH
= +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values
EXT
I
= -3mA, VL > 2V 0.4 V
LOAD
I
= -3mA, VL < 2V 0.2 x V
LOAD
= -2mA 0.4 V
= 2mA VL - 0.4 V
SPI and I2C mode 0.3 x V
SPI and I2C mode 0.7 x V
SPI and I2C mode 0.05 x V
V
= 0 to V
IN
SPI and I2C mode -1 +1
L,
SPI and I2C mode 5 pF
SPI and I2C mode 0.3 x V
SPI and I2C mode 0.7 x V
SPI and I2C mode 50 mV
V
= 0 to V
IN
SPI and I2C mode -1 +1
L,
SPI and I2C mode 5 pF
I
= -2mA 0.4 V
LOAD
V
= 0 to V
IRQ
V
= 0 to V
IN
I
= -2mA 0.4 V
LOAD
I
= 2mA V
LOAD
Output three-stated, V
IRQ is not asserted
L,
L
IN
High-Z mode 5 pF
V
= 0 to V
IN
V
= 0V 0.3 1.5 3
IN
I
LOAD
I
LOAD
EXT
= -2mA, push-pull or open drain 0.4 V
= 2mA, push-pull V
= 0 to V
EXT
L
L
L
-1 +1
0.3 x V
0.7 x V
L
50 mV
-1 +1
- 0.4 V
EXT
-1 +1
0.3 x V
0.7 x V
EXT
50 mV
-1 +1
5 pF
- 0.4 V
EXT
EXT
MAX3107
V
L
V
L
V
V
FA
V
L
V
FA
FA
V
L
V
FA
FA
V
V
FA
FA
_______________________________________________________________________________________ 7
SPI/I2C UART with 128-Word FIFOs
and Internal Oscillator
DC ELECTRICAL CHARACTERISTICS (continued)
(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, V
are at VA = +2.8V, VL = +1.8V, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Low Voltage V
Input High Voltage V
Pulldown Current I
MAX3107
Input Capacitance C
XIN
Input Low Voltage V
Input High Voltage V
Input Capacitance C
XOUT
Input Capacitance C
= +2.5V, TA = +25NC.) (Note 2)
EXT
IL
IH
PD
IN_IUART
IL
IH
XI
XO
AC ELECTRICAL CHARACTERISTICS
(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, V
are at VA = +2.8V, VL = +1.8V, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
UART CLOCKING
Internal Oscillator Frequency f
External Crystal Frequency f
External Clock Frequency f
External Clock Duty Cycle (Note 3) 45 55 %
Baud-Rate Generator Clock
Input
I2C BUS: TIMING CHARACTERISTICS (see Figure 1)
SCL Clock Frequency f
Bus Free Time Between a STOP
(P) and START (S) Condition
= +2.5V, TA = +25NC.) (Note 2)
EXT
INT
XOSC
CLK
f
REF
SCL
t
BUF
= +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values
EXT
Configured as an input 0.4 V
Configured as an input 2/3 x V
GPIO_ = V
Configured as an input 5 pF
= +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values
EXT
TA = +25NC
TA = 0NC to +70NC
TA = -40NC to +85NC
(Note 3) 96 MHz
Standard mode 100
Fast mode 400
Standard mode 4.7
Fast mode 1.3
EXT
VA ≤ 2.8V -0.25% 614.4 +0.25%
EXT
0.25 1 2.5
0.2 V
1.2 V
16 pF
16 pF
-0.4% 614.4 +0.4%
-2% 614.4 +2%
-3% 614.4 +3%
1 4 MHz
0.5 30 MHz
V
FA
A
V
kHz
kHz
Fs
Hold Time for START (S)
Condition and Repeated START
(Sr) Condition (Note 3)
Low Period of the SCL Clock t
High Period of the SCL Clock t
Data Hold Time t
8 ______________________________________________________________________________________
t
HD:STA
LOW
HIGH
HD:DAT
Standard mode 4.0
Fast mode 0.6
Standard mode 4.7
Fast mode 1.3
Standard mode 4.0
Fast mode 0.6
Standard mode 0 0.9
Fast mode 0 0.9
Fs
Fs
Fs
Fs
SPI/I2C UART with 128-Word FIFOs
and Internal Oscillator
AC ELECTRICAL CHARACTERISTICS (continued)
(VA = +2.35V to +3.6V, VL = +1.71V to +3.6V, V
are at VA = +2.8V, VL = +1.8V, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Data Setup Time t
Setup Time for Repeated START
(Sr) Condition
Rise Time of SDA and SCL
Signals Receiving
Fall Time of SDA and SCL
Signals
Setup Time for STOP (P)
Condition
Capacitive Load for SDA and
SCL (Note 3)
I/O Capacitance (SCL, SDA) C
Pulse Width of Spike
Suppressed
SPI BUS: TIMING CHARACTERISTICS (see Figure 2)
SCLK Clock Period t
SCLK Pulse-Width High t
SCLK Pulse-Width Low t
CS Fall to SCLK Rise Time
DIN Hold Time t
DIN Setup Time t
Output Data Propagation Delay t
DOUT Rise and Fall Times t
CS Hold Time
Note 2: All devices are production tested at TA = +25NC. Specifications over temperature are guaranteed by design.
Note 3: Not production tested. Guaranteed by design.
Note 4: When V18 is powered by an external voltage regulator, the external power supply must have current capability above or
equal to I18.
Note 5: CB is the total capacitance of either the clock or data line of the synchronous bus in pF.
= +2.5V, TA = +25NC.) (Note 2)
EXT
SU:DAT
t
SU:STA
t
R
t
F
t
SU:STO
C
B
I/O
t
SP
CH+CL
CH
CL
t
CSS
DH
DS
DO
FT
t
CSH
= +1.71V to +3.6V, TA = -40NC to +85NC, unless otherwise noted. Typical values
EXT
Standard mode 250
Fast mode 100
Standard mode 4.7
Fast mode 0.6
Standard mode (0.3 x VL to 0.7 x VL)
(Note 5)
Fast mode (0.3 x VL to 0.7 x VL) (Note 5)
Standard mode (0.7 x VL to 0.3 x VL)
(Note 5)
Fast mode (0.7 x VL to 0.3 x VL) (Note 5)
Standard mode 4.7
Fast mode 0.6
Standard mode 400
Fast mode 400
20 +
0.1C
B
20 +
0.1C
B
20 +
0.1C
B
20 +
0.1C
B
38.4 ns
16 ns
16 ns
0 ns
3 ns
5 ns
32 ns
1000
300
300
300
10 pF
50 ns
20 ns
10 ns
ns
Fs
ns
ns
Fs
pF
MAX3107
_______________________________________________________________________________________ 9
SPI/I2C UART with 128-Word FIFOs
and Internal Oscillator
Test Circuits/Timing Diagrams
START CONDITION
(S)
SDA
MAX3107
t
HD:STA
SCL
Figure 1. I2C Timing Diagram
CS
SCLK
t
CSH
t
CSS
t
HD:DAT
t
t
DS
t
SU:DAT
HIGH
t
REPEATED START CONDITION
t
SU:STA
t
R
t
CL
DH
t
F
t
CH
(Sr)
t
R
t
HD:STA
t
LOW
t
SU:STO
t
F
STOP CONDITION
(P)
t
CSH
t
BUF
START CONDITION
(S)
DIN
t
DO
DOUT
Figure 2. SPI Timing Diagram
10 _____________________________________________________________________________________
SPI/I2C UART with 128-Word FIFOs
and Internal Oscillator
Typical Operating Characteristics
(VA = 2.5V, VL = 2.5V, V
= 2.5V, LDOEN = VL, TA = +25NC, unless otherwise noted.)
EXT
MAX3107
IA SUPPLY CURRENT vs. VA VOLTAGE
(EXTERNAL CLOCK, PLL DISABLED)
140
EXTERNAL 3.6MHz CLOCK
BAUD RATE = 115kbps
120
100
80
(µA)
A
I
60
40
20
0
2.35 3.60
LDOEN = V
L
LDOEN = AGND
1.8V APPLIED TO V
VA (V)
IA SUPPLY CURRENT vs. VA VOLTAGE
(EXTERNAL CRYSTAL, PLL ENABLED)
1.100
1.075
1.050
1.025
1.000
(mA)
A
I
0.975
0.950
0.925
0.900
LDOEN = AGND
1.8V APPLIED TO V
2.35 3.60
18
LDOEN = V
3.686MHz EXT. CRYSTAL
BAUD RATE = 115kbps
6x PLL MULT.FACTOR
VA (V)
IA SUPPLY CURRENT vs. VA VOLTAGE
(EXTERNAL CLOCK, PLL ENABLED)
3.8
3.6
MAX3107 toc01
3.4
3.2
3.0
(mA)
A
I
2.8
2.6
18
3.353.102.852.60
2.4
2.2
2.0
2.35 3.60
LDOEN = V
L
LDOEN = AGND
1.8V APPLIED TO V
EXTERNAL 614kHz CLOCK
BAUD RATE = 115kbps
6x PLL MULT.FACTOR
VA (V)
MAX3107 toc02
18
3.353.102.852.60
IA SUPPLY CURRENT vs. TEMPERATURE
140
120
MAX3107 toc04
L
3.353.102.60 2.85
100
80
(µA)
A
I
60
40
20
0
-40 85
VA = 3.3V
MAX3107 toc05
VA = 2.5V
EXTERNAL 3.6MHz CLOCK
BAUD RATE = 115kbps
603510-15
TEMPERATURE (°C)
IA SUPPLY CURRENT vs. VA VOLTAGE
(INTERNAL CLOCK, PLL ENABLED)
4.3
4.1
3.9
3.7
3.5
(mA)
A
I
3.3
3.1
2.9
2.7
2.5
2.35 3.60
LDOEN = V
L
LDOEN = AGND
1.8V APPLIED TO V
BAUD RATE = 115kbps
6x PLL MULT.FACTOR
VA (V)
18
IA SUPPLY CURRENT vs. PLL FREQUENCY
5.75
5.50
5.25
5.00
4.75
4.50
4.25
4.00
(mA)
A
3.75
I
3.50
3.25
3.00
2.75
2.50
2.25
2.00
10 100
PLL = x48
PLL = x96
PLL = x144
PLL FREQUENCY (MHz)
MAX3107 toc03
3.353.102.852.60
MAX3107 toc06
INTERNAL OSCILLATOR FREQUENCY
VA (V)
VOLTAGE
A
3.353.102.60 2.85
DEVIATION vs. V
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
INTERNAL OSCILLATOR FREQUENCY DEVIATION (%)
-0.4
2.35 3.60
______________________________________________________________________________________ 11
MAX3107 toc07
GPIO_ OUTPUT HIGH VOLTAGE
vs. SOURCE CURRENT (PUSH-PULL)
35
30
25
20
(mA)
15
SOURCE
I
10
5
0
0 3.5
V
= 2.5V
EXT
V
VOH (V)
EXT
= 3.3V
GPIO_ OUTPUT LOW VOLTAGE
vs. SINK CURRENT (OPEN DRAIN)
35
V
= 3.3V
EXT
30
MAX3107 toc08
25
20
(mA)
SINK
I
15
10
5
0
3.02.52.01.51.00.5
0 3
V
EXT
VOL (V)
= 2.5V
21
MAX3107 toc09
SPI/I2C UART with 128-Word FIFOs
and Internal Oscillator
Pin Configurations
TOP VIEW
MAX3107
V
EXT
XOUT
XIN
AGND
RX
18 17 16 15 14 13
19
TX
20
21
22
23
V
24
A
+
1 2 3 4 5 6
18
V
RTS/CLKOUT
CTS
MAX3107
LDOEN
I2C/SPI
TQFN
GPIO3
GPIO2
*EP
SCLK/SCL
DOUT/SDA
GPIO1
CS/A0
+
1
XIN
2
AGND
V
3
12
GPIO0
11
DGND
10
V
L
RST
9
IRQ
8
DIN/A1
7
V
I2C/SPI
LDOEN
DOUT/SDA
SCLK/SCL
CS/A0
DIN/A1
IRQ
RST
A
4
18
MAX3107
5
6
7
8
9
11
SSOP
24
XOUT
V
23
EXT
TX
22
RX
21
20
RTS/CLKOUT
CTS
19
18
GPIO3
GPIO2
17
16
GPIO1
1510GPIO0
DGND
14
1312V
L
(3.5mm × 3.5mm)
*CONNECT EP TO AGND.
Pin Descriptions
PIN
TQFN-EP SSOP
1 4 V
2 5
3 6 LDOEN
NAME FUNCTION
18
I2C/SPI
Internal 1.8V LDO Output and 1.8V Logic Supply Input. Bypass V18 with a 0.1FF
ceramic capacitor to AGND.
SPI or Active-Low I2C Selector Input. Drive I2C/SPI high to enable SPI. Drive I2C/SPI
low to enable I2C.
LDO Enable Input. Drive LDOEN high to enable the internal 1.8V LDO. Drive LDOEN
low to disable the internal LDO. When LDO is low, V
nal voltage source.
can be supplied by an exter-
18
Serial-Data Output. When I2C/SPI is high, DOUT/SDA functions as the DOUT SPI
4 7 DOUT/SDA
serial-data output. When I2C/SPI is low, DOUT/SDA functions as the SDA I2C serialdata input/output.
Serial-Clock Input. When I2C/SPI is high, SCLK/SCL functions as the SCLK SPI
5 8 SCLK/SCL
serial-clock input (up to 26MHz). When I2C/SPI is low, SCLK/SCL functions as the
SCL I2C serial-clock input (up to 400kHz).
Active-Low Chip-Select and Address 0 Input. When I2C/SPI is high, CS/A0 functions
6 9
CS/A0
as the CS SPI active-low chip select. When I2C/SPI is low, CS/A0 functions as the
A0 I2C device address programming input. Connect CS/A0 to DGND or VL.
12 _____________________________________________________________________________________
SPI/I2C UART with 128-Word FIFOs
and Internal Oscillator
Pin Descriptions (continued)
MAX3107
PIN
TQFN-EP SSOP
7 10 DIN/A1
8 11
9 12
10 13 V
11 14 DGND Digital Ground
12 15 GPIO0
13 16 GPIO1
14 17 GPIO2
15 18 GPIO3
16 19
17 20
18 21 RX Receive Input. Serial UART data input. RX has an internal weak pullup resistor to V
19 22 TX Transmit Output. Serial UART data output.
20 23 V
21 24 XOUT
22 1 XIN
23 2 AGND Analog Ground
24 3 V
— — EP
NAME FUNCTION
Serial-Data and Address 1 Input. When I2C/SPI is high, DIN/A1 functions as the DIN
SPI serial-data input. When I2C/SPI is low, DIN/A1 functions as the A1 I2C device
address programming input and connects to DIN/A1 DGND or VL.
IRQ
RST
L
CTS Active-Low Clear-to-Send Input. CTS is a flow-control input.
RTS/CLKOUT
EXT
A
Active-Low Interrupt Open-Drain Output. IRQ is asserted when an interrupt is
pending.
Active-Low Reset Input. Drive RST low to force the UART into hardware reset mode.
In hardware reset mode, the oscillator and the internal PLL are shut down; there is
no clock activity.
Digital Interface Logic-Level Supply. VL powers the internal logic-level translators for
RST, IRQ, DIN/A1, CS/A0, SCLK/SCL, DOUT/SDA, LDOEN, and I2C/SPI. Bypass VL
with a 0.1FF ceramic capacitor to DGND.
General-Purpose Input/Output 0. GPIO0 is user programmable as an input or output
(push-pull or open drain). GPIO0 has a weak pulldown resistor to ground.
General-Purpose Input/Output 1. GPIO1 is user programmable as an input or output
(push-pull or open drain). GPIO1 has a weak pulldown resistor to ground.
General-Purpose Input/Output 2. GPIO2 is user programmable as an input or output
(push-pull or open drain). GPIO2 has a weak pulldown resistor to ground.
General-Purpose Input/Output 3. GPIO3 is user programmable as an input or output
(push-pull or open drain). GPIO3 has a weak pulldown resistor to ground.
Active-Low Request-to-Send Output. RTS/CLKOUT can be set high or low by programming bit 7 (RTS) of the LCR register.
Transceiver Interface Level Supply. V
for RX, TX, RTS, CTS, and GPIO_. Bypass V
DGND.
Crystal Output. When using an external crystal, connect one end of the crystal to
XOUT and the other to XIN. When using an external clock source or the internal
oscillator, leave XOUT unconnected.
Crystal/Clock Input. When using an external crystal, connect one end of the crystal
to XIN and the other one to XOUT. When using an external clock source, drive XIN
with the external clock. When using the internal oscillator, leave XIN unconnected.
Analog Supply. VA powers the internal oscillators, PLL, and internal LDO. Bypass
VA with a 0.1FF ceramic capacitor to AGND.
Exposed Paddle. Connect EP to AGND. EP is not intended as an electrical connection point. Only for TQFN-EP package.
powers the internal logic-level translators
EXT
with a 0.1FF ceramic capacitor to
EXT
EXT
.
______________________________________________________________________________________ 13
SPI/I2C UART with 128-Word FIFOs
and Internal Oscillator
Register Map
(All default reset values are 0x00, unless otherwise noted. All registers are R/W, unless otherwise noted.)
REGISTER ADDR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
FIFO DATA
†
RHR
†
THR
INTERRUPTS
MAX3107
IRQEn 0x01 CTSIEn RxEmtyIEn TxEmtyIEn TxTrgIEn RxTrgIEn STSIEn SpclChrIEn LSRErrIEn
*†
ISR
LSRIntEn 0x03 — — NoiseIntEn RBreakIEn FrameErrIEn ParityIEn ROverrIEn RTimoutIEn
*†
LSR
SpclChrIntEn 0x05 — — MltDrpIntEn BREAKIntEn XOFF2IntEn XOFF1IntEn XON2IntEn XON1IntEn
SpclCharInt
STSIntEn 0x07 — SleepIntEn ClkRdyIntEn — GPI3IntEn GPI2IntEn GPI1IntEn GPI0IntEn
*†
STSInt
UART MODES
MODE1 0x09 IRQSel AutoSleep ForcedSleep TrnscvCtrl RTSHiZ TXHiZ TxDisabl RxDisabl
MODE2 0x0A EchoSuprs MultiDrop Loopback SpecialChr RxEmtyInv RxTrigInv FIFORst RST
*
LCR
RxTimeOut 0x0C TimOut7 TimOut6 TimOut5 TimOut4 TimOut3 TimOut2 TimOut1 TimOut0
HDplxDelay 0x0D Setup3 Setup2 Setup1 Setup0 Hold3 Hold2 Hold1 Hold0
IrDA 0x0E — — TxInv RxInv MIR ShortIR SIR IrDAEn
FIFO CONTROL
FlowLvl 0x0F Resume3 Resume2 Resume1 Resume0 Halt3 Halt2 Halt1 Halt0
FIFOTrgLvl
TxFIFOLvl
RxFIFOLvl
FLOW CONTROL
FlowCtrl 0x13 SwFlow3 SwFlow2 SwFlow1 SwFlow0 SwFlowEn GPIAddr AutoCTS AutoRTS
XON1 0x14 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
XON2 0x15 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
XOFF1 0x16 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
XOFF2 0x17 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
GPIOs
GPIOConfg 0x18 GP3OD GP2OD GP1OD GP0OD GP3Out GP2Out GP1Out GP0Out
GPIOData 0x19 GPI3Dat GPI2Dat GPI1Dat GPI0Dat GPO3Dat GPO2Dat GPO1Dat GPO0Dat
CLOCK CONFIGURATION
PLLConfig* 0x1A PLLFactor1 PLLFactor0 PreDiv5 PreDiv4 PreDiv3 PreDiv2 PreDiv1 PreDiv0
BRGConfig 0x1B — — 4xMode 2xMode FRACT3 FRACT2 FRACT1 FRACT0
DIVLSB 0x1C Div7 Div6 Div5 Div4 Div3 Div2 Div1 Div0
DIVMSB 0x1D Div15 Div14 Div13 Div12 Div11 Div10 Div9 Div8
CLKSource
REVISION
*†
RevID
*Denotes nonzero default reset value: ISR = 0x60, LCR = 0x05, FIFOTrgLvl = 0xFF, PLLConfig = 0x01, DIVLSB = 0x01,
CLKSource = 0x08, RevID = 0xA1.
†Denotes nonread/write value: RHR = R, THR = W, ISR = COR, SpclCharInt = COR, STSInt = R/COR, LSR = R, TxFIFOLvl = R,
RxFIFOLvl = R, RevID = R.
0x00 RData7 RData6 RData5 RData4 RData3 RData2 RData1 RData0
0x00 TData7 TData6 TData5 TData4 TData3 TData2 TData1 TData0
0x02 CTSInt RxEmptyInt TxEmptyInt TFifoTriglnt RFifoTrigInt STSInt SpCharInt LSRErrInt
0x04
†
0x06 — — MultiDropInt BREAKInt XOFF2Int XOFF1Int XON2Int XON1Int
0x08 — SleepInt ClockReady — GPI3Int GPI2Int GPI1Int GPI0Int
0x0B
*
0x10 RxTrig3 RxTrig2 RxTrig1 RxTrig0 TxTrig3 TxTrig2 TxTrig1 TxTrig0
†
0x11 TxFL7 TxFL6 TxFL5 TxFL4 TxFL3 TxFL2 TxFL1 TxFL0
†
0x12 RxFL7 RxFL6 RxFL5 RxFL4 RxFL3 RxFL2 RxFL1 RxFL0
*
0x1E CLKtoRTS — —- ExtClock PLLBypass PLLEn CrystalEn IntOscEn
0x1F 1 0 1 0 0 0 0 1
CTSbit
RTS
— RxNoise RxBreak FrameErr RxParityErr RxOverrun RTimeout
TxBreak ForceParity EvenParity ParityEn StopBits Length1 Length0
14 _____________________________________________________________________________________
SPI/I2C UART with 128-Word FIFOs
Detailed Description
The MAX3107 UART is a bridge between an SPI/
MICROWIRE™ or I2C microprocessor bus and an
asynchronous serial-data communication link, such as
RS-485, RS-232, or IrDA. The MAX3107 contains an
advanced UART, a fractional baud-rate generator, and
four GPIOs. The MAX3107 is configured and monitored,
and data is written and read from 8-bit registers through
SPI or I2C. These registers are organized by related
function as shown in the Register Map.
The host controller loads and transmits data into the
Transmit Holding register (THR) through SPI or I2C. This
data is automatically pushed into the transmit FIFO and
sent out at TX. The MAX3107 adds START, STOP, and
parity bits to the data and sends the data out at the
selected baud rate. The clock configuration registers
determine the baud rate, clock source selection, and
clock frequency prescaling.
The receiver in the MAX3107 detects a START bit as a
high-to-low RX transition. An internal clock samples this
data. The received data is automatically placed in the
receive FIFO and can then be read out of the RxFIFO
through the RHR.
Register Set
The MAX3107 has a flat register structure without shadow registers. The registers are 8 bits wide. The MAX3107
registers have some similarities to the 16C550 registers.
Receive and Transmit FIFOs
The UART’s receiver and the transmitter each have a
128-word deep FIFO, reducing the intervals that the host
processor needs to dedicate for high-speed, high-volume data transfer. As the data rates of the asynchronous
RX, TX interfaces increase and get closer to those of the
host controller’s SPI/I2C data rates, UART management
and flow control can make up a significant portion of the
host’s activity. By increasing FIFO size, the host is interrupted less often and can utilize SPI/I2C burst data block
transfers to/from the FIFOs.
FIFO trigger levels can generate interrupts to the host
controller, signaling that programmed FIFO fill levels
have been reached. The transmitter and receiver trigger levels are programmed through FIFOTrgLvl with a
resolution of eight FIFO locations. When a receive FIFO
trigger is generated, the host knows that the receive
FIFO has a defined number of words waiting to be read
out or that a known number of vacant FIFO locations are
and Internal Oscillator
available and ready to be filled. The transmit FIFO trigger generates an interrupt when the transmit FIFO level
is above the programmed trigger level. The host then
knows to throttle data writing to the transmit FIFO.
The host can read out the number of words present in each
of the FIFOs through the TxFIFOLvl and RxFIFOLvl registers.
Transmitter Operation
Figure 3 shows the structure of the transmitter with the
TxFIFO. The transmit FIFO can hold up to 128 words that
are written to it through THR.
The current number of words in the TxFIFO can be read
out through the TxFIFOLvl register. The transmit FIFO
can be programmed to generate an interrupt when a
programmed number of words are present in the TxFIFO
through the FIFOTrgLvl register. The TxFIFO interrupt
trigger level is selectable through FIFOTrgLvl[3:0]. When
the transmit FIFO fill level reaches the programmed trigger level, the ISR[4] interrupt is set.
The transmit FIFO is empty when ISR[5]: TxEmtyInt is set.
ISR[5] turns high when the transmitter starts transmitting the last word in the TxFIFO. Hence, the transmitter
is completely empty after ISR[5] is set with an additional delay equal to the length of a complete character
(including START, parity, and STOP bits).
The contents of the TxFIFO and RxFIFOs are both
cleared through MODE2[1]: FIFORst.
2
TRIGGER
LEVEL
EMPTY
C INTERFACE
CURRENT FILL LEVEL
THR
FIFOTrgLvl[3:0]
TRANSMIT FIFO
TRANSMITTER TX
128
3
2
1
DATA FROM SPI/I
ISR[4]
TxFIFOLvl
ISR[5]
Figure 3. Transmit FIFO Signals
MAX3107
MICROWIRE is a trademark of National Semiconductor Corp.
______________________________________________________________________________________ 15
SPI/I2C UART with 128-Word FIFOs
and Internal Oscillator
LSB
RECEIVED DATA
MIDDATA
SAMPLING
Figure 4. Receive Data Format
START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP STOP
MAX3107
RX
BAUD
BLOCK
Figure 5. Midbit Sampling
To halt transmission, set MODE1[1]: TxDisabl to 1. After
MODE1[1] is set, the transmitter completes transmission
of the current character and then ceases transmission.
The TX output logic can be inverted through IrDA[5]:
TxInv. If not stated otherwise, all transmitter logic
described in this data sheet assumes IrDA[5] is 0.
The receiver expects the format of the data at RX to be
as shown in Figure 4. The quiescent logic state is a high
and the first bit (the START bit) is logic-low. The receiver
samples the data near the midbit instant (Figure 4). The
received words and their associated errors are deposited into the receive FIFO. Errors and status information
are stored for every received word (Figure 6). The host
reads data out of the receive FIFO through the Receive
Holding register (RHR), oldest data first. The status
information of the current word in the RHR is located in
the Line Status register (LSR). After a word is read out
of the RHR, the LSR contains the status information for
that word.
The following three error conditions are determined for
each received word: parity error, framing error, and
noise on the line. Line noise is detected by checking the
consistency of the logic of the three samples (Figure 5).
The receiver can be turned off through MODE1[0]:
RxDisabl. When this bit is set to 1, the MAX3107 turns the
receiver off immediately following the current word and
A
1
2 3 4 5 6 7 8 9
Receiver Operation
MSB
ONE BIT PERIOD
10 11
MAJORITY
CENTER
SAMPLER
12 13 14 15 16
does not receive any further data. The RX input logic can
be inverted through IrDA[4]: RxInv.
Line Noise Indication
When operating in standard (i.e., not 2x or 4x rate) mode,
the MAX3107 checks that the binary logic level of the
three samples per received bit are identical. If any of
the three samples have differing logic levels, then noise
on the transmission line has affected the received data
and is considered to be noisy. This noise indication is
reflected in the LSR[5]: RxNoise bit for each received
byte. Parity errors are another indication of noise, but are
not as sensitive.
Clocking and Baud-Rate Generation
The MAX3107 can be clocked by its internal oscillator,
an external crystal, or an external clock source. Figure 7
shows a simplified diagram of the clocking circuitry.
When the MAX3107 is clocked by the internal oscillator
or a crystal, the STSInt[5]: ClockReady indicates when
the clocks have settled and the baud-rate generator is
ready for stable operation.
The baud-rate clock can be routed to the RTS/CLKOUT
output. The clock rate is 16x the baud rate in standard
operating mode, and 8x the baud rate in 2x rate mode.
In 4x rate mode, the CLKOUT frequency is 4x the
programmed baud rate. If the fractional portion of the
baud-rate generator is used, the clock is not regular and
exhibits jitter.
16 _____________________________________________________________________________________
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