Rainbow Electronics MAX2769B User Manual

E V A L U A T I O N K IT A V A I L A B L E

19-5875; Rev 1; 8/11

MAX2769B

Universal GPS Receiver

General Description

The MAX2769B is a next-generation Global Navigation Satellite System (GNSS) receiver covering GPS, GLONASS, Galileo, and Compass navigation satellite systems on a single chip. This single-conversion GNSS receiver is designed to provide high performance for industrial and automotive applications.

Designed on Maxim’s advanced, low-power SiGe BiCMOS process technology, the MAX2769B offers the highest performance and integration at a low cost. Incorporated on the chip is the complete receiver chain, including a dual-input LNA and mixer, followed by the image-rejected filter, PGA, VCO, fractional-N frequency synthesizer, crystal oscillator, and a multibit ADC. The total cascaded noise figure of this receiver is as low as 1.4dB.

The MAX2769B completely eliminates the need for external IF filters by implementing on-chip monolithic filters and requires only a few external components to form a com plete low-cost GPS RF receiver solution.

The MAX2769B is the most flexible receiver on the market. The integrated delta-sigma fractional-N frequency synthesizer allows programming of the IF frequency within a ±30Hz (f

= 32MHz) accuracy while operat-

XTAL

ing with any reference or crystal frequencies that are available in the host system. The ADC outputs CMOS logic levels with 1 or 2 quantized bits for both I and Q channels, or up to 3 quantized bits for the I channel. I and Q analog outputs are also available.

The MAX2769B is packaged in a 5mm x 5mm, 28-pin thin QFN package with an exposed paddle.

Applications

Automotive Navigation Systems

Location-Enabled Mobile Handsets

PNDs (Personal Navigation Devices)

Telematics (Asset Tracking, Inventory Management)

Marine/Avionics Navigation

Software GPS

Laptops and Netbooks

For related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX2769B.related.

Features

S AEC-Q100 Automotive Qualified

S GPS/GLONASS/Galileo/Compass Systems

S 40pF Output Clock Drive Capability

S No External IF SAW or Discrete Filters Required

S Programmable IF Frequency

S Fractional-N Synthesizer with Integrated VCO

Supports Wide Range of Reference Frequencies

S Dual-Input Uncommitted LNA for Separate Passive

and Active Antenna Inputs

S 1.4dB Cascade Noise Figure

S Integrated Crystal Oscillator

S Integrated Active Antenna Sensor

S 2.7V to 3.3V Supply Voltage

S Small, 28-Pin, RoHS-Compliant, Thin QFN Lead-

Free Package (5mm x 5mm)

Ordering Information appears at end of data sheet.

Block Diagram

CC_ADC

V

N.C.

CC_IF

IDLE

LNA2

PGM

LNA1

N.C.

I0

20

21

22

+

1

ANTFLAG

ADC

MAX2769B

FILTER

LNA2

LNA1

2

LNAOUT

23

24

25

26

27

28

Q0

V

19 17 16

3 5

ANTBIAS

Q1I1CLKOUT

18

ADC

PLL

900

4 6

CC_RF

MIXIN

V

VCO

3-WIRE

INTERFACE

LD

XTAL

15

V

14

CCD

V

13

CC_CP

CPOUT

12

V

11

CC_VCO

10

CS

9

SCLK

8

SDATA

7

SHDN

�� Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

MAX2769B

Universal GPS Receiver

ABSOLUTE MAXIMUM RATINGS

V

to Ground ....................................................-0.3V to +4.2V

CC_

Other Pins Except LNA_, MIXIN, XTAL, and LNAOUT to

Ground............................. -0.3V to +(Operating V

Maximum RF Input Power ............................................. +15dBm

Continuous Power Dissipation (TA = +70NC)

TQFN (derates 27mW/NC above +70NC) ...................2500mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

CAUTION! ESD SENSITIVE DEVICE

CC_

+ 0.3V)

DC ELECTRICAL CHARACTERISTICS

(MAX2769B EV kit, V values are at V

Supply Voltage 2.7 2.85 3.3 V

Supply Current

Voltage Drop at ANTBIAS from V

CC_RF

Short-Circuit Protection Current at ANTBIAS

Active Antenna Detection Current To assert logic-high at ANTFLAG 1.1 mA

DIGITAL INPUT AND OUTPUT

Digital Input Logic-High Digital Input Logic-Low

CC_

PARAMETER CONDITIONS MIN TYP MAX UNITS

= 2.7V to 3.3V, TA = -40NC to +85NC, PGM = Ground. Registers are set to the default power-up states. Typical

CC_

= 2.85V and TA = +25NC, unless otherwise noted.) (Note 1)

Default mode, LNA1 is active (Note 2) 18 27 31

Idle ModeK, IDLE = low, SHDN = high Shutdown mode, SHDN = low

Sourcing 20mA at ANTBIAS 0.2 V

ANTBIAS is shorted to ground 57 mA

Measure at the SHDN pin Measure at the SHDN pin

Operating Temperature Range .......................... -40NC to +85NC

Junction Temperature .....................................................+150NC

Storage Temperature Range ............................ -65NC to +150NC

Lead Temperature (soldering, 10s) ................................+300NC

Soldering Temperature (reflow) ......................................+260NC

mADefault mode, LNA2 is active (Note 2) 15 25 30.5

5

200

1.5 V

0.4 V

FA

Idle Mode is a trademark of Maxim Integrated Products, Inc.

�� Maxim Integrated Products 2

*The parametric values (min, typ, max limits) shown in the Electrical Characteristics table supersede values quoted elsewhere in this data sheet.

MAX2769B

Universal GPS Receiver

AC ELECTRICAL CHARACTERISTICS*

(MAX2769B EV kit, V input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical values are at V

CASCADED RF PERFORMANCE

RF Frequency L1 band 1575.42 MHz

Noise Figure

Out-of-Band 3rd-Order Input Intercept Point

In-Band Mixer Input Referred 1dB Compression Point

Mixer Input Return Loss 10 dB Image Rejection 25 dB

Spurs at LNA1 Input

Maximum Voltage Gain Measured from the mixer to the baseband analog output 91 96 103 dB Variable Gain Range 55 59 dB

FILTER RESPONSE

Passband Center Frequency

Passband 3dB Bandwidth

Lowpass 3dB Bandwidth FBW = 11 9 MHz

Stopband Attenuation

LNA LNA1 INPUT

Power Gain 19 dB Noise Figure 0.83 dB Input IP3 (Note 5) -1.1 dBm Output Return Loss 10 dB Intput Return Loss 8 dB

CC_

PARAMETER CONDITIONS MIN TYP MAX UNITS

= 2.7V to 3.3V, TA = -40NC to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA

CC_

= 2.85V and TA = +25NC, unless otherwise noted.) (Note 1)

LNA1 input active, default mode (Note 3) 1.4

Measured at the mixer input 10.3

Measured at the mixer input (Note 4) -7 dBm

Measured at the mixer input -85 dBm

LO leakage -101 Reference harmonics leakage -103

FBW = 00 4

FBW = 01 9.27 FBW = 00 2.5

FBW = 01 9.66

3rd-order filter, bandwidth = 2.5MHz, measured at 4MHz offset 30 5th-order filter, bandwidth = 2.5MHz, measured at 4MHz offset 40 49.5

dBLNA2 input active, default mode (Note 3) 2.7

dBm

MHzFBW = 10 4

MHzFBW = 10 4.2

dB

�� Maxim Integrated Products 3

*The parametric values (min, typ, max limits) shown in the Electrical Characteristics table supersede values quoted elsewhere in this data sheet.

MAX2769B

Universal GPS Receiver

AC ELECTRICAL CHARACTERISTICS* (continued)

(MAX2769B EV kit, V input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical values are at V

LNA2 INPUT

Power Gain 13 dB Noise Figure 1.14 dB Input IP3 (Note 5) 1 dBm Output Return Loss 19 dB Input Return Loss 11 dB

FREQUENCY SYNTHESIZER

LO Frequency Range 0.2V < V

LO Tuning Gain 57 MHz/V Reference Input Frequency 8 44 MHz Main Divider Ratio 36 32,767 — Reference Divider Ratio 1 1023 —

Charge-Pump Current

TCXO INPUT BUFFER/OUTPUT CLOCK BUFFER

Frequency Range 8 32 MHz

Output Logic-Level High (VOH)

Output Logic-Level Low (VOL)

Capacitive Slew Current

Output Load 10||40 Reference Input Level Sine wave 0.5 V

Clock Output Multiply/Divide Range

ADC

ADC Differential Nonlinearity AGC enabled, 3-bit output ADC Integral Nonlinearity AGC enabled, 3-bit output

Note 1: MAX2769B is production tested at TA = +25NC and +85NC. All min/max specifications are guaranteed by design and char-

Note 2: Default, low-NF mode of the IC. LNA choice is gated by the ANT_FLAG signal. In the normal mode of operation without an

Note 3: The LNA output connects to the mixer input without a SAW filter between them. Note 4: Two tones are located at 12MHz and 24MHz offset frequencies from the GPS center frequency of 1575.42MHz at -60dBm/

Note 5: Measured from the LNA input to the LNA output. Two tones are located at 12MHz and 24MHz offset frequencies from the

CC_

PARAMETER CONDITIONS MIN TYP MAX UNITS

acterization from -40NC to +85NC, unless otherwise noted. Default register settings are not production tested or guaranteed. User must program the registers upon power-up.

active antenna, LNA1 is active. If an active antenna is connected and ANT_FLAG switches to 1, LNA1 is automatically disabled and LNA2 becomes active. PLL is in an integer-N mode with f complex IF filter is configured as a 5th-order Butterworth filter with a center frequency of 4MHz and bandwidth of 2.5MHz. Output data is in a 2-bit sign/magnitude format at CMOS logic levels in the I channel only.

tone. Passive pole at the mixer output is programmed to be 13MHz.

GPS center frequency of 1575.42MHz at -60dBm per tone.

= 2.7V to 3.3V, TA = -40NC to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA

CC_

= 2.85V and TA = +25NC, unless otherwise noted.) (Note 1)

< (V

TUNE

ICP = 0 0.5 ICP = 1 1

With respect to ground, IOH = 10FA (DC-coupled)

With respect to ground, IOL = 10FA (DC-coupled)

Load = 10kW + 40pF, f

/4, /2, /1 (x2, max input frequency of 16MHz)

- 0.3V) 1550 1610 MHz

CC_

2 V

0.8 V

CLKOUT

= 32MHz

COMP

= f

÷4 x2 —

/16 = 1.023MHz and ICP = 0.5mA. The

TCXO

11 mA

Q0.1 Q0.1

mA

kI||pF

P-P

LSB LSB

�� Maxim Integrated Products 4

*The parametric values (min, typ, max limits) shown in the Electrical Characteristics table supersede values quoted elsewhere in this data sheet.

MAX2769B

Universal GPS Receiver

Typical Operating Characteristics

(MAX2769B EV kit, V

= 2.7V to 3.3V, TA = -40°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA

CC_

input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical

values are at V

CASCADED RECEIVER GAIN

120

100

TA = +25°C

80

60

CASCADED RECEIVER GAIN (dB)

40

0 65

PGA GAIN CODE (DECIMAL FORMAT)

LNA1 GAIN AND NOISE FIGURE

vs. LNA1 BIAS DIGITAL CODE

1.6

1.4

1.2

1.0

0.8

0.6

NOISE FIGURE (dB)

0.4

0.2

0

1 15

LNA BIAS DIGITAL CODE (DECIMAL)

= 2.85V and TA = +25NC, unless otherwise noted.)

CC_

CASCADED GAIN AND NOISE FIGURE

vs. PGA GAIN CODE

2.0

TA = -40°C

TA = +85°C

MAX2769B toc04

GAIN

NOISE FIGURE

MAX2769B toc01

60555045403530252015105

25

20

15

10

5

0

14132 3 4 6 7 8 9 10 115 12

1.5

1.0

NOISE FIGURE (dB)

0.5

0

-40 85

1.4

1.2

1.0

0.8

0.6

LNA1 GAIN (dB)

NOISE FIGURE (dB)

0.4

0.2

0

-40 85

vs. TEMPERATURE

AGC GAIN

NOISE FIGURE

TEMPERATURE (°C)

LNA1 GAIN AND NOISE FIGURE

vs. TEMPERATURE

LNA BIAS = 1000

NOISE FIGURE

TEMPERATURE (°C)

GAIN

MAX2769B toc02

603510-15

MAX2769B toc05

603510-15

120

115

110

105

100

95

90

19.6

19.4

19.2

19.0

18.8

18.6

18.4

18.2

18.0

17.8

LNA1 |S21| AND |S12|

vs. FREQUENCY

40

30

20

10

0

-10

CASCADED GAIN

-20

LNA1 |S21| AND |S12| (dB)

-30

-40

-50

0.50 2.50

|S21|

|S12|

FREQUENCY (GHz)

LNA1 INPUT 1dB COMPRESSION POINT

vs. LNA1 BIAS DIGITAL CODE

5.0

2.5

0

-2.5

-5.0

-7.5

LNA1 GAIN (dB)

-10.0

-12.5

LNA1 INPUT 1dB COMPRESSION POINT (dBm)

-15.0 1 15

LNA BIAS DIGITAL CODE (DECIMAL)

MAX2769B toc03

2.252.001.50 1.751.00 1.250.75

MAX2769B toc06

14132 3 4 6 7 8 9 10 115 12

�� Maxim Integrated Products 5

MAX2769B

Universal GPS Receiver

Typical Operating Characteristics (continued)

(MAX2769B EV kit, V

= 2.7V to 3.3V, TA = -40°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA

CC_

input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical

values are at V

30

20

10

0

-10

-20

LNA2 |S21| AND |S12| (dB)

-30

-40

-50

0.50 2.50

= 2.85V and TA = +25NC, unless otherwise noted.)

CC_

LNA2 |S21| AND |S12|

LNA2 GAIN AND NOISE FIGURE

vs. FREQUENCY

2.0

|S21|

MAX2769B toc07

|S12|

2.252.000.75 1.00 1.25 1.50 1.75

FREQUENCY (GHz)

LNA BIAS = 10

1.8

1.6

1.4

1.2

1.0

0.8

NOISE FIGURE (dB)

NOISE FIGURE

0.6

0.4

0.2

0

-40 85

LNA OUTPUT RETURN LOSS

vs. FREQUENCY

0

-5

LNA1

-10

-15

LNA OUTPUT RETURN LOSS (dB)

-20

LNA2

1.0 2.2 FREQUENCY (GHz)

MAX2769B toc10

2.12.01.91.81.71.61.51.41.31.21.1

vs. TEMPERATURE

GAIN

TEMPERATURE (°C)

MAX2769B toc08

603510-15

13.6

13.4

13.2

13.0

12.8

12.6

12.4

12.2

LNA2 GAIN (dB)

MIXER INPUT REFERRED IP1dB

0

-10

-20

-30

-40

-50

-60

-70

MIXER INPUT REFERRED IP1dB (dB)

-80

-90 0 300

LNA INPUT RETURN LOSS

vs. FREQUENCY

0

LNA1

-10

-20

-30

LNA INPUT RETURN LOSS (dB)

-40

-50

1.0 2.2

LNA2

FREQUENCY (GHz)

vs. OFFSET FREQUENCY

PGA GAIN = 32dB

PGA GAIN = 51dB

PRF = -100dBm

25020015010050

OFFSET FREQUENCY (MHz)

2.12.01.91.81.71.61.51.41.31.21.1

MAX2769B toc11

MAX2769B toc09

�� Maxim Integrated Products 6

MAX2769B

MAGNITUDE (dB)

Universal GPS Receiver

Typical Operating Characteristics (continued)

(MAX2769B EV kit, V

= 2.7V to 3.3V, TA = -40°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA

CC_

input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical

values are at V

0

-5

-10

JAMMER POWER (dBm)

-15

-20 800 950

3RD-ORDER POLYPHASE FILTER MAGNITUDE

RESPONSE vs. BASEBAND FREQUENCY

10

FBW = 00b

0

-10

-20

-30

-40

-50

-60 1 10

= 2.85V and TA = +25NC, unless otherwise noted.)

CC_

1dB CASCADED NOISE FIGURE DESENSITIZATION vs. JAMMER FREQUENCY

MAX2769B toc12a

925900875850825 JAMMER FREQUENCY (MHz)

MAX2769B toc12b

205020001950190018501800 2100

5TH-ORDER POLYPHASE FILTER MAGNITUDE

RESPONSE vs. BASEBAND FREQUENCY

10

FBW = 00b

0

MAX2769B toc14

-10

-20

-30

-40

MAGNITUDE (dB)

-50

-60

98765432

BASEBAND FREQUENCY (MHz)

-70 1 10

BASEBAND FREQUENCY (MHz)

MIXER INPUT REFERRED NOISE FIGURE

vs. PGA GAIN

16

14

12

10

8

MIXER INPUT REFERRED NOISE FIGURE (dB)

6

5 65

PGA GAIN (dB)

5545352515

MIXER INPUT REFERRED GAIN

vs. PGA GAIN CODE

100

MAX2769B toc15

80

60

40

MIXER INPUT REFERRED GAIN (dB)

98765432

20

0 65

TA = -40°C

TA = +25°C

TA = +85°C

60555045403530252015105

PGA GAIN CODE (DECIMAL FORMAT)

MAX2769B toc13

MAX2769B toc16

�� Maxim Integrated Products 7

MAX2769B

Universal GPS Receiver

Typical Operating Characteristics (continued)

(MAX2769B EV kit, V

= 2.7V to 3.3V, TA = -40°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA

CC_

input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical

values are at V

vs. BASEBAND FREQUENCY (FBW = 01)

10

0

-10

-20

-30

-40

FREQUENCY RESPONSE (dB)

-50

-60 0 20

= 2.85V and TA = +25NC, unless otherwise noted.)

CC_

3RD-ORDER POLYPHASE FILTER

10

MAX2769B toc17

18161412108642

FREQUENCY (MHz)

0

-10

-20

-30

-40

FREQUENCY RESPONSE (dB)

-50

-60

5TH-ORDER POLYPHASE FILTER

vs. BASEBAND FREQUENCY (FBW = 01)

0 20

FREQUENCY (MHz)

18161412108642

vs. BASEBAND FREQUENCY (FBW = 10)

10

MAX2769B toc18

0

-10

-20

-30

-40

FREQUENCY RESPONSE (dB)

-50

-60 0 20

3RD-ORDER POLYPHASE FILTER

18161412108642

FREQUENCY (MHz)

5TH-ORDER POLYPHASE FILTER

vs. BASEBAND FREQUENCY (FBW = 10)

10

0

-10

-20

-30

-40

FREQUENCY RESPONSE (dB)

-50

-60 0 20

FREQUENCY (MHz)

3.5

3.0

MAX2769B toc20

2.5

2.0

1.5

1.0

CODE (DECIMAL VALUE)

0.5

18161412108642

-0.5

2-BIT ADC TRANSFER CURVE

0

-1.0 1.0 DIFFERENTIAL VOLTAGE (V)

0.80.6-0.8 -0.6 -0.4 0 0.2-0.2 0.4

7

6

MAX2769B toc21

5

4

3

2

CODE (DECIMAL VALUE)

1

0

-1.0 1.0

3-BIT ADC TRANSFER CURVE

0.80.6-0.8 -0.6 -0.4 0 0.2-0.2 0.4

DIFFERENTIAL VOLTAGE (V)

MAX2769B toc19

MAX2769B toc22

�� Maxim Integrated Products 8

MAX2769B

Universal GPS Receiver

Typical Operating Characteristics (continued)

(MAX2769B EV kit, V

= 2.7V to 3.3V, TA = -40°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA

CC_

input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical

values are at V

= 2.85V and TA = +25NC, unless otherwise noted.)

CC_

CRYSTAL OSCILLATOR FREQUENCY

DIGITAL OUTPUT CMOS LOGIC

20ns/div

MAX2769B toc23

CRYSTAL OSCILLATOR FREQUENCY

VARIATION vs. TEMPERATURE

10

8

6

4

2

0

-2

-4

-6

-8

-10

CRYSTAL OSCILLATOR FREQUENCY VARIATION (ppm)

-40 85 TEMPERATURE (°C)

603510-15

DIGITAL OUTPUT DIFFERENTIAL LOGIC

CLK 2V/div

SIGN DATA 2V/div

MAGNITUDE DATA 2V/div

TEMPERATURE SENSOR VOLTAGE

2.0

MAX2769B toc26

1.8

1.6

1.4

1.2

1.0

0.8

TEMPERATURE SENSOR VOLTAGE (V)

0.6

0.4

-40 85

40ns/div

vs. TEMPERATURE

TEMPERATURE (°C)

MAX2769B toc24

6035-15 10

16,368.10

CLK 1V/div

SIGN+ 1V/div

SIGN1V/div

MAX2769B toc27

16,368.05

16,368.00

16,367.95

16,367.90

CRYSTAL OSCILLATOR FREQUENCY (kHz)

16,367.85

vs. DIGITAL TUNING CODE

TA = +25°C

TA = -40°C

TA = +85°C

0 32

DIGITAL TUNING CODE (DECIMAL)

CLOCK OUTPUT DRIVER WITH

40pF LOAD

20ns/div

MAX2769B toc28

MAX2769B toc25

282420161284

�� Maxim Integrated Products 9

MAX2769B

Universal GPS Receiver

Typical Application Circuit

BASEBAND

OUTPUT

BASEBAND

CLOCK

REFERENCE

INPUT

C11

PLL

C10

VCO

3-WIRE

INTERFACE

LD

XTAL

15

7

SHDN

C6

V

CCD

14

V

CC_CP

13

CPOUT

12

V

CC_VCO

11

10

CS

9

SCLK

8

SDATA

SERIAL INPUT

C5

C1

C4

C2

TOP VIEW

I0

20

21

N.C.

V

CC_IF

IDLE

LNA2

PGM

LNA1

N.C.

22

+

1

ANTFLAG

ADC

MAX2769B

LNA2

LNA1

2

LNAOUT

23

24

25

26

27

28

C8

C9

C0

C7

CC_ADC

Q0

V

19 17 16

FILTER

3 5

ANTBIAS

Q1I1CLKOUT

18

ADC

900

4 6

CC_RF

MIXIN

V

C3 C13

ACTIVE

ANTENNA BIAS

C12

Table 1. Component List

DESIGNATION QUANTITY DESCRIPTION

C0, C9 2 0.47nF AC-coupling capacitors

C1 1 27pF PLL loop filter capacitor C2 1 0.47nF PLL loop filter capacitor

C3–C8 6

C10, C11 2 10nF AC-coupling capacitor

C12 1 0.47nF AC-coupling capacitor C13 1 0.1nF supply voltage bypass capacitor

R1 1

�� Maxim Integrated Products 10

0.1FF supply voltage bypass capacitor

20kI PLL loop filter resistor

MAX2769B

Universal GPS Receiver

Pin Configuration

TOP VIEW

V

N.C.

CC_IF

IDLE

LNA2

PGM

LNA1

N.C.

22

23

24

25

26

27

+

28

1 2

ANTFLAG

CC_ADC

V

I0

Q0

Q1I1CLKOUT

2021 19 17 16 15

18

MAX2769B

EP

4 5 6 7

3

LD

CC_RF

MIXIN

V

LNAOUT

ANTBIAS

XTAL

SHDN

14

V

CCD

V

13

CC_CP

12

CPOUT

V

11

CC_VCO

10

CS

SCLK

9

8

SDATA

TQFN

Pin Description

PIN NAME FUNCTION

1 ANTFLAG

2 LNAOUT 3 ANTBIAS Buffered Supply Voltage Output. Provides a supply voltage bias for an external active antenna.

4 V

CC_RF

5 MIXIN 6 LD Lock-Detector CMOS Logic Output. A logic-high indicates the PLL is locked. 7

SHDN

8 SDATA Data Digital Input of 3-Wire Serial Interface

9 SCLK

Active Antenna Flag Logic Output. A logic-high indicates that an active antenna is connected to the ANTBIAS pin.

LNA Output. The LNA output is internally matched to 50I.

RF Section Supply Voltage. Bypass to ground with 100nF and 100pF capacitors in parallel as close as possible to the pin.

Mixer Input. The mixer input is internally matched to 50I.

Operation Control Logic Input. A logic-low shuts off the entire device.

Clock Digital Input of 3-Wire Serial Interface. Active when CS is low. Data is clocked in on the rising edge of the SCLK.

�� Maxim Integrated Products 11

MAX2769B

Universal GPS Receiver

Pin Description (continued)

PIN NAME FUNCTION

10

11 V

12 CPOUT

13 V

14 V

15 XTAL XTAL or Reference Oscillator Input. Connect to XTAL or a DC-blocking capacitor if TCXO is used. 16 CLKOUT Reference Clock Output 17 Q1 18 Q0 19 V 20 I0 21 I1 22 N.C. No Connection. Leave this pin unconnected. 23 V

24

25 LNA2

26 PGM

27 LNA1

28 N.C. No connection. Leave this pin open.

— EP

CS

CC_VCO

CC_CP

CCD

CC_ADC

CC_IF

IDLE

Chip-Select Logic Input of 3-Wire Serial Interface. Set CS low to allow serial data to shift in. Set CS high when the loading action is completed.

VCO Supply Voltage. Bypass to ground with a 100nF capacitor as close as possible to the pin.

Charge-Pump Output. Connect a PLL loop filter as a shunt C and a shunt combination of series R and C (see the Typical Application Circuit).

PLL Charge-Pump Supply Voltage. Bypass to ground with a 100nF capacitor as close as possible to the pin.

Digital Circuitry Supply Voltage. Bypass to ground with a 100nF capacitor as close as possible to the pin.

Q-Channel Voltage Outputs. Bits 0 and 1 of the Q-channel ADC output or analog differential voltage output.

ADC Supply Voltage. Bypass to ground with a 100nF capacitor as close as possible to the pin.

I-Channel Voltage Outputs. Bits 0 and 1 of the I-channel ADC output or analog differential voltage output.

IF Section Supply Voltage. Bypass to ground with a 100nF capacitor as close as possible to the pin.

Operation Control Logic Input. A logic-low enables the idle mode, in which the XTAL oscillator is active, and all other blocks are off.

LNA Input Port 2. This port is typically used with an active antenna. Internally matched to 50I.

Logic Input. Connect to ground to use the serial interface. A logic-high allows programming to 8 hard-coded by device states connecting SDATA, CS, and SCLK to supply or ground according to Table 3.

LNA Input Port 1. This port is typically used with a passive antenna. Internally matched to 50I (see the Typical Application Circuit).

Exposed Pad. Ultra-low-inductance connection to ground. Place several vias to the PCB ground plane.

�� Maxim Integrated Products 12

Detailed Description

MAX2769B

Universal GPS Receiver

Integrated Active Antenna Sensor

The MAX2769B includes a low-dropout switch to bias an external active antenna. To activate the antenna switch output, set ANTEN in the Configuration 1 register to logic

1. This closes the switch that connects the antenna bias pin to V

to achieve a low 200mV dropout for a

CC_RF

20mA load current. A logic-low in ANTEN disables the antenna bias. The active antenna circuit also features short-circuit protection to prevent the output from being shorted to ground.

Low-Noise Amplifier (LNA)

The MAX2769B integrates two low-noise amplifiers. LNA1 is typically used with a passive antenna. This LNA requires an AC-coupling capacitor. In the default mode, the bias current is set to 4mA, the typical noise figure and IIP3 are approximately 0.8dB and -1.1dBm, respectively. LNA2 is typically used with an active antenna. The LNA2 is internally matched to 50. and requires a DC-blocking capacitor. Bits LNAMODE in the Configuration 1 register control the modes of the two LNAs. See Table 6 and

Table 7 for the LNA mode settings.

Mixer

The MAX2769B includes a quadrature mixer to output low-IF or zero IF I and Q signals. The quadrature mixer is internally matched to 50I and requires a low-side LO injection. The output of the LNA and the input of the mixer are brought off-chip to facilitate the use of a SAW filter.

Programmable Gain Amplifier (PGA)

The MAX2769B integrates a baseband programmable gain amplifier that provides 59dB of gain control range. The PGA gain can be programmed through the serial interface by setting bits GAININ in the Configuration 3 register. Set bits 12 and 11 (AGCMODE) in the Configuration 2 register to 10 to control the gain of the PGA directly from the 3-wire interface.

Automatic Gain Control (AGC)

The MAX2769B provides a control loop that automatically programs PGA gain to provide the ADC with an input power that optimally fills the converter and establishes a desired magnitude bit density at its output. An algorithm

BASEBAND

CLKOUT

16

MAX2769B

XTAL

15

Figure 1. Schematic of the Crystal Oscillator in the MAX2679B EV Kit

CLOCK

10nF

23pF

operates by counting the number of magnitude bits over 512 ADC clock cycles and comparing the magnitude bit count to the reference value provided through a control word (GAINREF). The desired magnitude bit density is expressed as a value of GAINREF in a decimal format divided by the counter length of 512. For example, to achieve the magnitude bit density of 33%, which is optimal for a 2-bit converter, program the GAINREF to 170, so that 170/512 = 33%.

Baseband Filter

The baseband filter of the receiver can be programmed to be a lowpass filter or a complex bandpass filter. The lowpass filter can be configured as a 3rd-order Butterworth filter for a reduced group delay by setting bit F3OR5 in the Configuration 1 register to be 1 or a 5th-order Butterworth filter for a steeper out-of-band rejection by setting the same bit to be 0. The two-sided 3dB corner bandwidth can be selected to be 2.5MHz,

4.2MHz, 9.66MHz, or by programming bits FBW in the Configuration 1 register. When the complex filter is enabled by changing bit FCENX in the Configuration 1 register to 1, the lowpass filter becomes a bandpass filter and the center frequency can be programmed by bits FCEN and FCENMSB in the Configuration 1 register.

�� Maxim Integrated Products 13

Table 2. Output Data Format

MAX2769B

Universal GPS Receiver

INTEGER

VALUE

7 0 01 011 1 11 111 0 01 011 5 0 01 010 1 11 110 0 01 010 3 0 00 001 1 10 101 0 00 001 1 0 00 000 1 10 110 0 00 000

-1 1 10 100 0 01 011 1 11 111

-3 1 10 101 0 01 010 1 11 110

-5 1 11 110 0 00 001 1 10 101

-7 1 11 111 0 00 000 1 10 100

The MAX2769B integrates a 20-bit sigma-delta fractionalN synthesizer allowing the device to tune to a required VCO frequency with an accuracy of approximately Q30Hz. The synthesizer includes a 10-bit reference divider with a divisor range programmable from 1 to 1023, a 15-bit integer portion main divider with a divisor range programmable from 36 to 32767, and also a 20-bit fractional portion main divider. The reference divider is programmable by bits RDIV in the PLL integer division ratio register (see Table 11), and can accommodate reference frequencies from 8MHz to 32MHz. The reference divider needs to be set so the comparison frequency falls between 0.05MHz to 32MHz.

The PLL loop filter is the only external block of the synthesizer. A typical PLL filter is a classic C-R-C network at the charge-pump output. The charge-pump output sink and source current is 0.5mA by default, and the LO tuning gain is 57MHz/V. As an example, see the

Typical Application Circuit for the recommended loop-

filter component values for f bandwidth = 50kHz.

The desired integer and fractional divider ratios can be calculated by dividing the LO frequency (fLO) by f f

can be calculated by dividing the TCXO frequency

COMP

(f

) by the reference division ratio (RDIV). For exam-

TCXO

ple, let the TCXO frequency be 20MHz, RDIV be 1, and the nominal LO frequency be 1575.42MHz. The following method can be used when calculating divider ratios supporting various reference and comparison frequencies:

Comparison Frequency 20MHz

LO Frequency Divider 78.771

SIGN/MAGNITUDE UNSIGNED BINARY TWO’S COMPLEMENT BINARY

1b 2b 3b 1b 2b 3b 1b 2b 3b

Synthesizer

Integer Divider = 78(d) = 000 000 0100 1110 (binary)

Fractional Divider = 0.771 x 220 = 808452 (decimal) =

1100 0101 0110 0000 0100

In the fractional mode, the synthesizer should not be operated with integer division ratios greater than 251.

Crystal Oscillator

The MAX2769B includes an on-chip crystal oscillator. A parallel mode crystal is required when the crystal oscillator is being used. It is recommended that an AC-coupling capacitor be used in series with the crystal and the XTAL pin to optimize the desired load capacitance and to center the crystal-oscillator frequency. Take the parasitic loss of interconnect traces on the PCB into account when optimizing the load capacitance. For example, the MAX2769B EV kit utilizes a 16.368MHz crystal that is designed for a 12pF load capacitance. A series capacitor of 23pF is used to center the crystal oscillator frequency, see Figure 1. In addition, the 5-bit serial-interface word, XTALCAP in the PLL Configuration register, can

= 1.023MHz and loop

COMP

be used to vary the crystal-oscillator frequency electronically. The range of the electronic adjustment depends on how much the chosen crystal frequency can be pulled

COMP

oscillator used on the MAX2769B EV kit has a range of

by the varying capacitor. The frequency of the crystal

.

approximately 200Hz.

The MAX2769B provides a reference clock output. The frequency of the clock can be adjusted to crystal-oscillator frequency, a quarter of the oscillator frequency, a half

f

TCXO

= = =

RDIV 1

f

LO

= = =

f 20MHz

COMP

20MHz

1575.42MHz

of the oscillator frequency (f oscillator frequency, by programming bits REFDIV in the PLL Configuration register.

P 16MHz), or twice the

XTAL

�� Maxim Integrated Products 14

MAX2769B

Universal GPS Receiver

ADC

The MAX2769B features an on-chip ADC to digitize the downconverted GPS signal. The maximum sampling rate of the ADC is approximately 50Msps. The sampled output is provided in a 2-bit format (1-bit magnitude and 1-bit sign) by default and also can be configured as a 1-bit or 2-bit in both I and Q channels, or 1-bit, 2-bit, or 3-bit in the I channel only. The ADC supports the digital outputs in three different formats: the unsigned binary, the sign and magnitude, or the two’s complement format by setting bits FORMAT in Configuration register 2. MSB bits are output at I1 or Q1 pins and LSB bits are output at I0 or Q0 pins, for I or Q channel, respectively. In the case of 3-bit, output data format is selected in the I channel only, the MSB is output at I1, the second bit is at I0, and the LSB is at Q1.

Figure 2 illustrates the ADC quantization levels for 2-bit

and 3-bit cases and also describes the sign/magnitude

data mapping. The variable T = 1 designates the location of the magnitude threshold for the 2-bit case.

ADC Fractional Clock Divider

A 12-bit fractional clock divider is located in the clock path prior to the ADC and can be used to generate the ADC clock that is a fraction of the reference input clock. In a fractional divider mode, the instantaneous division ratio alternates between integer division ratios to achieve the required fraction. For example, if the fractional output clock is 4.5 times slower than the input clock, an average division ratio of 4.5 is achieved through an equal series of alternating divide-by-4 and divide-by-5 periods. The fractional division ratio is given by:

f

OUT/fIN

where L

= L

COUNT

and M

/(4096 - M

COUNT

are the 12-bit counter val-

+ L

COUNT

)

ues programmed through the serial interface.

011

01

010

-6-7

110

11

111

Figure 2. ADC Quantization Levels for 2- and 3-Bit Cases

�� Maxim Integrated Products 15

-3-4-5

101

001

00

000

-1-2

100

10

1 2

3 4 5

T = 1

6 7

MAX2769B

Universal GPS Receiver

DSP Interface

GPS data is output from the ADC as the four logic sig nals (bit0, bit1, bit2, and bit3) that represent sign/magnitude, unsigned binary, or two’s complement binary data in the I (bit0 and bit1) and Q (bit2 and bit3) channels. The resolution of the ADC can be set up to 3 bits per channel. For example, the 2-bit I and Q data in sign/magnitude format is mapped as follows: bit0 = I bit2 = Q

, and bit3 = Q

SIGN

. The data can be serial-

MAG

SIGN

, bit1 = I

MAG

ized in 16-bit segments of bit0, followed by bit1, bit2, and bit3. The number of bits to be serialized is controlled by the bits STRMBITS in the Configuration 3 register. This selects between bit0; bit0 and bit1; bit0 and bit2; and bit0, bit1, bit2, and bit3 cases. If only bit0 is serialized, the data stream consists of bit0 data only. If a serialization of bit0 and bit1 (or bit2) is selected, the stream data pattern consists of 16 bits of bit0 data followed by 16 bits of bit (or bit2) data, which, in turn, is followed by 16 bits of bit0

I

ADC

Q

CONTROL

SIGNALS

FROM 3-WIRE

INTERFACE

data, and so on. In this case, the serial clock must be at least twice as fast as the ADC clock. If a 4-bit serialization of bit0, bit1, bit2, and bit3 is chosen, the serial clock must be at least four times faster than the ADC clock.

The ADC data is loaded in parallel into four holding registers that correspond to four ADC outputs. Holding registers are 16 bits long and are clocked by the ADC

,

clock. At the end of the 16-bit ADC cycle, the data is transferred into four shift registers and shifted serially to the output during the next 16-bit ADC cycle. Shift registers are clocked by a serial clock that must be chosen fast enough so that all data is shifted out before the next set of data is loaded from the ADC. An all-zero pattern follows the data after all valid ADC data are streamed to the output. A DATASYNC signal is used to signal the beginning of each valid 16-bit data slice. In addition,

1

there is a TIME_SYNC signal that is output every 128 to 16,384 cycles of the ADC clock.

STRM_EN

OUTPUT

DRIVER

DATA_OUT

BIT 0

CLK_SER

BIT 1 BIT 2

DATA_SYNC

BIT 3

TIME_SYNC

STRM_EN STRM_START STRM_STOP STRM_COUNT<2:0> DIEID<1:0> STRM_BITS<1:0> FRM_COUNT<27:0> STAMP_EN DAT_SYNCEN TIME_SYNCEN STRM_RST

CLK_ADC CLK_SER

STRM_EN

PIN 21

PIN 20

PIN 17

PIN 18

REF/XTAL

PIN 15

THROUGH

/2 /4 x2

REFDIV<1:0>

ADCCLK_SEL

SERCLK_SEL

L_CNT<11:0> M_CNT<11:0>

CLK_IN CLK_OUT

Figure 3. DSP Interface Top-Level Connectivity and Control Signals

�� Maxim Integrated Products 16

FRCLK_SEL

MAX2769B

Universal GPS Receiver

Preconfigured Device States

When a serial interface is not available, the device can be used in preconfigured states that don’t require programming through the serial interface. Connecting the PGM pin to logic-high and SCLK, SDATA, and CS pins to either logic-high or low sets the device in one of the preconfigured states according to Table 3.

Power-On Reset (POR)

The MAX2769B incorporates power-on reset circuitry to ensure that register settings are loaded upon power-up. To ensure proper operation, the rising edge of PGM must occur no sooner than when V

reaches 90% of its final

CC_

nominal value; see Figure 4 for details.

A serial interface is used to program the MAX2769B for configuring the different operating modes.

The serial interface is controlled by three signals: SCLK (serial clock), CS (chip select), and SDATA (serial data). The control of the PLL, AGC, test, and block selection is performed through the serial-interface bus from the baseband controller. A 32-bit word, with the MSB (D27) being sent first, is clocked into a serial shift register when the chip-select signal is asserted low. The timing of the interface signals is shown in Figure 5 and Table 4 along with typical values for setup and hold time requirements.

Serial Interface, Address, and

Bit Assignments

Table 3. Preconfigured Device States

DEVICE ELECTRICAL CHARACTERISTICS 3-WIRE CONTROL PINS

(MHz)

DEVICE STATE

REFERENCE

0 16.368 16 1536 I 1 Differential 4.092 2.5 5th 0 0 0 1 16.368 16 1536 I 1 Differential 4.092 2.5 3rd 0 0 1 2 16.368 16 1536 I 2 CMOS 4.092 2.5 5th 0 1 0 3 32.736 32 1536 I 2 CMOS 4.092 2.5 5th 0 1 1 4 19.2 96 7857 I 2 CMOS 4.092 2.5 5th 1 0 0 5 27.456 26 1488 I 3 CMOS 4.092 4.2 5th 1 0 1 6 16.368 16 1536 I 3 CMOS 4.092 4.2 5th 1 1 0 7 27.456 26 1508 I 3 CMOS 9.27075 9.66 5th 1 1 1

REFERENCE

FREQUENCY

MAIN

RATIO

DIVISION

RATIO

DIVISION

I AND Q OR I

ONLY

NUMBER OF

IQ BITS

I AND Q

LOGIC LEVEL

(MHz)

IF CENTER

FREQUENCY

BW (MHz)

IF FILTER

ORDER

IF FILTER

SCLK

DATA

CS

Figure 4. V

V

CC_

100%

90%

0%

PGM

Power-On Reset

CC_

�� Maxim Integrated Products 17

PGM = 0

PGM RISING EDGE ANYTIME AFTER V 90% OF ITS NOMINAL VALUE.

HAS REACHED

CC_

TIME (s)

SCLK

MAX2769B

Universal GPS Receiver

CS

t

CSS

t

DS

t

DH t

CSH

t

CSW

CH

t

CL

SDATA

DATA

MSB

DATA

LSB

ADDR MSB

ADDR LSB

Figure 5. 3-Wire Timing Diagram

Table 4. Serial-Interface Timing Requirements

SYMBOL PARAMETER TYP VALUE UNITS

t

CSS

t t t

t

CSH

t

CSW

DS

DH

CH

CL

Falling edge of CS to rising edge of the first SCLK time. Data to serial-clock setup time. 10 ns Data to clock hold time. 10 ns Serial clock pulse-width high. 25 ns Clock pulse-width low. 25 ns

Last SCLK rising edge to rising edge of CS. CS high pulse width.

10 ns

1 clock

Table 5. Default Register Settings Overview

REGISTER

NAME

CONF1 0000 Configures RX and IF sections, bias settings for individual blocks. CONF2 0001 Configures AGC and output sections. CONF3 0010 Configures support and test functions for IF filter and AGC.

PLLCONF 0011 PLL, VCO, and CLK settings.

DIV 0100 PLL main and reference division ratios, other controls.

FDIV 0101 PLL fractional division ratio, other controls.

STRM 0110 DSP interface number of frames to stream.

CLK 0111 Fractional clock-divider values. TEST1 1000 Reserved for test mode. TEST2 1001 Reserved for test mode.

ADDRESS

(A3:A0)

DATA

�� Maxim Integrated Products 18

Table 6. Default Register Settings

MAX2769B

Universal GPS Receiver

POWER-ON

REGISTER

NAME

CONF1 0000 A2919A3 A2919A3 A2919A3 A2919A7 A2919A3 A2919A3 A293573 A293573 A29B26B CONF2 0001 055028C 055121C 055028C 055121C 055028C 055028C 855030C 855030C 855030C CONF3 0010 EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC

PLLCONF 0011 9EC0008 9EC0008 9EC0008 9EC0008 9EC0008 9EC0008 9EC0008 9EC0008 9EC0008

DIV 0100 0C00080 0C00080 0C00080 0C00080 0C00100 3D62300 0BA00D0 0C00080 0BC80D0

FDIV 0101 8000070 8000070 8000070 8000070 8000070 8000070 8000070 8000070 8000070

STRM 0110 8000000 8000000 8000000 8000000 8000000 8000000 8000000 8000000 8000000

CLK 0111 10061B2 10061B2 10061B2 10061B2 10061B2 10061B2 10061B2 10061B2 10061B2 TEST1 1000 1E0F401 1E0F401 1E0F401 1E0F401 1E0F401 1E0F401 1E0F401 1E0F401 1E0F401 TEST2 1001 28C0402 28C0402 28C0402 28C0402 28C0402 28C0402 28C0402 28C0402 7CC0403

ADDRESS

(A3:A0)

RESET,

PGM = 0

(hex)

0 1 2 3 4 5 6 7

PRECONFIGURED DEVICE STATE, PGM = 1 (hex)

Detailed Register Definitions

Table 7. Configuration 1 (Address: 0000)

DEFAULT

DATA BIT LOCATION

CHIPEN 27 1

IDLE 26 0 Idle enable. Set 1 to put the chip in the idle mode and 0 for operating mode.

RESERVED 25:22 1000 — RESERVED 21:20 10 — RESERVED 19:18 10 — RESERVED 17:16 01 —

MIXPOLE 15 0

LNAMODE 14:13 00

MIXEN 12 1 Mixer enable. Set 1 to enable the mixer and 0 to shut down the mixer.

ANTEN 11 1 Antenna bias enable. Set 1 to enable the antenna bias and 0 to shut down the antenna bias.

FCEN 10:5 001101

FBW 4:3 00

F3OR5 2 0

FCENX 1 1

FGAIN 0 1 IF filter gain setting. Set 0 to reduce the filter gain by 6dB.

VALUE

(PGM = 0)

DESCRIPTION

Chip enable. Set 1 to enable the device and 0 to disable the entire device except the serial bus.

Mixer pole selection. Set 1 to program the passive filter pole at mixer output at 36MHz, or set 0 to program the pole at 13MHz.

LNA mode selection, D14:D13 = 00: LNA selection gated by the antenna bias circuit, 01: LNA2 is active; 10: LNA1 is active; 11: both LNA1 and LNA2 are off.

IF center frequency programming. Default for f MSB of FCEN is located in Register Test Mode 2 (Table 16). 001101 = 3.092MHz, 001011 = 4.092MHz, 010011 = 10.0MHz

IF filter center bandwidth selection. D4:D3 = 00: 2.5MHz; 10: 4.2MHz; 01: 9.66MHz; 11: Reserved.

Filter order selection. Set 0 to select the 5th-order Butterworth filter. Set 1 to select the 3rdorder Butterworth filter.

Polyphase filter selection. Set 1 to select complex bandpass filter mode. Set 0 to select lowpass filter mode.

= 3.092MHz, BW = 2.5MHz. The

CENTER

�� Maxim Integrated Products 19

Table 8. Configuration 2 (Address: 0001)

DEFAULT

DATA BIT LOCATION

IQEN 27 0

GAINREF 26:15 170d

RESERVED 14:13 00 Reserved.

AGCMODE 12:11 00

FORMAT 10:9 01

BITS 8:6 010

DRVCFG 5:4 00

RESERVED 3 1 — RESERVED 2 0 —

DIEID 1:0 00 Identifies a version of the IC.

VALUE

(PGM = 0)

I and Q channels enable. Set 1 to enable both I and Q channels and 0 to enable I channel only.

AGC gain reference value expressed by the number of MSB counts (magnitude bit density). 10101010 = 234 magnitude bit density reference, 1010100 = 84 magnitude bit density reference, 100111010 = 314 magnitude bit density reference.

AGC mode control. Set D12:D11 = 00: independent I and Q; 01: reserved; 10: gain is set directly from the serial interface by GAININ; 11: reserved.

Output data format. Set D10:D9 = 00: unsigned binary; 01: sign and magnitude; 1X: two’s complement binary.

Number of bits in the ADC. Set D8:D6 = 000: 1 bit, 001: reserved; 010: 2 bits; 011: reserved, 100: 3 bits.

Output driver configuration. Set D5:D4 = 00: CMOS logic, 01: reserved; 1X: analog outputs.

MAX2769B

Universal GPS Receiver

DESCRIPTION

Table 9. Configuration 3 (Address: 0010)

DEFAULT

DATA BIT LOCATION

GAININ 27:22 111010

RESERVED 21 1 — HILOADEN 20 0 Set 1 to enable the output driver to drive high loads.

RESERVED RESERVED RESERVED RESERVED

FHIPEN 15 1

RESERVED 14 1 — RESERVED 13 1 — RESERVED 12 0 —

STRMEN 11 0

19 1 — 18 1 — 17 1 — 16 1 —

�� Maxim Integrated Products 20

VALUE

(PGM = 0)

DESCRIPTION

PGA gain value programming from the serial interface in steps of dB per LSB. 000000 = PGA gain set to 0dB, 101011 = 42dB, 101100 = 43dB, 101110 = 45dB, 111010 = 57dB, 111111 = 62dB.

Highpass coupling enable. Set 1 to enable the highpass coupling between the filter and PGA, or 0 to disable the coupling.

DSP interface for serial streaming of data enable. This bit configures the IC such that the DSP interface is inserted in the signal path. Set 1 to enable the interface or 0 to disable the interface.

Universal GPS Receiver

Table 9. Configuration 3 (Address: 0010) (continued)

DEFAULT

DATA BIT LOCATION

STRMSTART 10 0

STRMSTOP 9 0

RESERVED 8:6 111 —

STRMBITS 5:4 01

STAMPEN 3 1

TIMESYNCEN 2 1

VALUE

(PGM = 0)

The positive edge of this command enables data streaming to the output. It also enables clock, data sync, and frame sync outputs.

The positive edge of this command disables data streaming to the output. It also disables clock, data sync, and frame sync outputs.

Number of bits streamed. D5:D4 = 00: reserved; 01: 1 MSB, 1 LSB; 10: reserved, Q MSB; 11: 1 MSB, 1 LSB, Q MSB, Q LSB.

The signal enables the insertion of the frame number at the beginning of each frame. If disabled, only the ADC data is streamed to the output.

This signal enables the output of the time sync pulses at all times when streaming is enabled by the STRMEN command. Otherwise, the time sync pulses are available only when data streaming is active at the output, for example, in the time intervals bound by the STRMSTART and STRMSTOP commands.

MAX2769B

DESCRIPTION

This control signal enables the sync pulses at the DATASYNC output. Each pulse is

DATSYNCEN 1 0

STRMRST 0 0

coincident with the beginning of the 16-bit data word that corresponds to a given output bit.

This command resets all the counters irrespective of the timing within the stream cycle.

Table 10. PLL Configuration (Address: 0011)

DEFAULT

DATA BIT LOCATION

RESERVED 27 1 — RESERVED 26 0 — RESERVED 25 0 —

REFOUTEN 24 1 Clock buffer enable. Set 1 to enable the clock buffer or 0 to disable the clock buffer.

RESERVED 23 1 —

REFDIV 22:21 11

IXTAL 20:19 01

RESERVED 18:14 10000 —

LDMUX 13:10 0000 PLL lock-detect enable.

VALUE

(PGM = 0)

DESCRIPTION

Clock output divider ratio. Set D22:D21 = 00: clock frequency = XTAL frequency x 2; 01: clock frequency = XTAL frequency/4; 10: clock frequency = XTAL frequency/2; 11: clock frequency = XTAL.

Current programming for XTAL oscillator/buffer. Set D20:D19 = 00: reserved; 01: buffer normal current; 10: reserved; 11: oscillator high current.

�� Maxim Integrated Products 21

MAX2769B

Universal GPS Receiver

Table 10. PLL Configuration (Address: 0011) (continued)

DEFAULT

DATA BIT LOCATION

ICP 9 0 Charge-pump current selection. Set 1 for 1mA and 0 for 0.5mA.

PFDEN 8 0 Set 0 for normal operation or 1 to disable the PLL phase frequency detector. RESERVED 7 0 — RESERVED 6:4 000 —

INT_PLL 3 1 PLL mode control. Set 1 to enable the integer-N PLL or 0 to enable the fractional-N PLL.

PWRSAV 2 0 PLL power-save mode. Set 1 to enable the power-save mode or 0 to disable. RESERVED 1 0 — RESERVED 0 0 —

Table 11. PLL Integer Division Ratio (Address 0100)

DATA BIT LOCATION

NDIV 27:13 1536d PLL integer division ratio.

RDIV 12:3 16d PLL reference division ratio.

RESERVED 2:0 000 —

VALUE

(PGM = 0)

DEFAULT

VALUE

(PGM = 0)

DESCRIPTION

Table 12. PLL Division Ratio (Address 0101)

DEFAULT

DATA BIT LOCATION

FDIV 27:8 80000h PLL fractional divider ratio.

RESERVED 7:0 01110000 —

VALUE

(PGM = 0)

Table 13. Reserved (Address 0110)

DEFAULT

DATA BIT LOCATION

RESERVED 27:0 8000000h —

�� Maxim Integrated Products 22

VALUE

(PGM = 0)

DESCRIPTION

Universal GPS Receiver

Table 14. Clock Fractional Division Ratio (Address 0111)

DEFAULT

DATA BIT LOCATION

L_CNT 27:16 256d

M_CNT 15:4 1563d

FCLKIN 3 0

ADCCLK 2 0

RESERVED 1 1 —

MODE 0 0 DSP interface mode selection.

Table 15. Test Mode 1 (Address 1000)

VALUE

(PGM = 0)

DESCRIPTION

Sets the value for the L counter. 000100000000 = 256 fractional clock divider, 100000000000 = 2048 fractional clock divider.

Sets the value for the M counter. 011000011011 = 1563 fractional clock divider, 100000000 = 2048 fractional clock divider.

Fractional clock divider. Set 1 to select the ADC clock to come from the fractional clock divider, or 0 to bypass the ADC clock from the fractional clock divider.

ADC clock selection. Set 0 to select the ADC and fractional divider clocks to come from the reference divider/multiplier.

MAX2769B

DEFAULT

DATA BIT LOCATION

RESERVED 27:0 1E0F401 —

VALUE

(PGM = 0)

DESCRIPTION

Table 16. Test Mode 2 (Address 1001)

DEFAULT

DATA BIT LOCATION

RESERVED 27:1 28C0402 —

FCENMSB 0 0 When combined with FCEN, this bit represents the MSB of a 7-bit FCEN word.

The LNA and mixer inputs require careful consideration in matching to 50I lines. Proper supply bypassing, grounding, and layout are required for reliable performance from any RF circuit.

The MAX2769B EV kit can be used as a starting point for layout. For best performance, take into consideration grounding and routing of RF, baseband, and powersupply PCB proper line. Make connections from vias to the ground plane as short as possible. On the highimpedance ports, keep traces short to minimize shunt capacitance. EV kit Gerber files can be requested at

www.maxim-ic.com.

VALUE

(PGM = 0)

Applications Information

Layout Issues

DESCRIPTION

Power-Supply Layout

To minimize coupling between different sections of the IC, a star power-supply routing configuration with a large decoupling capacitor at a central V mended. The V each going to a separate V

traces branch out from this node,

CC_

node in the circuit. Place a bypass capacitor as close as possible to each supply pin This arrangement provides local decoupling at each V

pin. Use at least one via per bypass capacitor for

CC_

a low-inductance ground connection. Do not share the capacitor ground vias with any other branch.

Refer to Maxim’s Wireless and RF Application Notes for more information.

node is recom-

�� Maxim Integrated Products 23

MAX2769B

Universal GPS Receiver

Chip Information

PROCESS: SiGe BiCMOS

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX2769BETI/V+

+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.

/V denotes an automotive qualified part.

-40NC to +85NC

28 TQFN-EP*

Package Information

For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

PACKAGE

TYPE

28 TQFN-EP T2855+3

PACKAGE

CODE

OUTLINE

NO.

21-0140 90-0023

LAND

PATTERN NO.

�� Maxim Integrated Products 24

MAX2769B

Universal GPS Receiver

Revision History

REVISION

NUMBER

0 5/11 Initial release — 1 8/11 Corrected part number in Ordering Information section. 24

REVISION

DATE

DESCRIPTION

PAGES

CHANGED

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 25

©

2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Rainbow Electronics MAX2769B User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

General Description

Applications

Features

Block Diagram

ABSOLUTE MAXIMUM RATINGS

DC ELECTRICAL CHARACTERISTICS

Typical Operating Characteristics

Typical Operating Characteristics (continued)

Typical Operating Characteristics (continued)

Typical Application Circuit

Table 1. Component List

Pin Configuration

Pin Description

Detailed Description

Integrated Active Antenna Sensor

Low-Noise Amplifier (LNA)

Mixer

Programmable Gain Amplifier (PGA)

Automatic Gain Control (AGC)

Baseband Filter

Table 2. Output Data Format

Synthesizer

Crystal Oscillator

DSP Interface

Preconfigured Device States

Power-On Reset (POR)

Table 3. Preconfigured Device States

Figure 5. 3-Wire Timing Diagram

Table 6. Default Register Settings

Detailed Register Definitions

Table 7. Configuration 1 (Address: 0000)

Table 8. Configuration 2 (Address: 0001)

Table 9. Configuration 3 (Address: 0010)

Table 13. Reserved (Address 0110)

Table 15. Test Mode 1 (Address 1000)

Table 16. Test Mode 2 (Address 1001)

Applications Information

Layout Issues

Power-Supply Layout

Chip Information

Ordering Information

Package Information

Revision History