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MAX2063
User Manual
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Rainbow Electronics MAX2063 User Manual

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19-5303; Rev 0; 6/10
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
General Description
The MAX2063 high-linearity, dual digital variable-gain amplifier (VGA) operates in the 50MHz to 1000MHz frequency range. Each digital attenuator is controlled as a slave peripheral using either the SPIK-compatible interface or a 5-bit parallel bus with 31dB total adjust­ment range in 1dB steps. An added feature allows “rapid-fire” gain selection between each of four steps, preprogrammed by the user through the SPI-compatible interface. A separate 2-pin control allows the user to quickly access any one of four customized attenuation states without reprogramming the SPI bus.
Since each of the stages has its own external RF input and RF output, this component can be configured to either optimize noise figure (amplifier configured first) or OIP3 (amplifier configured last). The device’s performance features include 24dB of amplifier gain (amplifier only), 5.6dB noise figure (NF) at maximum gain (including attenuator insertion losses), and a high OIP3 level of +41dBm. Each of these features makes the device an ideal VGA for multipath receiver and transmitter applications.
In addition, the device operates from a single +5V supply with full performance, or a +3.3V supply for an enhanced power-savings mode with lower performance. This device is available in a compact 48-pin thin QFN package (7mm x 7mm) with an exposed pad. Electrical performance is guaranteed over the extended tempera­ture range, from TC = -40NC to +85NC.
Applications
IF and RF Gain Stages
Temperature-Compensation Circuits
Cellular Band WCDMA and cdma2000M Base Stations
GSM 850/GSM 900 EDGE Base Stations
WiMAXK and LTE Base Stations and Customer Premise Equipment
Fixed Broadband Wireless Access
Wireless Local Loop
Military Systems
Features
S Independently Controlled Dual Paths
S 50MHz to 1000MHz RF Frequency Range
S Pin-Compatible Family Includes
MAX2062 (Analog/Digital VGA) MAX2064 (Analog-Only VGA)
S 21.3dB (typ) Maximum Gain
S 0.25dB Gain Flatness Over 100MHz Bandwidth
S 31dB Gain Range
S 58dB Path Isolation at 200MHz
S Supports Four “Rapid-Fire” Preprogrammed
Attenuator States Quickly Access Any One of Four Customized Attenuation States Without Reprogramming the SPI Bus Ideal for Fast-Attack, High-Level Blocker Protection Prevents ADC Overdrive Condition
S Excellent Linearity at 200MHz
+41dBm OIP3 +56dBm OIP2 +19dBm Output 1dB Compression Point
S 5.6dB Typical Noise Figure
S 25ns Digital Switching Time
S Very Low Distortion VGA Amplitude Overshoot/
Undershoot of 0.05dB
S Single +5V Supply (or +3.3V Operation)
S Amplifier Power-Down Mode for TDD Applications
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX2063ETM+ MAX2063ETM+T
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
T = Tape and reel.
-40NC to +85NC
-40NC to +85NC
48 Thin QFN-EP* 48 Thin QFN-EP*
MAX2063
SPI is a trademark of Motorola, Inc. cdma2000 is a registered trademark of Telecommunications
Industry Association. WiMAX is a trademark of WiMAX Forum.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
ABSOLUTE MAXIMUM RATINGS
V
CC_AMP_1
STA_A_1, STA_A_2, STA_B_1, STA_B_2, PD_1,
PD_2, AMPSET to GND ...................................-0.3V to +3.6V
DAT, CS, CLK, DA_SP to GND ............................-0.3V to +3.6V
D0_1, D1_1, D2_1, D3_1, D4_1, D0_2, D1_2,
D2_2, D3_2, D4_2 to GND ...............................-0.3V to +3.6V
AMP_IN_1, AMP_IN_2 to GND ..........................+0.95V to +1.2V
AMP_OUT_1, AMP_OUT_2 to GND .....................-0.3V to +5.5V
MAX2063
D_ATT_IN_1, D_ATT_IN_2, D_ATT_OUT_1,
D_ATT_OUT_2 to GND ......................................... 0V to +3.6V
REG_OUT .............................................................-0.3V to +3.6V
Note 1: Based on junction temperature TJ = TC + (BJC x VCC x ICC). This formula can be used when the temperature of the
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
Note 3: Junction temperature T
Note 4: T
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
, V
CC_AMP_2
exposed pad is known while the device is soldered down to a PCB. See the Applications Information section for details. The junction temperature must not exceed +150NC.
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
known. The junction temperature must not exceed +150NC.
is the temperature on the exposed pad of the package. TA is the ambient temperature of the device and PCB.
C
, V
to GND ..........-0.3V to +5.5V
CC_RG
= TA + (BJA x VCC x ICC). This formula can be used when the ambient temperature of the PCB is
J
RF Input Power (D_ATT_IN_1, D_ATT_IN_2) ............... +20dBm
RF Input Power (AMP_IN_1, AMP_IN_2) ...................... +18dBm
q
(Notes 1, 2) ......................................................... +12.3NC/W
JC
q
(Notes 2, 3) ............................................................ +38NC/W
JA
Continuous Power Dissipation (Note 1) .............................. 5.3W
Operating Case Temperature Range (Note 4) .. -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
+5V SUPPLY DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VCC = V
-40NC to +85NC. Typical values are at V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage V Supply Current I Power-Down Current I Input Low Voltage V Input High Voltage V Input Logic Current I
CC_AMP_1
CC_
DCPD
IH
= V
= +5.0V and T
CC
DC
PD_1 = PD_2 = 1, VIH = 3.3V 5.2 8 mA
IL
IH
, I
IL
CC_AMP_2
C
= V
= +25NC, unless otherwise noted.)
= +4.75V to +5.25V, AMPSET = 0, PD_1 = PD_2 = 0, T
CC_RG
+3.3V SUPPLY DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VCC = V = -40NC to +85NC. Typical values are at V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage V Supply Current I Power-Down Current I Input Low Voltage V Input High Voltage V
CC_AMP_1
DCPD
= V
= +3.3V and T
CC_
CC
DC
IL
IH
CC_AMP_2
PD_1 = PD_2 = 1, VIH = 3.3V 4.3 8 mA
= V
= +25NC, unless otherwise noted.)
C
= +3.135V to +3.465V, AMPSET = 1, PD_1 = PD_2 = 0, T
CC_RG
4.75 5 5.25 V 148 205 mA
0.5 V
1.7 3.465 V
-1 +1
3.135 3.3 3.465 V 88 145 mA
0.5 V
1.7 3.465 V
FA
=
C
C
2
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
RECOMMENDED AC OPERATING CONDITIONS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RF Frequency f
RF
+5V SUPPLY AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VCC = V RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz ≤ fRF ≤ 500MHz, TC = -40NC to +85NC. Typical values are at maximum gain setting, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Small-Signal Gain G
Gain vs. Temperature -0.006 dB/NC
Gain Flatness vs. Frequency
Noise Figure NF
Total Attenuation Range 30.8 dB
Output Second-Order Intercept Point (Minimum Attenuation)
Path Isolation
CC_AMP_1
= +5.0V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6)
CC_
OIP2 P
(Note 5) 50 1000 MHz
= V
CC_AMP_2
fRF = 50MHz 22.0 fRF = 100MHz 21.7 fRF = 200MHz 21.3 fRF = 350MHz, TC = +25NC 18 21.0 23 fRF = 450MHz 20.8 fRF = 750MHz 19.9 fRF = 900MHz 18.3
From 100MHz to 200MHz 0.35
Any 100MHz frequency band from 200MHz to 500MHz
fRF = 50MHz 5.2 fRF = 100MHz 5.4 fRF = 200MHz 5.6 fRF = 350MHz 5.8 fRF = 450MHz 5.9 fRF = 750MHz 6.4 fRF = 900MHz 6.7
OUT
RF input 1 amplified power measured at RF output 2 relative to RF output 1, all unused ports terminated to 50I
RF input 2 amplified power measured at RF output 1 relative to RF output 2, all unused ports terminated to 50I
= V
= 0dBm/tone, Df = 1MHz, f1 + f
= +4.75V to +5.25V, attenuators are set for maximum gain,
CC_RG
0.25
2
51.6 dBm
48.8
49.4
dB
dB
dB
dB
MAX2063
3
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
+5V SUPPLY AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, VCC = V RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz ≤ fRF ≤ 500MHz, TC = -40NC to +85NC. Typical values are at maximum gain setting, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CC_AMP_1
CC_
MAX2063
Output Third-Order Intercept Point
Output -1dB Compression Point P Second Harmonic HD2 P Third Harmonic HD3 P Group Delay Includes EV kit PCB delays 0.87 ns
Amplifier Power-Down Time
Amplifier Power-Up Time
Input Return Loss RL Output Return Loss RL
DIGITAL ATTENUATOR (each path, unless otherwise noted)
Insertion Loss IL 3.0 dB
Input Second-Order Intercept Point
Input Third-Order Intercept Point
Attenuation Range 30.8 dB Step Size 1 dB Relative Attenuation Accuracy 0.11 dB Absolute Attenuation Accuracy 0.23 dB
Insertion Phase Step fRF = 170MHz
OIP3
= V
CC_AMP_2
= +5.0V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6)
P
OUT
Df = 1MHz, fRF = 50MHz
P
OUT
Df = 1MHz, fRF = 100MHz
P
OUT
Df = 1MHz, fRF = 200MHz
P
OUT
Df = 1MHz, fRF = 350MHz
P
OUT
Df = 1MHz, fRF = 450MHz
P
OUT
Df = 1MHz, fRF = 750MHz
P
OUT
Df = 1MHz, fRF = 900MHz
1dB
OUT
IIP2
IIP3
(Note 7) 18.8 dBm
OUT
OUT
PD_1 or PD_2 from 0 to 1, amplifier DC supply current settles to within 0.1mA
PD_1 or PD_2 from 1 to 0, amplifier DC supply current settles to within 1%
50I source 23.3 dB
IN
50I load 24.4 dB
P
RF1
attenuation), Df = 1MHz, f1 + f
P
IN1
attenuation), Df = 1MHz
= V
= 0dBm/tone,
= 0dBm/tone,
= 0dBm/tone,
= 0dBm/tone,
= 0dBm/tone,
= 0dBm/tone,
= 0dBm/tone,
= +3dBm -54.8 dBc = +3dBm -72.9 dBc
= 0dBm P
= 0dBm P
= +4.75V to +5.25V, attenuators are set for maximum gain,
CC_RG
47.1
43.9
41.0
37.0
35.2
28.7
26.5
0.5 Fs
0.5 Fs
= 0dBm (minimum
RF2
= 0dBm (minimum
IN2
0dB to 16dB -0.4
0dB to 31dB 0.9
2
53.1 dBm
43.2 dBm
dBm
Degrees0dB to 24dB 0.6
4
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
+5V SUPPLY AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, VCC = V RF ports are driven from 50I sources, AMPSET = 0, PD_1 = PD_2 = 0, 100MHz ≤ fRF ≤ 500MHz, TC = -40NC to +85NC. Typical values are at maximum gain setting, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Amplitude Overshoot/ Undershoot
Switching Speed
Input Return Loss RL Output Return Loss RL
SERIAL PERIPHERAL INTERFACE (SPI)
Maximum Clock Speed f Data-to-Clock Setup Time t Data-to-Clock Hold Time t Clock-to-CS Setup Time t
CS Positive Pulse Width t CS Setup Time t
Clock Pulse Width t
CC_AMP_1
CC_
= V
CC_AMP_2
= +5.0V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6)
Between any two states
RF settled to within Q0.1dB
50I source 21.6 dB
IN
OUT
CLK
CS
CH
ES
EW
EWS
CW
50I load 21.2 dB
= V
= +4.75V to +5.25V, attenuators are set for maximum gain,
CC_RG
Elapsed time = 15ns 1.0 Elapsed time = 40ns 0.05 31dB to 0dB 25 0dB to 31dB 21
dB
ns
20 MHz
2 ns
2.5 ns 3 ns 7 ns
3.5 ns 5 ns
MAX2063
+3.3V SUPPLY AC ELECTRICAL CHARACTERISTIC
(Typical Application Circuit, VCC = V are driven from 50I sources, AMPSET = 1, PD_1 = PD_2 = 0, 100MHz ≤ fRF ≤ 500MHz, TC = -40NC to +85NC. Typical values are at maximum gain setting, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Small-Signal Gain G 20.9 dB
Output Third-Order Intercept Point
Noise Figure NF 5.9 dB Total Attenuation Range 30.8 dB
Path Isolation
Output -1dB Compression Point P
Note 5: Operation outside this range is possible, but with degraded performance of some parameters. See the Typical Operating
Characteristics.
Note 6: All limits include external component losses. Output measurements are performed at the RF output port of the Typical
Application Circuit.
Note 7: It is advisable not to continuously operate RF input 1 or RF input 2 above +15dBm.
= +3.3V, PIN = -20dBm, fRF = 350MHz, and TC = +25NC, unless otherwise noted.) (Note 6)
CC_
CC_AMP_1
OIP3 P
1dB
= V
CC_AMP_2
OUT
RF input 1 amplified power measured at RF output 2 relative to RF output 1, all unused ports terminated to 50I
RF input 2 amplified power measured at RF output 1 relative to RF output 2, all unused ports terminated to 50I
(Note 7) 13.4 dBm
= V
= 0dBm/tone 29.6 dBm
= +3.3V, attenuators are set for maximum gain, RF ports
CC_RG
48.8
49.1
dB
5
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
Typical Operating Characteristics
(Typical Application Circuit, V driven from 50ω sources, AMPSET = 0, PD_1 = PD_2 = 0, P
CC
= V
CC_AMP_1
= V
CC_AMP_2
= V
CC_RG
= -20dBm, f
IN
= 5V, attenuators are set for maximimum gain, RF ports are
= 350MHz, T
RF
= +25°C, unless otherwise noted.)
C
170
MAX2063
160
150
SUPPLY CURRENT (mA)
140
130
4.750 5.250
TC = -40°C
TC = +25°C
GAIN OVER ATTENUATOR SETTING
vs. RF FREQUENCY
25
15
5
-5
GAIN OVER ATTENUATOR SETTING (dB)
-15 50 1050
RF FREQUENCY (MHz)
SUPPLY CURRENT vs. V
VCC (V)
CC
TC = +85°C
5.1255.0004.875
850650450250
24
MAX2063 toc01
22
20
GAIN (dB)
18
16
1.00
0.75
MAX2063 toc04
0.50
0.25
-0.25
RELATIVE ERROR (dB)
-0.50
-0.75
-1.00
GAIN vs. RF FREQUENCY
TC = -40°C
TC = +85°C
50 1050
TC = +25°C
850650450250
RF FREQUENCY (MHz)
ATTENUATOR RELATIVE
ERROR vs. RF FREQUENCY
0
ERROR FROM 23dB TO 24dB
50 1050
RF FREQUENCY (MHz)
850650250 450
24
MAX2063 toc02
22
20
GAIN (dB)
18
16
1.00
0.75
MAX2063 toc05
0.50
0.25
0
-0.25
ABSOLUTE ERROR (dB)
-0.50
-0.75
-1.00
GAIN vs. RF FREQUENCY
VCC = 4.75V, 5.00V, 5.25V
50 1050
RF FREQUENCY (MHz)
850650450250
ATTENUATOR ABSOLUTE
ERROR vs. RF FREQUENCY
25dB
24dB
50 1050
RF FREQUENCY (MHz)
850650250 450
MAX2063 toc03
MAX2063 toc06
INPUT MATCH OVER ATTENUATOR
SETTING vs. RF FREQUENCY
0
16dB
-10
-20
-30
-40
INPUT MATCH OVER ATTENUATOR SETTING (dB)
-50 0 1000
8dB
1dB
2dB
31dB
RF FREQUENCY (MHz)
0dB
4dB
MAX2063 toc07
800600400200
OUTPUT MATCH OVER ATTENUATOR
SETTING vs. RF FREQUENCY
0
-10
16dB, 31dB
-20
-30
OUTPUT MATCH OVER ATTENUATOR SETTING (dB)
-40
1dB, 4dB, 8dB
0dB
0 1000
2dB
800600400200
RF FREQUENCY (MHz)
MAX2063 toc08
6
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
Typical Operating Characteristics (continued)
(Typical Application Circuit, V driven from 50ω sources, AMPSET = 0, PD_1 = PD_2 = 0, P
CC
= V
CC_AMP_1
= V
CC_AMP_2
IN
= V
CC_RG
= -20dBm, f
= 5V, attenuators are set for maximimum gain, RF ports are
= 350MHz, T
RF
= +25°C, unless otherwise noted.)
C
MAX2063
REVERSE GAIN OVER ATTENUATOR
SETTING vs. RF FREQUENCY
-30
-40
-50
-60
-70
REVERSE GAIN OVER ATTENUATOR SETTING (dB)
-80 50 1050
ATTEN 0dB
ATTEN 31dB
RF FREQUENCY (MHz)
CHANNEL ISOLATION vs. RF FREQUENCY
(MINIMUM GAIN)
75
65
55
45
CHANNEL ISOLATION (dB)
35
25
RELATIVE POWERS AT RF OUTPUTS
CH1 TO CH2
CH2 TO CH1
50 1050
RF FREQUENCY (MHz)
ATTENUATOR PHASE CHANGE
BETWEEN STATES vs. RF FREQUENCY
60
REFERENCED TO HIGH GAIN STATE
50
MAX2063 toc09
850650450250
POSITIVE PHASE = ELECTRICALLY SHORTER
40
30
20
10
0
-10
-20
-30 50 1050
ATTENUATOR PHASE CHANGE BETWEEN STATES (DEGREES)
RF FREQUENCY (MHz)
850650450250
MAX2063 toc10
NOISE FIGURE vs. RF FREQUENCY
9
MAX2063 toc12
850650450250
8
7
6
NOISE FIGURE (dB)
5
4
3
50 1050
TC = +85°C
TC = +25°C
TC = -40°C
RF FREQUENCY (MHz)
MAX2063 toc13
850650450250
CHANNEL ISOLATION vs. RF FREQUENCY
(MAXIMUM GAIN)
75
65
55
45
CHANNEL ISOLATION (dB)
35
25
RELATIVE POWERS AT RF OUTPUTS
CH1 TO CH2
50 1050
RF FREQUENCY (MHz)
CH2 TO CH1
NOISE FIGURE vs. RF FREQUENCY
9
8
7
6
NOISE FIGURE (dB)
5
4
3
50 1050
VCC = 4.75V, 5.00V, 5.25V
RF FREQUENCY (MHz)
MAX2063 toc11
850650450250
MAX2063 toc14
850650450250
OUTPUT P
22
20
18
(dBm)
1dB
TC = +85°C
16
OUTPUT P
14
12
50 1050
vs. RF FREQUENCY
1dB
TC = -40°C
TC = +25°C
RF FREQUENCY (MHz)
OUTPUT P
22
MAX2063 toc15
850650450250
20
18
(dBm)
1dB
VCC = 4.75V
16
OUTPUT P
14
12
50 1050
vs. RF FREQUENCY
1dB
VCC = 5.25V
VCC = 5.00V
RF FREQUENCY (MHz)
MAX2063 toc16
850650450250
7
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
Typical Operating Characteristics (continued)
(Typical Application Circuit, V driven from 50ω sources, AMPSET = 0, PD_1 = PD_2 = 0, P
CC
= V
CC_AMP_1
= V
CC_AMP_2
= V
CC_RG
= -20dBm, f
IN
= 5V, attenuators are set for maximimum gain, RF ports are
= 350MHz, T
RF
= +25°C, unless otherwise noted.)
C
OUTPUT IP3 vs. RF FREQUENCY
50
MAX2063
45
40
35
30
OUTPUT IP3 (dBm)
25
20
50 1050
TC = -40°C
RF FREQUENCY (MHz)
2ND HARMONIC vs. RF FREQUENCY
70
60
50
TC = -40°C
2ND HARMONIC (dBc)
40
TC = +85°C
TC = +85°C
TC = +25°C
P
= 0dBm/TONE
OUT
TC = +25°C
P
OUT
850650450250
= 3dBm
50
45
MAX2063 toc17
40
35
OUTPUT IP3 (dBm)
30
25
20
70
MAX2063 toc20
60
50
2ND HARMONIC (dBc)
40
OUTPUT IP3 vs. RF FREQUENCY
P
= 0dBm/TONE
VCC = 5.00V
VCC = 4.75V
50 1050
RF FREQUENCY (MHz)
OUT
VCC = 5.25V
850650450250
2ND HARMONIC vs. RF FREQUENCY
P
= 3dBm
VCC = 5.25V
VCC = 5.00V
VCC = 4.75V
OUT
45
MAX2063 toc18
40
OUTPUT IP3 (dBm)
35
30
65
MAX2063 toc21
60
55
50
2ND HARMONIC (dBc)
45
OUTPUT IP3 vs. ATTENUATOR STATE
P
= 0dBm/TONE
OUT
RF = 350MHz
TC = -40°C, LSB, USB
TC = +25°C, LSB, USB
TC = +85°C, LSB, USB
0 28
ATTENUATOR STATE (dB)
2420161284
2ND HARMONIC vs. ATTENUATOR STATE
P
= 3dBm
TC = +25°C
OUT
RF = 350MHz
TC = +85°C
TC = -40°C
MAX2063 toc19
MAX2063 toc22
30
50 1050
RF FREQUENCY (MHz)
3RD HARMONIC vs. RF FREQUENCY
100
90
80
70
3RD HARMONIC (dBc)
TC = +85°C
60
50
50 1050
TC = -40°C
RF FREQUENCY (MHz)
8
850650450250
P
= 3dBm
OUT
TC = +25°C
850650450250
30
100
MAX2063 toc23
90
80
70
3RD HARMONIC (dBc)
60
50
50 1050
RF FREQUENCY (MHz)
850650450250
3RD HARMONIC vs. RF FREQUENCY
P
= 3dBm
OUT
VCC = 5.25V
VCC = 5.00V
VCC = 4.75V
50 1050
RF FREQUENCY (MHz)
850650450250
40
80
MAX2063 toc24
75
70
3RD HARMONIC (dBc)
65
0 28
ATTENUATOR STATE (dB)
2420161284
3RD HARMONIC vs. ATTENUATOR STATE
P
= 3dBm
OUT
TC = -40°C
TC = +85°C
0 28
ATTENUATOR STATE (dB)
RF = 350MHz
TC = +25°C
2420161284
MAX2063 toc25
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
Typical Operating Characteristics (continued)
(Typical Application Circuit, V driven from 50ω sources, AMPSET = 0, PD_1 = PD_2 = 0, P
CC
= V
CC_AMP_1
= V
CC_AMP_2
IN
= V
CC_RG
= -20dBm, f
= 5V, attenuators are set for maximimum gain, RF ports are
= 350MHz, T
RF
= +25°C, unless otherwise noted.)
C
MAX2063
OUTPUT IP2 vs. RF FREQUENCY
70
TC = +85°C
60
50
TC = +25°C
40
OUTPUT IP2 (dBm)
30
20
50 1050
TC = -40°C
RF FREQUENCY (MHz)
P
= 0dBm/TONE
OUT
GAIN vs. RF FREQUENCY
0
-1
-2
GAIN (dB)
-3
TC = -40°C
MAX2063 toc26
850650450250
(ATTENUATOR ONLY)
TC = +25°C
OUTPUT IP2 vs. RF FREQUENCY
70
60
50
40
OUTPUT IP2 (dBm)
30
20
50 1050
VCC = 5.25V
VCC = 4.75V
RF FREQUENCY (MHz)
MAX2063 toc29
P
OUT
VCC = 5.00V
= 0dBm/TONE
-1
-2
GAIN (dB)
-3
OUTPUT IP2 vs. ATTENUATOR STATE
60
MAX2063 toc27
55
50
OUTPUT IP2 (dBm)
45
850650450250
40
TC = +85°C
TC = -40°C
0 28
ATTENUATOR STATE (dB)
TC = +25°C
P
= 0dBm/TONE
OUT
RF = 350MHz
20161284
MAX2063 toc28
24
GAIN vs. RF FREQUENCY
(ATTENUATOR ONLY)
0
MAX2063 toc30
-4
TC = +85°C
-5 50 1050
RF FREQUENCY (MHz)
850650450250
-4
-5
VCC = 4.75V, 5.00V, 5.25V
50 1050
RF FREQUENCY (MHz)
850650450250
9
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
Typical Operating Characteristics
(Typical Application Circuit, V driven from 50ω sources, AMPSET = 1, PD_1 = PD_2 = 0, P
CC
= V
CC_AMP_1
= V
CC_AMP_2
= V
CC_RG
= -20dBm, f
IN
= 3.3V, attenuators are set for maximimum gain, RF ports are
= 350MHz, T
RF
= +25°C, unless otherwise noted.)
C
120
SUPPLY CURRENT vs. V
MAX2063
110
100
90
80
SUPPLY CURRENT (mA)
70
60
TC = -40°C
TC = +85°C
3.1 3.5
0
-10
-20
-30
-40
INPUT MATCH OVER ATTENUATOR SETTING (dB)
-50
CC
TC = +25°C
3.43.33.2
VCC (V)
MAX2063 toc31
24
22
20
GAIN (dB)
18
16
50 1050
INPUT MATCH OVER ATTENUATOR
SETTING vs. RF FREQUENCY
VCC = 3.3V
16dB
4dB
31dB
50 1050
RF FREQUENCY (MHz)
8dB
0dB
2dB
1dB
850650450250
GAIN vs. RF FREQUENCY
TC = -40°C
TC = +25°C
TC = +85°C
RF FREQUENCY (MHz)
MAX2063 toc34
GAIN vs. RF FREQUENCY
MAX2063 toc32
24
22
20
GAIN (dB)
18
16
VCC = 3.465V
VCC = 3.135V
50 1050
RF FREQUENCY (MHz)
VCC = 3.3V
850650450250
OUTPUT MATCH OVER ATTENUATOR
SETTING vs. RF FREQUENCY
0
-10
16dB, 31dB
1dB
2dB
-20
-30
OUTPUT MATCH OVER ATTENUATOR SETTING (dB)
-40 50 1050
8dB
4dB
0dB
RF FREQUENCY (MHz)
MAX2063 toc33
VCC = 3.3V
850650450250
VCC = 3.3V
MAX2063 toc35
850650450250
10
NOISE FIGURE vs. RF FREQUENCY
9
8
TC = +85°C
7
6
5
NOISE FIGURE (dB)
4
TC = -40°C
3
2
50 1050
RF FREQUENCY (MHz)
TC = +25°C
VCC = 3.3V
850650450250
MAX2063 toc36
NOISE FIGURE vs. RF FREQUENCY
9
8
7
6
5
NOISE FIGURE (dB)
4
3
2
50 1050
VCC = 3.135V
VCC = 3.3V
VCC = 3.465V
RF FREQUENCY (MHz)
MAX2063 toc37
850650450250
Dual 50MHz to 1000MHz High-Linearity,
ATTENUATOR STATE (dB)
Serial/Parallel-Controlled Digital VGA
Typical Operating Characteristics (continued)
(Typical Application Circuit, V driven from 50ω sources, AMPSET = 1, PD_1 = PD_2 = 0, P
CC
= V
CC_AMP_1
= V
CC_AMP_2
= V
CC_RG
= -20dBm, f
IN
= 3.3V, attenuators are set for maximimum gain, RF ports are
= 350MHz, T
RF
= +25°C, unless otherwise noted.)
C
MAX2063
OUTPUT P
16
TC = +25°C
14
(dBm)
12
1dB
10
OUTPUT P
8
6
50 1050
vs. RF FREQUENCY
1dB
TC = +85°C
RF FREQUENCY (MHz)
TC = -40°C
OUTPUT IP3 vs. RF FREQUENCY
50
40
30
OUTPUT IP3 (dBm)
VCC = 3.135V
20
VCC = 3.465V
P
= 0dBm/TONE
OUT
VCC = 3.3V
VCC = 3.3V
850650450250
MAX2063 toc38
(dBm)
1dB
OUTPUT P
MAX2063 toc41
OUTPUT IP3 (dBm)
OUTPUT P
16
14
12
VCC = 3.465V
10
8
6
50 1050
vs. RF FREQUENCY
1dB
VCC = 3.3V
VCC = 3.135V
RF FREQUENCY (MHz)
850650450250
OUTPUT IP3 vs. ATTENUATOR STATE
34
TC = -40°C LSB, USB
32
30
28
26
TC = +85°C LSB, USB
24
TC = +25°C LSB, USB
VCC = 3.3V P
= 0dBm/TONE
OUT
RF = 350MHz
50
MAX2063 toc39
40
30
OUTPUT IP3 (dBm)
20
10
80
70
MAX2063 toc42
60
50
40
2ND HARMONIC (dBc)
30
OUTPUT IP3 vs. RF FREQUENCY
P
= 0dBm/TONE
OUT
V
= 3.3V
CC
TC = -40°C
TC = +25°C
TC = +85°C
50 1050
RF FREQUENCY (MHz)
850650450250
2ND HARMONIC vs. RF FREQUENCY
V
= 3.3V
CC
P
= 3dBm
OUT
T
= +25°C
C
TC = -40°C
TC = +85°C
MAX2063 toc40
MAX9888 toc43
10
50 1050
850650450250
RF FREQUENCY (MHz)
2ND HARMONIC vs. RF FREQUENCY
80
70
60
50
40
2ND HARMONIC (dBc)
30
20
VCC = 3.465V
VCC = 3.135V
50 1050
RF FREQUENCY (MHz)
P
OUT
VCC = 3.3V
22
0 28
ATTENUATOR STATE (dB)
= 3dBm
MAX9888 toc44
850650450250
20
2420161284
50 1050
2ND HARMONIC vs. ATTENUATOR STATE
80
70
TC = +85°C
60
50
2ND HARMONIC (dBc)
40
T
30
0 28
C
TC = +25°C
= -40°C
RF FREQUENCY (MHz)
VCC = 3.3V P
= 3dBm
OUT
RF = 350MHz
MAX2063 toc45
2420161284
850650450250
11
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
Typical Operating Characteristics (continued)
(Typical Application Circuit, V driven from 50ω sources, AMPSET = 1, PD_1 = PD_2 = 0, P
CC
= V
CC_AMP_1
= V
CC_AMP_2
= V
CC_RG
= -20dBm, f
IN
= 3.3V, attenuators are set for maximimum gain, RF ports are
= 350MHz, T
RF
= +25°C, unless otherwise noted.)
C
MAX2063
3RD HARMONIC (dBc)
3RD HARMONIC (dBc)
3RD HARMONIC vs. RF FREQUENCY
80
70
60
50
40
TC = -40°C
TC = +85°C
50 1050
RF FREQUENCY (MHz)
VCC = 3.3V P
OUT
TC = +25°C
= 3dBm
850650450250
3RD HARMONIC vs. ATTENUATOR STATE
70
TC = -40°C
65
60
55
TC = +85°C
50
0 28
ATTENUATOR STATE (dB)
TC = +25°C
VCC = 3.3V P
= 3dBm
OUT
RF = 350MHz
3RD HARMONIC vs. RF FREQUENCY
MAX2063 toc46
80
70
VCC = 3.465V
VCC = 3.135V
60
3RD HARMONIC (dBc)
50
40
50 1050
VCC = 3.3V
RF FREQUENCY (MHz)
P
OUT
= 3dBm
MAX2063 toc47
850650450250
OUTPUT IP2 vs. RF FREQUENCY
70
MAX2063 toc48
2420161284
60
50
40
OUTPUT IP2 (dBm)
30
20
TC = +85°C
TC = +25°C
50 1050
RF FREQUENCY (MHz)
TC = -40°C
VCC = 3.3V P
= 0dBm/TONE
OUT
MAX2063 toc49
850650450250
12
OUTPUT IP2 vs. RF FREQUENCY
70
60
VCC = 3.465V
50
40
OUTPUT IP2 (dBm)
30
20
50 1050
RF FREQUENCY (MHz)
VCC = 3.3V
VCC = 3.135V
P
OUT
= 0dBm/TONE
850650450250
MAX2063 toc50
OUTPUT IP2 vs. ATTENUATOR STATE
70
P
= 0dBm/TONE
OUT
60
50
OUTPUT IP2 (dBm)
40
30
0 28
TC = +85°C
TC = -40°C
ATTENUATOR STATE (dB)
TC = +25°C
RF = 350MH
VCC = 3.3V
2420161284
Z
MAX2063 toc51
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
Pin Configuration
TOP VIEW
V
CC_AMP_1
GND
GND
GND
GND
D4_1
D_ATT_OUT_1
D3_1
D2_1
D1_1
D0_1
GND
AMP_IN_1
PD_1
GND
35
34 33 32 31 30 29 28 27
36
37
38
39
40
41
42
43
44
45
46
47
48
+
ACTIVE
BIAS
DIGITAL
ATTENUATOR
1
2
3 4 5 6 7 8 9 10
1
GND
STA_A_1
D_ATT_IN_1
AMP_OUT_1
GND
AMP AMP
MAX2063
DAT
STA_B_1
AMPSET
SPI
CLK
AMP_OUT_2
REG_OUT
ATTENUATOR
CS
CC_RG
V
GND
ACTIVE
BIAS
EXPOSED
PAD
DIGITAL
2
STA_B_2
THIN QFN
(7mm O 7mm)
AMP_IN_2
PD_2
26
11
STA_A_2
D_ATT_IN_2
GND
25
V
24
CC_AMP_2
GND
23
22
GND
21
DA_SP
GND
20
D4_2
19
18
D_ATT_OUT_2
17
D3_2
16
D2_2
D1_2
15
D0_2
14
13
GND
12
GND
MAX2063
Pin Description
PIN NAME FUNCTION
1, 12, 13, 20,
22, 23, 25, 28, 33, 36,
38–41, 48
2 D_ATT_IN_1 5-Bit Digital Attenuator RF Input (50I), Path 1. Requires a DC-blocking capacitor.
3 STA_A_1
4 STA_B_1
5 DAT SPI Data Digital Input 6 CLK SPI Clock Digital Input 7 CS SPI Chip-Select Digital Input
GND Ground
Digital Attenuator Preprogrammed Attenuation-State Logic Input, Path 1 State A State B Digital Attenuator 1 Logic = 0 Logic = 0 Preprogrammed State 1 Logic = 1 Logic = 0 Preprogrammed State 2 Logic = 0 Logic = 1 Preprogrammed State 3 Logic = 1 Logic = 1 Preprogrammed State 4
13
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
Pin Description (continued)
PIN NAME FUNCTION
8 V
CC_RG
Regulator Supply Input. Connect to a 3.3V or 5V external power supply. V circuits except for the driver amplifiers. Bypass with a 10nF capacitor as close as possible to the pin.
CC_RG
powers all
MAX2063
9 STA_B_2
10 STA_A_2
11 D_ATT_IN_2 5-Bit Digital Attenuator Input (50I), Path 2. Requires a DC-blocking capacitor. 14 D0_2 1dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable 15 D1_2 2dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable 16 D2_2 4dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable 17 D3_2 8dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable
18 D_ATT_OUT_2
19 D4_2 16dB Attenuator Logic Input, Path 2. Logic 0 = disable, Logic 1 = enable.
21 DA_SP
24 V
26 AMP_IN_2 Driver Amplifier Input (50I), Path 2. Connect to D_ATT_OUT_2 through a 1000pF capacitor. 27 PD_2 Power-Down, Path 2. See Table 2 for operation details. 29 AMP_OUT_2 Driver Amplifier Output (50I), Path 2. Connect a pullup inductor from AMP_OUT_2 to V 30 REG_OUT Regulator Output. Bypass with a 1FF capacitor.
31 AMPSET
32 AMP_OUT_1 Driver Amplifier Output (50I), Path 1. Connect a pullup inductor from AMP_OUT_1 to V 34 PD_1 Power-Down, Path 1. See Table 2 for operation details. 35 AMP_IN_1 Driver Amplifier Input (50I), Path 1. Connect to D_ATT_OUT_1 through a 1000pF capacitor.
37 V
42 D4_1 16dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable, path 1.
43 D_ATT_OUT_1
44 D3_1 8dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable. 45 D2_1 4dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable. 46 D1_1 2dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable. 47 D0_1 1dB Attenuator Logic Input, Path 1. Logic 0 = disable, Logic 1 = enable.
— EP
CC_AMP_2
CC_AMP_1
Digital Attenuator Preprogrammed Attenuation-State Logic Input, Path 2 State A State B Digital Attenuator 2 Logic = 0 Logic = 0 Preprogrammed State 1 Logic = 1 Logic = 0 Preprogrammed State 2 Logic = 0 Logic = 1 Preprogrammed State 3 Logic = 1 Logic = 1 Preprogrammed State 4
5-Bit Digital Attenuator Output (50I), Path 2. Requires a DC-blocking capacitor. Connect to AMP_IN_2 through a 1000pF capacitor.
Digital Attenuator Serial/Parallel Control Select. Set DA_SP to 1 to select serial control. Set DA_SP to 0 to select parallel control.
Driver Amplifier Supply Voltage Input, Path 2. Bypass with a 10nF capacitor as close as possible to the pin.
.
CC_
Driver Amplifier Bias Setting for 3.3V Operation. Set to logic 1 for 3.3V on pins V V
CC_AMP2
Driver Amplifier Supply Voltage Input, Path 1. Bypass with a 10nF capacitor as close as possible to the pin.
5-Bit Digital Attenuator Output (50I), Path 1. Requires a DC-blocking capacitor. Connect to AMP_IN_1 through a 1000pF capacitor.
Exposed Pad. Internally connected to GND. Connect to a large PCB ground plane for proper RF performance and enhanced thermal dissipation.
. Set to logic 0 for 5V.
CC_AMP1
CC_
and
.
14
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
Detailed Description
The MAX2063 high-linearity digital VGA is a general­purpose, high-performance amplifier designed to interface with 50I systems operating in the 50MHz to 1000MHz frequency range. Each channel of the device integrates one digital attenuator to provide 31dB of total gain control, as well as a driver amplifier optimized to provide high gain, high output IP3, low NF, and low power consumption.
Each digital attenuator is controlled as a slave peripheral using either the SPI-compatible interface or a 5-bit parallel bus with 31dB total adjustment range in 1dB steps. An added feature allows “rapid-fire” gain selection between each of four steps, preprogrammed by the user through the SPI-compatible interface. A separate 2-pin control allows the user to quickly access any one of four customized attenuation states without reprogramming the SPI bus.
Because each of the two stages in the separate signal paths has its own RF input and RF output, this component can be configured to either optimize NF (amplifier configured first) or OIP3 (amplifier configured last). The device’s performance features include 24dB of amplifier gain (amplifier only), 5.6dB NF at maximum gain (includes attenuator insertion losses), and a high OIP3 level of +41dBm. Each of these features makes the device an ideal VGA for multipath receiver and transmitter applications.
5-Bit Digital Attenuator Control
The device integrates two 5-bit digital attenuators to achieve a high level of dynamic range. Each digital attenuator has a 31dB control range, a 1dB step size, and can be programmed either through a dedicated 5-bit parallel bus or through the 3-wire SPI. See the Applications Information section and Table 1 for attenu­ator programming details. The attenuators can be used for both static and dynamic power control.
Driver Amplifiers
The device includes two high-performance drivers with a fixed gain of 24dB. Each driver amplifier circuit is optimized for high linearity for the 50MHz to 1000MHz frequency range.
Table 1. Control Logic
DA_SP DIGITAL ATTENUATOR
0 Parallel controlled
1
SPI controlled (control voltages show up on the parallel control pins)
Table 2. Operating Modes
RESULT V
All on
AMP1 off AMP2 on
AMP1 on AMP2 off
All off
(V) AMPSET PD_1 PD_2
CC_
5 0 0 0
3.3 1 0 0 5 0 1 0
3.3 1 1 0 5 0 0 1
3.3 1 0 1 5 0 1 1
3.3 1 1 1
Applications Information
Operating Modes
The device features an optional +3.3V supply voltage oper­ation with reduced linearity performance. The AMPSET pin needs to be biased accordingly in each mode, as listed in Table 2. In addition, the driver amplifiers can be shut down independently to conserve DC power. See the biasing scheme outlined in Table 2 for details.
SPI Interface and Attenuator Settings
The attenuators can be programmed through the 3-wire SPI/MICROWIREK-compatible serial interface using 5-bit words. Fifty-six bits of data are shifted in MSB first and framed by CS. The first 28 bits set the first attenua­tor, and the following 28 bits set the second attenuator. When CS is low, the clock is active and data is shifted on the rising edge of the clock. When CS transitions high, the data is latched and the attenuator setting changes (Figure 1). See Table 3 for details on the SPI data format.
MAX2063
MICROWIRE is a trademark of National Semiconductor Corp.
15
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
1st Digital Attenuator Programming
D0:D7 Reserved. Set to logic 0.
D8:D12 Preprogrammed Attenuation State 1
D8 = 1dB bit, D9 = 2dB bit, D10 = 4dB bit,
D11 = 8dB bit, D12 = 16dB bit
D13:D17 Preprogrammed Attenuation State 2
D13 = 1dB bit, D14 = 2dB bit, D15 = 4dB bit,
MAX2063
D16 = 8dB bit, D17 = 16dB bit
D18:D22 Preprogrammed Attenuation State 3
D18 = 1dB bit, D19 = 2dB bit, D20 = 4dB bit,
D21 = 8dB bit, D22 = 16dB bit
D23:D27 Preprogrammed Attenuation State 4
D23 = 1dB bit, D24 = 2dB bit, D25 = 4dB bit,
D26 = 8dB bit, D27 = 16dB bit
MSB LSB
DATA
CLOCK
CS
DN D1 D0D(N-1)
t
CS
2nd Digital Attenuator Programming
D28:D35 Reserved. Set to logic 0.
D36:D40 Preprogrammed Attenuation State 1
D36 = 1dB bit, D37 = 2dB bit, D38 = 4dB bit,
D39 = 8dB bit, D40 = 16dB bit
D41:D45 Preprogrammed Attenuation State 2
D41 = 1dB bit, D42 = 2dB bit, D43 = 4dB bit,
D44 = 8dB bit, D45 = 16dB bit
D46:D50 Preprogrammed Attenuation State 3
D46 = 1dB bit, D47 = 2dB bit, D48 = 4dB bit,
D49 = 8dB bit, D50 = 16dB bit
D51:D55 Preprogrammed Attenuation State 4
D51 = 1dB bit, D52 = 2dB bit, D53 = 4dB bit,
D54 = 8dB bit, D55 = 16dB bit
t
t
CH
CW
Figure 1. SPI Timing Diagram
16
t
EWS
NOTES:
DATA ENTERED ON CLOCK RISING EDGE. ATTENUATOR REGISTER STATE CHANGE ON CS RISING EDGE. N = NUMBER OF DATA BITS.
t
ES
t
EW
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
Table 3. SPI Data Format
FUNCTION BIT DESCRIPTION
D55 (MSB) 16dB step (MSB of the 5-bit word used to program the digital attenuator state 4)
2nd Digital Attenuator State 4
2nd Digital Attenuator State 3
2nd Digital Attenuator State 2
2nd Digital Attenuator State 1
Reserved
1st Digital Attenuator State 4
1st Digital Attenuator State 3
1st Digital Attenuator State 2
D54 8dB step D53 4dB step D52 2dB step D51 1dB step D50 16dB step (MSB of the 5-bit word used to program the digital attenuator state 3) D49 8dB step D48 4dB step D47 2dB step D46 1dB step D45 16dB step (MSB of the 5-bit word used to program the digital attenuator state 2) D44 8dB step D43 4dB step D42 2dB step D41 1dB step D40 16dB step (MSB of the 5-bit word used to program the digital attenuator state 1) D39 8dB step D38 4dB step D37 2dB step D36 1dB step D35 D34 D33 D32 D31 D30 D29 D28 D27 16dB step (MSB of the 5-bit word used to program the digital attenuator state 4) D26 8dB step D25 4dB step D24 2dB step D23 1dB step D22 16dB step (MSB of the 5-bit word used to program the digital attenuator state 3) D21 8dB step D20 4dB step D19 2dB step D18 1dB step D17 16dB step (MSB of the 5-bit word used to program the digital attenuator state 2) D16 8dB step D15 4dB step D14 2dB step D13 1dB step
MAX2063
Bits D[35:28] are reserved. Set to logic 0.
17
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
Table 3. SPI Data Format (continued)
FUNCTION BIT DESCRIPTION
D12 16dB step (MSB of the 5-bit word used to program the digital attenuator state 1)
1st Digital Attenuator State 1
MAX2063
Reserved
D11 8dB step D10 4dB step
D9 2dB step D8 1dB step D7 D6 D5 D4 D3 D2 D1
D0 (LSB)
Bits D[7:0] are reserved. Set to logic 0.
Digital Attenuator Settings Using
the Parallel Control Bus
To capitalize on its fast 25ns switching capability, the device offers a supplemental 5-bit parallel control inter­face for each attenuator. The two buses of the digital logic attenuator-control pins (D0_ _–D4_ _) enable the attenuator stages (Table 4).
Direct access to these 5-bit buses enables the user to avoid any programming delays associated with the SPI interface. One of the limitations of any SPI bus is the speed at which commands can be clocked into each peripheral device. By offering direct access to the 5-bit parallel interface, the user can quickly shift between digital attenuator states as needed for critical “fast­attack” automatic gain-control (AGC) applications.
Note that when the digital attenuators are controlled by the SPI bus, the control voltages of each digital attenuator show on the five parallel control pins (pins 14–17, 19 for digital attenuator 2, and pins 42, 44–47 for digital attenuator 1). When the digital attenuators are in SPI mode, the parallel control pins must be open.
“Rapid-Fire” Preprogrammed
Attenuation States
The device has an added feature that provides “rapid-fire” gain selection between four preprogrammed attenuation steps. As with the supplemental 5-bit buses previously mentioned, this “rapid-fire” gain selection allows the user to quickly access any one of four customized digital attenuation states without incurring
the delays associated with reprogramming the device through the SPI bus.
The switching speed is comparable to that achieved using the supplemental 5-bit parallel buses. However, by employing this specific feature, the digital attenuator I/O is further reduced by a factor of either 5 or 2.5 (5 control bits vs. 1 or 2, respectively), depending on the number of states desired.
The user can employ the STA_A_1 and STA_B_1 (STA_A_2 and STA_B_2 for attenuator 2) logic input pins to apply each step as required (see Tables 5 and 6). Toggling just the STA_A_1 pin (1 control bit) yields two preprogrammed attenuation states; toggling both the STA_A_1 and STA_B_1 pins together (2 control bits) yields four preprogrammed attenuation states.
As an example, assume that the AGC application requires a static attenuation adjustment to trim out gain inconsistencies within a receiver lineup. The same AGC circuit can also be called upon to dynamically attenuate an unwanted blocker signal that could desense the receiver and lead to an ADC overdrive condition. In this example, the device would be preprogrammed (through the SPI bus) with two customized attenuation states—one to address the static gain-trim adjustment, the second to counter the unwanted blocker condition.
Toggling just the STA_A_1 control bit enables the user to switch quickly between the static and dynamic attenuation settings with only one I/O pin.
18
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
If desired, the user can also program two additional attenuation states by using the STA_B_1 control bit as a second I/O pin. These two additional attenuation settings are useful for software-defined radio applications where multiple static gain settings are needed to account for different frequencies of operation, or where multiple dynamic attenuation settings are needed to account for different blocker levels (as defined by multiple wireless standards).
Power-Supply Sequencing
The sequence to be used is:
1) Power supply
2) Control lines
Table 4. Digital Attenuator Settings (Parallel Control, DA_SP = 0)
INPUT LOGIC = 0 (OR GROUND) LOGIC = 1
D0_ _ Disable 1dB attenuator Enable 1dB attenuator D1_ _ Disable 2dB attenuator Enable 2dB attenuator D2_ _ Disable 4dB attenuator Enable 4dB attenuator D3_ _ Disable 8dB attenuator Enable 8dB attenuator D4_ _ Disable 16dB attenuator Enable 16dB attenuator
The pin configuration of the device is optimized to facili­tate a very compact physical layout of the device and its associated discrete components. The exposed pad (EP) of the device’s 48-pin thin QFN-EP package provides a low thermal-resistance path to the die. It is important that the PCB on which the device is mounted be designed to conduct heat from the EP. In addition, provide the EP with a low inductance path to electrical ground. The EP MUST be soldered to a ground plane on the PCB, either directly or through an array of plated via holes.
Table 7 lists typical application circuit component values.
Layout Considerations
MAX2063
Table 5. Programmed Attenuation State Settings for Attenuator 1 (DA_SP = 1)
STA_A_1 STA_B_1 SETTING FOR DIGITAL ATTENUATOR 1*
0 0 Preprogrammed attenuation state 1 1 0 Preprogrammed attenuation state 2 0 1 Preprogrammed attenuation state 3 1 1 Preprogrammed attenuation state 4
*Defined by SPI programming bits D8:D27 (see Table 3 for details).
Table 6. Programmed Attenuation State Settings for Attenuator 2 (DA_SP = 1)
STA_A_2 STA_B_2 SETTING FOR DIGITAL ATTENUATOR 2*
0 0 Preprogrammed attenuation state 1 1 0 Preprogrammed attenuation state 2 0 1 Preprogrammed attenuation state 3 1 1 Preprogrammed attenuation state 4
*Defined by SPI programming bits D36:D55 (see Table 3 for details).
19
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
Table 7. Typical Application Circuit Component Values
DESIGNATION QTY DECRIPTION COMPONENT SUPPLIER
C1, C2, C6, C8,
C9, C13
C4, C7, C11,
C14, C16
MAX2063
C15 1
L1, L2 2
U1 1
1000pF capacitors (0402)
6
Murata GRM1555C1H102J
10nF capacitors (0402)
5
Murata GRM155R71E103K
1mF capacitor (0603) Murata GRM188R71C105K
820nH inductors (1008) Coilcraft 1008CS-821XJLC
VGA (48-pin thin QFN-EP, 7mm x 7mm) Maxim MAX2063ETM+
Murata North America Electronics, Inc.
Murata North America Electronics, Inc.
Murata North America Electronics, Inc.
Coilcraft, Inc.
Maxim Integrated Products, Inc.
20
Dual 50MHz to 1000MHz High-Linearity,
Serial/Parallel-Controlled Digital VGA
Typical Application Circuit
MAX2063
GND
AMP_IN_2
GND
D_ATT_IN_2
RF OUTPUT 2
C13
V
24
GND
23
GND
22
DA_SP
21
GND
20
D4_2
19
D_ATT_OUT_2
18
D3_2
17
D2_2
16
D1_2
15
D0_2
14
GND
13
CC_AMP_2
V
CC
C11
C9
RF
OUTPUT 1
C6
L1 L2
AMP_IN_1
GND
PD_1
GND
35
34 33 32 31 30 29 28 272625
V
CC
C4
C2
V
CC_AMP_1
GND
GND
GND
GND
D4_1
D_ATT_OUT_1
D3_1
D2_1
D1_1
D0_1
GND
36
37
38
39
40
41
42
43
44
45
46
47
48
+
ACTIVE
BIAS
DIGITAL
ATTENUATOR
1
2
3 4 5 6 7 8 9 101112
1
GND
STA_B_1
STA_A_1
D_ATT_IN_1
C7
C15
AMPSET
AMP_OUT_1
AMP AMP
MAX2063
SPI
CLK
DAT
V
CC
REG_OUT
CS
GND
AMP_OUT_2
ACTIVE
BIAS
EXPOSED
PAD
DIGITAL
ATTENUATOR
2
CC_RG
V
STA_B_2
C14
PD_2
STA_A_2
C1
RF
INPUT 1
Chip Information
PROCESS: SiGe BiCMOS
V
CC
C16
C8
RF INPUT 2
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
48 Thin QFN-EP T4877+7
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
21-0144 90-0133
21
Dual 50MHz to 1000MHz High-Linearity, Serial/Parallel-Controlled Digital VGA
Revision History
REVISION
NUMBER
0 6/10 Initial release —
REVISION
DATE
MAX2063
DESCRIPTION
PAGES
CHANGED
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©
2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
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