The MAX2038 8-channel variable-gain amplifier (VGA)
and programmable octal mixer array is designed for
high linearity, high dynamic range, and low noise performance targeting ultrasound imaging and Doppler
applications. Each amplifier features differential inputs
and outputs and a total gain range of 42dB (typ). In
addition, the VGAs offer very low output-referred noise
performance suitable for interfacing with 12-bit ADCs.
The MAX2038 VGA is optimized for less than ±0.25dB
absolute gain error to ensure minimal channel-to-channel ultrasound beamforming focus error. The device’s
differential outputs are designed to directly drive ultrasound ADCs through an external passive anti-aliasing
filter. A switchable clamp is also provided at each
amplifier’s output to limit the output signals, thereby
preventing ADC overdrive or saturation.
Dynamic performance of the device is optimized to
reduce distortion to support second-harmonic imaging.
The device achieves a second-harmonic distortion
specification of -70dBc at V
OUT
= 1.5V
P-P
and f
IN
=
5MHz and an ultrasound-specific*, two-tone, third-order
intermodulation distortion specification of -52dBc at
V
OUT
= 1.5V
P-P
and f
IN
= 5MHz.
The MAX2038 also integrates an octal quadrature mixer
array and programmable LO phase generators for a
complete CW beamforming solution. The LO phase
selection for each channel can be programmed using a
digital serial interface and a single high-frequency clock
or the LOs for each complex mixer pair can be directly
driven using separate 4 x LO clocks. The serial interface
is designed to allow multiple devices to be easily daisy
chained to minimize program interface wiring. The LO
phase dividers can be programmed to allow 4, 8, or 16
quadrature phases. The input path of each CW mixer
consists of a selectable lowpass filter for optimal CWD
noise performance. The outputs of the mixers are
summed into I and Q differential current outputs. The
mixers and LO generators are designed to have exceptionally low noise performance of -155dBc/Hz at 1kHz
offset from a 1.25MHz carrier.
The MAX2038 operates from a +5.0V power supply,
consuming only 120mW/channel in VGA mode and
269mW/channel in normal power CW mode. A lowpower CW mode is also available and consumes only
226mW/channel. The device is available in a lead-free
100-pin TQFP package (14mm x 14mm x 1mm) with an
exposed pad. Electrical performance is guaranteed
over a 0°C to +70°C temperature range.
Applications
Ultrasound ImagingSonar
Features
o 8-Channel Configuration
o High Integration for Ultrasound Imaging
Applications
o Pin Compatible with the MAX2037 Ultrasound VGA
VGA Features
o Maximum Gain, Gain Range, and Output-Referred
Noise Optimized for Interfacing with 12-Bit ADCs
Maximum Gain of 29.5dB
Total Gain Range of 42dB
22nV/√√Hz Ultra-Low Output-Referred Noise at
5MHz
o ±0.25dB Absolute Gain Error
o 120mW Consumption per Channel
o Switchable Output VGA Clamp Eliminating ADC
Overdrive
o Fully Differential VGA Outputs for Direct ADC
Drive
o Variable Gain Range Achieves 42dB Dynamic
Range
o -70dBc HD2 at V
OUT
= 1.5V
P-P
and fIN= 5MHz
o Two-Tone Ultrasound-Specific* IMD3 of
-52dBc at V
OUT
= 1.5V
P-P
and fIN= 5MHz
CW Doppler Mixer Features
o Low Mixer Noise of -155dBc/Hz at 1kHz Offset
from 1.25MHz Carrier
o Serial-Programmable LO Phase Generator for 4, 8,
16 LO Quadrature Phase Resolution
o Optional Individual Channel 4 x fLOLO Input
Drive Capability
o 269mW Power Consumption per Channel (Normal
Power Mode) and 226mW Power Consumption
per Channel (Low-Power Mode)
= 0, LOW_PWR = 0,
M4_EN = 0, CW_FILTER = 0 or 1, TMODE = 0, PD = 0, CW_VG = 1, CW_M1 = 0, CW_M2 = 0, no RF signals applied, capacitance to
GND at each of the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF,
R
L =
1kΩ, CW mixer outputs pulled up to +11V through four separate ±0.1% 115Ω resistors, all CW channels programmed off.
Typical values are at V
CC
= V
REF
= 5V, T
A =
+25°C, unless otherwise noted.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC, V
REF
to GND .................................................-0.3V to +5.5V
Any Other Pins to GND...............................-0.3V to (V
CC
+ 0.3V)
CW Mixer Output Voltage to GND (CW_IOUT+, CW_IOUT-,
= 0, LOW_PWR = 0,
M4_EN = 0, CW_FILTER = 0 or 1, TMODE = 0, PD = 0, CW_VG = 0, CW_M1 = 0, CW_M2 = 0, no RF signals applied,
capacitance to GND at each of the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF,
R
L =
1kΩ, CW mixer outputs pulled up to +11V through four separate ±0.1% 115Ω resistors. Typical values are at VCC= V
REF
= 5V,
T
A =
+25°C, unless otherwise noted.) (Note 2)
CW MIXER MODE
Current in Full-Power Mode
5V V
Current in Full-Power Mode
11V V
Current in Full-Power Mode
5V V
Power Dissipation in Full-Power
Mode
Current in Low-Power Mode
5V V
Current in Low-Power Mode
11V V
Current in Low-Power Mode
5V V
Power Dissipation in Low-Power
Mode
Mixer LVDS LO Input CommonMode Voltage
LVDS LO Differential Input
Voltage
LVDS LO Input
Common-Mode Current
LVDS LO Differential
Input Resistance
Mixer IF Common-Mode Output
Current
DATA Output High Voltage
DATA Output Low Voltage
PARAMETERSYMBOLCONDTIONSMINTYPMAXUNITS
Supply
CC
Supply
MIX
Supply
REF
Supply
CC
Supply
MIX
Supply
REF
I
CC_FP
I
MIX_FP
I
REF_FP
P
DISS_FP
I
CC_LP
I
MIX_LP
I
REF_LP
P
DISS_LP
Refer s to V
Refer s to V
Refer s to V
Total power dissipation (all 8 channels
including both 5V (V
mixer pullup supply power dissipation in the
device) (Note 4)
LOW _P WR = 1; r efer s to V
( al l 8 channel s)
LOW _P WR = 1; r efer s to V
( al l 8 channel s)
LOW _P WR = 1; r efer s to V
( al l 8 channel s)
LOW_PWR = 1; total power dissipation
(all 8 channels including both 5V (V
V
REF
dissipation in the device) (Note 4)
Modes 1 and 2 (Note 5)
Modes 1 and 2200700mV
Per pin150200µA
Modes 1 and 2 (Note 6)30kΩ
Common-mode current in each of the
differential mixer outputs (Note 7)
DOUT voltage when terminated in DIN
(daisy chain) (Note 8)
DOUT voltage when terminated in DIN
(daisy chain) (Note 8)
tance to GND at each of the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF, R
L
= 1kΩ, CW
mixer outputs pulled up to +11V through four separate ±0.1% 115Ω resistors, differential mixer inputs are driven from a low impedance source. Typical values are at V
tance to GND at each of the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF, R
L
= 1kΩ, CW
mixer outputs pulled up to +11V through four separate ±0.1% 115Ω resistors, differential mixer inputs are driven from a low impedance source. Typical values are at V
Note 2: Specifications at TA= +25°C and TA = +70°C are guaranteed by production test. Specifications at TA= 0°C are guaran-
teed by design and characterization.
Note 3: Noise performance of the device is dependent on the noise contribution from the supply to V
REF
. Use a low-noise supply for
V
REF
. V
CC
and V
REF
can be connected together to share the same supply voltage if the supply for V
CC
exhibits low noise.
Note 4: Total on-chip power dissipation is calculated as P
DISS
= V
CC
x ICC+ V
REF
x I
REF
+ [11V - (I
MIX
/4) x 115] x I
MIX
.
Note 5: Note that the LVDS CWD LO clocks are DC-coupled. This is to ensure immediate synchronization when the clock is first
turned on. An AC-coupled LO is problematic in that the RC time constant associated with the coupling capacitors and the
input impedance of the pin causes there to be a period of time (related to the RC time constant) when the DC level on the
chip side of the capacitor is outside the acceptable common-mode range and the LO swing does not exceed both the
logic thresholds required for proper operation. This problem associated with AC-coupling would cause an inability to
ensure synchronization among beam-forming channels. The LVDS signal is terminated differentially with an external 100Ω
resistor on the board.
Note 6: External 100Ω resistor terminates the LVDS differential signal path.
Note 7: The mixer common-mode current (3.25mA/channel) is specified as the common-mode current in each of the differential
Note 8: Specification guaranteed only for DOUT driving DIN of the next device in a daisy-chain fashion.
Note 9: This response time does not include the CW output highpass filter. When switching to VGA mode, the CW outputs stop
drawing current and the output voltage goes to the rail. If a highpass filter is used, the recovery time can be excessive and
a switching network is recommended as shown in the
Applications Information
section.
Note 10: See the
Ultrasound-Specific IMD3 Specification
in the
Applications Information
section.
Note 11: Mixer output-voltage compliance is the range of acceptable voltages allowed on the CW mixer outputs.
Note 12: Channel-to-channel gain-and-phase matching measured on 30 pieces during engineering characterization at room tem-
perature. Each mixer is used as a phase detector and produces a DC voltage in the IQ plane. The phase is given by the
angle of the vector drawn on that plane. Multiple channels from multiple parts are compared to each other to produce the
phase variation.
Note 13: Transconductance is defined as the quadrature summing of the CW differential output current at baseband divided by the
+5V Reference Supply. Connect to a low-noise power supply. Bypass to GND with a 0.1µF capacitor
37, 93V
REF
as close as possible to the pins. Note that noise performance of the device is dependent on the noise
contribution from the supply to V
connected together to share the same supply voltage if the supply for V
. Use a low-noise supply for V
REF
. V
REF
and V
CC
exhibits low noise.
CC
REF
can be
38EXT_RES
39CW_VG
40PD
41CW_FILTER
43M4_EN
44LOW_PWRLow-Power Enable. Set high to enable low-power CW mixer mode for the device.
45DOUT
47N.C.No Connect. Leave this pin unconnected.
48LO8CW LO Input for Channel 8. LO clock input for modes 3 and 4.
External Resistor. Connect a 0.1% 7.5kΩ resistor to ground as close as possible to the pin to set the
bias for the internal biasing circuitry.
CW Mixer VGA Enable. Selects for VGA or CW mixer operation. Set CW_VG to a logic-high to enable
the VGAs while the CW mixers are powered down. Set CW_VG to a logic-low to enable the CW mixers
while the VGAs are powered down.
Power-Down Switch. Drive PD high to set the device in power-down mode. Drive PD low for normal
operation.
CW Filter Mode Corner Frequency Select. Selects in corner frequency of the internal lowpass filter for
the CW path. Set CW_FILTER to a logic-high for a corner frequency of 9.5MHz. Set CW_FILTER to a
logic-low for a corner frequency of 4.5MHz.
Mode 4 Enable. Set M4_EN to a logic-high to override the serial port and activate all 8 channels of the
CW path.
Serial Port Data Output. Data output for ease of daisy-chaining CW channels for analog beamforming
programming.
VGA Analog Gain Control Differential Input. Set the differential voltage to -2V for maximum gain
(+29.5dB), and to +2V for minimum gain (-12.5dB).
CW Mode Select Input 1. Input for programming beamforming mode 1, 2, 3, or 4. See Table 1 for
mode programming details.
CW Mode Select Input 2. Input for programming beamforming mode 1, 2, 3, or 4. See Table 1 for
mode programming details.
VGA Clamp Mode Enable. Drive VG_CLAMP_MODE high to enable high VGA clamp mode. VGA
output is clamped at typically 2.4V
clamp mode. VGA output is clamped at typically 2.8V
Serial Port Load. Loads the data from the serial shift registers into the I/Q phase dividers. Pull LOAD
bus from high to low and from low to high for programming the I/Q phase dividers.
The MAX2038 is an 8-channel VGA integrated with a
programmable octal quadrature mixer array designed
for ultrasound imaging and Doppler applications. The
device is optimized for efficient power consumption,
high dynamic range, and for exceptionally low noise
performance. The VGA path features differential inputs,
analog variable gain control, differential outputs for
direct ADC drive, and a selectable output voltage
clamp to avoid ADC overdrive. The integrated octal
quadrature mixer array includes serial programmable
LO phase generators for CWD beamforming applications. The LO phase dividers can be programmed for 4,
8, or 16 quadrature phases. Lowpass filters are integrated at the input paths of each CW mixer. The outputs for the mixers are summed into single I/Q
differential current outputs.
The MAX2038 also integrates an octal quadrature mixer
array and programmable LO phase generators for a
complete continuous wave (CW) Doppler beamforming
solution. The LO phase selection for each channel is
programmed using a digital serial interface and a single high-frequency clock, or the LOs for each complex
mixer pair can be directly driven using separate 4 x LO
clocks. The serial interface is designed to allow multiple
devices to be easily daisy chained in order to minimize
program interface wiring. The LO phase dividers can
be programmed to allow 4, 8, or 16 quadrature phases.
The input path of each CW mixer consists of a selectable lowpass filter for optimal CWD noise performance.
The outputs of the mixers are summed into single I and
Q differential current outputs. The mixers and LO generators are designed to have exceptionally low noise
performance of -155dBc/Hz at 1kHz offset from a
1.25MHz carrier, measured with 900mV
P-P
differential
clutter signal.
Variable Gain Amplifier (VGA)
The MAX2038’s VGAs are optimized for high linearity,
high dynamic range, and low output-noise performance,
making this component ideal for ultrasound imaging
applications. The VGA paths also exhibit a channel-tochannel crosstalk of -80dB at 10MHz and an absolute
gain error of less than ±0.25dB for minimal channel-tochannel focusing error in an ultrasound system. Each
VGA path includes circuitry for adjusting analog gain, an
output buffer with differential output ports (VGOUT_+,
VGOUT_-) for driving ADCs, and differential input ports
(VGIN_+, VGIN_-), which are ideal for directly interfacing to the MAX2034 quad LNA. See the
High-Level
Wave Mixer and Programmable Beamformer Functional
Diagram
for details.
The VGA has an adjustable gain range from -12.5dB to
+29.5dB, achieving a total dynamic range of 42dB
(typ). The VGA gain can be adjusted through the differential gain control inputs VG_CTL+ and VG_CTL-. Set
the differential gain-control input voltage at +2V for minimum gain and -2V for maximum gain. The differential
analog control common-mode voltage is 3V (typ).
A clamp is provided to limit the VGA output signals to
avoid overdriving the ADC or to prevent ADC saturation. Set VG_CLAMP_MODE low to clamp the VGA differential outputs at 2.4V
P-P
. Set the VG_CLAMP_MODE
high to disable the clamp.
Power-Down
The device can also be powered down with PD. Set PD
to logic-high for power-down mode. In power-down
mode, the device draws a total supply current of 27mA.
Set PD to a logic-low for normal operation.
Overload Recovery
The device is also optimized for quick overload recovery
for operation under the large input-signal conditions that
are typically found in ultrasound input buffer imaging
applications. See the
Typical Operating Characteristics
for an illustration of the rapid recovery time from a transmit-related overload.
Octal Continuous Wave (CW) Mixer
The MAX2038 CW mixers are designed using an active
double-balanced topology. The mixers achieve high
dynamic range and high linearity performance, with
exceptionally low noise, which is ideal for ultrasound
CWD signal reception. The octal quadrature mixer
array provides noise performance of -155dBc/Hz at
1kHz from a 1.25MHz carrier, and a two-tone thirdorder ultrasound specific intermodulation product of
typically -50dBc. See the
Ultrasound-Specific IMD3
Specification
in the
Applications Information
section
.
The octal array exhibits quadrature and in-phase differential current outputs (CW_QOUT+, CW_QOUT-,
CW_IOUT+, CW_IOUT-) to produce the total CWD
beamformed signal. The maximum differential current
output is typically 3mA
The outputs from the octal mixer array are summed
internally to produce the total CWD summed beamformed signal. The octal array produces eight differential quadrature (Q) outputs and eight differential
in-phase (I) outputs. All quadrature and in-phase outputs are summed into single I and Q differential current
outputs (CW_QOUT+, CW_QOUT-, CW_IOUT+,
CW_IOUT-).
LO Phase Select
The LO phase dividers can be programmed through the
shift registers to allow for 4, 8, or 16 quadrature phases
for a complete CW beamforming solution.
CWD Beamforming Modes
There are four separate modes of operating the CWD
beamformer. See Table 1 for a summary of the different
modes of operation. The mode of operation can be
selected by the CW_M1 and CW_M2 logic inputs.
Phase generation is controlled through the serial interface. See the
Serial Interface
section in the
Applications
Information
section for details on how to program for dif-
ferent quadrature phases.
Mode 1
For mode 1 operation, the LO_LVDS input frequency is
typically 16 x fLO. As the CWD LO frequency range is
1MHz to 7.5MHz, the input frequency ranges from
16MHz to 120MHz. This high LO clock frequency
requires a differential LVDS input. The 16 x fLOinput is
then divided by 16 to produce 16 phases. These 16
phases are generated for each of the 8 channels and
programmed for the selected phase by a serial shift
register. Each channel has a corresponding 5-bit shift
register, which is used to program the output phase of
the divide-by-16 circuit. The first 4 bits of the shift register are for programming the 16 phases, the fifth bit
turns each channel on/off individually. For mode 1, set
both CW_M1 and CW_M2 to a logic-low.
The LO_LVDS input frequency is 8 x fLO(typ) for mode
2 operation. The CWD LO frequency range is 1MHz to
7.5MHz, and the input frequency ranges from 8MHz to
60MHz. This high LO clock frequency requires a differential LVDS input. The 8 x f
LO
input is then divided by 8
to produce 8 phases. These 8 phases are generated
for each of the 8 channels and programmed for the
selected phase by the serial shift register. Note that the
serial shift register is common to modes 1, 2, 3, and
where each channel has a corresponding 5-bit shift
register, which is used to program the output phase.
However, since mode 2 generates 8 phases only, 3 of
the 4 phase-programming bits are used; 5 bits are still
loaded per channel using the serial shift register, but
the phase-programming MSB is a don’t-care bit. The
fifth bit in the shift register always turns each channel
on/off individually. For mode 2, set CW_M1 to a logiclow and set CW_M2 to a logic-high. See Table 3.
Mode 3
The LO_LVDS input is not used in this mode. Separate
4 x fLOclock inputs are provided using LO1–LO8 for
each channel. The CWD LO frequency range is 1MHz
to 7.5MHz, and the input frequency provides ranges
from 4MHz to 30MHz. Note that the LO clock frequency
can utilize 3V CMOS inputs. The 4 x fLOLO1–LO8
inputs are divided by 4 to produce 4 phases. These
4 phases are generated for each of the 8 channels and
programmed for the selected phase by the serial shift
register. For mode 3, 4 phases are generated, and only
2 of the 4 phase-programming bits are required where
the 2-phase programming MSBs are “don’t-care” bits.
For mode 3, set CW_M1 to a logic-high and set CW_M2
to a logic-low. See Table 4.
Mode 4
The LO_LVDS input is not used in this mode. The
appropriate phases are externally provided using separate 4 x fLOLO1–LO8 inputs for each channel. A 4 x f
LO
input is required so the device can internally generate
accurate duty-cycle independent quadrature LO drives.
Note that the serial shift register is not used in this
mode. The CWD LO frequency range is 1MHz to
7.5MHz and the input frequency ranges from 4MHz to
30MHz. The appropriate inputs are provided at LO1 to
LO8. A reset line is provided to the customer so that
they can synchronize all the CWD channels. The reset
line is implemented through the RESET. For mode 4, set
both CW_M1 and CW_M2 to logic-high. See Table 5.
Figure 1 illustrates the serial programming of the 8 individual channels through the serial data port. Note that
the serial data can be daisy chained from one part to
another, allowing a single data line to be used to program multiple chips in the system.
CW Lowpass Filter
The MAX2038 also includes selectable lowpass filters
between each CW differential input pair and corresponding mixer input. Shunt capacitors and resistors
are integrated on chip for high band and low band. The
parallel capacitor/resistor networks, which appear differentially across each of the CW differential inputs, are
selectable through the CW_FILTER. Drive CW_FILTER
high to set the corner frequency of the filter to be fC=
9.5MHz. Drive CW_FILTER low to set the corner frequency equal to fC= 4.5MHz. The CW_VG allows the filter inputs to be disconnected from input nodes (internal
to chip) to prevent overloading the LNA output and to
not change the PW input common-mode voltage.
VGA and CW Mixer Operation
During normal operation, the MAX2038 is configured
such that either the VGA path is enabled while the mixer
array is powered down (VGA mode), or the quadrature
mixer array is enabled while the VGA path is powered
down (CW mode). During VGA mode, besides powering
down the CW mixer array, the differential inputs to the
lowpass filters and CW mixers also are internally disconnected from the input nodes, making the CW differential
inputs (CWIN_+, CWIN_-) high impedance. The CW
mode disconnects the VGA inputs internally from the
input ports of the device. For VGA mode, set CW_VG to a
logic-high, while for CW mode, set CW_VG to a logic-low.
Power-Down and Low-Power Modes
During device power-down, both the VGA and CW
mixer are disabled regardless of the logic set at
CW_VG. Both the VGA and CW mixer inputs are high
impedance since the internal switches to the inputs are
all disconnected. The total supply current of the device
reduces to 27mA. Set PD to a logic-high for device
power-down.
A low-power mode is available to lower the required
power for CWD operation. When selected, the complex
mixers operate at lower quiescent currents and the total
per-channel current is lowered to 53mA. Note that
operation in this mode slightly reduces the dynamic
performance of the device. Table 6 shows the logic
function of standard operating modes.
Figure 1. Data Flow of Serial Shift Register
Table 6. Logic Function of Standard Operating Modes
The mode select response time is the time that the
device takes to switch between CW and VGA modes.
One possible approach to interfacing the CW outputs to
an instrumentation amplifier used to drive an ADC is
shown in Figure 2. In this implementation, there are four
large-value (in the range of 470nF to 1µF) capacitors
between each of the CW_IOUT+, CW_IOUT-,
CW_QOUT+, CW_QOUT- outputs and the circuitry they
are driving. The output of the CW mixer usually drives
the input of an instrumentation amplifier made up of op
amps whose input impedance is set by common-mode
setting resistors.
There are clearly both a highpass corner and a lowpass
corner present in this output network. The lowpass corner is set primarily by the 115Ω mixer pullup resistors,
the series 50Ω resistors, and the shunt 0.022µF capacitor. This lowpass corner is used to filter a combination
of LO leakage and upper sideband. The highpass corner, however, is of a larger concern due to the fact that
it is dominated by the combination of a 1µF DC-blocking capacitor and the pair of shunt 31.6kΩ resistors.
If drawn, the simplified dominant highpass network
would look like Figure 3.
The highpass pole in this case is at f
P
= 1/(2 x pi x RC)
~ 5Hz. Note that this low highpass corner frequency is
required in order to filter the downconverted clutter tone,
which appears at DC, but not interfere with CWD imaging
at frequencies as low as 400Hz. For example, if one wanted to use CWD down to 400Hz, then a good choice for
the highpass pole would be at least a decade below this
(< 40Hz) as not to incur rolloff due to pole. Remember, if
the highpass pole is put at 400Hz, the response is 3dB
down at that corner frequency. The placement of the
highpass pole at 5Hz in the above example is between
the DC and 40Hz limitations just discussed.
The bottom line is that any reasonably sized DC block
between the output of the mixer and the instrumentation
amplifier will pose a significant time constant that slows
the mode select switching speed.
An alternative solution to the approach in Figure 2,
which enables faster mode select response time, is
shown in Figure 4.
In Figure 4, the outputs of the CWD mixers are DCcoupled into the inputs of the instrumentation amplifiers. Therefore, the op amps must be able to accommodate the full compliance range of the mixer outputs,
which is a maximum of 11V when the mixers are disabled, down to the 5V supply of the MAX2038 when the
mixers are enabled. The op amps can be powered
from 11V for the high rail and 5V for the low rail, requiring a 6V op amp.
Figure 2. Typical Example of a CW Mixer’s Output Circuit
Figure 3. Simplified Circuit of Highpass Pole
Figure 4. Improved Mode Select Response Time Achieved with
DC-Coupled Input to Instrumentation Amplifier
The serial interface of the MAX2038 programs the LO for
16, 8, or 4 quadrature phases using a serial shift register implementation. Data is shifted into the device on
DIN. The serial shift register clock is applied to the CLK
input. The serial shift register has 5 bits per channel.
The first 4 bits are for phase programming, and the fifth
bit enables or disables each channel of the mixer array.
Each mixer can be programmed to 1 of 16 phases;
therefore, 4 bits are required for each channel for programming. The master high-frequency mixer clock is
applied to differential inputs LO_LVDS+ and LO_LVDS(for modes 1 and 2) and LO_ (for modes 3 and 4). The
LOAD input is provided to allow the user to load the
phase counters with the programming values to generate the correct LO phases. The input signals for mixing
are applied to the eight differential inputs, CWIN_+ and
CWIN_-. The summed I/Q baseband differential outputs
are provided on CW_IOUT+/- and CW_QOUT+/-.
CW_M1 and CW_M2 are used to select one of the four
possible modes of operation. See Table 1.
The serial interface is designed to allow multiple
devices to be easily daisy chained in order to minimize
program interface wiring. DOUT is available for this
daisy-chain function.
Programming the Beamformer
During normal CWD operation, the mixer clock at LO_ or
LO_LVDS+/- is on and the programming signals on DIN,
CLK, and LOAD are off. (LOAD = high, CLK = low, and
DIN = don’t care, but fixed to a high or low). To start the
programming sequence, turn off the mixer clock. Data is
shifted into the shift register at a recommended 10MHz
programming rate or 100ns minimum data clock
period/time. See Figure 5 for timing details.
After the shift registers are programmed, pull the LOAD
bus to logic-low and then back to logic-high to load the
internal counters into I/Q phase divider/selectors with
the proper values. LOAD must remain low for a minimum time of t
CLH
. The user turns on the mixer clock to
start beamforming. The clock must turn on such that it
starts at the beginning of a mixer clock cycle.
The maximum differential current output is typically
3mA
P-P
and the mixer output compliance voltage
ranges from 4.75V to 12V per mixer channel. The mixer
common-mode current in each of the differential mixer
outputs is typically 3.25mA. The total summed current
would equal N x 3.25mA in each of the 115Ω load
resistors (where N = number of channels). In this case,
the quiescent output voltage at +V
SUM
and -V
SUM
out-
puts would be 11V - (N x 3.25mA x 115) = 11V - (8 x
3.25mA x 115) = 8.05V. The voltage swing at each output, with one channel driven at max output current (differential 3mA
P-P
) while the other channels are not
driven, would be 1.5mA
P-P
x 115Ω or 174mV
P-P
and
the differential voltage would be 348mV
P-P
. The voltage
compliance range is defined as the valid range for
+V
SUM
and -V
SUM
in this example.
External Compensation
External compensation is required for bypassing internal biasing circuitry. Connect as close as possible a
4.7µF capacitor from EXT_C1, EXT_C2, and EXT_C3
(pins 13, 14, 15) to ground.
External Bias Resistor
An external resistor at EXT_RES is required to set the
bias for the internal biasing circuitry. Connect, as close
as possible, a 7.5kΩ (0.1%) resistor from EXT_RES (pin
38) to ground.
Analog Input and Output Coupling
In typical applications, the MAX2038 is being driven from
a low-noise amplifier (such as the MAX2034) and the
VGA is typically driving a discrete differential anti-alias filter into an ADC (such as the MAX1436 octal ADC). The
differential input impedance of the MAX2038 is typically
240Ω. The differential outputs of the VGA are capable of
driving a differential load capacitance to GND at each of
the VGA differential outputs of 60pF, and differential
capacitance across the VGA outputs is 10pF, RL=
1kΩ. The differential outputs have a common-mode
bias of approximately 3.75V. AC-couple these differential outputs if the next stage has a different commonmode input range.
Ultrasound-Specific IMD3 Specification
Unlike typical communications specifications, the two
input tones are not equal in magnitude for the ultrasound-specific IMD3 two-tone specification. In this
measurement, f
1
represents reflections from tissue and
f2 represents reflections from blood. The latter reflections are typically 25dB lower in magnitude, and hence
the measurement is defined with one input tone 25dB
lower than the other. The IMD3 product of interest (f
1
-
(f
2
- f1)) presents itself as an undesired Doppler error
signal in ultrasound applications. See Figure 6.
Board Layout
The pin configuration of the MAX2038 is optimized to
facilitate a very compact physical layout of the device
and its associated discrete components. A typical
application for this device might incorporate several
devices in close proximity to handle multiple channels
of signal processing.
The exposed pad (EP) of the MAX2038’s TQFP-EP
package provides a low thermal-resistance path to the
die. It is important that the PCB on which the MAX2038
is mounted be designed to conduct heat from the EP.
In addition, provide the EP with a low-inductance path
to electrical ground. The EP MUST be soldered to a
ground plane on the PCB, either directly or through an
array of plated via holes.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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