Rainbow Electronics MAX19516 User Manual

General Description

The MAX19516 dual-channel, analog-to-digital convert­er (ADC) provides 10-bit resolution and a maximum
sample rate of 100Msps.

The MAX19516 analog input accepts a wide 0.4V to

1.4V input common-mode voltage range, allowing DC­coupled inputs for a wide range of RF, IF, and base­band front-end components. The MAX19516 provides
excellent dynamic performance from baseband to high
input frequencies beyond 400MHz, making the device
ideal for zero-intermediate frequency (ZIF) and high­intermediate frequency (IF) sampling applications. The
typical signal-to-noise ratio (SNR) performance is
60dBFS and typical spurious-free dynamic range
(SFDR) is 82dBc at f

IN

= 70MHz and f

CLK

= 100MHz.

The MAX19516 operates from a 1.8V supply.
Additionally, an integrated, self-sensing voltage regula­tor allows operation from a 2.5V to 3.3V supply (AVDD).
The digital output drivers operate on an independent
supply voltage (OVDD) over the 1.8V to 3.5V range.
The analog power consumption is only 57mW per chan­nel at V

AVDD

= 1.8V. In addition to low operating
power, the MAX19516 consumes only 1mW in power­down mode and 17mW in standby mode.

Various adjustments and feature selections are avail­able through programmable registers that are
accessed through the 3-wire serial-port interface.
Alternatively, the serial-port interface can be disabled,
with the three pins available to select output mode,
data format, and clock-divider mode. Data outputs are
available through a dual parallel CMOS-compatible out­put data bus that can also be configured as a single
multiplexed parallel CMOS bus.

The MAX19516 is available in a small 7mm x 7mm 48­pin thin QFN package and is specified over the -40°C
to +85°C extended temperature range.

Refer to the MAX19505, MAX19506, and MAX19507
data sheets for pin- and feature-compatible 8-bit,
65Msps, 100Msps, and 130Msps versions, respectively.
Refer to the MAX19515 and MAX19517 data sheets for
pin- and feature-compatible 10-bit, 65Msps and
130Msps versions, respectively.

Applications

IF and Baseband Communications, Including
Cellular Base Stations and Point-to-Point
Microwave Receivers

Ultrasound and Medical Imaging
Portable Instrumentation and Low-Power Data

Acquisition
Digital Set-Top Boxes

Features

♦ Very-Low-Power Operation (57mW/Channel at

100Msps)

♦ 1.8V or 2.5V to 3.3V Analog Supply

♦ Excellent Dynamic Performance

60dBFS SNR at 70MHz
82dBc SFDR at 70MHz

♦ User-Programmable Adjustments and Feature

Selection through an SPI™ Interface

♦ Selectable Data Bus (Dual CMOS or Single

Multiplexed CMOS)

♦ DCLK Output and Programmable Data Output

Timing Simplifies High-Speed Digital Interface

♦ Very Wide Input Common-Mode Voltage Range

(0.4V to 1.4V)

♦ Very High Analog Input Bandwidth (> 850MHz)

♦ Single-Ended or Differential Analog Inputs

♦ Single-Ended or Differential Clock Input

♦ Divide-by-One (DIV1), Divide-by-Two (DIV2), and

Divide-by-Four (DIV4) Clock Modes

♦ Two’s Complement, Gray Code, and Offset Binary

Output Data Format

♦ Out-of-Range Indicator (DOR)

♦ CMOS Output Internal Termination Options

(Programmable)

♦ Reversible Bit Order (Programmable)

♦ Data Output Test Patterns

♦ Small 7mm x 7mm 48-Pin Thin QFN Package with

Exposed Pad

MAX19516

Dual-Channel, 10-Bit, 100Msps ADC

________________________________________________________________

Maxim Integrated Products

1

Ordering Information

19-4226; Rev 0; 7/08

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

+

Denotes a lead-free/RoHS-compliant package.

*

EP = Exposed pad.

Pin Configuration appears at end of data sheet.

SPI is a trademark of Motorola, Inc.

PART TEMP RANGE PIN-PACKAGE

MAX19516ETM+

-40°C to +85°C 48 TQFN-EP*

MAX19516

Dual-Channel, 10-Bit, 100Msps ADC

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

OVDD, AVDD to GND............................................-0.3V to +3.6V

CMA, CMB, REFIO, INA+, INA-, INB+,

INB- to GND ......................................................-0.3V to +2.1V

CLK+, CLK-, SYNC, SPEN, CS, SCLK, SDIN

to GND ..........-0.3V to the lower of (V

AVDD

+ 0.3V) and +3.6V

DCLKA, DCLKB, D9A–D0A, D9B–D0B, DORA, DORB

to GND..........-0.3V to the lower of (V

OVDD

+ 0.3V) and +3.6V

Continuous Power Dissipation (T

A

= +70°C)
48-Pin Thin QFN, 7mm x 7mm x 0.8mm (derate 40mW/°C

above +70°C).............................................................3200mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER

CONDITIONS

UNITS

DC ACCURACY

Resolution 10 Bits

Integral Nonlinearity INL fIN = 3MHz

LSB

Differential Nonlinearity DNL fIN = 3MHz

LSB

Offset Error OE Internal reference

%FS

Gain Error GE External reference = 1.25V

%FS

ANALOG INPUTS (INA+, INA-, INB+, INB-) (Figure 3)

Differential Input-Voltage Range V

DIFF

Differential or single-ended inputs 1.5 V

P-P

Common-Mode Input-Voltage
Range

V

CM

(Note 2) 0.4 1.4 V

Fixed resistance

Input Resistance R

IN

Differential input resistance, common mode
connected to inputs

4

kΩ

Input Current I

IN

Switched capacitance input current, each
input

54 µA

C

PAR

Fixed capacitance to ground, each input 0.7

Input Capacitance

Switched capacitance, each input 1.2

pF

CONVERSION RATE

Maximum Clock Frequency f

CLK

MHz

Minimum Clock Frequency f

CLK

50 MHz

Data Latency Figures 9, 10 9

Cycles

SYMBOL

MIN TYP MAX

-0.8 ±0.25 +0.8

-0.7 ±0.2 +0.7

-0.4 ±0.1 +0.4

-1.5 ±0.3 +1.5

> 100

C

SAMPLE

100

MAX19516

Dual-Channel, 10-Bit, 100Msps ADC

_______________________________________________________________________________________ 3

PARAMETER

CONDITIONS

UNITS

DYNAMIC PERFORMANCE

Small-Signal Noise Floor SSNF fIN = 70MHz, < -35dBFS

dBFS

fIN = 3MHz

fIN = 70MHz

Signal-to-Noise Ratio SNR

f

IN

= 175MHz

dBFS

fIN = 3MHz

fIN = 70MHz

Signal-to-Noise Plus Distortion
Ratio

SINAD

f

IN

= 175MHz

dB

fIN = 3MHz 84

fIN = 70MHz

83

Spurious-Free Dynamic Range
(2nd and 3rd Harmonic)

SFDR1

f

IN

= 175MHz 80

dBc

fIN = 3MHz 82

fIN = 70MHz 74 82

Spurious-Free Dynamic Range
(4th and Higher Harmonics)

SFDR2

f

IN

= 175MHz 82

dBc

fIN = 3MHz -84

fIN = 70MHz -83

Second Harmonic HD2

f

IN

= 175MHz -80

dBc

fIN = 3MHz -86

fIN = 70MHz -86 -74

Third Harmonic HD3

f

IN

= 175MHz -82

dBc

fIN = 3MHz -80

fIN = 70MHz -79

Total Harmonic Distortion THD

f

IN

= 175MHz -77

dBc

fIN = 70MHz ± 1.5MHz, -7dBFS -90

Third-Order Intermodulation IM3

f

IN

= 175MHz ± 2.5MHz, -7dBFS -80

dBc

Full-Power Bandwidth FPBW

MHz

Aperture Delay t

AD

ps

Aperture Jitter t

AJ

0.3

ps

RMS

Overdrive Recovery Time ±10% beyond full scale 1

Cycles

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

SYMBOL

MIN TYP MAX

-60.3

60.1

58.9 60.0

59.7

59.6

58.3 59.5

59.2

72.2

850

850

-72.2

-70.5

MAX19516

Dual-Channel, 10-Bit, 100Msps ADC

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER

CONDITIONS

UNITS

INTERCHANNEL CHARACTERISTICS

f

INA

or f

INB

= 70MHz at -1dBFS 95

Crosstalk

f

INA

or f

INB

= 175MHz at -1dBFS 85

dBc

Gain Match fIN = 70MHz

dB

Offset Match fIN = 70MHz

%FSR

Phase Match fIN = 70MHz

D eg r ees

ANALOG OUTPUTS (CMA, CMB)

CMA, CMB Output Voltage V

COM

Default programmable setting

0.9

V

INTERNAL REFERENCE

REFIO Output Voltage

V

REFIO Temperature Coefficient TC

REF

ppm/°C

EXTERNAL REFERENCE

REFIO Input-Voltage Range V

REFIN

V

REFIO Input Resistance R

REFIN

10

kΩ

CLOCK INPUTS (CLK+, CLK-)—DIFFERENTIAL MODE

Differential Clock Input Voltage

V

P-P

Self-biased 1.2

Differential Input Common-Mode
Voltage

DC-coupled clock signal

V

Differential, default 10 kΩ

Differential, internal termination selected

ΩInput Resistance R

CLK

Common mode 9 kΩ

Input Capacitance C

CLK

To ground, each input 3 pF

CLOCK INPUTS (CLK+, CLK-)—SINGLE-ENDED MODE (V

CLK-

< 0.1V)

Single-Ended Mode Selection
Threshold (V

CLK-

)

0.1 V

Allowable Logic Swing (V

CLK+

)

V

Single-Ended Clock Input High
Threshold (V

CLK+

)

1.5 V

Single-Ended Clock Input Low
Threshold (V

CLK+

)

0.3 V

V

CLK+

= V

AVDD

= 1.8V or 3.3V

Input Leakage (CLK+)

V

CLK+

= 0

µA

Input Leakage (CLK-) V

CLK-

= 0

-50 µA

Input Capacitance (CLK+) 3pF

SYMBOL

MIN TYP MAX

±0.05

±0.1

±0.5

V

REFOUT

0.85

1.23 1.25 1.27

< ±60

1.25 +5/

-10%

±20%

0.4 to 2.0

1.0 to 1.4

100

0.95

0 - V

AVDD

-0.5

-150

+0.5

MAX19516

Dual-Channel, 10-Bit, 100Msps ADC

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER

CONDITIONS

UNITS

CLOCK INPUTS (SYNC)

Allowable Logic Swing

V

Sync Clock Input High Threshold

1.5 V

Sync Clock Input Low Threshold

0.3 V

V

SYNC

= V

AVDD

= 1.8V or 3.3V

Input Leakage

V

SYNC

= 0

µA

Input Capacitance 4.5 pF

DIGITAL INPUTS (SHDN, SPEN)

Allowable Logic Swing

V

Input High Threshold 1.5 V

Input Low Threshold 0.3 V

V

SHDN/VSPEN

= V

AVDD

= 1.8V or 3.3V

Input Leakage

V

SHDN/VSPEN

= 0

µA

Input Capacitance C

DIN

3pF

SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = 0V)—SERIAL-PORT CONTROL MODE

Allowable Logic Swing

V

Input High Threshold 1.5 V

Input Low Threshold 0.3 V

V

SCLK/VSDIN/VCS

= V

AVDD

= 1.8V or 3.3V

Input Leakage

V

SCLK/VSDIN/VCS

= 0

µA

Input Capacitance C

DIN

3pF

SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = V

AVDD

)—PARALLEL CONTROL MODE (Figure 5)

V

SCLK/VSDIN/VCS

= V

AVDD

= 1.8V 7 12 17

Input Pullup Current

V

SCLK/VSDIN/VCS

= V

AVDD

= 3.3V 16 21 26

µA

V

SCLK/VSDIN/VCS

= 0, V

AVDD

= 1.8V -65 -50 -35

Input Pulldown Current

V

SCLK/VSDIN/VCS

= 0, V

AVDD

= 3.3V

-90 -75

µA

I = 0V, V

AVDD

= 1.8V

Open-Circuit Voltage V

OC

I = 0V, V

AVDD

= 3.3V

V

DIGITAL OUTPUTS (75Ω, D0–D9 (A and B Channel), DCLKA, DCLKB, DORA, DORB)

Output-Voltage Low V

OL

I

SINK

= 200µA 0.2 V

Output-Voltage High V

OH

I

SOURCE

= 200µA

V

OVDD

V

V

OVDD

applied

Three-State Leakage Current I

LEAK

GND applied

µA

SYMBOL

MIN TYP MAX

0 - V

AVDD

-0.5

0 - V

AVDD

-0.5

0 - V

AVDD

-0.5

-105

1.35 1.45 1.55

2.58 2.68 2.78

- 0.2

-0.5

+0.5

+0.5

+0.5

+0.5

MAX19516

Dual-Channel, 10-Bit, 100Msps ADC

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER-MANAGEMENT CHARACTERISTICS

Wake-Up Time from Shutdown t

Wake-Up Time from Standby t

WAKE

WAKE

Internal reference, C

= 0.1µF (10τ)5ms

REFIO

Internal reference 15 µs

SERIAL-PORT INTERFACE TIMING (Note 2) (Figure 7)

SCLK Period t
SCLK to CS Setup Time t
SCLK to CS Hold Time t

SDIN to SCLK Setup Time t

SDIN to SCLK Hold Time t

SCLK to SDIN Output Data Delay t

SCLK

CSS

CSH

SDS

SDH

SDD

Serial-data write 10 ns

Serial-data write 0 ns

Serial-data read 10 ns

50 ns

10 ns

10 ns

TIMING CHARACTERISTICS—DUAL BUS PARALLEL MODE (Figure 9) (Default Timing, see Table 5)

Clock Pulse-Width High t

Clock Pulse-Width Low t

Clock Duty Cycle tCH/t

Data Delay After Rising Edge of
CLK+

Data to DCLK Setup Time t

Data to DCLK Hold Time t

CH

CL

CLK

t

DD

SETUP

HOLD

CL = 10pF, V

CL = 10pF, V

CL = 10pF, V

CL = 10pF, V

= 1.8V (Note 2) 2.9 4.8 6.6

OVDD

= 3.3V 3.6

OVDD

= 1.8V (Note 2) 8.2 8.8 ns

OVDD

= 1.8V (Note 2) 0.7 1.2 ns

OVDD

TIMING CHARACTERISTICS—MULTIPLEXED BUS PARALLEL MODE (Figure 10) (Default Timing, see Table 5)

Clock Pulse-Width High t

Clock Pulse-Width Low t

Clock Duty Cycle tCH/t

Data Delay After Rising Edge of
CLK+

Data to DCLK Setup Time t

Data to DCLK Hold Time t

DCLK Duty Cycle t

MUX Data Duty Cycle t

CH

CL

CLK

t

DD

SETUP

HOLD

DCH/tCLKCL

CHA/tCLKCL

CL = 10pF, V

CL = 10pF, V

CL = 10pF, V

CL = 10pF, V

= 10pF, V

= 10pF, V

= 1.8V (Note 2) 2.6 4.4 6.5

OVDD

= 3.3V 3.5

OVDD

= 1.8V (Note 2) 2.8 4.0 ns

OVDD

= 1.8V (Note 2) -0.2 1.0 ns

OVDD

= 1.8V (Note 2) 42 50 59 %

OVDD

= 1.8V (Note 2) 40 50 65 %

OVDD

TIMING CHARACTERISTICS—SYNCHRONIZATION (Figure 12)

Setup Time for Valid Clock Edge t

Hold-Off Time for Invalid Clock
Edge

Minimum Synchronization Pulse
Width

SUV

t

HO

Edge mode (Note 2) 0.7 ns

Edge mode (Note 2) 0.5 ns

Relative to input clock period 2 Cycles

5.0 ns

5.0 ns

30 to 70 %

ns

5.0 ns

5.0 ns

30 to 70 %

ns

MAX19516

Dual-Channel, 10-Bit, 100Msps ADC

_______________________________________________________________________________________ 7

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER

CONDITIONS

UNITS

POWER REQUIREMENTS

Low-level V

AVDD

1.7 1.9

Analog Supply Voltage V

AVDD

High-level V

AVDD

(regulator mode, invoked

automatically)

2.3 3.5

V

Digital Output Supply Voltage V

OVDD

1.7 3.5 V

Dual channel 63 77

Single channel active 37

Standby mode 9.5 13

Power-down mode

0.9

Analog Supply Current I

AVDD

Power-down mode, V

AVDD

= 3.3V 1.6

mA

Dual channel

139

Dual channel, V

AVDD

= 3.3V

Single channel active 67

Standby mode 17 24

Power-down mode 1.2 1.6

Analog Power Dissipation P

DA

Power-down mode, V

AVDD

= 3.3V 2.9

mW

Dual-channel mode, CL = 10pF 20

Digital Output Supply Current I

OVDD

Power-down mode

mA

Note 1: Specifications ≥ +25°C guaranteed by production test, specifications < +25°C guaranteed by design and characterization.
Note 2: Guaranteed by design and characterization.

SYMBOL

MIN TYP MAX

0.65

113

208

< 0.1

MAX19516

Dual-Channel, 10-Bit, 100Msps ADC

8 _______________________________________________________________________________________

Typical Operating Characteristics

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= +25°C, unless otherwise noted.)

0

-20

-40

-60

-80

AMPLITUDE (dBFS)

-100

-120
0 5 10 15 25 3020 40 45 5035

FREQUENCY (MHz)

3MHz INPUT FFT PLOT

0

-20

-40

-60

-80

AMPLITUDE (dBFS)

175MHz INPUT FFT PLOT

fIN = 175.489044MHz

= -0.506dBFS

A

IN

SNR = 59.222dB
SINAD = 59.187dB
THD = -80.109dBc
SFDR1 = 87.850dBc
SFDR2 = 83.290dBc

fIN = 2.99911499MHz

= -0.446dBFS

A

IN

SNR = 59.591dB
SINAD = 59.566dB
THD = -82.007dBc
SFDR1 = 90.747dBc
SFDR2 = 86.163dBc

MAX19516 toc01

AMPLITUDE (dBFS)

MAX19516 toc04

AMPLITUDE (dBFS)

3MHz SINGLE-ENDED INPUT FFT PLOT

0

-20

-40

-60

-80

-100

-120
0 5 10 15 25 3020 40 45 5035

fIN = 2.99911499MHz

= -0.474dBFS

A

IN

SNR = 59.139dB
SINAD = 58.968dB
THD = -73.092dBc
SFDR1 = 74.814dBc
SFDR2 = 79.872dBc

FREQUENCY (MHz)

70MHz TWO-TONE IMD PLOT

0

f

= 68.4169769MHz

IN1

= 71.4000701MHz

f

IN2

-20

-40

-60

-80

MAX19516 toc02

AMPLITUDE (dBFS)

MAX19516 toc05

AMPLITUDE (dBFS)

0

fIN = 70.0935363MHz

= -0.473dBFS

A

IN

-20
SNR = 59.422dB

SINAD = 59.398dB
THD = -81.978dBc

-40
SFDR1 = 88.062dBc

SFDR2 = 86.514dBc

-60

-80

-100

-120
0 5 10 15 25 3020 40 45 5035

FREQUENCY (MHz)

175MHz TWO-TONE IMD PLOT

0

f

= 177.29835MHz

IN1

= 172.40028MHz

f

IN2

-20

-40

-60

-80

70MHz INPUT FFT PLOT

MAX19516 toc03

MAX19516 toc06

-100

-120
0 5 10 15 25 3020 40 45 5035

FREQUENCY (MHz)

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

-0.2

-0.4

-0.6

-0.8

-1.0
0 256 512 768 1024

DIGITAL OUTPUT CODE

MAX19516 toc07

-100

-120
0 5 10 15 25 3020 40 45 5035

FREQUENCY (MHz)

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

-0.2

-0.4

-0.6

-0.8

-1.0
0 256 512 768 1024

DIGITAL OUTPUT CODE

-100

-120

95

90

MAX19516 toc08

85

80

75

70

65

PERFORMANCE (dBFS)

60

55

50

0 5 10 15 25 3020 40 45 5035

FREQUENCY (MHz)

PERFORMANCE vs. INPUT FREQUENCY

-THD

SNR

0 50 100 150 200 250 300 350 400

INPUT FREQUENCY (MHz)

SFDR2

MAX19516 toc09

SFDR1

SINAD

Typical Operating Characteristics (continued)

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= +25°C, unless otherwise noted.)

MAX19516

Dual-Channel, 10-Bit, 100Msps ADC

_______________________________________________________________________________________ 9

PERFORMANCE

vs. SAMPLING FREQUENCY

SAMPLING FREQUENCY (Msps)

PERFORMANCE (dBFS)

MAX19516 toc12

60 65 70 75 80 85 90 95 100 105 110

50

55

60

65

70

75

80

85

90

100

95

SFDR1

SFDR2

-THD

SINAD

SNR

PERFORMANCE

vs. COMMON-MODE VOLTAGE

COMMON-MODE VOLTAGE (V)

PERFORMANCE (dBFS)

MAX19516 toc13

0.35 0.55 0.75 0.95 1.15 1.35

50

60

70

80

90

100

110

SFDR2

SFDR1

-THD

SINAD

SNR

PERFORMANCE

vs. ANALOG SUPPLY VOLTAGE

ANALOG SUPPLY VOLTAGE (V)

PERFORMANCE (dBFS)

MAX19516 toc14

1.65 1.70 1.75 1.80 1.85 1.90 1.95

50

55

60

65

70

75

80

85

90

95

SFDR2

SFDR1

-THD

SINAD

SNR

PERFORMANCE

vs. ANALOG SUPPLY VOLTAGE

ANALOG SUPPLY VOLTAGE (V)

PERFORMANCE (dBFS)

MAX19516 toc15

2.3 2.5 2.7 2.9 3.1 3.3 3.5

50

55

60

65

70

75

80

85

90

95

SFDR2

SFDR1

-THD

SINAD

SNR

SINGLE-ENDED PERFORMANCE

vs. INPUT FREQUENCY

85

80

75

70

65

60

55

SINGLE-ENDED PERFORMANCE (dBFS)

50

0 10203040506070

SFDR1

SNR

SINAD

INPUT FREQUENCY (MHz)

SFDR2

-THD

110

100

MAX19516 toc10

90

80

70

PERFORMANCE (dBFS)

60

50

PERFORMANCE

vs. ANALOG INPUT AMPLITUDE

SFDR1

SNR

-60 -50 -40 -30 -20 -10 0
ANALOG INPUT AMPLITUDE (dBFS)

SINAD

SFDR2

-THD

MAX19516 toc11

ANALOG SUPPLY CURRENT

vs. SAMPLING FREQUENCY

68

66

64

62

60

58

56

54

ANALOG SUPPLY CURRENT (mA)

52

50

60 65 70 75 80 85 90 95 100 105 110

SAMPLING FREQUENCY (MHz)

ANALOG SUPPLY CURRENT

vs. SUPPLY VOLTAGE

1.65 1.70 1.75 1.80 1.85 1.90 1.95
SUPPLY VOLTAGE (V)

69

67

MAX19516 toc16

65

63

61

59

ANALOG SUPPLY CURRENT (mA)

57

55

-40 -20 0 20 40 60 80

ANALOG SUPPLY CURRENT

vs. TEMPERATURE

TEMPERATURE (°C)

69

MAX19516 toc17

67

65

63

61

59

ANALOG SUPPLY CURRENT (mA)

57

55

MAX19516 toc18

10 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= +25°C, unless otherwise noted.)

MAX19516

Dual-Channel, 10-Bit, 100Msps ADC

67.5

67.0

66.5

66.0

65.5

65.0

ANALOG SUPPLY CURRENT (mA)

64.5

64.0

2.3 2.5 2.7 2.9 3.1 3.3 3.5

ANALOG SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX19516 toc19

DIGITAL SUPPLY CURRENT (mA)

SUPPLY VOLTAGE (V)

DIGITAL SUPPLY CURRENT

vs. SAMPLING FREQUENCY

20

OVDD = 1.8V

18

16

14

12

10

8

6

4

2

0

60 65 70 75 80 85 90 95 100 105 110

SAMPLING FREQUENCY (Msps)

MAX19516 toc20

DIGITAL SUPPLY CURRENT

vs. SAMPLING FREQUENCY

40

OVDD = 3.6V

35

30

25

20

15

10

DIGITAL SUPPLY CURRENT (mA)

5

0

60 65 70 75 80 85 90 95 100 105 110

SAMPLING FREQUENCY (Msps)

MAX19516 toc21

DIGITAL SUPPLY CURRENT

vs. TEMPERATURE

35

33

31

29

27

25

23

21

19

DIGITAL SUPPLY CURRENT (mA)

17

15

-40 -20 0 20 40 60 80

OVDD = 3.6V

OVDD = 1.8V

TEMPERATURE (°C)

PERFORMANCE vs. CLOCK DUTY CYCLE

95

SFDR1

90

85

80

75

-THD

70

PERFORMANCE (dBFS)

65

60

55

SINAD

30 6040 50 5545 6535

CLOCK DUTY CYCLE (%)

SFDR2

SNR

30

DUAL BUS

25

MAX19516 toc22

20

15

10

DIGITAL SUPPLY CURRENT (mA)

5

0

1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5

PERFORMANCE vs. TEMPERATURE

95

90

MAX19516 toc25

85

80

75

70

65

PERFORMANCE (dBFS)

60

55

50

-40 40200-20 8060

DIGITAL SUPPLY CURRENT

vs. SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

SFDR1

-THD

SFDR2

SNR

SINAD

TEMPERATURE (°C)

50

MULTIPLEXED BUS

45

40

MAX19516 toc23

35

30

25

20

15

10

DIGITAL SUPPLY CURRENT (mA)

5

0

1.7 2.5 2.92.1 2.71.9 2.3 3.1 3.53.3

GAIN ERROR vs. TEMPERATURE

0.05

0.04

0.03

MAX19516 toc26

0.02

0.01

0

-0.01

GAIN ERROR (%)

-0.02

-0.03

-0.04

-0.05

-40 40200-20 8060

DIGITAL SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX19516 toc24

SUPPLY VOLTAGE (V)

MAX19516 toc27

TEMPERATURE (°C)

Typical Operating Characteristics (continued)

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= +25°C, unless otherwise noted.)

MAX19516

Dual-Channel, 10-Bit, 100Msps ADC

______________________________________________________________________________________ 11

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4

OFFSET ERROR (mV)

-0.5

-0.6

-0.7

-40 40200-20 8060

OFFSET ERROR vs. TEMPERATURE

1.2516

MAX19516 toc28

1.2495

1.2474

REFERENCE VOLTAGE (V)

1.2453

1.2432

TEMPERATURE (°C)

GAIN ERROR vs. SUPPLY VOLTAGE

0.08

0.06

0.04

0.02

0

-0.02

GAIN ERROR (%)

-0.04

-0.06

-0.08

1.6 2.6 3.42.4 3.23.02.82.01.8 3.62.2

REGULATOR MODE

SUPPLY VOLTAGE (V)

REFERENCE VOLTAGE vs. TEMPERATURE

-40 40200-20 8060
TEMPERATURE (°C)

MAX19516 toc31

vs. COMMON-MODE VOLTAGE

90

80

70

60

50

INPUT CURRENT (mA)

40

30

0.4 0.9 1.30.8 1.21.11.00.60.5 1.40.7
COMMON-MODE VOLTAGE (V)

COMMON-MODE REFERENCE VOLTAGE

vs. TEMPERATURE

1.6

1.4

MAX19516 toc29

1.2

1.0

0.8

0.6

0.4

0.2

COMMON-MODE REFERENCE VOLTAGE (V)

0

-40 40200-20 8060

VCM = 1.35V

VCM = 1.2V

VCM = 1.05V

VCM = 0.9V

VCM = 0.75V

VCM = 0.6V

VCM = 0.45V

TEMPERATURE (°C)

INPUT CURRENT

MAX19516 toc32

MAX19516 toc30