Rainbow Electronics MAX19506 User Manual

General Description

The MAX19506 dual-channel, analog-to-digital converter
(ADC) provides 8-bit resolution and a maximum sample
rate of 100Msps.

The MAX19506 analog input accepts a wide 0.4V to

1.4V input common-mode voltage range, allowing DC­coupled inputs for a wide range of RF, IF, and base­band front-end components. The MAX19506 provides
excellent dynamic performance from baseband to high
input frequencies beyond 400MHz, making the device
ideal for zero-intermediate frequency (ZIF) and high­intermediate frequency (IF) sampling applications. The
typical signal-to-noise ratio (SNR) performance is

49.8dBFS and typical spurious-free dynamic range
(SFDR) is 69dBc at fIN= 70MHz and f

CLK

= 100MHz.

The MAX19506 operates from a 1.8V supply.
Additionally, an integrated, self-sensing voltage regula­tor allows operation from a 2.5V to 3.3V supply (AVDD).
The digital output drivers operate on an independent
supply voltage (OVDD) over the 1.8V to 3.5V range.
The analog power consumption is only 57mW per chan­nel at V

AVDD

= 1.8V. In addition to low operating
power, the MAX19506 consumes only 1mW in power­down mode and 17mW in standby mode.

Various adjustments and feature selections are avail­able through programmable registers that are
accessed through the 3-wire serial-port interface.
Alternatively, the serial-port interface can be disabled,
with the three pins available to select output mode,
data format, and clock-divider mode. Data outputs are
available through a dual parallel CMOS-compatible out­put data bus that can also be configured as a single
multiplexed parallel CMOS bus.

The MAX19506 is available in a small 7mm x 7mm, 48­pin thin QFN package and is specified over the -40°C
to +85°C extended temperature range.

Refer to the MAX19515, MAX19516, and MAX19517
data sheets for pin- and feature-compatible 10-bit,
65Msps, 100Msps, and 130Msps versions, respectively.
Refer to the MAX19505 and MAX19507 data sheets for
pin- and feature-compatible 8-bit, 65Msps and 130Msps
versions, respectively.

Applications

IF and Baseband Communications, Including
Cellular Base Stations and Point-to-Point
Microwave Receivers

Ultrasound and Medical Imaging
Portable Instrumentation and Low-Power Data

Acquisition
Digital Set-Top Boxes

Features

o Very-Low-Power Operation (57mW/Channel at

100Msps)

o 1.8V or 2.5V to 3.3V Analog Supply

o Excellent Dynamic Performance

49.8dBFS SNR at 70MHz
69dBc SFDR at 70MHz

o User-Programmable Adjustments and Feature

Selection through an SPI™ Interface

o Selectable Data Bus (Dual CMOS or Single

Multiplexed CMOS)

o DCLK Output and Programmable Data Output

Timing Simplifies High-Speed Digital Interface

o Very Wide Input Common-Mode Voltage Range

(0.4V to 1.4V)

o Very High Analog Input Bandwidth (> 850MHz)

o Single-Ended or Differential Analog Inputs

o Single-Ended or Differential Clock Input

o Divide-by-One (DIV1), Divide-by-Two (DIV2), and

Divide-by-Four (DIV4) Clock Modes

o Two’s Complement, Gray Code, and Offset Binary

Output Data Format

o Out-of-Range Indicator (DOR)

o CMOS Output Internal Termination Options

(Programmable)

o Reversible Bit Order (Programmable)

o Data Output Test Patterns

o Small 7mm x 7mm, 48-Pin Thin QFN Package with

Exposed Pad

MAX19506

Dual-Channel, 8-Bit, 100Msps ADC

________________________________________________________________

Maxim Integrated Products

1

Ordering Information

19-4312; Rev 0; 10/08

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

PART TEMP RANGE PIN-PACKAGE

MAX19506ETM+

-40°C to +85°C 48 TQFN-EP*

+

Denotes a lead-free/RoHS-compliant package.

*

EP = Exposed pad.

Pin Configuration appears at end of data sheet.

SPI is a trademark of Motorola, Inc.

MAX19506

Dual-Channel, 8-Bit, 100Msps ADC

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

OVDD, AVDD to GND............................................-0.3V to +3.6V

CMA, CMB, REFIO, INA+, INA-, INB+,

INB- to GND ......................................................-0.3V to +2.1V

CLK+, CLK-, SYNC, SPEN, CS, SCLK, SDIN

to GND ..........-0.3V to the lower of (V

AVDD

+ 0.3V) and +3.6V

DCLKA, DCLKB, D7A–D0A, D7B–D0B, DORA, DORB

to GND..........-0.3V to the lower of (V

OVDD

+ 0.3V) and +3.6V

Continuous Power Dissipation (T

A

= +70°C)
48-Pin Thin QFN, 7mm x 7mm x 0.8mm (derate 40mW/°C

above +70°C).............................................................3200mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

DC ACCURACY

Resolution 8 Bits

Integral Nonlinearity INL fIN = 3MHz -0.3 ±0.1 +0.3 LSB

Differential Nonlinearity DNL fIN = 3MHz -0.3 ±0.1 +0.3 LSB

Offset Error OE Internal reference -0.4 ±0.1 +0.4 %FS

Gain Error GE External reference = 1.25V -1.5 ±0.3 +1.5 %FS

ANALOG INPUTS (INA+, INA-, INB+, INB-) (Figure 3)

Differential Input-Voltage Range V

Common-Mode Input-Voltage
Range

Input Resistance R

Input Current I

Input Capacitance

CONVERSION RATE

Maximum Clock Frequency f

Minimum Clock Frequency f

Data Latency Figures 9, 10 9 Cycles

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DIFF

V

C

PAR

C

SAMPLE

CLK

CLK

CM

IN

Differential or single-ended inputs 1.5 V

(Note 2) 0.4 1.4 V

Fixed resistance, common mode, and
differential mode

IN

Differential input resistance, common mode
connected to inputs

Switched capacitance common-mode input
current, each input

Fixed capacitance to ground, each input 0.7

Switched capacitance, each input 1.2

> 100

4

54 µA

100 MHz

50 MHz

P-P

kΩ

pF

MAX19506

Dual-Channel, 8-Bit, 100Msps ADC

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

DYNAMIC PERFORMANCE

Small-Signal Noise Floor SSNF fIN = 70MHz, < -35dBFS -49.8 dBFS

Signal-to-Noise Plus Distortion
Ratio

Spurious-Free Dynamic Range
(2nd and 3rd Harmonic)

Spurious-Free Dynamic Range
(4th and Higher Harmonics)

Third Harmonic HD3

Third-Order Intermodulation IM3

Full-Power Bandwidth FPBW R

Aperture Delay t

Aperture Jitter t

Overdrive Recovery Time ±10% beyond full scale 1 Cycles

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

fIN = 3MHz 49.8

fIN = 70MHz 49.0 49.8Signal-to-Noise Ratio SNR

= 175MHz 49.8

f

IN

fIN = 3MHz 49.3

SINAD

SFDR1

SFDR2

AD

AJ

fIN = 70MHz 48.5 49.3

f

= 175MHz 49.3

IN

fIN = 3MHz 77.0

fIN = 70MHz 65.0 77.0

= 175MHz 77.0

f

IN

fIN = 3MHz 69.0

fIN = 70MHz 64.0 69.0

f

= 175MHz 69.0

IN

fIN = 3MHz -78.0

fIN = 70MHz -78.0 -65.0Second Harmonic HD2

= 175MHz -78.0

f

IN

fIN = 3MHz -82.0

fIN = 70MHz -82.0 -65.0

= 175MHz -80.0

f

IN

fIN = 3MHz -72.0

fIN = 70MHz -72.0 -63.0Total Harmonic Distortion THD

= 175MHz -72.0

f

IN

fIN = 70MHz ± 1.5MHz, -7dBFS -80

= 175MHz ± 2.5MHz, -7dBFS -75

f

IN

SOURCE

= 50Ω differential, -3dB rolloff 850 MHz

850 ps

0.3 ps

dBFS

dB

dBc

dBc

dBc

dBc

dBc

dBc

RMS

MAX19506

Dual-Channel, 8-Bit, 100Msps ADC

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

INTERCHANNEL CHARACTERISTICS

f

or f

Crosstalk

f

INA

INA

= 70MHz at -1dBFS 95

INB

or f

= 175MHz at -1dBFS 85

INB

dBc

Gain Match fIN = 70MHz ±0.05 dB

Offset Match fIN = 70MHz ±0.1 %FSR

Phase Match fIN = 70MHz ±0.5 D eg r ees

ANALOG OUTPUTS (CMA, CMB)

CMA, CMB Output Voltage V

COM

Default programmable setting 0.85 0.9 0.95 V

INTERNAL REFERENCE

REFIO Output Voltage V

REFOUT

REFIO Temperature Coefficient TC

REF

1.23 1.25 1.27 V

< ±60 ppm/°C

EXTERNAL REFERENCE

REFIO Input-Voltage Range V

REFIO Input Resistance R

REFIN

REFIN

1.25

+5/-10%

10

±20%

V

kΩ

CLOCK INPUTS (CLK+, CLK-)—DIFFERENTIAL MODE

Differential Clock Input Voltage 0.4 to 2.0 V

Differential Input Common-Mode
Voltage

Self-biased 1.20

DC-coupled clock signal 1.0 to 1.4

P-P

V

Differential, default 10 kΩ

Input Resistance R

CLK

Differential, programmable internal
termination selected

100 Ω

Common mode 9 kΩ

Input Capacitance C

CLK

CLOCK INPUTS (CLK+, CLK-)—SINGLE-ENDED MODE (V

Single-Ended Mode Selection
Threshold (V

Allowable Logic Swing (V

CLK-

)

) 0 - V

CLK+

Single-Ended Clock Input High
Threshold (V

CLK+

)

Single-Ended Clock Input Low
Threshold (V

CLK+

)

Input Leakage (CLK+)

Input Leakage (CLK-) V

To ground, each input 3 pF

< 0.1V)

CLK-

0.1 V

AVDD

1.5 V

0.3 V

V

= V

CLK+

= 0 -0.5

V

CLK+

= 0 -150 -50 µA

CLK-

= 1.8V or 3.3V +0.5

AVDD

µA

V

Input Capacitance (CLK+) 3pF

MAX19506

Dual-Channel, 8-Bit, 100Msps ADC

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

CLOCK INPUTS (SYNC)

Allowable Logic Swing 0 - V

AVDD

Sync Clock Input High Threshold 1.5 V

Sync Clock Input Low Threshold 0.3 V

Input Leakage

= V

SYNC

= 0 -0.5

V

SYNC

= 1.8V or 3.3V +0.5

AVDD

V

Input Capacitance 4.5 pF

DIGITAL INPUTS (SHDN, SPEN)

Allowable Logic Swing 0 - V

AVDD

Input High Threshold 1.5 V

Input Low Threshold 0.3 V

Input Leakage

Input Capacitance C

DIN

V

SHDN/VSPEN

V

SHDN/VSPEN

= V

= 1.8V or 3.3V +0.5

AVDD

= 0 -0.5

3pF

SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = 0V)—SERIAL-PORT CONTROL MODE

Allowable Logic Swing 0 - V

AVDD

Input High Threshold 1.5 V

Input Low Threshold 0.3 V

V

Input Leakage

Input Capacitance C

DIN

SCLK/VSDIN/VCS

V

SCLK/VSDIN/VCS

SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = V

V

Input Pullup Current

Input Pulldown Current

Open-Circuit Voltage V

OC

SCLK/VSDIN/VCS

V

SCLK/VSDIN/VCS

V

SCLK/VSDIN/VCS

V

SCLK/VSDIN/VCS

I = 0V, V

I = 0V, V

AVDD

AVDD

= V

= 1.8V or 3.3V +0.5

AVDD

= 0 -0.5

3pF

)—PARALLEL CONTROL MODE (Figure 5)

AVDD

= V

= V

= 0, V

= 0, V

= 1.8V 7 12 17

AVDD

= 3.3V 16 21 26

AVDD

= 1.8V -65 -50 -35

AVDD

= 3.3V -105 -90 -75

AVDD

= 1.8V 1.35 1.45 1.55

= 3.3V 2.58 2.68 2.78

DIGITAL OUTPUTS (CMOS MODE, 75Ω, D0–D7 (A and B Channel), DCLKA, DCLKB, DORA, DORB)

Output-Voltage Low V

Output-Voltage High V

Three-State Leakage Current I

OL

OH

LEAK

I

= 200µA 0.2 V

SINK

V

I

SOURCE

V

= 200µA

applied +0.5

OVDD

OVDD

- 0.2

GND applied -0.5

V

µA

V

µA

V

µA

µA

µA

V

V

µA

MAX19506

Dual-Channel, 8-Bit, 100Msps ADC

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER-MANAGEMENT CHARACTERISTICS

Wake-Up Time from Shutdown t

Wake-Up Time from Standby t

WAKE

WAKE

Internal reference, C

= 0.1µF (10τ)5ms

REFIO

Internal reference 15 µs

SERIAL-PORT INTERFACE TIMING (Note 2) (Figure 7)

SCLK Period t
SCLK to CS Setup Time t
SCLK to CS Hold Time t

SDIN to SCLK Setup Time t

SDIN to SCLK Hold Time t

SCLK to SDIN Output Data Delay t

SCLK

CSS

CSH

SDS

SDH

SDD

Serial-data write 10 ns

Serial-data write 0 ns

Serial-data read 10 ns

50 ns

10 ns

10 ns

TIMING CHARACTERISTICS—DUAL BUS PARALLEL MODE (Figure 9), (Default Timing see Table 5)

Clock Pulse-Width High t

Clock Pulse-Width Low t

Clock Duty Cycle tCH/t

Data Delay After Rising Edge of
CLK+

Data to DCLK Setup Time t

Data to DCLK Hold Time t

CH

CL

CLK

t

DD

SETUP

HOLD

CL = 10pF, V

CL = 10pF, V

CL = 10pF, V

CL = 10pF, V

= 1.8V (Note 2) 2.9 4.8 6.6

OVDD

= 3.3V 3.6

OVDD

= 1.8V (Note 2) 8.2 8.8 ns

OVDD

= 1.8V (Note 2) 0.7 1.2 ns

OVDD

TIMING CHARACTERISTICS—MULTIPLEXED BUS PARALLEL MODE (Figure 10), (Default Timing see Table 5)

Clock Pulse-Width High t

Clock Pulse-Width Low t

Clock Duty Cycle tCH/t

Data Delay After Rising Edge of
CLK+

Data to DCLK Setup Time t

Data to DCLK Hold Time t

DCLK Duty Cycle t

MUX Data Duty Cycle t

CH

CL

CLK

t

DD

SETUP

HOLD

DCH/tCLK

CHA/tCLK

CL = 10pF, V

CL = 10pF, V

CL = 10pF, V

CL = 10pF, V

CL = 10pF, V

CL = 10pF, V

= 1.8V (Note 2) 2.6 4.4 6.5

OVDD

= 3.3V 3.5

OVDD

= 1.8V (Note 2) 2.8 4.0 ns

OVDD

= 1.8V (Note 2) -0.2 1.0 ns

OVDD

= 1.8V (Note 2) 42 50 59 %

OVDD

= 1.8V (Note 2) 40 50 65 %

OVDD

TIMING CHARACTERISTICS—SYNCHRONIZATION (Figure 12)

Setup Time for Valid Clock Edge t

Hold-Off Time for Invalid Clock
Edge

Minimum Synchronization Pulse
Width

SUV

t

HO

Edge mode (Note 2) 0.7 ns

Edge mode (Note 2) 0.5 ns

Relative to input clock period 2 Cycles

5.0 ns

5.0 ns

30 to 70 %

ns

5.0 ns

5.0 ns

30 to 70 %

ns

MAX19506

Dual-Channel, 8-Bit, 100Msps ADC

_______________________________________________________________________________________ 7

ELECTRICAL CHARACTERISTICS (continued)

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)

Note 1: Specifications at ≥ +25°C guaranteed by production test, specifications at < +25°C guaranteed by design and characterization.
Note 2: Guaranteed by design and characterization.

POWER REQUIREMENTS

Analog Supply Voltage V

Digital Output Supply Voltage V

Analog Supply Current I

Analog Power Dissipation P

Digital Output Supply Current I

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

AVDD

OVDD

AVDD

DA

OVDD

Low-level V

High-level V
automatically)

Dual channel 63 77

Single channel active 37

Standby mode 9.5 13

Power-down mode 0.65 0.9

Power-down mode, V

Dual channel 113 139

Dual channel, V

Single channel active 67

Standby mode 17 24

Power-down mode 1.2 1.6

Power-down mode, V

Dual-channel mode, CL = 10pF 17

Power-down mode < 0.1

AVDD

AVDD

AVDD

(regulator mode, invoked

AVDD

= 3.3V 208

AVDD

1.7 1.9

2.3 3.5

1.7 3.5 V

= 3.3V 1.6

= 3.3V 2.9

V

mA

mW

mA

MAX19506 toc06

FREQUENCY (MHz)

AMPLITUDE (dBFS)

40302010

-80

-70

-60

-50

-40

-30

-20

-10

0

-100

-90

0 50

f

IN1

= 172.50290MHz

f

IN2

= 177.49523MHz

175MHz TWO-TONE FFT PLOT

MAX19506 toc05

FREQUENCY (MHz)

AMPLITUDE (dBFS)

40302010

-80

-70

-60

-50

-40

-30

-20

-10

0

-90

-100
0

50

f

IN1

= 71.501922MHz

f

IN2

= 68.509674MHz

70MHz TWO-TONE FFT PLOT

MAX19506 toc04

FREQUENCY (MHz)

AMPLITUDE (dBFS)

40302010

-80

-70

-60

-50

-40

-30

-20

-10

0

-90
0

50

fIN = 175.099945MHz
A

IN

= -0.492dBFS
SNR = 49.240dB
SINAD = 49.223dB
THD = -73.096dBc
SFDR1 = 76.572dBc
SFDR2 = 69.564dBc

175MHz INPUT FFT PLOT

MAX19506 toc03

FREQUENCY (MHz)

AMPLITUDE (dBFS)

37.525.012.5

-80

-70

-60

-50

-40

-30

-20

-10

0

-90
0

50.0

fIN = 70.0935363MHz
A

IN

= -0.517dBFS
SNR = 49.391dB
SINAD = 49.378dB
THD = -80.148dBc
SFDR1 = 81.688dBc
SFDR2 = 68.992dBc

70MHz INPUT FFT PLOT

MAX19506 toc02

FREQUENCY (MHz)

AMPLITUDE (dBFS)

40302010

-80

-70

-60

-50

-40

-30

-20

-10

0

-90
0

50

fIN = 2.99911499MHz
A

IN

= -0.489dBFS
SNR = 49.348dB
SINAD = 49.326dB
THD = -72.29dBc
SFDR1 = 73.498dBc
SFDR2 = 70.34dBc

3MHz SINGLE-ENDED INPUT FFT PLOT

MAX19506

Dual-Channel, 8-Bit, 100Msps ADC

8 _______________________________________________________________________________________

Typical Operating Characteristics

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= +25°C, unless otherwise noted.)

3MHz INPUT FFT PLOT

MAX19506 toc01

FREQUENCY (MHz)

AMPLITUDE (dBFS)

40302010

-80

-70

-60

-50

-40

-30

-20

-10

0

-90
0

50

fIN = 2.99911499MHz
A

IN

= -0.476dBFS
SNR = 49.169dB
SINAD = 49.165dB
THD = -79.250dBc
SFDR1 = 87.836dBc
SFDR2 = 68.557dBc

MAX19506 toc07

DIGITAL OUTPUT CODE

INL (LSB)

19212864

-0.06

-0.08

-0.04

-0.02

0

0.02

0.04

0.06

0.08

0.10

-0.10
0

256

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX19506 toc08

DIGITAL OUTPUT CODE

DNL (LSB)

19212864

-0.06

-0.08

-0.04

-0.02

0

0.02

0.04

0.06

0.08

0.10

-0.10
0

256

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

PERFORMANCE

vs. INPUT FREQUENCY

85

80

75

70

65

SFDR2

60

PERFORMANCE (dBFS)

55

50

45

SNR

0

INPUT FREQUENCY (MHz)

-THD

SFDR1

SINAD

MAX19506 toc09

300200100

400

Typical Operating Characteristics (continued)

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= +25°C, unless otherwise noted.)

MAX19506

Dual-Channel, 8-Bit, 100Msps ADC

_______________________________________________________________________________________

9

SINGLE-ENDED PERFORMANCE

vs. INPUT FREQUENCY

85

80

75

70

65

60

PERFORMANCE (dBFS)

55

50

45

0

SFDR1

SNR

INPUT FREQUENCY (MHz)

PERFORMANCE

vs. COMMON-MODE VOLTAGE

85

80

75

70

65

60

PERFORMANCE (dBFS)

SINAD

55

50

45

0.35 1.35

-THD

SFDR2

COMMON-MODE VOLTAGE (V)

-THD

SNR

SFDR2

SINAD

SFDR1

PERFORMANCE

vs. ANALOG INPUT AMPLITUDE

85

80

MAX19506 toc10

75

70

65

60

PERFORMANCE (dBFS)

55

50

50 604010 20 30

70

45

SFDR2

SFDR1

-60 0
ANALOG INPUT AMPLITUDE (dBFS)

PERFORMANCE

vs. ANALOG SUPPLY VOLTAGE

85

80

MAX19506 toc13

75

70

65

60

PERFORMANCE (dBFS)

55

50

45

1.150.950.55 0.75

1.65 1.90 1.951.70

-THD

SFDR2

SNR

ANALOG SUPPLY VOLTAGE (V)

SFDR1

SINAD

SNR

1.851.801.75

PERFORMANCE

vs. SAMPLING FREQUENCY

-THD

SINAD

85

80

MAX19506 toc11

75

70

65

60

PERFORMANCE (dBFS)

55

50

45

-10-20-50 -40 -30

60 110

SFDR1

SNR

SAMPLING FREQUENCY (Msps)

PERFORMANCE

vs. ANALOG SUPPLY VOLTAGE

85

80

MAX19506 toc14

75

70

65

60

PERFORMANCE (dBFS)

55

50

45

SNR

2.3 3.3 3.52.5

-THD

SFDR2

ANALOG SUPPLY VOLTAGE (V)

MAX19506 toc12

-THD

SFDR2

SINAD

1009070 80

SFDR1

MAX19506 toc15

SINAD

3.12.92.7

ANALOG SUPPLY CURRENT

vs. SAMPLING FREQUENCY

68

66

64

62

60

58

56

54

ANALOG SUPPLY CURRENT (mA)

52

50

60 65 70 75 80 85 90 95 100 105 110

SAMPLING FREQUENCY (MHz)

69

67

MAX19506 toc16

65

63

61

59

ANALOG SUPPLY CURRENT (mA)

57

55

-40-200 20406080

ANALOG SUPPLY CURRENT

vs. TEMPERATURE

TEMPERATURE (°C)

69

MAX19506 toc17

67

65

63

61

59

ANALOG SUPPLY CURRENT (mA)

57

55

1.65 1.70 1.75 1.80 1.85 1.90 1.95

ANALOG SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX19506 toc18

SUPPLY VOLTAGE (V)

10 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= +25°C, unless otherwise noted.)

MAX19506

Dual-Channel, 8-Bit, 100Msps ADC

67.5

67.0

66.5

66.0

65.5

65.0

ANALOG SUPPLY CURRENT (mA)

64.5

64.0

2.3 2.5 2.7 2.9 3.1 3.3 3.5

ANALOG SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX19506 toc19

DIGITAL SUPPLY CURRENT (mA)

SUPPLY VOLTAGE (V)

DIGITAL SUPPLY CURRENT

vs. SAMPLING FREQUENCY

18

OVDD = 1.8V

16

14

12

10

8

6

4

2

0

60 70 80 90 100 110

SAMPLING FREQUENCY (Msps)

40

OVDD = 3.6V

35

MAX19506 toc20

30

25

20

15

10

DIGITAL SUPPLY CURRENT (mA)

5

0

60 70 80 90 100 110

DIGITAL SUPPLY CURRENT

vs. SAMPLING FREQUENCY

MAX19506 toc21

SAMPLING FREQUENCY (Msps)

DIGITAL SUPPLY CURRENT

vs. TEMPERATURE

35

30

25

20

15

DIGITAL SUPPLY CURRENT (mA)

10

-40 -20 0 20 6040 80

OVDD = 3.6V

OVDD = 1.8V

TEMPERATURE (°C)

PERFORMANCE

vs. CLOCK DUTY CYCLE

85

SFDR1

80

75

70

65

60

PERFORMANCE (dBFS)

55

50

45

30 60 6535

SFDR2

SINAD

CLOCK DUTY CYCLE (%)

-THD

SNR

DIGITAL SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MULTIPLEXED BUS

MAX19506 toc24

5

0

1.7 1.9 2.1 2.3 3.12.7 2.92.5 3.3 3.5
SUPPLY VOLTAGE (V)

35

DUAL BUS

30

MAX19506 toc22

25

20

15

10

DIGITAL SUPPLY CURRENT (mA)

5

0

1.8 2.0 2.2 2.4 3.22.8 3.02.6 3.4

DIGITAL SUPPLY CURRENT

vs. SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

30

25

MAX19506 toc23

20

15

10

DIGITAL SUPPLY CURRENT (mA)

PERFORMANCE

85

vs. TEMPERATURE

SFDR1

80

MAX19506 toc25

75

70

65

60

PERFORMANCE (dBFS)

55

50

55504540

45

SNR

-40 80-20

SFDR2

SINAD

TEMPERATURE (°C)

-THD

6040200

MAX19506 toc26

GAIN ERROR (%)

GAIN ERROR vs. TEMPERATURE

0.05

0.04

0.03

0.02

0.01

0

-0.01

-0.02

-0.03

-0.04

-0.05

-40 40200-20 8060

TEMPERATURE (°C)

MAX19506 toc27

Typical Operating Characteristics (continued)

(V

AVDD

= V

OVDD

= 1.8V, internal reference, differential clock, V

CLK

= 1.5V

P-P

, f

CLK

= 100MHz, AIN= -0.5dBFS, data output termina-

tion = 50Ω, T

A

= +25°C, unless otherwise noted.)

COMMON-MODE REFERENCE VOLTAGE

vs. TEMPERATURE

TEMPERATURE (°C)

COMMON-MODE REFERENCE VOLTAGE (V)

MAX19506 toc30

-40 40200-20 8060

0

1.2

0.8

0.4

0.2

1.4

1.0

0.6

1.6
VCM = 1.35V

VCM = 1.2V

VCM = 0.9V

VCM = 0.6V

VCM = 0.75V

VCM = 0.45V

VCM = 1.05V

OFFSET ERROR vs. TEMPERATURE

TEMPERATURE (°C)

OFFSET ERROR (mV)

MAX19506 toc28

-40 40200-20 8060

-0.7

-0.3

-0.1

0

0.1

-0.2

-0.5

-0.6

-0.4

0.2

MAX19506

Dual-Channel, 8-Bit, 100Msps ADC

______________________________________________________________________________________

11

REFERENCE VOLTAGE (V)

GAIN ERROR vs. SUPPLY VOLTAGE

0.08

0.06

0.04

0.02

0

-0.02

GAIN ERROR (%)

-0.04

-0.06

-0.08

1.6 2.6 3.42.4 3.23.02.82.01.8 3.62.2

REGULATOR MODE

SUPPLY VOLTAGE (V)

REFERENCE VOLTAGE vs. TEMPERATURE

1.2516

1.2495

1.2474

1.2453

1.2432

-40 40200-20 8060

TEMPERATURE (°C)

MAX19506 toc31

vs. COMMON-MODE VOLTAGE

90

80

70

60

50

INPUT CURRENT (mA)

40

30

0.4 0.9 1.30.8 1.21.11.00.60.5 1.40.7
COMMON-MODE VOLTAGE (V)

MAX19506 toc29

INPUT CURRENT

MAX19506 toc32