Rainbow Electronics MAX188 User Manual

19-0123; Rev. 4; 8/96

EVALUATION KIT

AVAILABLE

_______________General Description

The MAX186/MAX188 are 12-bit data-acquisition sys­tems that combine an 8-channel multiplexer, high-band­width track/hold, and serial interface together with high
conversion speed and ultra-low power consumption.
The devices operate with a single +5V supply or dual
±5V supplies. The analog inputs are software config­urable for unipolar/bipolar and single-ended/differential
operation.

The 4-wire serial interface directly connects to SPI™,
QSPI™ and Microwire™ devices without external logic. A
serial strobe output allows direct connection to TMS320
family digital signal processors. The MAX186/MAX188
use either the internal clock or an external serial-interface
clock to perform successive-approximation A/D conver­sions. The serial interface can operate beyond 4MHz
when the internal clock is used.

The MAX186 has an internal 4.096V reference while the
MAX188 requires an external reference. Both parts
have a reference-buffer amplifier that simplifies gain
trim .

The MAX186/MAX188 provide a hard-wired SHDN pin
and two software-selectable power-down modes.
Accessing the serial interface automatically powers up
the devices, and the quick turn-on time allows the
MAX186/MAX188 to be shut down between every
conversion. Using this technique of powering down
between conversions, supply current can be cut to
under 10µA at reduced sampling rates.

The MAX186/MAX188 are available in 20-pin DIP and
SO packages, and in a shrink small-outline package
(SSOP), that occupies 30% less area than an 8-pin DIP.
For applications that call for a parallel interface, see the
MAX180/MAX181 data sheet. For anti-aliasing filters,
consult the MAX274/MAX275 data sheet.

________________________Applications

Portable Data Logging
Data-Acquisition
High-Accuracy Process Control
Automatic Testing
Robotics
Battery-Powered Instruments
Medical Instruments

SPI and QSPI are registered trademarks of Motorola.
Microwire is a registered trademark of National Semiconductor.

Low-Power, 8-Channel,

Serial 12-Bit ADCs

____________________________Features

♦ 8-Channel Single-Ended or 4-Channel

Differential Inputs

♦ Single +5V or ±5V Operation
♦ Low Power: 1.5mA (operating mode)

2µA (power-down mode)

♦ Internal Track/Hold, 133kHz Sampling Rate
♦ Internal 4.096V Reference (MAX186)
♦ SPI-, QSPI-, Microwire-, TMS320-Compatible

4-Wire Serial Interface

♦ Software-Configurable Unipolar or Bipolar Inputs
♦ 20-Pin DIP, SO, SSOP Packages
♦ Evaluation Kit Available

______________Ordering Information

†

PART

MAX186_CPP 20 Plastic DIP
MAX186_CWP 20 SO
MAX186_CAP
MAX186DC/D Dice*
MAX186_EPP 20 Plastic DIP
MAX186_EWP 20 SO
MAX186_EAP -40°C to +85°C 20 SSOP
MAX186_MJP -55°C to +125°C 20 CERDIP**

Ordering Information continued on last page.

†

NOTE: Parts are offered in grades A, B, C and D (grades defined
in Electrical Characteristics). When ordering, please specify grade.
Contact factory for availability of A-grade in SSOP package.
* Dice are specified at +25°C, DC parameters only.
* * Contact factory for availability and processing to MIL-STD-883.

____________________Pin Configuration

TOP VIEW

TEMP. RANGE

0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C

-40°C to +85°C

-40°C to +85°C

CH0

1
2

CH1

3

CH2
CH3

4
5

CH4

6

CH5
CH6

7
8

CH7

9

V

SS

10

DIP/SO/SSOP

MAX186
MAX188

PIN-PACKAGE

20 SSOP

V

20

DD

SCLK

19

CS

18
17

DIN

16

SSTRB
DOUT

15



DGND

14
13

AGND

12

REFADJ

11

VREFSHDN

MAX186/MAX188

________________________________________________________________ Maxim Integrated Products

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone]

Low-Power, 8-Channel,
Serial 12-Bit ADCs

ABSOLUTE MAXIMUM RATINGS

VDDto AGND............................................................-0.3V to +6V

VSSto AGND............................................................+0.3V to -6V

VDDto VSS..............................................................-0.3V to +12V

AGND to DGND.....................................................-0.3V to +0.3V

CH0–CH7 to AGND, DGND.............(VSS- 0.3V) to (VDD+ 0.3V)

CH0–CH7 Total Input Current ..........................................±20mA

VREF to AGND ...........................................-0.3V to (VDD+ 0.3V)

REFADJ to AGND.......................................-0.3V to (VDD+ 0.3V)

Digital Inputs to DGND...............................-0.3V to (VDD+ 0.3V)

Digital Outputs to DGND............................-0.3V to (VDD+ 0.3V)

Digital Output Sink Current.................................................25mA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

MAX186/MAX188

(VDD= 5V ±5%; VSS= 0V or -5V; f

4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T
noted.)

PARAMETER SYMBOL MIN TYP MAX UNITS

DC ACCURACY (Note 1)

Resolution 12 Bits

Relative Accuracy (Note 2)

Differential Nonlinearity DNL ±1 LSB

Offset Error

Gain Error (Note 3)

Gain Temperature Coefficient ±0.8 ppm/°C
Channel-to-Channel

Offset Matching
DYNAMIC SPECIFICATIONS (10kHz sine wave input, 4.096V
Signal-to-Noise + Distortion Ratio
Total Harmonic Distortion

(up to the 5th harmonic)
Spurious-Free Dynamic Range SFDR 80 dB
Channel-to-Channel Crosstalk -85 dB

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—

CLK

MAX186A/MAX188A
MAX186B/MAX188B
MAX186C
MAX188C
MAX186D/MAX188D
No missing codes over temperature
MAX186A/MAX188A
MAX186B/MAX188B
MAX186C/MAX188C
MAX186D/MAX188D
MAX186 (all grades)

External reference

4.096V (MAX188)

External reference, 4.096V

SINAD 70 dB

THD -80 dB

65kHz, VIN= 4.096V

Continuous Power Dissipation (TA= +70°C)

Plastic DIP (derate 11.11mW/°C above +70°C) ...........889mW

SO (derate 10.00mW/°C above +70°C)........................800mW

SSOP (derate 8.00mW/°C above +70°C) .....................640mW

CERDIP (derate 11.11mW/°C above +70°C)................889mW

Operating Temperature Ranges:

MAX186_C/MAX188_C........................................0°C to +70°C

MAX186_E/MAX188_E......................................-40°C to +85°C

MAX186_M/MAX188_M..................................-55°C to +125°C

Storage Temperature Range.............................-60°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

= T

to T

A

MIN

CONDITIONS

MAX188A
MAX188B
MAX188C
MAX188D

±0.1 LSB

, 133ksps, 2.0MHz external clock, bipolar input mode)

P-P

(Note 4)

P-P

, unless otherwise

MAX

±0.5
±0.5
±1.0

±0.75

±1.0

±2.0
±3.0
±3.0
±3.0
±3.0
±1.5
±2.0
±2.0
±3.0

LSB

LSB

LSB

2 _______________________________________________________________________________________

Low-Power, 8-Channel,

Serial 12-Bit ADCs

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 5V ±5%; VSS= 0V or -5V; f

4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T
noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Small-Signal Bandwidth -3dB rolloff 4.5 MHz
Full-Power Bandwidth 800 kHz

CONVERSION RATE

Conversion Time (Note 5) t
Track/Hold Acquisition Time t

Aperture Delay 10 ns
Aperture Jitter <50 ps
Internal Clock Frequency 1.7 MHz

External Clock Frequency Range

ANALOG INPUT

Input Voltage Range,
Single-Ended and Differential
(Note 9)

Multiplexer Leakage Current
Input Capacitance (Note 6) 16 pF

INTERNAL REFERENCE (MAX186 only, reference buffer enabled)
VREF Output Voltage
VREF Short-Circuit Current 30 mA

VREF Tempco

Load Regulation (Note 7) 0mA to 0.5mA output load 2.5 mV
Capacitive Bypass at VREF

Capacitive Bypass at REFADJ
REFADJ Adjustment Range ±1.5 %

EXTERNAL REFERENCE AT VREF (Buffer disabled, VREF = 4.096V)
Input Voltage Range V
Input Current 200 350 µA

Input Resistance 12 20 kΩ
Shutdown VREF Input Current 1.5 10 µA

Buffer Disable Threshold REFADJ

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—

CLK

CONV

AZ

Internal clock 5.5 10
External clock, 2MHz, 12 clocks/conversion 6

External compensation, 4.7µF
Internal compensation (Note 6) 0.1 0.4
Used for data transfer only 10

Unipolar, VSS= 0V

Bipolar, VSS= -5V
On/off leakage current, VIN= ±5V

TA= +25°C

MAX186A, MAX186B,
MAX186C

MAX186D ±30

Internal compensation 0
External compensation 4.7
Internal compensation 0.01
External compensation 0.01

MAX186_C
MAX186_E
MAX186_M

= T

to T

A

MIN

0.1 2.0

±0.01 ±1 µA

4.076 4.096 4.116 V

±30 ±50
±30 ±60
±30 ±80

2.50

VDD­50mV

, unless otherwise

MAX

1.5 µs

0 to

VREF

±VREF/2

V

DD

+

50mV

ppm/°C

MAX186/MAX188

µs

MHz

V

µF

µF

V

_______________________________________________________________________________________ 3

Low-Power, 8-Channel,

SHDN

Serial 12-Bit ADCs

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 5V ±5%; VSS= 0V or -5V; f

4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T
noted.)

PARAMETER

EXTERNAL REFERENCE AT REFADJ

Reference-Buffer Gain

DIGITAL INPUTS (DIN, SCLK, CS,

DIN, SCLK, CS Input High Voltage

MAX186/MAX188

DIN, SCLK, CS Input Low Voltage
DIN, SCLK, CS Input Hysteresis
DIN, SCLK, CS Input Leakage
DIN, SCLK, CS Input Capacitance

SHDN Input High Voltage
SHDN Input Low Voltage
SHDN Input Current, High
SHDN Input Current, Low
SHDN Input Mid Voltage
SHDN Voltage, Floating
SHDN Max Allowed Leakage,

Mid Input

DIGITAL OUTPUTS (DOUT, SSTRB)

Output Voltage Low V
Output Voltage High V

Three-State Leakage Current I
Three-State Output Capacitance C

POWER REQUIREMENTS

Positive Supply Voltage V
Negative Supply Voltage V

Positive Supply Current I

Negative Supply Current I

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—

CLK

SYMBOL CONDITIONS MIN TYP MAX

Internal compensation mode 0
External compensation mode 4.7
MAX186 1.678
MAX188 1.638
MAX186 ±50
MAX188 ±5

)

V

INH

V

INL

V

HYST

C
V
V

I

I

V
V

I

INH

INL
INH
INL

FLT

OH

OUT

DD

DD

SS

VIN= 0V or V

IN

(Note 6) 15 pF

IN

SHDN = V
SHDN = 0V

IM

SHDN = open
SHDN = open

I

OL

SS

SINK

I

SINK

I

SOURCE

CS = 5V

L

CS = 5V (Note 6)

Operating mode 1.5 2.5
Fast power-down 30 70
Full power-down 210
Operating mode and fast power-down 50
Full power-down 10

DD

DD

= 5mA 0.4
= 16mA 0.3

= 1mA 4 V

= T

to T

A

MIN

2.4 V

0.15 V

VDD- 0.5 V

-4.0 µA

1.5 VDD-1.5

2.75 V

-100 100 nA

5 ±5% V

0 or

-5 ±5%

, unless otherwise

MAX

0.8 V

±1 µA

0.5 V

4.0 µA

±10 µA

15 pF

UNITS

V/V

mA

µFCapacitive Bypass at VREF

µAREFADJ Input Current

V

V

V

µA

µA

4 _______________________________________________________________________________________

Low-Power, 8-Channel,

Serial 12-Bit ADCs

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 5V ±5%; VSS= 0V or -5V; f

4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T
noted.)

PARAMETER SYMBOL CONDITIONS UNITS

Positive Supply Rejection
(Note 8)

Negative Supply Rejection
(Note 8)

Note 1: Tested at VDD= 5.0V; VSS= 0V; unipolar input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: MAX186 – internal reference, offset nulled; MAX188 – external reference (VREF = +4.096V), offset nulled.
Note 4: Ground on-channel; sine wave applied to all off channels.
Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: Measured at V

SUPPLY

+5% and V

Note 9: The common-mode range for the analog inputs is from V

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—

CLK

= T

to T

A

MIN

, unless otherwise

MAX

MIN TYP MAX

PSR ±0.06 ±0.5 mV

PSR

VDD= 5V ±5%; external reference, 4.096V;
full-scale input

VSS= -5V ±5%; external reference, 4.096V;
full-scale input

-5% only.

SUPPLY

SS

to VDD.

±0.01 ±0.5 mV

TIMING CHARACTERISTICS

(VDD= 5V ±5%; V

=0V or -5V, TA= T

SS

MIN

to T

, unless otherwise noted.)

MAX

MAX186/MAX188

PARAMETER SYMBOL CONDITIONS UNITS

Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold

SCLK Fall to Output Data Valid

CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold

SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS Fall to SSTRB Output Enable

(Note 6)
CS Rise to SSTRB Output Disable

(Note 6)
SSTRB Rise to SCLK Rise

(Note 6)

_______________________________________________________________________________________ 5

t

AZ

t

DS

t

DH

t

DO

t

DV

t

TR

t

CSS

t

CSH

t

CH

t

CL

t

SSTRB

t

SDV

t

STR

t

SCK

MIN TYP MAX

1.5 µs

100 ns

0 ns
C
C

C

LOAD

LOAD
LOAD

= 100pF
= 100pF

= 100pF

MAX18_ _C/E
MAX18_ _M

20 150 ns
20 200 ns

100 ns
100 ns

100 ns

0 ns
200 ns
200 ns

C

= 100pF

LOAD

External clock mode only, C

External clock mode only, C

LOAD

LOAD

= 100pF

= 100pF

200 ns
200 ns

200 ns

Internal clock mode only 0 ns

Low-Power, 8-Channel,
Serial 12-Bit ADCs

__________________________________________Typical Operating Characteristics

POWER-SUPPLY REJECTION

vs. TEMPERATURE

0.30

0.25

0.20

0.15

0.10

PSR (LSBs)

0.05

0.00

MAX186/MAX188

-0.05

-60 140

-20 0 40 80 120

-40 20 100
TEMPERATURE (°C)

VDD = +5V ±5%
VSS = 0V or -5V

60

20

0

-20

-40

-60

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

2.456

2.455

2.454

VREFADJ (V)

2.453

2.452

-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)

MAX186/MAX188 FFT PLOT – 133kHz

ft = 10kHz
fs = 133kHz

ft = 10kHz



= 133kHz

f

s

= +25°C

T

A



CHANNEL-TO-CHANNEL OFFSET MATCHING

vs. TEMPERATURE

0.16

0.14

0.12

0.10

0.08

0.06

0.04

OFFSET MATCHING (LSBs)

0.02
0

-60 -20 60 140

-40 0 40 80 120

20 100

TEMPERATURE (°C)

-80

AMPLITUDE (dB)

-100

-120

-140
0

 

   

FREQUENCY

33.25kHz



66.5kHz

_____________________________________________________________Pin Description

PIN NAME FUNCTION

1-8 CH0-CH7 Sampling Analog Inputs

9

10

11 VREF

6

________________________________________________________________________________________________

V

SS

SHDN

Negative Supply Voltage. Tie to -5V ±5% or AGND
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX186/MAX188 down to 10µA (max)

supply current, otherwise the MAX186/MAX188 are fully operational. Pulling SHDN high puts the ref­erence-buffer amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer
amplifier in external compensation mode.

Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier
(4.096V in the MAX186, 1.638 x REFADJ in the MAX188). Add a 4.7µF capacitor to ground when
using external compensation mode. Also functions as an input when used with a precision external
reference.

Low-Power, 8-Channel,

Serial 12-Bit ADCs

________________________________________________Pin Description (continued)

PIN NAME FUNCTION

12 REFADJ

13 AGND Analog Ground. Also IN- Input for single-ended conversions.
14 DGND
15 DOUT

16 SSTRB

17 DIN

18

CS

19 SCLK

20

V

DD

Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to
V

.

DD

Digital Ground
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high.

Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX186/MAX188 begin the
A/D conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance whenCS is high (external mode).

Serial Data Input. Data is clocked in at the rising edge of SCLK.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT

is high impedance.
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets

the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
Positive Supply Voltage, +5V ±5%

+5V

MAX186/MAX188

DOUT

3k

a. High-Z to V

DGND

and VOL to V

OH

C

LOAD

OH

DOUT

b. High-Z to VOL and VOH to V

Figure 1. Load Circuits for Enable Time

DOUT

3k

DGND

a VOH to High-Z b VOL to High-Z

C

DOUT

LOAD

Figure 2. Load Circuits for Disabled Time

+5V

3k

C

LOAD

DGND

3k

C

LOAD

DGND

18

CS

19

SCLK

DIN

SHDN

OL

CH0
CH1
CH2

CH3
CH4

CH5
CH6
CH7

AGND

REFADJ

VREF

SHIFT

REGISTER

10

1
2
3

4

ANALOG

INPUT

5

MUX

6



7
8

13

12
11

CONTROL

+2.46V

REFERENCE

(MAX186)

LOGIC

T/H

20k

INPUT

17

CLOCK

IN

A

≈ 1.65

+4.096V

INT

CLOCK

12-BIT

SAR
ADC

REF

OUTPUT

REGISTER

OUT

MAX186
MAX188

SHIFT

15

DOUT

16

SSTRB

20

V

DD

14

DGND

9

V

SS

Figure 3. Block Diagram

_______________________________________________________________________________________ 7

Low-Power, 8-Channel,
Serial 12-Bit ADCs

_______________Detailed Description

The MAX186/MAX188 use a successive-approximation
conversion technique and input track/hold (T/H) circuit­ry to convert an analog signal to a 12-bit digital output.
A flexible serial interface provides easy interface to
microprocessors. No external hold capacitors are
required. Figure 3 shows the block diagram for the
MAX186/MAX188.

Pseudo-Differential Input

The sampling architecture of the ADC’s analog com­parator is illustrated in the Equivalent Input Circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0-CH7 and IN- is switched to AGND. In
differential mode, IN+ and IN- are selected from pairs
of CH0/CH1, CH2/CH3, CH4/CH5 and CH6/CH7.

MAX186/MAX188

Configure the channels with Table 3 and Table 4.
In differential mode, IN- and IN+ are internally switched

to either one of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta­ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. Accomplish this
by connecting a 0.1µF capacitor from AIN- (the select­ed analog input, respectively) to AGND.

During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui­sition interval, the T/H switch opens, retaining charge
on C

as a sample of the signal at IN+.

HOLD

The conversion interval begins with the input multiplex­er switching C

from the positive input (IN+) to the

HOLD

negative input (IN-). In single-ended mode, IN- is sim­ply AGND. This unbalances node ZERO at the input of
the comparator. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 12-bit resolution. This
action is equivalent to transferring a charge of 16pF x

+) - (VIN-)] from C

[(V

IN

to the binary-weighted

HOLD

capacitive DAC, which in turn forms a digital represen­tation of the analog input signal.

The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. The T/H enters its hold mode on the falling
clock edge after the eighth bit of the control word has
been shifted in. If the converter is set up for

HOLD

Track/Hold

. The

12-BIT CAPACITIVE DAC

VREF

C

INPUT

CH0
CH1

CH2
CH3
CH4
CH5
CH6
CH7

AGND
SINGLE-ENDED MODE: IN+ = CHO-CH7, IN– = AGND.

DIFFERENTIAL MODE: IN+ AND IN– SELECTED FROM PAIRS OF
 CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.

Figure 4. Equivalent Input Circuit

MUX

–

C

SWITCH

HOLD

16pF

TRACK

+

T/H

SWITCH

10k
R

S

COMPARATOR

ZERO

HOLD

AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES 
FROM THE SELECTED IN+ 
CHANNEL TO THE SELECTED 
IN– CHANNEL.

single-ended inputs, IN- is connected to AGND, and
the converter samples the “+” input. If the converter is
set up for differential inputs, IN- connects to the “-”
input, and the difference of

|IN+ - IN-| is sampled. At

the end of the conversion, the positive input connects
back to IN+, and C

charges to the input signal.

HOLD

The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. Acquisition time is cal­culated by:

= 9 x (RS+ RIN) x 16pF,

t

AZ

where R
input signal, and t

= 5kΩ, RS= the source impedance of the

IN

is never less than 1.5µs. Note that

AZ

source impedances below 5kΩ do not significantly
affect the AC performance of the ADC. Higher source
impedances can be used if an input capacitor is con­nected to the analog inputs, as shown in Figure 5. Note
that the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s signal bandwidth.

Input Bandwidth

The ADC’s input tracking circuitry has a 4.5MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig­nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.

8 _______________________________________________________________________________________