Rainbow Electronics MAX188 User Manual

19-0123; Rev. 4; 8/96

EVALUATION KIT

AVAILABLE

_______________General Description

The MAX186/MAX188 are 12-bit data-acquisition sys­tems that combine an 8-channel multiplexer, high-band­width track/hold, and serial interface together with high
conversion speed and ultra-low power consumption.
The devices operate with a single +5V supply or dual
±5V supplies. The analog inputs are software config­urable for unipolar/bipolar and single-ended/differential
operation.

The 4-wire serial interface directly connects to SPI™,
QSPI™ and Microwire™ devices without external logic. A
serial strobe output allows direct connection to TMS320
family digital signal processors. The MAX186/MAX188
use either the internal clock or an external serial-interface
clock to perform successive-approximation A/D conver­sions. The serial interface can operate beyond 4MHz
when the internal clock is used.

The MAX186 has an internal 4.096V reference while the
MAX188 requires an external reference. Both parts
have a reference-buffer amplifier that simplifies gain
trim .

The MAX186/MAX188 provide a hard-wired SHDN pin
and two software-selectable power-down modes.
Accessing the serial interface automatically powers up
the devices, and the quick turn-on time allows the
MAX186/MAX188 to be shut down between every
conversion. Using this technique of powering down
between conversions, supply current can be cut to
under 10µA at reduced sampling rates.

The MAX186/MAX188 are available in 20-pin DIP and
SO packages, and in a shrink small-outline package
(SSOP), that occupies 30% less area than an 8-pin DIP.
For applications that call for a parallel interface, see the
MAX180/MAX181 data sheet. For anti-aliasing filters,
consult the MAX274/MAX275 data sheet.

________________________Applications

Portable Data Logging
Data-Acquisition
High-Accuracy Process Control
Automatic Testing
Robotics
Battery-Powered Instruments
Medical Instruments

SPI and QSPI are registered trademarks of Motorola.
Microwire is a registered trademark of National Semiconductor.

Low-Power, 8-Channel,

Serial 12-Bit ADCs

____________________________Features

♦ 8-Channel Single-Ended or 4-Channel

Differential Inputs

♦ Single +5V or ±5V Operation
♦ Low Power: 1.5mA (operating mode)

2µA (power-down mode)

♦ Internal Track/Hold, 133kHz Sampling Rate
♦ Internal 4.096V Reference (MAX186)
♦ SPI-, QSPI-, Microwire-, TMS320-Compatible

4-Wire Serial Interface

♦ Software-Configurable Unipolar or Bipolar Inputs
♦ 20-Pin DIP, SO, SSOP Packages
♦ Evaluation Kit Available

______________Ordering Information

†

PART

MAX186_CPP 20 Plastic DIP
MAX186_CWP 20 SO
MAX186_CAP
MAX186DC/D Dice*
MAX186_EPP 20 Plastic DIP
MAX186_EWP 20 SO
MAX186_EAP -40°C to +85°C 20 SSOP
MAX186_MJP -55°C to +125°C 20 CERDIP**

Ordering Information continued on last page.

†

NOTE: Parts are offered in grades A, B, C and D (grades defined
in Electrical Characteristics). When ordering, please specify grade.
Contact factory for availability of A-grade in SSOP package.
* Dice are specified at +25°C, DC parameters only.
* * Contact factory for availability and processing to MIL-STD-883.

____________________Pin Configuration

TOP VIEW

TEMP. RANGE

0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C

-40°C to +85°C

-40°C to +85°C

CH0

1
2

CH1

3

CH2
CH3

4
5

CH4

6

CH5
CH6

7
8

CH7

9

V

SS

10

DIP/SO/SSOP

MAX186
MAX188

PIN-PACKAGE

20 SSOP

V

20

DD

SCLK

19

CS

18
17

DIN

16

SSTRB
DOUT

15



DGND

14
13

AGND

12

REFADJ

11

VREFSHDN

MAX186/MAX188

________________________________________________________________ Maxim Integrated Products

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone]

Low-Power, 8-Channel,
Serial 12-Bit ADCs

ABSOLUTE MAXIMUM RATINGS

VDDto AGND............................................................-0.3V to +6V

VSSto AGND............................................................+0.3V to -6V

VDDto VSS..............................................................-0.3V to +12V

AGND to DGND.....................................................-0.3V to +0.3V

CH0–CH7 to AGND, DGND.............(VSS- 0.3V) to (VDD+ 0.3V)

CH0–CH7 Total Input Current ..........................................±20mA

VREF to AGND ...........................................-0.3V to (VDD+ 0.3V)

REFADJ to AGND.......................................-0.3V to (VDD+ 0.3V)

Digital Inputs to DGND...............................-0.3V to (VDD+ 0.3V)

Digital Outputs to DGND............................-0.3V to (VDD+ 0.3V)

Digital Output Sink Current.................................................25mA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

MAX186/MAX188

(VDD= 5V ±5%; VSS= 0V or -5V; f

4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T
noted.)

PARAMETER SYMBOL MIN TYP MAX UNITS

DC ACCURACY (Note 1)

Resolution 12 Bits

Relative Accuracy (Note 2)

Differential Nonlinearity DNL ±1 LSB

Offset Error

Gain Error (Note 3)

Gain Temperature Coefficient ±0.8 ppm/°C
Channel-to-Channel

Offset Matching
DYNAMIC SPECIFICATIONS (10kHz sine wave input, 4.096V
Signal-to-Noise + Distortion Ratio
Total Harmonic Distortion

(up to the 5th harmonic)
Spurious-Free Dynamic Range SFDR 80 dB
Channel-to-Channel Crosstalk -85 dB

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—

CLK

MAX186A/MAX188A
MAX186B/MAX188B
MAX186C
MAX188C
MAX186D/MAX188D
No missing codes over temperature
MAX186A/MAX188A
MAX186B/MAX188B
MAX186C/MAX188C
MAX186D/MAX188D
MAX186 (all grades)

External reference

4.096V (MAX188)

External reference, 4.096V

SINAD 70 dB

THD -80 dB

65kHz, VIN= 4.096V

Continuous Power Dissipation (TA= +70°C)

Plastic DIP (derate 11.11mW/°C above +70°C) ...........889mW

SO (derate 10.00mW/°C above +70°C)........................800mW

SSOP (derate 8.00mW/°C above +70°C) .....................640mW

CERDIP (derate 11.11mW/°C above +70°C)................889mW

Operating Temperature Ranges:

MAX186_C/MAX188_C........................................0°C to +70°C

MAX186_E/MAX188_E......................................-40°C to +85°C

MAX186_M/MAX188_M..................................-55°C to +125°C

Storage Temperature Range.............................-60°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

= T

to T

A

MIN

CONDITIONS

MAX188A
MAX188B
MAX188C
MAX188D

±0.1 LSB

, 133ksps, 2.0MHz external clock, bipolar input mode)

P-P

(Note 4)

P-P

, unless otherwise

MAX

±0.5
±0.5
±1.0

±0.75

±1.0

±2.0
±3.0
±3.0
±3.0
±3.0
±1.5
±2.0
±2.0
±3.0

LSB

LSB

LSB

2 _______________________________________________________________________________________

Low-Power, 8-Channel,

Serial 12-Bit ADCs

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 5V ±5%; VSS= 0V or -5V; f

4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T
noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Small-Signal Bandwidth -3dB rolloff 4.5 MHz
Full-Power Bandwidth 800 kHz

CONVERSION RATE

Conversion Time (Note 5) t
Track/Hold Acquisition Time t

Aperture Delay 10 ns
Aperture Jitter <50 ps
Internal Clock Frequency 1.7 MHz

External Clock Frequency Range

ANALOG INPUT

Input Voltage Range,
Single-Ended and Differential
(Note 9)

Multiplexer Leakage Current
Input Capacitance (Note 6) 16 pF

INTERNAL REFERENCE (MAX186 only, reference buffer enabled)
VREF Output Voltage
VREF Short-Circuit Current 30 mA

VREF Tempco

Load Regulation (Note 7) 0mA to 0.5mA output load 2.5 mV
Capacitive Bypass at VREF

Capacitive Bypass at REFADJ
REFADJ Adjustment Range ±1.5 %

EXTERNAL REFERENCE AT VREF (Buffer disabled, VREF = 4.096V)
Input Voltage Range V
Input Current 200 350 µA

Input Resistance 12 20 kΩ
Shutdown VREF Input Current 1.5 10 µA

Buffer Disable Threshold REFADJ

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—

CLK

CONV

AZ

Internal clock 5.5 10
External clock, 2MHz, 12 clocks/conversion 6

External compensation, 4.7µF
Internal compensation (Note 6) 0.1 0.4
Used for data transfer only 10

Unipolar, VSS= 0V

Bipolar, VSS= -5V
On/off leakage current, VIN= ±5V

TA= +25°C

MAX186A, MAX186B,
MAX186C

MAX186D ±30

Internal compensation 0
External compensation 4.7
Internal compensation 0.01
External compensation 0.01

MAX186_C
MAX186_E
MAX186_M

= T

to T

A

MIN

0.1 2.0

±0.01 ±1 µA

4.076 4.096 4.116 V

±30 ±50
±30 ±60
±30 ±80

2.50

VDD­50mV

, unless otherwise

MAX

1.5 µs

0 to

VREF

±VREF/2

V

DD

+

50mV

ppm/°C

MAX186/MAX188

µs

MHz

V

µF

µF

V

_______________________________________________________________________________________ 3

Low-Power, 8-Channel,

SHDN

Serial 12-Bit ADCs

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 5V ±5%; VSS= 0V or -5V; f

4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T
noted.)

PARAMETER

EXTERNAL REFERENCE AT REFADJ

Reference-Buffer Gain

DIGITAL INPUTS (DIN, SCLK, CS,

DIN, SCLK, CS Input High Voltage

MAX186/MAX188

DIN, SCLK, CS Input Low Voltage
DIN, SCLK, CS Input Hysteresis
DIN, SCLK, CS Input Leakage
DIN, SCLK, CS Input Capacitance

SHDN Input High Voltage
SHDN Input Low Voltage
SHDN Input Current, High
SHDN Input Current, Low
SHDN Input Mid Voltage
SHDN Voltage, Floating
SHDN Max Allowed Leakage,

Mid Input

DIGITAL OUTPUTS (DOUT, SSTRB)

Output Voltage Low V
Output Voltage High V

Three-State Leakage Current I
Three-State Output Capacitance C

POWER REQUIREMENTS

Positive Supply Voltage V
Negative Supply Voltage V

Positive Supply Current I

Negative Supply Current I

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—

CLK

SYMBOL CONDITIONS MIN TYP MAX

Internal compensation mode 0
External compensation mode 4.7
MAX186 1.678
MAX188 1.638
MAX186 ±50
MAX188 ±5

)

V

INH

V

INL

V

HYST

C
V
V

I

I

V
V

I

INH

INL
INH
INL

FLT

OH

OUT

DD

DD

SS

VIN= 0V or V

IN

(Note 6) 15 pF

IN

SHDN = V
SHDN = 0V

IM

SHDN = open
SHDN = open

I

OL

SS

SINK

I

SINK

I

SOURCE

CS = 5V

L

CS = 5V (Note 6)

Operating mode 1.5 2.5
Fast power-down 30 70
Full power-down 210
Operating mode and fast power-down 50
Full power-down 10

DD

DD

= 5mA 0.4
= 16mA 0.3

= 1mA 4 V

= T

to T

A

MIN

2.4 V

0.15 V

VDD- 0.5 V

-4.0 µA

1.5 VDD-1.5

2.75 V

-100 100 nA

5 ±5% V

0 or

-5 ±5%

, unless otherwise

MAX

0.8 V

±1 µA

0.5 V

4.0 µA

±10 µA

15 pF

UNITS

V/V

mA

µFCapacitive Bypass at VREF

µAREFADJ Input Current

V

V

V

µA

µA

4 _______________________________________________________________________________________

Low-Power, 8-Channel,

Serial 12-Bit ADCs

ELECTRICAL CHARACTERISTICS (continued)

(VDD= 5V ±5%; VSS= 0V or -5V; f

4.7µF capacitor at VREF pin; MAX188—external reference, VREF = 4.096V applied to VREF pin; T
noted.)

PARAMETER SYMBOL CONDITIONS UNITS

Positive Supply Rejection
(Note 8)

Negative Supply Rejection
(Note 8)

Note 1: Tested at VDD= 5.0V; VSS= 0V; unipolar input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has

been calibrated.

Note 3: MAX186 – internal reference, offset nulled; MAX188 – external reference (VREF = +4.096V), offset nulled.
Note 4: Ground on-channel; sine wave applied to all off channels.
Note 5: Conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: External load should not change during conversion for specified accuracy.
Note 8: Measured at V

SUPPLY

+5% and V

Note 9: The common-mode range for the analog inputs is from V

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX186—

CLK

= T

to T

A

MIN

, unless otherwise

MAX

MIN TYP MAX

PSR ±0.06 ±0.5 mV

PSR

VDD= 5V ±5%; external reference, 4.096V;
full-scale input

VSS= -5V ±5%; external reference, 4.096V;
full-scale input

-5% only.

SUPPLY

SS

to VDD.

±0.01 ±0.5 mV

TIMING CHARACTERISTICS

(VDD= 5V ±5%; V

=0V or -5V, TA= T

SS

MIN

to T

, unless otherwise noted.)

MAX

MAX186/MAX188

PARAMETER SYMBOL CONDITIONS UNITS

Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold

SCLK Fall to Output Data Valid

CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold

SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS Fall to SSTRB Output Enable

(Note 6)
CS Rise to SSTRB Output Disable

(Note 6)
SSTRB Rise to SCLK Rise

(Note 6)

_______________________________________________________________________________________ 5

t

AZ

t

DS

t

DH

t

DO

t

DV

t

TR

t

CSS

t

CSH

t

CH

t

CL

t

SSTRB

t

SDV

t

STR

t

SCK

MIN TYP MAX

1.5 µs

100 ns

0 ns
C
C

C

LOAD

LOAD
LOAD

= 100pF
= 100pF

= 100pF

MAX18_ _C/E
MAX18_ _M

20 150 ns
20 200 ns

100 ns
100 ns

100 ns

0 ns
200 ns
200 ns

C

= 100pF

LOAD

External clock mode only, C

External clock mode only, C

LOAD

LOAD

= 100pF

= 100pF

200 ns
200 ns

200 ns

Internal clock mode only 0 ns

Low-Power, 8-Channel,
Serial 12-Bit ADCs

__________________________________________Typical Operating Characteristics

POWER-SUPPLY REJECTION

vs. TEMPERATURE

0.30

0.25

0.20

0.15

0.10

PSR (LSBs)

0.05

0.00

MAX186/MAX188

-0.05

-60 140

-20 0 40 80 120

-40 20 100
TEMPERATURE (°C)

VDD = +5V ±5%
VSS = 0V or -5V

60

20

0

-20

-40

-60

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

2.456

2.455

2.454

VREFADJ (V)

2.453

2.452

-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)

MAX186/MAX188 FFT PLOT – 133kHz

ft = 10kHz
fs = 133kHz

ft = 10kHz



= 133kHz

f

s

= +25°C

T

A



CHANNEL-TO-CHANNEL OFFSET MATCHING

vs. TEMPERATURE

0.16

0.14

0.12

0.10

0.08

0.06

0.04

OFFSET MATCHING (LSBs)

0.02
0

-60 -20 60 140

-40 0 40 80 120

20 100

TEMPERATURE (°C)

-80

AMPLITUDE (dB)

-100

-120

-140
0

 

   

FREQUENCY

33.25kHz



66.5kHz

_____________________________________________________________Pin Description

PIN NAME FUNCTION

1-8 CH0-CH7 Sampling Analog Inputs

9

10

11 VREF

6

________________________________________________________________________________________________

V

SS

SHDN

Negative Supply Voltage. Tie to -5V ±5% or AGND
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX186/MAX188 down to 10µA (max)

supply current, otherwise the MAX186/MAX188 are fully operational. Pulling SHDN high puts the ref­erence-buffer amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer
amplifier in external compensation mode.

Reference Voltage for analog-to-digital conversion. Also, Output of the Reference Buffer Amplifier
(4.096V in the MAX186, 1.638 x REFADJ in the MAX188). Add a 4.7µF capacitor to ground when
using external compensation mode. Also functions as an input when used with a precision external
reference.

Low-Power, 8-Channel,

Serial 12-Bit ADCs

________________________________________________Pin Description (continued)

PIN NAME FUNCTION

12 REFADJ

13 AGND Analog Ground. Also IN- Input for single-ended conversions.
14 DGND
15 DOUT

16 SSTRB

17 DIN

18

CS

19 SCLK

20

V

DD

Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to
V

.

DD

Digital Ground
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high.

Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX186/MAX188 begin the
A/D conversion and goes high when the conversion is done. In external clock mode, SSTRB pulses
high for one clock period before the MSB decision. High impedance whenCS is high (external mode).

Serial Data Input. Data is clocked in at the rising edge of SCLK.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT

is high impedance.
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets

the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
Positive Supply Voltage, +5V ±5%

+5V

MAX186/MAX188

DOUT

3k

a. High-Z to V

DGND

and VOL to V

OH

C

LOAD

OH

DOUT

b. High-Z to VOL and VOH to V

Figure 1. Load Circuits for Enable Time

DOUT

3k

DGND

a VOH to High-Z b VOL to High-Z

C

DOUT

LOAD

Figure 2. Load Circuits for Disabled Time

+5V

3k

C

LOAD

DGND

3k

C

LOAD

DGND

18

CS

19

SCLK

DIN

SHDN

OL

CH0
CH1
CH2

CH3
CH4

CH5
CH6
CH7

AGND

REFADJ

VREF

SHIFT

REGISTER

10

1
2
3

4

ANALOG

INPUT

5

MUX

6



7
8

13

12
11

CONTROL

+2.46V

REFERENCE

(MAX186)

LOGIC

T/H

20k

INPUT

17

CLOCK

IN

A

≈ 1.65

+4.096V

INT

CLOCK

12-BIT

SAR
ADC

REF

OUTPUT

REGISTER

OUT

MAX186
MAX188

SHIFT

15

DOUT

16

SSTRB

20

V

DD

14

DGND

9

V

SS

Figure 3. Block Diagram

_______________________________________________________________________________________ 7

Low-Power, 8-Channel,
Serial 12-Bit ADCs

_______________Detailed Description

The MAX186/MAX188 use a successive-approximation
conversion technique and input track/hold (T/H) circuit­ry to convert an analog signal to a 12-bit digital output.
A flexible serial interface provides easy interface to
microprocessors. No external hold capacitors are
required. Figure 3 shows the block diagram for the
MAX186/MAX188.

Pseudo-Differential Input

The sampling architecture of the ADC’s analog com­parator is illustrated in the Equivalent Input Circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0-CH7 and IN- is switched to AGND. In
differential mode, IN+ and IN- are selected from pairs
of CH0/CH1, CH2/CH3, CH4/CH5 and CH6/CH7.

MAX186/MAX188

Configure the channels with Table 3 and Table 4.
In differential mode, IN- and IN+ are internally switched

to either one of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta­ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. Accomplish this
by connecting a 0.1µF capacitor from AIN- (the select­ed analog input, respectively) to AGND.

During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui­sition interval, the T/H switch opens, retaining charge
on C

as a sample of the signal at IN+.

HOLD

The conversion interval begins with the input multiplex­er switching C

from the positive input (IN+) to the

HOLD

negative input (IN-). In single-ended mode, IN- is sim­ply AGND. This unbalances node ZERO at the input of
the comparator. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 12-bit resolution. This
action is equivalent to transferring a charge of 16pF x

+) - (VIN-)] from C

[(V

IN

to the binary-weighted

HOLD

capacitive DAC, which in turn forms a digital represen­tation of the analog input signal.

The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. The T/H enters its hold mode on the falling
clock edge after the eighth bit of the control word has
been shifted in. If the converter is set up for

HOLD

Track/Hold

. The

12-BIT CAPACITIVE DAC

VREF

C

INPUT

CH0
CH1

CH2
CH3
CH4
CH5
CH6
CH7

AGND
SINGLE-ENDED MODE: IN+ = CHO-CH7, IN– = AGND.

DIFFERENTIAL MODE: IN+ AND IN– SELECTED FROM PAIRS OF
 CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.

Figure 4. Equivalent Input Circuit

MUX

–

C

SWITCH

HOLD

16pF

TRACK

+

T/H

SWITCH

10k
R

S

COMPARATOR

ZERO

HOLD

AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES 
FROM THE SELECTED IN+ 
CHANNEL TO THE SELECTED 
IN– CHANNEL.

single-ended inputs, IN- is connected to AGND, and
the converter samples the “+” input. If the converter is
set up for differential inputs, IN- connects to the “-”
input, and the difference of

|IN+ - IN-| is sampled. At

the end of the conversion, the positive input connects
back to IN+, and C

charges to the input signal.

HOLD

The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. Acquisition time is cal­culated by:

= 9 x (RS+ RIN) x 16pF,

t

AZ

where R
input signal, and t

= 5kΩ, RS= the source impedance of the

IN

is never less than 1.5µs. Note that

AZ

source impedances below 5kΩ do not significantly
affect the AC performance of the ADC. Higher source
impedances can be used if an input capacitor is con­nected to the analog inputs, as shown in Figure 5. Note
that the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s signal bandwidth.

Input Bandwidth

The ADC’s input tracking circuitry has a 4.5MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig­nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.

8 _______________________________________________________________________________________

Low-Power, 8-Channel,

Serial 12-Bit ADCs

MAX186/MAX188

V

DD

DGND

AGND

V

SCLK

DOUT

SSTRB

SHDN

**

CS

DIN

SS

+5V

N.C.

0V TO

4.096V

ANALOG

0.01µF

INPUT

+5V

D1

1N4148

C2

0.01µF

* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
**REQUIRED FOR MAX188 ONLY. A POTENTIOMETER MAY BE USED IN PLACE OF THE REFERENCE FOR TEST PURPOSES.

C1

4.7µF

CH7

REFADJ

VREF

+2.5V

MAX186
MAX188

+2.5V

REFERENCE

+5V

0.1µF

2MHz

OSCILLATOR

CH1 CH2

OSCILLOSCOPE

CH3

SCLK

SSTRB
DOUT*

CH4

Figure 5. Quick-Look Circuit

Analog Input Range and Input Protection

Internal protection diodes, which clamp the analog
input to V
swing from V

and VSS, allow the channel input pins to

DD

- 0.3V to VDD+ 0.3V without damage.

SS

However, for accurate conversions near full scale, the
inputs must not exceed V
lower than V

by 50mV.

SS

by more than 50mV, or be

DD

If the analog input exceeds 50mV beyond the sup­plies, do not forward bias the protection diodes of
off-channels over two milliamperes, as excessive
current will degrade the conversion accuracy of the
on-channel.

The full-scale input voltage depends on the voltage at
VREF. See Tables 1a and 1b.

Quick Look

To evaluate the analog performance of the
MAX186/MAX188 quickly, use the circuit of Figure 5.
The MAX186/MAX188 require a control byte to be writ­ten to DIN before each conversion. Tying DIN to +5V
feeds in control bytes of $FF (HEX), which trigger

_______________________________________________________________________________________ 9

Table 1a. Unipolar Full Scale and Zero Scale

Reference

Internal Reference
(MAX186 only)

External Reference

at REFADJ
at VREF 0V VREF

Zero

Scale

0V +4.096V

0V

* A = 1.678 for the MAX186, 1.638 for the MAX188

Full Scale

V

REFADJ

Table 1b. Bipolar Full Scale, Zero Scale, and
Negative Full Scale

Reference

Internal Reference
(MAX186 only)

External Reference

at REFADJ
at VREF -1/2 VREF 0V

Negative

Full Scale

-4.096V/2

-1/2V

REFADJ

x A*

* A = 1.678 for the MAX186, 1.638 for the MAX188

Zero

Scale

0V

0V

Full Scale

+4.096V/2

+1/2V

+1/2 VREF

REFADJ

x A*

x A*

Low-Power, 8-Channel,
Serial 12-Bit ADCs

single-ended unipolar conversions on CH7 in external
clock mode without powering down between conver­sions. In external clock mode, the SSTRB output pulses
high for one clock period before the most significant bit
of the 12-bit conversion result comes out of DOUT.
Varying the analog input to CH7 should alter the
sequence of bits from DOUT. A total of 15 clock cycles
is required per conversion. All transitions of the SSTRB
and DOUT outputs occur on the falling edge of SCLK.

How to Start a Conversion

A conversion is started on the MAX186/MAX188 by
clocking a control byte into DIN. Each rising edge on
SCLK, with CS low, clocks a bit from DIN into the
MAX186/MAX188’s internal shift register. After CS falls,
the first arriving logic “1” bit defines the MSB of the

MAX186/MAX188

control byte. Until this first “start” bit arrives, any num­ber of logic “0” bits can be clocked into DIN with no
effect. Table 2 shows the control-byte format.

Table 2. Control-Byte Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(MSB) (LSB)

START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0

The MAX186/MAX188 are fully compatible with
Microwire and SPI devices. For SPI, select the correct
clock polarity and sampling edge in the SPI control reg­isters: set CPOL = 0 and CPHA = 0. Microwire and SPI
both transmit a byte and receive a byte at the same
time. Using the
software interface requires only three 8-bit transfers to
perform a conversion (one 8-bit transfer to configure
the ADC, and two more 8-bit transfers to clock out the
12-bit conversion result).

Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.

1) Set up the control byte for external clock mode, call
it TB1. TB1 should be of the format: 1XXXXX11
Binary, where the Xs denote the particular channel
and conversion-mode selected.

Typical Operating Circuit

Example: Simple Software Interface

, the simplest

Bit Name Description

7(MSB) START The first logic “1” bit after CS goes low defines the beginning of the control byte.

6 SEL2 These three bits select which of the eight channels are used for the conversion.
5 SEL1 See Tables 3 and 4.
4 SEL0

3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar

mode, an analog input signal from 0V to VREF can be converted; in bipolar mode, the

signal can range from -VREF/2 to +VREF/2.

2 SGL/DIF 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In

single-ended mode, input signal voltages are referred to AGND. In differential mode,
the voltage difference between two channels is measured. See Tables 3 and 4.

1 PD1 Selects clock and power-down modes.
0(LSB) PD0 PD1 PD0 Mode

00Full power-down (IQ= 2µA)
01Fast power-down (IQ= 30µA)
10Internal clock mode

1 1 External clock mode

10 ______________________________________________________________________________________

Low-Power, 8-Channel,

DIFF

DIFF

Serial 12-Bit ADCs

Table 3. Channel Selection in Single-Ended Mode (SGL/

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 AGND

000 + –
100 + –
001 + –
101 + –
010 + –
110 + –
011 + –
111 + –

Table 4. Channel Selection in Differential Mode (SGL/

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

000 + –
001 + –
010 + –

= 1)

= 0)

MAX186/MAX188

011 +–
100 – +
101 – +
110 – +
111 –+

2) Use a general-purpose I/O line on the CPU to pull
CS on the MAX186/MAX188 low.

3) Transmit TB1 and simultaneously receive a byte
and call it RB1. Ignore RB1.

4) Transmit a byte of all zeros ($00 HEX) and simulta­neously receive byte RB2.

5) Transmit a byte of all zeros ($00 HEX) and simulta­neously receive byte RB3.

6) Pull CS on the MAX186/MAX188 high.

______________________________________________________________________________________ 11

Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 will contain the result of the conversion
padded with one leading zero and three trailing zeros.
The total conversion time is a function of the serial
clock frequency and the amount of dead time between
8-bit transfers. Make sure that the total conversion time
does not exceed 120µs, to avoid excessive T/H droop.

Digital Output

In unipolar input mode, the output is straight binary
(see Figure 15). For bipolar inputs, the output is
twos-complement (see Figure 16). Data is clocked out
at the falling edge of SCLK in MSB-first format.

Low-Power, 8-Channel,
Serial 12-Bit ADCs

CS

t

ACQ

SCLK

DIN

14 8 12 16 20 24

UNI/

START

SEL2 SEL1 SEL0

BIP

SCL/

DIFF

PD1 PD0

SSTRB

RB1

DOUT

ACQUISITION

1.5µs (CLK = 2MHz)

t

CSS

t

DS

t

DH

DV



t

CL

t

IDLE

CSH

t

A/D STATE

Figure 6. 24-Bit External Clock Mode Conversion Timing (SPI, QSPI and Microwire Compatible)

MAX186/MAX188

CS

SCLK

DIN

DOUT

MSB

t

B11

CH

RB2

B10 B9 B8 B7 B6 B5 B4 B3 B2 B1

CONVERSION

• • •

• • •

• • •

• • •

RB3

FILLED WITH 

B0

ZEROS

LSB

IDLE

t

CSH

t

DO

t

TR

Figure 7. Detailed Serial-Interface Timing

Internal and External Clock Modes

The MAX186/MAX188 may use either an external serial
clock or the internal clock to perform the
successive-approximation conversion. In both clock
modes, the external clock shifts data in and out of the
MAX186/MAX188. The T/H acquires the input signal as
the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 7 through 10 show the timing
characteristics common to both modes.

External Clock

In external clock mode, the external clock not only shifts
data in and out, it also drives the analog-to-digital con-

version steps. SSTRB pulses high for one clock period
after the last bit of the control byte. Successive-approxi­mation bit decisions are made and appear at DOUT on
each of the next 12 SCLK falling edges (see Figure 6).
SSTRB and DOUT go into a high-impedance state when
CS goes high; after the next CS falling edge, SSTRB will
output a logic low. Figure 8 shows the SSTRB timing in
external clock mode.

The conversion must complete in some minimum time, or
else droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if the
clock period exceeds 10µs, or if serial-clock interruptions
could cause the conversion interval to exceed 120µs.

12 ______________________________________________________________________________________

Low-Power, 8-Channel,

Serial 12-Bit ADCs

MAX186/MAX188

CS

SSTRB

SCLK

• • •

t

SDV

• • •

• • •

Figure 8. External Clock Mode SSTRB Detailed Timing

CS

SCLK

DIN

SSTRB

DOUT

A/D STATE

14 8

2 3 5 6 7 9 10 11 19 21 22 23

UNI/

START

SEL2 SEL1 SEL0

IDLE

SCL/

DIP

PD1 PD0

DIFF

ACQUISITION

1.5µs (CLK = 2MHz)



PD0 CLOCKED IN

t

CONV

CONVERSION

10µs MAX

t

SSTRB

12

B11

B10 B9 B2 B1

MSB

IDLE

• • •

t

STR

• • •

t

SSTRB

• • • • •

18

20

FILLED WITH 

B0

ZEROS

LSB

24

Figure 9. Internal Clock Mode Timing

Internal Clock

In internal clock mode, the MAX186/MAX188 generate
their own conversion clock internally. This frees the
microprocessor from the burden of running the SAR con­version clock, and allows the conversion results to be
read back at the processor’s convenience, at any clock
rate from zero to typically 10MHz. SSTRB goes low at the
start of the conversion and then goes high when the con­version is complete. SSTRB will be low for a maximum of
10µs, during which time SCLK should remain low for best
noise performance. An internal register stores data when
the conversion is in progress. SCLK clocks the data out
at this register at any time after the conversion is com­plete. After SSTRB goes high, the next falling clock edge

______________________________________________________________________________________ 13

will produce the MSB of the conversion at DOUT, fol­lowed by the remaining bits in MSB-first format (see
Figure 9). CS does not need to be held low once a con­version is started. Pulling CS high prevents data from
being clocked into the MAX186/MAX188 and three­states DOUT, but it does not adversely effect an internal
clock-mode conversion already in progress. When inter­nal clock mode is selected, SSTRB does not go into a
high-impedance state when CS goes high.

Figure 10 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shifted in and
out of the MAX186/MAX188 at clock rates exceeding

4.0MHz, provided that the minimum acquisition time, t

AZ

is kept above 1.5µs.

,

Low-Power, 8-Channel,
Serial 12-Bit ADCs

CS • • •

t

CSH

SSTRB • • •

t

SSTRB

SCLK • • •

PD0 CLOCK IN

MAX186/MAX188

Figure 10. Internal Clock Mode SSTRB Detailed Timing

Data Framing

The falling edge of CS does not start a conversion on the
MAX186/MAX188. The first logic high clocked into DIN is
interpreted as a start bit and defines the first bit of the
control byte. A conversion starts on the falling edge of
SCLK, after the eighth bit of the control byte (the PD0 bit)
is clocked into DIN. The start bit is defined as:

The first high bit clocked into DIN with CS low any­time the converter is idle, e.g. after V

OR

The first high bit clocked into DIN after bit 5 of a
conversion in progress is clocked onto the DOUT pin.

If a falling edge on CS forces a start bit before bit 5
(B5) becomes available, then the current conversion
will be terminated and a new one started. Thus, the
fastest the MAX186/MAX188 can run is 15 clocks per
conversion. Figure 11a shows the serial-interface timing
necessary to perform a conversion every 15 SCLK
cycles in external clock mode. If CS is low and SCLK is
continuous, guarantee a start bit by first clocking in 16
zeros.

Most microcontrollers require that conversions occur in
multiples of 8 SCLK clocks; 16 clocks per conversion
will typically be the fastest that a microcontroller can
drive the MAX186/MAX188. Figure 11b shows the
serial-interface timing necessary to perform a conver­sion every 16 SCLK cycles in external clock mode.

is applied.

CC

t

CONV

NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

t

SCK

t

CSS

__________ Applications Information

Power-On Reset

When power is first applied and if SHDN is not pulled
low, internal power-on reset circuitry will activate the
MAX186/MAX188 in internal clock mode, ready to con­vert with SSTRB = high. After the power supplies have
been stabilized, the internal reset time is 100µs and no
conversions should be performed during this phase.
SSTRB is high on power-up and, if CS is low, the first
logical 1 on DIN will be interpreted as a start bit. Until a
conversion takes place, DOUT will shift out zeros.

Reference-Buffer Compensation

In addition to its shutdown function, the SHDN pin also
selects internal or external compensation. The compen­sation affects both power-up time and maximum conver­sion speed. Compensated or not, the minimum clock
rate is 100kHz due to droop on the sample-and-hold.

To select external compensation, float SHDN. See the

Typical Operating Circuit

VREF. A value of 4.7µF or greater ensures stability and
allows operation of the converter at the full clock speed of
2MHz. External compensation increases power-up time (see
the

Choosing Power-Down Mode

Internal compensation requires no external capacitor at
VREF, and is selected by pulling SHDN high. Internal com­pensation allows for shortest power-up times, but is only
available using an external clock and reduces the maxi­mum clock rate to 400kHz.

, which uses a 4.7µF capacitor at

section, and Table 5).

14 ______________________________________________________________________________________

CS

SCLK

Low-Power, 8-Channel,

Serial 12-Bit ADCs

MAX186/MAX188

1

8181

DIN

DOUT

SSTRB

Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing

CS

SCLK

DIN

DOUT

Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing

S CONTROL BYTE 0

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 0

S CONTROL BYTE 0

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B11 B10 B9 B8

CONVERSION RESULT 0

Power-Down

Choosing Power-Down Mode

You can save power by placing the converter in a
low-current shutdown state between conversions.
Select full power-down or fast power-down mode via
bits 7 and 8 of the DIN control byte with SHDN high or
floating (see Tables 2 and 6). Pull SHDN low at any time
to shut down the converter completely. SHDN overrides
bits 7 and 8 of DIN word (see Table 7).

Full power-down mode turns off all chip functions that draw
quiescent current, reducing IDDand ISStypically to 2µA.

Fast power-down mode turns off all circuitry except the
bandgap reference. With the fast power-down mode, the
supply current is 30µA. Power-up time can be shortened
to 5µs in internal compensation mode.

In both software shutdown modes, the serial interface
remains operational, however, the ADC will not convert.
Table 5 illustrates how the choice of reference-buffer
compensation and power-down mode affects both
power-up delay and maximum sample rate.

In external compensation mode, the power-up time is
20ms with a 4.7µF compensation capacitor (200ms with
a 33µF capacitor) when the capacitor is fully discharged.
In fast power-down, you can eliminate start-up time by

CONTROL BYTE 1S

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

CONVERSION RESULT 1

CONTROL BYTE 1S

CONTROL BYTE 2S

• • •

• • •

• • •

• • •

CONVERSION RESULT 1

using low-leakage capacitors that will not discharge
more than 1/2LSB while shut down. In shutdown, the
capacitor has to supply the current into the reference
(1.5µA typ) and the transient currents at power-up.

Figures 12a and 12b illustrate the various power-down
sequences in both external and internal clock modes.

Software Power-Down

Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 6, PD1 and
PD0 also specify the clock mode. When software shut­down is asserted, the ADC will continue to operate in
the last specified clock mode until the conversion is
complete. Then the ADC powers down into a low quies­cent-current state. In internal clock mode, the interface
remains active and conversion results may be clocked
out while the MAX186/MAX188 have already entered a
software power-down.

The first logical 1 on DIN will be interpreted as a start
bit, and powers up the MAX186/MAX188. Following the
start bit, the data input word or control byte also deter­mines clock and power-down modes. For example, if
the DIN word contains PD1 = 1, then the chip will
remain powered up. If PD1 = 0, a power-down will
resume after one conversion.

______________________________________________________________________________________ 15

Low-Power, 8-Channel,

SHDN

Serial 12-Bit ADCs

CLOCK

MODE

SHDN

DOUT

MODE

MAX186/MAX188

Figure 12a. Timing Diagram Power-Down Modes, External Clock

DIN

INTERNAL

XXXX

SX

EXTERNAL

SETS EXTERNAL
CLOCK MODE

11 S 01

DATA VALID

(12 DATA BITS)

POWERED UP

XXXXX XXXXX

SETS FAST
POWER-DOWN 
MODE

DATA VALID

(12 DATA BITS)

SETS EXTERNAL

CLOCK MODE

S11

FAST

POWER-DOWN

POWERED UP

VALID

EXTERNAL

DATA INVALID

FULL

POWER

DOWN

Table 5. Typical Power-Up Delay Times

Reference Reference- VREF Power- Power-Up Maximum
Buffer Buffer Capacitor Down Delay Sampling

Compensation (µF) Mode (sec) Rate (ksps)
Mode

Enabled Internal Fast 5µ 26
Enabled Internal Full 300µ 26
Enabled External 4.7 Fast See Figure 14c 133
Enabled External 4.7 Full See Figure 14c 133
Disabled Fast 2µ 133
Disabled Full 2µ 133

POWERED

UP

Table 6. Software Shutdown and Clock Mode

Table 7. Hard-Wired Shutdown and
Compensation Mode

PD1 PD0 Device Mode

1 1 External Clock Mode
1 0 Internal Clock Mode
0 1 Fast Power-Down Mode
0 0 Full Power-Down Mode

16 ______________________________________________________________________________________

State Mode Compensation

1 Enabled Internal Compensation

Floating Enabled External Compensation

0 Full Power-Down N/A

Device Reference-Buffer

Low-Power, 8-Channel,

Serial 12-Bit ADCs

MAX186/MAX188

CLOCK

MODE

DIN

DOUT

SSTRB

MODE

SX

SETS INTERNAL
CLOCK MODE

XXXX

10 S 00

CONVERSION

POWERED UP

INTERNAL CLOCK MODE

DATA VALID

Figure 12b. Timing Diagram Power-Down Modes, Internal Clock

Hardware Power-Down

The SHDN pin places the converter into the full
power-down mode. Unlike with the software shut-down
modes, conversion is not completed. It stops coinci­dentally with SHDN being brought low. There is no
power-up delay if an external reference is used and is
not shut down. The SHDN pin also selects internal or
external reference compensation (see Table 7).

Power-Down Sequencing

The MAX186/MAX188 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. The following discussion illus­trates the various power-down sequences.

SETS FULL
POWER-DOWN

XXXXX 

DATA VALID

CONVERSION

FULL

POWER-DOWN

S

POWERED

UP

Lowest Power at up to 500

Conversions/Channel/Second

The following examples illustrate two different power-down
sequences. Other combinations of clock rates, compen­sation modes, and power-down modes may give lowest
power consumption in other applications.

Figure 14a depicts the MAX186 power consumption for
one or eight channel conversions utilizing full
power-down mode and internal reference compensation.
A 0.01µF bypass capacitor at REFADJ forms an RC filter
with the internal 20kΩ reference resistor with a 0.2ms
time constant. To achieve full 12-bit accuracy, 10 time
constants or 2ms are required after power-up. Waiting
2ms in FASTPD mode instead of full power-up will reduce
the power consumption by a factor of 10 or more. This is
achieved by using the sequence shown in Figure 13.

COMPLETE CONVERSION SEQUENCE

DIN

100

FULLPD FASTPD NOPD FULLPD FASTPD

REFADJ

VREF

2.5V

0V

4V

0V

(ZEROS)

101 1 11100 101

τ = RC = 20kΩ x C

Figure 13. MAX186 FULLPD/FASTPD Power-Up Sequence

______________________________________________________________________________________ 17

2ms WAIT

REFADJ

CH1 CH7

t

≈ 15µs

BUFFEN

(ZEROS)

Low-Power, 8-Channel,
Serial 12-Bit ADCs

MAX186

1000

2ms FASTPD WAIT
400kHz EXTERNAL CLOCK
INTERNAL COMPENSATION

100

10

AVG. SUPPLY CURRENT (µA)

1

0 100 300 500

50 150 250 350 450

MAX186/MAX188

Figure 14a. MAX186 Supply Current vs. Sample Rate/Second,
FULLPD, 400kHz Clock

FULL POWER-DOWN

8 CHANNELS

1 CHANNEL

200 400

CONVERSIONS PER CHANNEL PER SECOND

Lowest Power at Higher Throughputs

Figure 14b shows the power consumption with
external-reference compensation in fast power-down,
with one and eight channels converted. The external

4.7µF compensation requires a 50µs wait after power-up,
accomplished by 75 idle clocks after a dummy conver­sion. This circuit combines fast multi-channel conversion
with lowest power consumption possible. Full
power-down mode may provide increased power sav­ings in applications where the MAX186/MAX188 are
inactive for long periods of time, but where intermittent
bursts of high-speed conversions are required.

External and Internal References

The MAX186 can be used with an internal or external
reference, whereas an external reference is required for
the MAX188. Diode D1 shown in the

Circuit

ensures correct start-up. Any standard signal

Typical Operating

diode can be used. For both parts, an external refer­ence can either be connected directly at the VREF ter­minal or at the REFADJ pin.

An internal buffer is designed to provide 4.096V at
VREF for both the MAX186 and MAX188. The
MAX186’s internally trimmed 2.46V reference is
buffered with a gain of 1.678. The MAX188's buffer is
trimmed with a buffer gain of 1.638 to scale an external

2.5V reference at REFADJ to 4.096V at VREF.

MAX186 Internal Reference

The full-scale range of the MAX186 with internal reference
is 4.096V with unipolar inputs, and ±2.048V with bipolar
inputs. The internal reference voltage is adjustable to
±1.5% with the Reference-Adjust Circuit of Figure 17.

MAX186-14A

MAX186/MAX188

10,000

1000

100

AVG. SUPPLY CURRENT (µA)

10

0

2k

Figure 14b. MAX186/MAX188 Supply Current vs. Sample
Rate/Second, FASTPD, 2MHz Clock

3.0

2.5

2.0

1.5

1.0

POWER-UP DELAY (ms)

0.5

0

0.0001 0.001 0.01 0.1 1 10

Figure 14c. Typical Power-Up Delay vs. Time in Shutdown

FAST POWER-DOWN

8 CHANNELS

1 CHANNEL

2MHz EXTERNAL CLOCK
EXTERNAL COMPENSATION
50µs WAIT

4k 6k 8k 10k 12k 14k 16k 18k

CONVERSIONS PER CHANNEL PER SECOND

TIME IN SHUTDOWN (sec)

External Reference

With both the MAX186 and MAX188, an external refer­ence can be placed at either the input (REFADJ) or the
output (VREF) of the internal buffer amplifier. The
REFADJ input impedance is typically 20kΩ for the
MAX186 and higher than 100kΩ for the MAX188, where
the internal reference is omitted. At VREF, the input
impedance is a minimum of 12kΩ for DC currents.
During conversion, an external reference at VREF must
be able to deliver up to 350µA DC load current and have
an output impedance of 10Ω or less. If the reference has
higher output impedance or is noisy, bypass it close to
the VREF pin with a 4.7µF capacitor.

18 ______________________________________________________________________________________

OUTPUT CODE

11 . . . 111
11 . . . 110

11 . . . 101

00 . . . 011
00 . . . 010

00 . . . 001
00 . . . 000

0

123

INPUT VOLTAGE (LSBs)

FULL-SCALE
TRANSITION

FS = +4.096V

1LSB = FS

4096

FS - 3/2LSB

Low-Power, 8-Channel,

Serial 12-Bit ADCs

MAX186/MAX188

011 . . . 111
011 . . . 110

000 . . . 010
000 . . . 001
000 . . . 000

111 . . . 111
111 . . . 110
111 . . . 101

100 . . . 001
100 . . . 000

FS

FS = +4.096

2

1LSB = +4.096

4096

-FS

0V

INPUT VOLTAGE (LSBs)

+FS - 1LSB

Figure 15. MAX186/MAX188 Unipolar Transfer Function,

4.096V = Full Scale

Using the buffered REFADJ input avoids external
buffering of the reference. To use the direct VREF input,
disable the internal buffer by tying REFADJ to VDD.

Transfer Function and Gain Adjust

Figure 15 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 16 shows the bipolar
input/output transfer function. Code transitions occur
halfway between successive integer LSB values. Output
coding is binary with 1 LSB = 1.00mV (4.096V/4096) for
unipolar operation and 1 LSB = 1.00mV ((4.096V/2 -

-4.096V/2)/4096) for bipolar operation.
Figure 17, the MAX186 Reference-Adjust Circuit, shows

how to adjust the ADC gain in applications that use the
internal reference. The circuit provides ±1.5%
(±65LSBs) of gain adjustment range.

Layout, Grounding, Bypassing

For best performance, use printed circuit boards.
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi­tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.

Figure 18 shows the recommended system ground
connections. A single-point analog ground (“star”
ground point) should be established at AGND, sepa­rate from the logic ground. All other analog grounds

Figure 16. MAX186/MAX188 Bipolar Transfer Function,
±4.096V/2 = Full Scale

+5V

510k

100k

24k

Figure 17. MAX186 Reference-Adjust Circuit

0.01µF

MAX186

REFADJ

12

and DGND should be connected to this ground. No
other digital system ground should be connected to
this single-point analog ground. The ground return to
the power supply for this ground should be low imped­ance and as short as possible for noise-free operation.

High-frequency noise in the V

power supply may

DD

affect the high-speed comparator in the ADC. Bypass
these supplies to the single-point analog ground with

0.1µF and 4.7µF bypass capacitors close to the
MAX186/MAX188. Minimize capacitor lead lengths for
best supply-noise rejection. If the +5V power supply is
very noisy, a 10Ω resistor can be connected as a low­pass filter, as shown in Figure 18.

______________________________________________________________________________________ 19

Low-Power, 8-Channel,
Serial 12-Bit ADCs

SUPPLIES

+5V

R* = 10Ω

DD

MAX186/MAX188

* OPTIONAL

AGNDV

MAX186/MAX188

Figure 18. Power-Supply Grounding Connection

-5V

GND

SS

DGND+5VDGNDV

DIGITAL

CIRCUITRY

High-Speed Digital Interfacing with QSPI

The MAX186/MAX188 can interface with QSPI at high
throughput rates using the circuit in Figure 19. This
QSPI circuit can be programmed to do a conversion on
each of the eight channels. The result is stored in mem­ory without taxing the CPU since QSPI incorporates its
own micro-sequencer. Figure 19 depicts the MAX186,
but the same circuit could be used with the MAX188 by
adding an external reference to VREF and connecting
REFADJ to V

Figure 20 details the code that sets up QSPI for
autonomous operation. In external clock mode, the
MAX186/MAX188 perform a single-ended, unipolar con­version on each of their eight analog input channels.
Figure 21, QSPI Assembly-Code Timing, shows the tim­ing associated with the assembly code of Figure 20. The
first byte clocked into the MAX186/MAX188 is the control
byte, which triggers the first conversion on CH0. The last
two bytes clocked into the MAX186/MAX188 are all zero
and clock out the results of the CH7 conversion.

DD

.

1



CH0

2

CH1
CH2

3
4

10

5
6

7
8
9

CH3
CH4
CH5

CH6
CH7
V

SS

SHDN

MAX186

ANALOG 

INPUTS



Figure 19. MAX186 QSPI Connection

V

SCLK

CS

DIN

SSTRB

DOUT

DGND

AGND

REFADJ

VREF

DD

20
19

18

17
16

15

14
13

12
11

+5V

V

, V

0.1µF 4.7µF



0.1µF

+

4.7µF

0.01µF

* CLOCK CONNECTIONS NOT SHOWN

DDI

SCK

PCS0

MOSI

MISO

, V

DDE

MC68HC16

VSSE

V

SSI

DDSYN

, V

STBY

20 ______________________________________________________________________________________

Low-Power, 8-Channel,

Serial 12-Bit ADCs

*Title : MAX186.ASM
* Description :
* This is a shell program for using a stand-alone 68HC16 without any external memory. The internal 1K RAM
* is put into bank $0F to maintain 68HC11 code compatibility. This program was written with software
* provided in the Motorola 68HC16 Evaluation Kit.
*
* Roger J.A. Chen, Applications Engineer
* MAXIM Integrated Products
* November 20, 1992
*
******************************************************************************************************************************************************

INCLUDE ‘EQUATES.ASM’ ;Equates for common reg addrs
INCLUDE ‘ORG00000.ASM’ ;initialize reset vector
INCLUDE ‘ORG00008.ASM’ ;initialize interrupt vectors
ORG $0200 ;start program after interrupt vectors
INCLUDE ‘INITSYS.ASM’ ;set EK=F,XK=0,YK=0,ZK=0

;set sys clock at 16.78 MHz, COP off

INCLUDE ‘INITRAM.ASM’ ;turn on internal SRAM at $10000

;set stack (SK=1, SP=03FE)

MAIN:

JSR INITQSPI

MAINLOOP:

JSR READ186

WAIT:

LDAA SPSR
ANDA #$80
BEQ WAIT ;wait for QSPI to finish
BRA MAINLOOP

ENDPROGRAM:

MAX186/MAX188

INITQSPI:
;This routine sets up the QSPI microsequencer to operate on its own.

;The sequencer will read all eight channels of a MAX186/MAX188 each time
;it is triggered. The A/D converter results will be left in the
;receive data RAM. Each 16 bit receive data RAM location will
;have a leading zero, 12 bits of conversion result and three zeros.
;
;Receive RAM Bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
;A/D Result 0 MSB LSB 0 0 0
***** Initialize the QSPI Registers ******

PSHA
PSHB
LDAA #%01111000
STAA QPDR ;idle state for PCS0-3 = high
LDAA #%01111011
STAA QPAR ;assign port D to be QSPI
LDAA #%01111110
STAA QDDR ;only MISO is an input
LDD #$8008
STD SPCR0 ;master mode,16 bits/transfer,

;CPOL=CPHA=0,1MHz Ser Clock
LDD #$0000
STD SPCR1 ;set delay between PCS0 and SCK,

Figure 20. MAX186/MAX188 Assembly-Code Listing

______________________________________________________________________________________ 21

Low-Power, 8-Channel,
Serial 12-Bit ADCs

;set delay between transfers
LDD #$0800
STD SPCR2 ;set ENDQP to $8 for 9 transfers

***** Initialize QSPI Command RAM *****

LDAA #$80 ;CONT=1,BITSE=0,DT=0,DSCK=0,PCS0=ACTIVE
STAA $FD40 ;store first byte in COMMAND RAM
LDAA #$C0 ;CONT=1,BITSE=1,DT=0,DSCK=0,PCS0=ACTIVE
STAA $FD41
STAA $FD42
STAA $FD43
STAA $FD44
STAA $FD45
STAA $FD46
STAA $FD47
LDAA #$40 ;CONT=0,BITSE=1,DT=0,DSCK=0,PCS0=ACTIVE

MAX186/MAX188

STAA $FD48

***** Initialize QSPI Transmit RAM *****

LDD #$008F

STD $FD20

LDD #$00CF

STD $FD22

LDD #$009F

STD $FD24

LDD #$00DF

STD $FD26

LDD #$00AF

STD $FD28

LDD #$00EF

STD $FD2A

LDD #$00BF

STD $FD2C

LDD #$00FF

STD $FD2E

LDD #$0000

STD $FD30
PULB
PULA
RTS

READ186:
;This routine triggers the QSPI microsequencer to autonomously
;trigger conversions on all 8 channels of the MAX186. Each
;conversion result is stored in the receive data RAM.

PSHA
LDAA #$80
ORAA SPCR1
STAA SPCR1 ;just set SPE
PULA
RTS

***** Interrupts/Exceptions *****
BDM: BGND ;exception vectors point here

Figure 20. MAX186/MAX188 Assembly-Code Listing (continued)

22 ______________________________________________________________________________________

• • • •

Low-Power, 8-Channel,

Serial 12-Bit ADCs

MAX186/MAX188

CS

Figure 21. QSPI Assembly-Code Timing

TMS320C3x to MAX186 Interface

Figure 22 shows an application circuit to interface the
MAX186/MAX188 to the TMS320 in external clock
mode. The timing diagram for this interface circuit is
shown in Figure 23.

Use the following steps to initiate a conversion in the
MAX186/MAX188 and to read the results:

1) The TMS320 should be configured with CLKX (trans­mit clock) as an active-high output clock and CLKR
(TMS320 receive clock) as an active-high input clock.
CLKX and CLKR of the TMS320 are tied together with
the SCLK input of the MAX186/MAX188.

2) The MAX186/MAX188 CS is driven low by the XF_
I/O port of the TMS320 to enable data to be clocked
into DIN of the MAX186/MAX188.

3) An 8-bit word (1XXXXX11) should be written to the
MAX186/MAX188 to initiate a conversion and place
the device into external clock mode. Refer to Table
2 to select the proper XXXXX bit values for your spe­cific application.

4) The SSTRB output of the MAX186/MAX188 is moni­tored via the FSR input of the TMS320. A falling
edge on the SSTRB output indicates that the conver­sion is in progress and data is ready to be received
from the MAX186/MAX188.

• • • •

• • • •

• • • •

SCLK

SSTRB

DIN

XF

CLKX

TMS320C3x

CLKR

DX

DR

FSR

Figure 22. MAX186/MAX188 to TMS320 Serial Interface

CS

SCLK



DIN

DOUT

SSTRB

MAX186
MAX188

5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits rep­resent the 12-bit conversion result followed by four
trailing bits, which should be ignored.

6) Pull CS high to disable the MAX186/MAX188 until
the next conversion is initiated.

______________________________________________________________________________________ 23

Low-Power, 8-Channel,
Serial 12-Bit ADCs

CS

SCLK

DIN

SSTRB

DOUT

START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0

Figure 23. TMS320 Serial Interface Timing Diagram

MAX186/MAX188

__________Typical Operating Circuit

+5V

C4 

0.1µF

V

DD

I/O
SCK (SK)*
MOSI (SO)
MISO (SI)

C1

4.7µF

0V to

4.096V

ANALOG

INPUTS

C2 

0.01µF

CH0

CH7

VREF

REFADJ

MAX186

V

DGND

AGND

V

CS

SCLK

DIN

DOUT

SSTRB

SHDN

DD

C3

0.1µF

SS

CPU

V

SS

HIGH
IMPEDANCE

MSB B10 B1 LSB

HIGH
IMPEDANCE

___________________Chip Topography

SCLK

CS

DIN

SSTRB

DOUT

DGND
AGND

0.151"



(3.84 mm)

CH2
CH3

CH4

CH5
CH6

CH7

V

CH0CH1

DD

_Ordering Information (continued)

†

PART

MAX188_CPP 20 Plastic DIP
MAX188_CWP 20 SO
MAX188_CAP 20 SSOP
MAX188DC/D Dice*
MAX188_EPP Plastic DIP
MAX188_EWP 20 SO

TEMP. RANGE

0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C

-40°C to +85°C

-40°C to +85°C

PIN-PACKAGE

SHDN VREF REFADJ

SS



0.117"



(2.97 mm)

MAX186/MAX188

TRANSISTOR COUNT: 2278;
SUBSTRATE CONNECTED TO V

AGNDV

DD

MAX188_EAP -40°C to +85°C 20 SSOP
MAX188_MJP

-55°C to +125°C

PART BOARD TYPETEMP. RANGE

MAX186EVKIT-DIP Through-Hole

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

24

____________________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 [phone]

0°C to +70°C

20 CERDIP**

†

NOTE: Parts are offered in grades A, B, C and D (grades defined
in Electrical Characteristics). When ordering, please specify grade.
* Dice are specified at +25°C, DC parameters only.
* * Contact factory for availability and processing to MIL-STD-883.

© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.