Rainbow Electronics MAX1865 User Manual

General Description

The MAX1864/MAX1865 power-supply controllers are
designed to address cost-conscious applications such
as cable modem Consumer Premise Equipment (CPE),
xDSL CPE, and set-top boxes. Operating off a low-cost,
unregulated DC supply (such as a wall adapter output),
the MAX1864 generates three positive outputs, and the
MAX1865 generates four positive outputs and one neg­ative output to provide a cost-effective system power
supply.

The MAX1864 includes a current-mode synchronous
step-down controller and two positive regulator gain
blocks. The MAX1865 has one additional positive gain
block and one negative regulator gain block. The main
synchronous step-down controller generates a
high-current output that is preset to 3.3V or adjustable
from 1.236V to 0.8 ✕ VINwith an external resistive­divider. The 100kHz/200kHz operating frequency
allows the use of low-cost aluminum-electrolytic capaci­tors and low-cost power magnetics. Additionally, the
MAX1864/MAX1865 step-down controllers sense the
voltage across the low-side MOSFET’s on-resistance to
efficiently provide the current-limit signal, eliminating
the need for costly current-sense resistors.

The MAX1864/MAX1865 generate additional supply
rails at low cost. The positive regulator gain blocks use
an external PNP pass transistor to generate low-voltage
rails directly from the main step-down converter (such
as 2.5V or 1.8V from the main 3.3V output) or higher
voltages using coupled windings from the step-down
converter (such as 5V, 12V, or 15V). The MAX1865’s
negative gain block uses an external NPN pass transis­tor in conjunction with a coupled winding to generate

-5V, -12V, or -15V.

All output voltages are externally adjustable, providing
maximum flexibility. Additionally, the MAX1864/
MAX1865 feature soft-start for the step-down converter
and all the positive linear regulators, and have a power­good output that monitors all of the output voltages.

Applications

xDSL, Cable, and ISDN Modems

Set-Top Boxes

Wireless Local Loop

Features

♦ 4.5V to 28V Input Voltage Range

♦ Master DC-DC Step-Down Converter

Preset 3.3V or Adjustable (1.236V to 0.8 ✕ V

IN

)

Output Voltage

Fixed-Frequency (100kHz/200kHz) PWM
Controller

No Current-Sense Resistor

Adjustable Current Limit

95% Efficient

♦ Two (MAX1864)/Four (MAX1865) Analog

Gain Blocks

Positive Analog Blocks Drive Low-Cost PNP
Pass Transistors to Build Positive Linear
Regulators

Negative Analog Block (MAX1865) Drives a
Low-Cost NPN Pass Transistor to Build a
Negative Linear Regulator

♦ Power-Good Indicator

♦ Soft-Start Ramp for All Positive Regulators

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output

Power Supplies

________________________________________________________________ Maxim Integrated Products 1

Pin Configurations

Ordering Information

19-2030; Rev 0; 4/01

Pin Configurations continued at end of data sheet.

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART

MAX1864TEEE -40°C to +85°C 16 QSOP 200

MAX1864UEEE -40°C to +85°C 16 QSOP 100

MAX1865TEEP -40°C to +85°C 20 QSOP 200

MAX1865UEEP -40°C to +85°C 20 QSOP 100

TEMP.

RANGE

PIN­PACKAGE

TOP VIEW

1

POK IN

COMP

2

OUT

3

MAX1864

4

FB

B2

5

FB2

6

B3

7

FB3

8

16

15

VL

14

BST

13

DH

12

LX

DL

11

10

GND

9

ILIM

f

OSC

(kHz)

16 QSOP

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output
Power Supplies

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VIN= 12V, ILIM = FB = GND, V

BST

- VLX= 5V, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

IN, B2, B3, B4 to GND............................................-0.3V to +30V

B5 to OUT...............................................................-20V to +0.3V

VL, POK, FB, FB2, FB3, FB4, FB5 to GND ...............-0.3V to +6V

LX to BST..................................................................-6V to +0.3V

BST to GND ............................................................-0.3V to +36V

DH to LX....................................................-0.3V to (V

BST

+ 0.3V)

DL, OUT, COMP, ILIM to GND......................-0.3V to (V

L

+ 0.3V)

VL Output Current ...............................................................50mA

VL Short Circuit to GND...................................................≤100ms

Continuous Power Dissipation (T

A

= +70°C)

16-Pin QSOP (derate 8.3mW/°C above +70°C)...........666mW

20-Pin QSOP (derate 9.1mW/°C above +70°C)...........727mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

GENERAL

Operating Input Voltage Range
(Note 1)

V

IN

4.5 28 V

MAX1864 1.0 2

Quiescent Supply Current I

IN

VFB = 0, V

OUT

= 4V,

V

FB2

= V

FB3

= V

FB4

= 1.5V,

V

FB5

= -0.1V

MAX1865 1.4 3

mA

VL REGULATOR

Output Voltage VL 6V < VIN < 28V, 0.1mA < I

LOAD

< 20mA

V

Power-Supply Rejection PSRR VIN = 6V to 28V 3 %

Undervoltage Lockout Trip Level

VL rising, 3% hysteresis (typ) 3.2 3.5 3.8 V

Minimum Bypass Capacitance

)

10mΩ < ESR < 500mΩ 1µF

DC-DC CONTROLLER

Output Voltage (Preset Mode) V

OUT

FB = GND

V

Typical Output Voltage Range
(Adjustable Mode) (Note 2)

V

OUT

V

FB Set Voltage
(Adjustable Mode)

V

SET

FB = COMP

V

FB Dual Mode™ Threshold 50

mV

FB Input Leakage Current I

FB

VFB = 1.5V

nA

FB to COMP Transconductance g

m

FB = COMP, I

COMP

= ±5µA 70

µS

Current-Sense Amplifier Voltage
Gain

A

LIM

VIN - VLX = 250mV

4.9

V/V

Current-Limit Threshold
(Internal Mode)

V

ILIM

= 5.0V

mV

Current-Limit Threshold
(External Mode)

V

ILIM

= 2.5V

mV

Dual Mode is a trademark of Maxim Integrated Products, Inc.

V

UVLO

C

BYP(MIN

V

VALLEY

V

VALLEY

4.75 5.00 5.25

3.272 3.314 3.355

1.236 0.8 x V

1.221 1.236 1.252

100 150

0.01 100

100 140

4.46

190 250 310

440 530 620

IN

5.44

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output

Power Supplies

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VIN= 12V, ILIM = FB = GND, V

BST

- VLX= 5V, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Switching Frequency f

Maximum Duty Cycle D

Soft-Start Period t

Soft-Start Steps V

DH Output Low Voltage I

DH Output High Voltage I

DL Output Low Voltage I

DL Output High Voltage I

DH, DL On-Resistance 310Ω

Output Drive Current Sourcing or sinking, VDH or VDL = VL/2 0.5 A

LX, BST Leakage Current V

POSITIVE ANALOG GAIN BLOCKS

FB2, FB3, FB4 Regulation
Voltage

FB2, FB3, FB4 to B_
Transconductance

Feedback Input Leakage
Current

Driver Sink Current IB_

NEGATIVE ANALOG GAIN BLOCK

FB5 Regulation Voltage

FB5 to B5 Transconductance ∆V

Feedback Input Leakage
Current

Driver Source Current I

POWER GOOD (POK)

OUT Trip Level (Preset Mode) FB = GND, falling edge, 1% hysteresis (typ) 2.88 3 3.12 V

FB Trip Level (Adjustable Mode) Falling edge, 1% hysteresis (typ) 1.070 1.114 1.159 V

FB2, FB3, FB4 Trip Level Falling edge, 1% hysteresis (typ) 1.070 1.114 1.159 V

FB5 Trip Level Rising edge, 35mV hysteresis (typ) 368 500 632 mV

POK Output Low Level I

POK Output High Leakage V

THERMAL PROTECTION (Note 3)

Thermal Shutdown Rising temperature 160 °C
Thermal Shutdown Hysteresis 15 °C

OSC

SOFT

∆V

I

I

MAX

FB

FB5

B5

MAX186_T 160 200 240

MAX186_U 80 100 120

77 82 90 %

1024 1/f

/64 V

REF

= 10mA, measured from DH to LX 0.1 V

SINK

= 10mA, measured from BST to DH 0.1 V

SOURCE

= 10mA, measured from DL to GND 0.1 V

SINK

= 10mA, measured from DL to GND VL - 0.1 V

SOURCE

= VLX = VIN = 28V, VFB = 1.5V 0.03 20 µA

BST

VB2 = VB3 = VB4 = 5V,
I

= IB3 = IB4 = 1mA (sink)

B2

V

= VB3 = VB4 = 5V, IB2 = IB3 = IB4 =

B2

_

FB

0.5mA to 5mA (sink)

_V

FB2

V

FB2

V

FB4

V

B5

= V

FB3

= V

FB3

= 1.188V

= V

OUT

= V

FB4

=

- 2V, V

= 1.5V 0.01 100 nA

VB2 = VB3 = VB4 = 2.5V 10 23

V

= VB3 = VB4 = 4.0V 26

B2

= 3.5V, IB5 = 1mA

OUT

(source)

VB5 = 0, IB5 = 0.5mA to 5mA (source) -13 -20 mV

FB5

V

= -100mV 0.01 100 nA

FB5

V

= 200mV, VB5 = V

FB5

OUT

- 2.0V, V

OUT

3.5V

= 1mA 0.4 V

SINK

= 5V 1 µA

POK

1.226 1.240 1.257 V

-1 -1.75 %

-20 -5 +10 mV

=

10 25 mA

kHz

OSC

mA

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output
Power Supplies

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS

(VIN= 12V, ILIM = FB = GND, V

BST

- VLX= 5V, TA= -40°C to +85°C, unless otherwise noted.) (Note 4)

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

GENERAL

Operating Input Voltage Range
(Note 1)

Quiescent Supply Current I

VL REGULATOR

Output Voltage VL 6V < VIN < 28V, 0.1mA < I

Power-Supply Rejection PSRR VIN = 6V to 28V 3 %

Undervoltage Lockout Trip Level V

DC-DC CONTROLLER

Output Voltage (Preset Mode) V

Feedback Set Voltage
(Adjustable Mode)

Current-Sense Amplifier Voltage
Gain

Current-Limit Threshold
(Internal Mode)

Current-Limit Threshold
(External Mode)

Switching Frequency f

Maximum Duty Cycle D

POSITIVE ANALOG GAIN BLOCKS

FB2, FB3, FB4 Regulation
Voltage

V

IN

VFB = 0, V

IN

UVLO

OUT

V

SET

A

LIM

V

VALLEYVILIM

V

VALLEYVILIM

OSC

MAX

= V
V

VL rising, 3% hysteresis (typ) 3 4 V

FB = GND 3.247 3.380 V

FB = COMP 1.211 1.261 V

VIN - VLX = 250mV 4.12 5.68 V/V

MAX186_T 160 240

MAX186_U 80 120

VB2 = VB3 = VB4 = 5V, IB2 = IB3 = IB4 =
1mA (sink)

FB3

= -0.1V

FB5

= 5V 150 350 mV

= 2.5V 400 660 mV

= V

OUT

FB4

= 4V, V

= 1.5V,

FB2

MAX1864 2

MAX1865 3

<20mA 4.75 5.25 V

LOAD

4.5 28 V

74 90 %

1.215 1.265 V

mA

kHz

FB2, FB3, FB4 to B_
Transconductance

NEGATIVE ANALOG GAIN BLOCK

FB5 Regulation Voltage

FB5 to B5 Transconductance ∆V

∆V

FB

FB5

V

= VB3 = VB4 = 5V, IB2 = IB3 = IB4 =

B2

_

0.5mA to 5mA (sink)

V

= V

OUT

- 2V, V

B5

(source)

VB5 = 0, IB5 = 0.5mA to 5mA (source) -30 mV

= 3.5V, IB5 = 1mA

OUT

-25 +10 mV

-2.25 %

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output

Power Supplies

_______________________________________________________________________________________ 5

Note 1: Connect VL to IN for operation with VIN< 5V.
Note 2: See Output Voltage Selection section.
Note 3: The internal 5V linear regulator (VL) powers the thermal shutdown block. Shorting VL to GND disables thermal shutdown.
Note 4: Specifications to -40°C are guaranteed by design, not production tested.

ELECTRICAL CHARACTERISTICS (continued)

(VIN= 12V, ILIM = FB = GND, V

BST

- VLX= 5V, TA= -40°C to +85°C, unless otherwise noted.) (Note 4)

Typical Operating Characteristics

(Circuit of Figure 1, VIN= 12V, V

OUT

= 3.3V, TA = +25°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

POWER GOOD (POK)

OUT Trip Level (Preset Mode) FB = GND, falling edge, 1% hysteresis (typ) 2.85 3.15 V

FB Trip Level
(Adjustable Mode)

FB2, FB3, FB4 Trip Level Falling edge, 1% hysteresis (typ) 1.058 1.17 V

FB5 Trip Level Rising edge, 35mV hysteresis (typ) 325 675 mV

Falling edge, 1% hysteresis (typ) 1.058 1.17 V

EFFICIENCY vs. LOAD CURRENT

(PRESET MODE)

100

VIN = 6.5V

90

80

70

EFFICIENCY (%)

60

50

0.01 1010.1
LOAD CURRENT (A)

EFFICIENCY vs. LOAD CURRENT

(ADJUSTABLE MODE)

100

VIN = 6.5V

90

80

70

EFFICIENCY (%)

60

50

0.01 1010.1
LOAD CURRENT (A)

VIN = 8V

VIN = 12V

VIN = 18V

VIN = 24V

V

= 5.0V

OUT

VIN = 8V

VIN = 12V

VIN = 18V

VIN = 24V

OUTPUT VOLTAGE vs. LOAD CURRENT

(PRESET MODE)

3.33

3.32

MAX1864/65 toc01

3.31

3.30

3.29

OUTPUT VOLTAGE (V)

3.28

V

= 3.3V

OUT

3.27
0 1.0 1.50.5 2.0 2.5 3.0

LOAD CURRENT (A)

MAX1864/65 toc02

MAX1864/65 toc03

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output
Power Supplies

6 _______________________________________________________________________________________

E

Typical Operating Characteristics (continued)

(Circuit of Figure 1, VIN= 12V, V

OUT

= 3.3V, TA = +25°C, unless otherwise noted.)

4.95

4.97

4.99

5.01

5.03

5.05

01.00.5 1.5 2.0 2.5 3.0

OUPUT VOLTAGE vs. LOAD CURRENT

(ADJUSTABLE MODE)

MAX1864/65 toc04

LOAD CURRENT (mA)

OUTPUT VOLTAGE (V)

4.95

4.97

4.99

5.01

5.03

5.05

0105 15202530

INTERNAL 5V LINEAR REGULATOR

vs. LOAD CURRENT

MAX1864/65 toc05

LOAD CURRENT (mA)

VL (V)

1ms/div

LOAD TRANSIENT

(STEP-DOWN CONVERTER)

3.5V

3.1V

B

A

MAX1864/65 toc06

1A

0

3.3V

A. V

OUT

= 3.3V (PRESET), 200mV/div

B. I

OUT

= 10mA TO 1A, 500mA/div

V

IN

= 12V

SWITCHING WAVEFORMS

(STEP-DOWN CONVERTER)

3.35V

3.30V

1.5A

1A

0.5A

10V

0

A. V

= 3.3V (PRESET), I

OUT

B. INDUCTOR CURRENT, 500mA/div

, 10V/div

C. V

LX

= 12V

V

IN

2µs/div

OUT

MAX1864/65 toc07

= 1A, 50mV/div

SOFT-START

5V

A

B

C

0

4V

2V

0

1A

0

, 5V/div

A. V

L

= 3.3V (PRESET), 2V/div

B. V

OUT

C. INDUCTOR CURRENT, 1A/div

= 0 TO 12V

V

IN

1ms/div

MAX1864/65 toc08

A

B

C

DRIVE CURRENT vs. BASE-DRIVE VOLTAG

40

V

= 1.0V

35

30

25

20

15

10

BASE-DRIVE SINK CURRENT (mA)

5

0

0246810

FB_

V

= 0.96V

FB_

(MAX1865) ONLY

BASE VOLTAGE (V)

REF

B2, B3 AND B4

MAX1864/65 toc09

POSITIVE LINEAR REGULATOR BASE-

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output

Power Supplies

_______________________________________________________________________________________ 7

Typical Operating Characteristics (continued)

(Circuit of Figure 1, VIN= 12V, V

OUT

= 3.3V, TA = +25°C, unless otherwise noted.)

2.50

0.01 10.1 100

POSITIVE LINEAR REGULATOR

OUTPUT VOLTAGE vs. LOAD CURRENT

(Q

LDO

= 2N3905)

2.42

2.44

2.46

2.48

MAX18664/65 toc10

LOAD CURRENT (mA)

OUTPUT VOLTAGE (V)

10 1000

V

SUP(POS)

= 5.0V

V

SUP(POS)

= 3.3V

2.42

2.44

2.46

2.48

2.50

243 5678

POSITIVE LINEAR REGULATOR

OUTPUT VOLTAGE vs. SUPPLY VOLTAGE

(Q

LDO

= 2N3905)

MAX1864/65 toc11

SUPPLY VOLTAGE (V)

OUTPUT VOLTAGE (V)

I

OUT2

= 1mA

I

OUT2

= 100mA

80

70

60

50

40

30

20

10

0

0.1 10 1001 1000

POSITIVE LINEAR REGULATOR

POWER-SUPPLY REJECTION RATIO

(Q

LDO

= 2N3905)

MAX1864/65 toc12

FREQUENCY (kHz)

PSRR (dB)

I

OUT2

= 50mA

POSITIVE LINEAR REGULATOR

LOAD TRANSIENT

(Q

LDO

= 2W3905)

MAX1864/65 toc13

100mA

2.457V

2.467V

A. I

OUTZ

= 1mA TO 100mA, 50mA/div

B. V

OUTZ

= 2.5V, 5mV/div

C

LDO(POS)

= 10µF CERAMIC, V

SUP(POS)

= 3.3V

CIRCUIT OF FIGURE 1

0

B

A

10µs/div

2.50

0.01 0.1 1000100

POSITIVE LINEAR REGUALTOR

OUTPUT VOLTAGE vs. LOAD CURRENT

(Q

LDO

= TIP30)

2.42

2.44

2.46

2.48

MAX1864/65 toc14

LOAD CURRENT (mA)

OUTPUT VOLTAGE (V)

110

V

SUP(POS)

= 5.0V

V

SUP(POS)

= 3.3V

2.42

2.44

2.46

2.48

2.50

24681012

POSITIVE LINEAR REGULATOR

OUTPUT VOLTAGE vs. SUPPLY VOLTAGE

(Q

LDO

= TIP30)

MAX1864/65 toc15

SUPPLY VOLTAGE (V)

OUTPUT VOLTAGE (V)

I

OUT2

= 1mA

I

OUT2

= 100mA

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output
Power Supplies

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

(Circuit of Figure 1, VIN= 12V, V

OUT

= 3.3V, TA = +25°C, unless otherwise noted.)

-12.00

-12.06

-12.12

-12.18

-12.24

0.01 1

10

1000.1 1000

NEGATIVE LINEAR REGULATOR

OUTPUT VOLTAGE vs. LOAD CURRENT

(Q

LDO

= TIP29)

MAX1864/65 toc19

LOAD CURRENT (mA)

OUTPUT VOLTAGE (V)

V

SUP(NEG)

= -15V

V

OUT3

= 5V

-12.24

-12.18

-12.12

-12.06

-12.00

-20 -18 -16 -14 -12 -10

NEGATIVE LINEAR REGULATOR

OUTPUT VOLTAGE vs. SUPPLY VOLTAGE

(Q

LDO

= TIP29)

MAX1864/65 toc20

SUPPLY VOLTAGE (V)

OUTPUT VOLTAGE (V)

I

LDO(NEG)

= 100mA

I

LDO(NEG)

= 1mA

80

70

60

50

40

30

20

10

0

0.1 10 10011000

POSITIVE LINEAR REGULATOR

POWER-SUPPLY REJECTION RATIO

(Q

LDO

= TIP30)

MAX1864/65 toc16

FREQUENCY (kHz)

PSRR (dB)

I

OUT2

= 150mA

POSITIVE LINEAR REGULATOR

LOAD TRANSIENT

(Q

LDO

= TIP30)

MAX1864/65 toc17

250mA

2.453V

2.473V

A. I

OUT2

= 10mA TO 250mA, 200mA/div

B. V

OUT2

= 2.5V, 10mV/div

C

LDO(POS)

= 10µF CERAMIC, V

SUP(POS)

= 3.3V

CIRCUIT OF FIGURE 1

0

B

A

10µs

0

10

5

25

20

15

40

35

30

45

0426810

NEGATIVE LINEAR REGULATOR BASE-

DRIVE CURRENT vs. BASE-DRIVE VOLTAGE

MAX1864/65 toc18

V

OUT

- VB5 (V)

BASE-DRIVE SOURCE CURRENT (mA)

V

FB5

= 250mV

V

FB5

= 50mV

V

OUT

= 5.0V

V

OUT

= 3.3V

B5 (MAX1865) ONLY

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output

Power Supplies

_______________________________________________________________________________________ 9

Pin Description

PIN

MAX1864 MAX1865

1 1 POK

2 2 COMP

3 3 OUT

44FB

55B2

6 6 FB2

77B3

NAME FUNCTION

Open-Drain Power-Good Output. POK is low when the output voltage is more than
10% below the regulation point. POK is high impedance when the output is in
regulation. Connect a resistor between POK and VL for logic-level voltages.

Compensation Pin. Connect a series RC to GND to compensate the control loop.
Typical values are 47kΩ and 8.2nF.

Regulated Output Voltage High-Impedance Sense Input. Internally connected to a
resistive-divider and negative gain block (MAX1865).

Dual-Mode Switching-Regulator Feedback Input. Connect to GND for the preset 3.3V
output. Connect to a resistive-divider from output to FB to GND to adjust the output

✕ V

voltage between 1.236V and 0.8

Open-Drain Output PNP Transistor Driver (Regulator #2). Internally connected to the
drain of a DMOS. B2 connects to the base of an external PNP pass transistor to form a
positive linear regulator.

Analog Gain-Block Feedback Input (Regulator #2). Connect to a resistive-divider
between the positive linear regulator’s output and GND to adjust the output voltage.
The feedback set point is 1.24V.

Open-Drain Output PNP Transistor Driver (Regulator #3). Internally connected to the
drain of a DMOS. B3 connects to the base of an external PNP pass transistor to form a
positive linear regulator.

. The feedback set point is 1.236V.

IN

Analog Gain-Block Feedback Input (Regulator #3). Connect to a resistive-divider

8 8 FB3

— 9B4

— 10 FB4

— 11 B5

— 12 FB5

between the positive linear regulator’s output and GND to adjust the output voltage.
The feedback set point is 1.24V.

Open-Drain Output PNP Transistor Driver (Regulator #4). Internally connected to the
drain of a DMOS. B4 connects to the base of an external PNP pass transistor to form a
positive linear regulator.

Analog Gain-Block Feedback Input (Regulator #4). Connect to a resistive-divider
between the positive linear regulator’s output and GND to adjust the output voltage.
The feedback set point is 1.24V.

Open-Drain Output NPN Transistor Driver (Regulator #5). Internally connected to the
drain of a P-channel MOSFET. B5 connects to the base of an external NPN pass
transistor to form a negative linear regulator.

Analog Gain-Block Feedback Input (Regulator #5). Connect to a resistive-divider
between the negative linear regulator’s output and a positive reference voltage,
typically one of the positive linear regulator outputs, to adjust the output voltage. The
feedback set point is at GND.

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output
Power Supplies

10 ______________________________________________________________________________________

Detailed Description

The MAX1864/MAX1865 power-supply controllers pro­vide system power for cable and xDSL modems. The
main step-down DC-DC controller operates in a cur­rent-mode pulse-width-modulation (PWM) control
scheme to ease compensation requirements and pro­vide excellent load- and line-transient response.

The MAX1864 includes two analog gain blocks to regu­late two additional positive auxiliary output voltages,
and the MAX1865 includes four analog gain blocks to
regulate three additional positive and one negative aux­iliary output voltages. The positive regulator gain blocks
can be used to generate low-voltage rails directly from
the main step-down converter or higher voltages using
coupled windings from the step-down converter. The
negative gain block can be used in conjunction with a
coupled winding to generate -5V, -12V, or -15V.

DC-DC Controller

The MAX1864/MAX1865 step-down converters use a
pulse-width-modulated (PWM) current-mode control
scheme (Figure 2). An internal transconductance
amplifier establishes an integrated error voltage at the
COMP pin. The heart of the current-mode PWM con­troller is an open-loop comparator that compares the

integrated voltage-feedback signal against the ampli­fied current-sense signal plus the slope compensation
ramp. At each rising edge of the internal clock, the
high-side MOSFET turns-on until the PWM comparator
trips or the maximum duty cycle is reached. During this
on-time, current ramps up through the inductor, sourc­ing current to the output and storing energy in a mag­netic field. The current-mode feedback system
regulates the peak inductor current as a function of the
output voltage error signal. Since the average inductor
current is nearly the same as the peak inductor current
(assuming that the inductor value is relatively high to
minimize ripple current), the circuit acts as a switch­mode transconductance amplifier. It pushes the output
LC filter pole, normally found in a voltage-mode PWM,
to a higher frequency. To preserve inner loop stability
and eliminate inductor stair-casing, a slope-compensa­tion ramp is summed into the main PWM comparator.

During the second-half of the cycle, the high-side MOS­FET turns off and the low-side N-channel MOSFET turns
on. Now the inductor releases the stored energy as its
current ramps down, providing current to the output.
Therefore, the output capacitor stores charge when the
inductor current exceeds the load current and dis­charges when the inductor current is lower, smoothing

Pin Description (continued)

PIN

MAX1864 MAX1865

9 13 ILIM

10 14 GND Ground

11 15 DL Low-Side Gate-Driver Output. DL swings between GND and VL.

12 16 LX

13 17 DH High-Side Gate-Driver Output. DH swings between LX and BST.

14 18 BST

15 19 VL

NAME FUNCTION

Dual-Mode Current-Limit Adjustment Input. Connect to VL for the default 250mV
current-limit threshold. In adjustable mode, the current-limit threshold voltage is 1/5th
the voltage present at ILIM. Connect to a resistive-divider between VL and GND to
adjust V
default value is approximately VL - 1V.

Inductor Connection. Used for current sense between IN and LX, and used for current
limit between LX and GND.

Boost Flying Capacitor Connection. Connect BST to the external boost diode and
capacitor as shown in the standard application circuit (Figures 1 and 6).

Internal 5V Linear-Regulator Output. Supplies the IC and powers the DL low-side gate
driver and external boost diode and capacitor. Bypass with a 1µF or greater ceramic
capacitor to GND.

between 1V and 2.5V. The logic threshold for switchover to the 250mV

ILIM

16 20 IN

Input Supply Voltage, 4.5V to 28V. Bypass to GND with a 1µF or greater ceramic
capacitor close to the IC.

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output

Power Supplies

______________________________________________________________________________________ 11

the voltage across the load. Under overload conditions,
when the inductor current exceeds the selected cur­rent-limit (see Current Limit), the high-side MOSFET is
not turned on at the rising edge of the clock and the
low-side MOSFET remains on to let the inductor current
ramp down.

The MAX1864/MAX1865 operate in a forced-PWM
mode, so even under light loads the controller main­tains a constant switching frequency to minimize cross­regulation errors in applications that use a transformer.
The low-side gate-drive waveform is the complement of
the high-side gate-drive waveform, which causes the
inductor current to reverse under light loads.

Current-Sense Amplifier

The MAX1864/MAX1865s’ current-sense circuit ampli­fies (A

V

= 5) the current-sense voltage generated by

the high-side MOSFET’s on-resistance (R

DS(ON)

✕

I

INDUCTOR

). This amplified current-sense signal and
the internal slope compensation signal are summed
together (V

SUM

) and fed into the PWM comparator’s
inverting input. The PWM comparator turns-off the high­side MOSFET when V

SUM

exceeds the integrated feed-

back voltage (V

COMP)

. Place the high-side MOSFET no
further than 5mm from the controller, and connect IN
and LX to the MOSFET using Kelvin sense connections
to guarantee current-sense accuracy and improve
stability.

Figure 1. Standard MAX1864 Application Circuit

1µF

1µF

INPUT

D1
CENTRAL CMPSH-3

BST

OUT
GND

FB2

FB3

R

DH

10Ω

DH

C

BST

0.1µF

LX

R

DL

10Ω

DL

C

BE2

2200pF

R

BE2

R3

30kΩ

10kΩ

R1

10kΩ

R2

10kΩ

4700pF

R4

220Ω

C

BE3

R

BE3

220Ω

B2

B3

POK

COMP

IN

VL

ILIM

MAX1864

POK

FB

COMP

C1

C2

R

100kΩ

R

47kΩ

C

COMP

8.2nF

9V TO 18V

C

IN

470µF

N

H

T1

1

N

L

Q1

Q2

C7
10µF

C4
10µF

C3
10µF

C6
10µF

V

V

OUT3

OUT2

300mA

100mA

V

= 2.5V

= 5.0V

NL, NH: INTERNATIONAL RECTIFIER

Q1: TIP30
Q2: 2N3905

= 3.3V

OUT

1A

C

OUT

470µF

T1

D2
NIHON EP05Q03L

C5
470µF

IRF7303

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output
Power Supplies

12 ______________________________________________________________________________________

Figure 2. Functional Diagram

BIAS

MAX1864
MAX1865

OK

V

REF

COMP

OUT

FB

100mV

FB_

B_

0.9V

REF

FB1

SOFT­START

FB1

V

REF

1.236V

CLK

ENABLE

∑

VL LDO

5V

1.114V

3.5V

IN

VL

BST

DH

LX

DL

GND

THERMAL

SHDN

= 5

A

V

SLOPE
COMP

= 5

A

V

100kΩ

0.9V

REF

400kΩ

ILIM

✕

VL

B5*

FB5*

*MAX1865 ONLY

OUT

250mV

0.9

ENABLE

500mV

POK

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output

Power Supplies

______________________________________________________________________________________ 13

Current-Limit Circuit

The current-limit circuit employs a unique “valley” cur­rent-limiting algorithm that uses the low-side MOSFET’s
on-resistance as a sensing element (Figure 3). If the
voltage across the low-side MOSFET (R

DS(ON)

✕

I

IN-

DUCTOR

) exceeds the current-limit threshold at the
beginning of a new oscillator cycle, the MAX1864/
MAX1865 will not turn on the high-side MOSFET. The
actual peak current is greater than the current-limit
threshold by an amount equal to the inductor ripple
current. Therefore, the exact current-limit characteristic
and maximum load capability are a function of the low­side MOSFET on-resistance, inductor value, input volt­age, and output voltage. The reward for this uncertainty
is robust, loss-less overcurrent limiting.

In adjustable mode, the current-limit threshold voltage
is 1/5th the voltage seen at ILIM (I

VALLEY

= 0.2 ✕V

ILIM

).
Adjust the current-limit threshold by connecting a resis­tive-divider from VL to ILIM to GND. The current-limit
threshold can be set from 106mV to 530mV, which cor­responds to ILIM input voltages of 500mV to 2.5V. This
adjustable current limit accommodates MOSFETs with
a wide range of on-resistance characteristics (see
Design Procedure). The current-limit threshold defaults
to 250mV when ILIM is connected to VL. The logic
threshold for switchover to the 250mV default value is
approximately VL - 1V.

Carefully observe the PC board layout guidelines to
ensure that noise and DC errors don’t corrupt the cur­rent-sense signals seen by LX and GND. The IC must
be mounted close to the low-side MOSFET with short
(less than 5mm), direct traces making a Kelvin sense
connection.

Synchronous Rectifier Driver (DL)

Synchronous rectification reduces conduction losses in
the rectifier by replacing the normal Schottky catch
diode with a low-resistance MOSFET switch. The
MAX1864/MAX1865 also use the synchronous rectifier
to ensure proper startup of the boost gate-driver circuit
and to provide the current-limit signal.

The DL low-side drive waveform is always the comple­ment of the DH high-side drive waveform (with con­trolled dead time to prevent cross-conduction or
“shoot-through”). A dead-time circuit monitors the DL
output and prevents the high-side FET from turning on
until DL is fully off. For the dead-time circuit to work
properly, there must be a low-resistance, low-induc­tance path from the DL driver to the MOSFET gate.
Otherwise, the sense circuitry in the MAX1864/
MAX1865 will interpret the MOSFET gate as “off” when
gate charge actually remains. Use very short, wide

traces (50mil to 100mil wide if the MOSFET is 1 inch
from the device). The dead time at the other edge (DH
turning off) is determined by a fixed internal delay.

High-Side Gate-Drive Supply (BST)

Gate-drive voltage for the high-side N-channel switch is
generated by a flying-capacitor boost circuit (Figure 1).
The capacitor between BST and LX is alternately
charged from the VL supply and placed parallel to the
high-side MOSFET’s gate-source terminals.

On startup, the synchronous rectifier (low-side MOS­FET) forces LX to ground and charges the boost
capacitor to 5V. On the second half-cycle, the switch­mode power supply turns on the high-side MOSFET by
closing an internal switch between BST and DH. This
provides the necessary gate-to-source voltage to turn
on the high-side switch, an action that boosts the 5V
gate-drive signal above the battery voltage.

Internal 5V Linear Regulator (VL)

All MAX1864/MAX1865 functions, except the current­sense amplifier, are internally powered from the on­chip, low-dropout 5V regulator. The maximum regulator
input voltage (VIN) is 28V. Bypass the regulator’s output
(VL) with at least a 1µF ceramic capacitor to GND. The
VIN-to-VL dropout voltage is typically 200mV, so when
VINis less than 5.2V, VL is typically VIN- 200mV.

The internal linear regulator can source up to 20mA to
supply the IC, power the low-side gate driver, charge
the external boost capacitor, and supply small external
loads. When driving particularly large FETs, little or no
regulator current may be available for external loads.
For example, when switched at 200kHz, a large FET
with 40nC total gate charge requires 40nC x 200kHz,
or 8mA.

Figure 3. “Valley” Current-Limit Threshold Point

(VIN - V

INDUCTOR CURRENT

TIME

I

PEAK

= I

VALLEY

OUT

+

[

L

-I

PEAK

I

LOAD

I

VALLEY

)

V

OUT

()

]

VINf

OSC

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output
Power Supplies

14 ______________________________________________________________________________________

Undervoltage Lockout

If VL drops below 3.5V, the MAX1864/MAX1865
assume that the supply voltage is too low to make valid
decisions, so the undervoltage lockout (UVLO) circuitry
inhibits switching, forces POK low, and forces the DL
and DH gate drivers low. After VL rises above 3.5V,
internal digital soft-start is initiated (see Soft-Start).

Startup Sequence

Externally, the MAX1864/MAX1865 starts switching
when VL rises above the 3.5V undervoltage lockout
threshold. However, the controller is not enabled unless
all four of the following conditions are met: 1) VL
exceeds the 3.5V undervoltage lockout threshold, 2)
the internal reference exceeds 90% of its nominal value
(V

REF

> 1.114V), 3) the internal bias circuitry powers
up, and 4) the thermal limit is not exceeded. Once the
MAX1864/MAX1865 assert the internal enable signal,
the step-down controller starts switching and enables
soft-start.

Soft-Start

Upon power-up, the MAX1864/MAX1865 begin a start­up sequence. First, the reference powers up. Then, the
main DC-DC step-down converter and positive linear
regulators power up with soft-start enabled. Once the
regulators reach 90% of their nominal value and soft­start is complete, the active-high ready signal (POK)
goes high (see Power-Good Output).

Soft-start gradually ramps up to the reference voltage
in order to control the rate of rise of the output voltages
and reduce input surge currents during startup. The
soft-start period is 1024 clock cycles (1024/f

OSC

), and
the internal soft-start DAC ramps up the voltage in 64
steps. The output reaches regulation when soft-start is
completed, regardless of output capacitance and load.

Power-Good Output

The power-good output (POK) is an open-drain output.
The MOSFET turns on and pulls POK low when any out­put is less than 90% of its nominal regulation voltage or
during soft-start. Once all of the outputs exceed 90% of
their nominal regulation voltages and soft-start is com­pleted, POK goes high impedance. To obtain a logic
voltage output, connect a pullup resistor from POK to
VL. A 100kΩ resistor works well for most applications. If
unused, leave POK grounded or unconnected.

Thermal-Overload Protection

Thermal-overload protection limits total power dissipa­tion in the MAX1864/MAX1865. When the junction tem­perature exceeds TJ= +160°C, a thermal sensor shuts
down the device, forcing DL and DH low, allowing the
IC to cool. The thermal sensor turns the part on again
after the junction temperature cools by 10°C, resulting
in a pulsed output during continuous thermal-overload
conditions. If the VL output is short circuited, thermal­overload protection is disabled.

During a thermal event, the main step-down converter
and the linear regulators are turned off, POK goes low,
and soft-start is reset.

Design Procedure

DC-DC Step-Down Converter

Output Voltage Selection

The step-down controller’s feedback input features
dual-mode operation. Connect the output to OUT and
connect FB to GND for the preset 3.3V output voltage.
Alternatively, the MAX1864/MAX1865 output voltage
may be adjusted by connecting a voltage-divider from
the output to FB to GND (Figure 4). Select R2 in the
5kΩ to 50kΩ range. Calculate R1 with the following
equation:

where V

SET

= 1.236V, and V

OUT

may range from

1.236V to approximately 0.8 x VIN(up to 20V). If V

OUT

> 5.5V, then connect OUT to GND (MAX1864) or to one
of the positive linear regulators (MAX1865) with an out­put voltage between 2V and 5V.

Inductor Value

Three key inductor parameters must be specified:
inductance value (L), peak current (I

PEAK

), and DC
resistance (RDC). The following equation includes a
constant LIR, which is the ratio of inductor peak-to­peak AC current to DC load current. A higher LIR value
allows smaller inductance but results in higher losses
and higher output ripple. A good compromise between
size and losses is a 30% ripple-current to load-current
ratio (LIR = 0.3). The switching frequency, input volt­age, output voltage, selected LIR determine the induc­tor value as follows:





V

RR

12 1=

L

=

VI LIR

IN SW LOAD MAX

OUT





V





SET



VVV

()

OUT IN OUT

ƒ





-










-

()

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output

Power Supplies

______________________________________________________________________________________ 15

where fSWis 200kHz for MAX186_T and 100kHz for
MAX186_U. The exact inductor value is not critical and
can be adjusted to make trade-offs among size, cost,
and efficiency. Lower inductor values minimize size
and cost, but they also increase the output ripple and
reduce the efficiency due to higher peak currents. On
the other hand, higher inductor values increase effi­ciency, but at some point resistive losses due to extra
turns of wire will exceed the benefit gained from lower
AC current levels.

Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, though powdered iron
is inexpensive and can work well at 200kHz. The cho­sen inductor’s saturation rating must exceed the peak
inductor current:

Setting the Current Limit

The minimum current-limit threshold must be high
enough to support the maximum load current at the
minimum tolerance level of the current-limit circuit. The

valley of the inductor current occurs at I

LOAD(MAX)

minus half of the ripple current:

where R

DS(ON)

is the on-resistance of the low-side
MOSFET (NL). For the MAX1864/MAX1865, the mini­mum current-limit threshold is 190mV (for the typical
250mV default setting). Use the worst-case maximum
value for R

DS(ON

) from the MOSFET NLdata sheet, and

add some margin for the rise in R

DS(ON)

over tempera­ture. A good general rule is to allow 0.5% additional
resistance for each °C of the MOSFET junction temper­ature rise.

Connect ILIM to VL for the default 250mV (typ) current­limit threshold. For an adjustable threshold, connect a
resistive-divider from VL to ILIM to GND. The 500mV to

2.5V external adjustment range corresponds to a
106mV to 530mV current-limit threshold. When adjust­ing the current limit, use 1% tolerance resistors and a
10µA divider current to prevent a significant increase in
the current-limit tolerance.

Figure 4. Adjustable Output Voltage

* FOR OUTPUT VOLTAGES > 5V, SEE "OUTPUT VOLTAGE SELECTION."

INPUT

D1

MAX1864

IN

C1

C2

R

POK

R

COMP

C

COMP

MAX1865

VL

ILIM

POK

COMP

BST

DH

OUT
GND

C

BST

LX

DL

FB

4.5V TO 28V

C

IN

N

H

L

N

L

R1

R2

C

OUT

OUTPUT

1.25V TO 5V*

LIR



II

=+

PEAK LOAD MAX LOAD MAX

() ()



I









2

V

VALLEY LOW

R

()

DS ON

()

>

I

LOAD MAX LOAD MAX

() ()

LIR





-

I









2

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output
Power Supplies

16 ______________________________________________________________________________________

MOSFET Selection

The MAX1864/MAX1865s’ step-down controller drives
two external logic-level N-channel MOSFETs as the cir­cuit switch elements. The key selection parameters are:

• On-resistance (R

DS(ON)

)

• Maximum drain-to-source voltage (V

DS(MAX)

)

• Minimum threshold voltage (V

TH(MIN)

)

• Total gate charge (Qg)

• Reverse transfer capacitance (C

RSS

)

The high-side N-channel MOSFET must be a logic-level
type with guaranteed on-resistance specifications at
VGS≤ 4.5V. Select the high-side MOSFET’s R

DS(ON)

so

I

PEAK

x R

DS(ON)

≤ 225mV for the current-sense range.

For maximum efficiency, choose a high-side MOSFET
(NH) that has conduction losses equal to the switching
losses at the optimum input voltage. Check to ensure
that the conduction losses at minimum input voltage
don’t exceed the package thermal limits or violate the
overall thermal budget. Check to ensure that the con­duction losses plus switching losses at the maximum
input voltage don’t exceed package ratings or violate
the overall thermal budget.

The low-side MOSFET (NL) provides the current-limit
signal, so choose a MOSFET with an R

DS(ON)

large
enough to provide adequate circuit protection (see
Setting the Current-Limit):

Use the worst-case maximum value for R

DS(ON)

from
the MOSFET NLdata sheet, and add some margin for
the rise in R

DS(ON)

over temperature. A good general
rule is to allow 0.5% additional resistance for each °C of
the MOSFET junction temperature rise. Ensure that the
MAX1864/MAX1865 DL gate drivers can drive NL; in
other words, check that the dv/dt caused by NHturning
on does not pull up the NLgate due to drain-to-gate
capacitance, causing cross-conduction problems.

MOSFET package power dissipation often becomes a
dominant design factor. I2R power losses are the great­est heat contributor for both high-side and low-side
MOSFETs. I2R losses are distributed between NHand
NLaccording to duty factor as shown in the equations
below. Generally, switching losses affect only the high­side MOSFET since the low-side MOSFET is a zero-volt­age switched device when used in the buck topology.

Gate-charge losses are dissipated by the driver and do
not heat the MOSFET. Calculate the temperature rise
according to package thermal-resistance specifications

to ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature. The
worst-case dissipation for the high-side MOSFET (P

NH

)
occurs at both extremes of input voltage, and the
worst-case dissipation for the low-side MOSFET (PNL)
occurs at maximum input voltage.

where I

GATE

is the DH driver peak output current capa­bility (1A typ), and 20ns is the DH driver inherent
rise/fall-time. To reduce EMI caused by switching
noise, add a 0.1µF ceramic capacitor from the high­side switch drain to the low-side switch source, or add
resistors (47Ω max) in series with DL and DH to
increase the switches’ turn-on and turn-off times (Figure

5).

The minimum load current should exceed the high-side
MOSFET’s maximum leakage current over temperature
if fault conditions are expected.

Input Capacitor

The input filter capacitor reduces peak currents drawn
from the power source and reduces noise and voltage
ripple on the input caused by the circuit’s switching.
The input capacitor must meet the ripple current
requirement (I

RMS

) imposed by the switching currents

defined by the following equation:

For most applications, nontantalum capacitors (ceram­ic, aluminum, polymer, or OS-CON) are preferred due
to their robustness with high inrush currents typical of
systems with low-impedance battery inputs.
Additionally, two (or more) smaller value low-ESR
capacitors can be connected in parallel for lower cost.
Choose an input capacitor that exhibits less than
+10°C temperature rise at the RMS input current for
optimal circuit long-term reliability.

V

R

DS ON

()

=

VALLEY

I

VALLEY

V

Duty Cycle D

PVI

()

NH SWITCHING IN LOAD OSC

PIRD

() ()

NH CONDUCTION LOAD DS ON NH

PP

() ( )

NH TOTAL NH SWITCHING

P

NH CONDUCTION

PI R D

NL LOAD DS ON NL

:

=+

()

=

OUT

=

V

IN

=ƒ

=

2

()

2

1-

()



VC

IN RSS



I



GATE






II

=

RMS LOAD

VVV

OUT IN OUT

-

()

V

IN

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output

Power Supplies

______________________________________________________________________________________ 17

Output Capacitor

The key selection parameters for the output capacitor
are the actual capacitance value, the equivalent series
resistance (ESR), and voltage-rating requirements,
which affect the overall stability, output ripple voltage,
and transient response.

The output ripple has two components: variations in the
charge stored in the output capacitor, and the voltage
drop across the capacitor’s ESR caused by the current
into and out of the capacitor:

The output voltage ripple as a consequence of the ESR
and output capacitance is:

where I

P-P

is the peak-to-peak inductor current (see
Inductor Selection). These equations are suitable for
initial capacitor selection, but final values should be set
by testing a prototype or evaluation circuit. As a gener­al rule, a smaller ripple current results in less output rip­ple. Since the inductor ripple current is a factor of the
inductor value and input voltage, the output voltage rip­ple decreases with larger inductance but increases
with lower input voltages.

With low-cost aluminum electrolytic capacitors, the
ESR-induced ripple can be larger than that caused by
the current into and out of the capacitor. Consequently,
high-quality low-ESR aluminum-electrolytic, tantalum,
polymer, or ceramic filter capacitors are required to
minimize output ripple. Best results at reasonable cost
are typically achieved with an aluminum-electrolytic
capacitor in the 470µF range, in parallel with a 0.1µF
ceramic capacitor.

Since the MAX1864/MAX1865 use a current-mode con­trol scheme, the output capacitor forms a pole that
affects circuit stability (see Compensation Design).
Furthermore, the output capacitor’s ESR also forms a
zero.

The MAX1864/MAX1865s’ response to a load transient
depends on the selected output capacitor. After a load
transient, the output instantly changes by ESR

✕

∆I

LOAD

. Before the controller can respond, the output
will sag further, depending on the inductor and output
capacitor values.

After a short period of time (see Typical Operating
Characteristics), the controller responds by regulating
the output voltage back to its nominal state. For appli­cations that have strict transient requirements, low-ESR
high-capacitance electrolytic capacitors are recom­mended to minimize the transient voltage swing.

Do not exceed the capacitor’s voltage or ripple-current
ratings.

Compensation Design

The MAX1864/MAX1865 controllers use an internal
transconductance error amplifier whose output com­pensates the control loop. Connect a series resistor
and capacitor between COMP and GND to form a pole­zero pair. The external inductor, high-side MOSFET,
output capacitor, compensation resistor, and compen­sation capacitor determine the loop stability. The induc­tor and output capacitor are chosen based on
performance, size, and cost. Additionally, the compen­sation resistor and capacitor are selected to optimize
control-loop stability. The component values shown in
the standard application circuits (Figures 1 and 6) yield
stable operation over a broad range of input-to-output
voltages.

The controller uses a current-mode control scheme that
regulates the output voltage by forcing the required
current through the external inductor, so the
MAX1864/MAX1865 use the voltage across the high­side MOSFET’s R

DS(ON)

to sense the inductor current.
Using the current-sense amplifier’s output signal and
the amplified feedback voltage, the control loop deter­mines the peak inductor current by:

Figure 5. Reducing the Switching EMI

MAX1864
MAX1865

TO VL

BST

GND

R

GATE

(OPTIONAL)

DH

C

LX

DH

BST

R

GATE

(OPTIONAL)

N

H

L

N

L

VV V

RIPPLE RIPPLE ESR RIPPLE C

=+

() ()

V I ESR

RIPPLE ESR p p

V

RIPPLE C

I

=

pp

-

=

()

()



VVLV

IN OUTSWOUT



ƒ



=

-

2

C

OUT SW

-

I

pp






-

ƒ









V





IN

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output
Power Supplies

18 ______________________________________________________________________________________

where A

VCS

is the current-sense amplifier’s gain (4.9

typ), A

VEA

is the DC gain of the error amplifier (2000

typ), and V

OUT(NOMINAL)

is the output voltage set by
the feedback resistive-divider (internal or external).
Since the output voltage is a function of the load cur­rent and load resistance, the total DC loop gain
(A

V(DC)

) is approximately:

The compensation capacitor (C

COMP

) creates the dom­inant pole. Due to the current-mode control scheme,
the output capacitor also creates a pole in the system
that is a function of the load resistance. As the load
resistance increases, the frequency of the output
capacitor’s pole decreases. However, the DC loop gain
increases with larger load resistance, so the unity gain
bandwidth remains fixed. Additionally, the compensa­tion resistor and the output capacitor’s ESR both gener­ate zeros. Therefore, to achieve stable operation, use
the following procedure to properly compensate the
system:

1) First, select the desired crossover frequency. The

crossover frequency must be less than both 1/5th
the switching frequency and 1/3rd the zero frequen­cy set by the output capacitor’s ESR:

2) Next, determine the pole set by the output capacitor

and the load resistor:

3) Determine the compensation resistor required to set

the desired crossover frequency:

where the error amplifier’s transconductance (g

m

) is

100µS (see Electrical Characteristics).

4) Finally, select the compensation capacitor:

Boost-Supply Diode

A signal diode, such as the 1N4148, works well in most
applications. If the input voltage goes below 6V, use a
small 20mA Schottky diode for slightly improved effi­ciency and dropout characteristics. Do not use large
power diodes, such as the 1N5817 or 1N4001, since
high junction capacitance can charge up VL to exces­sive voltages.

Linear Regulator Controllers

Positive Output Voltage Selection

The MAX1864/MAX1865s’ positive linear regulator out­put voltages are set by connecting a voltage-divider
from the output to FB_ to GND (Figure 6). Select R4 in
the 5kΩ to 50kΩ range. Calculate R3 with the following
equation:

where VFB= 1.24V, and V

OUT

may range from 1.24V to

30V.

Negative Output Voltage Selection (MAX1865)

The MAX1865’s negative output voltage is set by con­necting a voltage-divider from the output to FB5 to a
positive voltage reference (Figure 6). Select R6 in the
5kΩ to 50kΩ range. Calculate R5 with the following
equation:

where V

REF

is the positive reference voltage used, and

V

OUT

may be set between 0 and -20V.

If the negative regulator is used, the OUT pin must be
connected to a voltage supply between 2V and 5V that
can source at least 25mA. Typically, the OUT pin is
connected to the step-down converter’s output.
However, if the step-down converter’s output voltage is
set higher than 5V, OUT may be connected to one of
the positive linear regulators with an output voltage
between 2V and 5V.

VVA

I

=

PEAK

VRA

OUT REF VEA

OUT NOMINAL DS ON VCS

()()

I

A

VDC

()

PEAK

≈≈

I

LOAD

≈

VR A

REF LOAD VEA

VRA

OUT NOMINAL DS ON VCS

()()

VR

×400

REF LOAD

VR

OUT NOMINAL DS ON()()

IJ

c

1

CR

65π

OUT ESR

and

ƒ

SW

ƒ= =

POLE OUT

()

1

CR

22ππ

OUT LOAD

I

LOAD MAX

()

CV

OUT OUT

׃

R

COMP

=

2000

gA

m V DC POLE OUT

() ( )

c

ƒ

C

COMP

≤

R

2π

1

ƒ

COMP POLE OUT

()

RR

34 1=













V

OUT

V





-








FB







V

RR

56=

OUT





V





REF

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output

Power Supplies

______________________________________________________________________________________ 19

Figure 6. Standard MAX1865 Application Circuit

C

BE5

2200pF

C12

10µF

V

OUT5

-12V AT 50mA

R

BE5

220Ω

TO LOGIC

Q4

TIP29

1µF

1µF

C1

C2

100kΩ

C

COMP

8.2nF

C15
10nF

R10

470Ω

R

POK

R

COMP

47kΩ

C13
10µF

R8

120kΩ

CENTRAL CMPSH-3

IN

VL

ILIM

POK

FB

COMP

MAX1865

B5

FB5

R7

50kΩ

INPUT

FAIRCHILD
FDS6912A

T1

1

C4
10µF

C6
10µF

C7
10µF

C

BE4

2200pF

R

BE4

220Ω

R5

30kΩ

R6

10kΩ

9V TO 18V

C

IN

470µF

C3
10µF

V

OUT2

2.5V AT 500mA

V

OUT3

5.0V AT 100mA

Q3
TIP30

D2

NIHON

EP05Q03L

C5
470µF

C10
10µF

C

OUT

470µF

C9
10µF

1

V

OUT1

3.3V AT 1A

T1

NIHON

EP05Q03L

C8
470µF

V

OUT3

12V AT 100mA

T1

2

D3

R

SNUB

300Ω

C

SNUB

100pF

D1

BST

R

NH

DH

LX

DL

OUT
GND

B2

FB2

B3

FB3

B4

FB4

CONNECT
TO V

OUT3

R

10Ω

10Ω

C

BST

0.1µF

NL

10kΩ

R3

30kΩ

10kΩ

470Ω

10kΩ

4700pF

R4

C14

10nF

2200pF

R1

R2

C

BE3

R

BE3

220Ω

R9

C

BE2

R
220Ω

N

H

N

L

BE2

Q1
TIP30

Q2
2N3905

T1

C11
470µF

NIHON

EC10QS10

4

D4

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output
Power Supplies

20 ______________________________________________________________________________________

Transistor Selection

The pass transistors must meet specifications for cur­rent gain (hFE), input capacitance, collector-emitter sat­uration voltage, and power dissipation. The transistor’s
current gain limits the guaranteed maximum output cur­rent to:

where I

DRV

is the minimum base-drive current, and R

BE

(220Ω) is the pullup resistor connected between the
transistor’s base and emitter. Furthermore, the transis­tor’s current gain increases the linear regulator’s DC
loop gain (see Stability Requirements), so excessive
gain will destabilize the output. Therefore, transistors
with current gain over 100 at the maximum output cur­rent, such as Darlington transistors, are not recom­mended. The transistor’s input capacitance and input
resistance also create a second pole, which could be
low enough to destabilize the output when heavily
loaded.

The transistor’s saturation voltage at the maximum out­put current determines the minimum input-to-output
voltage differential that the linear regulator will support.
Alternatively, the package’s power dissipation could
limit the useable maximum input-to-output voltage dif­ferential. The maximum power dissipation capability of
the transistor’s package and mounting must exceed the
actual power dissipation in the device. The power dissi­pated equals the maximum load current times the maxi­mum input-to-output voltage differential:

Stability Requirements

The MAX1864/MAX1865 linear regulators use an inter­nal transconductance amplifier to drive an external
pass transistor. The transconductance amplifier, pass
transistor’s specifications, the base-emitter resistor,
and the output capacitor determine the loop stability. If
the output capacitor and pass transistor are not proper­ly selected, the linear regulator will be unstable.

The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base cur­rent. Since the output voltage is a function of the load
current and load resistance, the total DC loop gain
(A

V (LDO)

) is approximately:

where V

T

is 26mV, and I

BIAS

is the current through the

base-to-emitter resistor (R

BE

). This bias resistor is typical-

ly 220Ω, providing approximately 3.2mA of bias current.

The output capacitor creates the dominant pole.
However, the pass transistor’s input capacitance creates
a second pole in the system. Additionally, the output
capacitor’s ESR generates a zero, which may be used to
cancel the second pole if necessary. Therefore, to
achieve stable operation, use the following equations to
verify that the linear regulator is properly compensated:

1) First, determine the dominant pole set by the linear
regulator’s output capacitor and the load resistor:

2) Next, determine the second pole set by the base-to­emitter capacitance (including the transistor’s input
capacitance), the transistor’s input resistance, and
the base-to-emitter pullup resistor:

3) A third pole is set by the linear regulator’s feedback
resistance and the capacitance between FB_ and
GND, including 20pF stray capacitance:

4) If the second and third poles occur well after unity­gain crossover, the linear regulator will remain stable:

However, if the ESR zero occurs before unity-gain
crossover, cancel the zero with ƒ

POLE(FB)

by changing

circuit components such that:

II

LOAD MAX DRV

PI V V I V

=

LOAD MAX LDOIN OUT LOAD MAX CE

() ()



=

()

-






-







V

BE

h



BE

FE MIN() ()








=



R











.

55

A

V LDO

ƒ= =

POLE CLDO

()

Unity GainCrossover A

ƒ=

POLE CBE

ƒ>ƒ

≈



V



T

CR

22ππ

LDO LOAD

()

ƒ=

POLE FB

POLE CBE POLE CLDO V LDO

22π

RI Vh

BE LOAD T FE

=

()

() ( )()

2

Ih

BIAS FE

+

1









=ƒ

CR R

π

I





LOAD



1

V LDO POLE CLDO

() ( )

1

()

BE BE IN NPN

+

CRVh

BE BE T FE

1

FB

CRR

(|| )

212π

I

||

A





V



REF()








LOAD MAX

()

CV

LDO LDO

()

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output

Power Supplies

______________________________________________________________________________________ 21

Do not use output capacitors with more than 200mΩ of
ESR. Typically, more output capacitance provides the
best solution, since this also reduces the output voltage
drop immediately after a load transient.

Linear Regulator Output Capacitors

Connect at least a 1µF capacitor between the linear
regulator’s output and ground, as close to the
MAX1864/MAX1865 and external pass transistors as
possible. Depending on the selected pass transistor,
larger capacitor values may be required for stability
(see Stability Requirements). Furthermore, the output
capacitor’s ESR affects stability, providing a zero that
may be necessary to cancel the second pole. Use out­put capacitors with an ESR less than 200mΩ to ensure
stability and optimum transient response.

Once the minimum capacitor value for stability is deter­mined, verify that the linear regulator’s output does not
contain excessive noise. Although adequate for stabili­ty, small capacitor values may provide too much band­width, making the linear regulator sensitive to noise.
Larger capacitor values reduce the bandwidth, thereby
reducing the regulator’s noise sensitivity.

If noise on the ground reference causes the design to
be marginally stable for the negative linear regulator,
bypass the negative output back to its reference volt­age (V

REF

, Figure 7). This technique reduces the differ-

ential noise on the output.

Base-Drive Noise Reduction

The high-impedance base driver is susceptible to sys­tem noise, especially when the linear regulator is lightly
loaded. Capacitively coupled switching noise or induc­tively coupled EMI onto the base drive causes fluctua­tions in the base current, which appear as noise on the
linear regulator’s output. Keep the base-drive traces
away from the step-down converter and as short as
possible to minimize noise coupling. Resistors in series
with the gate drivers (DH and DL) reduce the LX
switching noise generated by the step-down converter
(Figure 5). Additionally, a bypass capacitor may be
placed across the base-to-emitter resistor (Figure 7).
This bypass capacitor, in addition to the transistor’s
input capacitance, could bring in a second pole that
will destabilize the linear regulator (see Stability
Requirements). Therefore, the stability requirements
determine the maximum base-to-emitter capacitance:

where C

IN(Q)

is the transistor’s input capacitance, and

f

POLE(CBE)

is the second pole required for stability.

Transformer Selection

In systems where the step-down controller’s output is
not the highest voltage, a transformer may be used to
provide additional postregulated, high-voltage outputs.
The transformer generates unregulated, high-voltage
supplies that power the positive and negative linear
regulators. These unregulated supply voltages must be
high enough to keep the pass transistors from saturat­ing. For positive output voltages, connect the trans­former as shown in figure 6 where the minimum turns
ratio (N) is determined by:

where V

SAT

is the pass transistor’s saturation voltage

under full load. For negative output voltages (MAX1865

Figure 7. Base-Drive Noise Reduction

ƒ≈

POLE FB

()

1

2π

CR

OUT ESR

V

SUP

C

C

B_

FB_

BF5

B5

1

()

BE

R1

R2

R4

R3

C

BE



RI Vh

BE LOAD T FE




MAX1864
MAX1865

a) POSITIVE OUTPUT VOLTAGE

MAX1865

b) NEGATIVE OUTPUT VOLTAGE (MAX1865 ONLY)

C

≤

BE

ƒ

2π

POLE CBE

R

BE

Q

C

LDO

V

REF

Q

R

BE

+

RVh

BE T FE

PASS

PASS

BYP

V

POS

V

NEG

C

NEG

V

SUP

C

BYP



C

-

IN Q

()




VVV



N

POS

LDO POS SAT DIODE

≥




++

()

V

OUT

-1






MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output
Power Supplies

22 ______________________________________________________________________________________

only), connect the transformer as shown in Figure 6,
where the minimum turns ratio is determined by:

Since power transfer occurs when the low-side MOS­FET is on (DL = high), the transformer cannot support
heavy loads with high duty cycles.

Snubber Design

The MAX1864/MAX1865 use a current-mode control
scheme that senses the current across the high-side
MOSFET (NH). Immediately after the high-side MOSFET
has turned on, the MAX1864/MAX1865 use a 60ns cur­rent-sense blanking period to minimize noise sensitivity.
When the MOSFET turns on, however, the transformer’s
secondary inductance and the diode’s parasitic capac­itance form a resonant circuit that causes ringing.
Reflected back through the transformer to the primary
side, these oscillations across the high-side MOSFET
may last longer than the blanking period. A series RC
snubber circuit at the diode (Figure 6) increases the
damping factor, allowing the ringing to settle quickly.
Applications with multiple transformer windings require
only one snubber circuit on the highest output voltage.
Applications with low turn ratios (1:1), such as the
MAX1864 typical application circuit (Figure 1), may not
require a snubber curcuit.

The diode’s parasitic capacitance can be estimated
using the diode’s reverse voltage rating (V

RRM

), current
capability (IO), and recovery time (TRR). A rough
approximation is:

For the EC10QS10 Nihon diode used in figure 6, the
capacitance is roughly 15pF. The output snubber must
only dampen the ringing, so the initial turn-on spike that
occurs during the blanking period remains preset. A
100pF capacitor works well in most applications; larger
capacitance values require more charge, thereby
increasing the power dissipation.

The snubber’s time constant (t

SNUB

) must be smaller
than the 100ns blanking time. A typical RC time con­stant of approximately 30ns was chosen for Figure 6:

Minimum Load Requirements (Linear Regulators)

Under no-load conditions, leakage currents from the
pass transistors supply the output capacitor, even
when the transistor is off. Generally, this is not a prob­lem since the feedback resistors’ current drains the
excess charge. However, charge may build up on the
output capacitor over temperature, making V

LDO

rise
above its set point. Care must be taken to ensure that
the feedback resistors’ current exceeds the pass tran­sistor’s leakage current over the entire temperature
range.

Applications Information

PC Board Layout Guidelines

Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention.
Follow these guidelines for good PC board layout:

1) Place the power components first, with ground ter-

minals adjacent (NLsource, CIN, C

OUT

). If possible,
make all these connections on the top layer with
wide, copper-filled areas. Keep these high-current
paths short, especially at ground terminals.

2) Mount the MAX1864/MAX1865 adjacent to the
switching MOSFETs to keep IN-LX current-sense
lines, LX-GND current-limit sense lines, and the dri­ver lines (DL and DH) short and wide. The current­sense amplifier inputs are connected between IN
and LX, so these pins must be connected as close
as possible to the high-side MOSFET. The current­limit comparator inputs are connected between LX
and GND, but accuracy is not as important, so give
priority to the high-side MOSFET connections. The
IN, LX, and GND connections to the MOSFETs must
be made using Kelvin sense connections to guaran­tee current-sense and current-limit accuracy.

3) Group the gate-drive components (BST diode and
capacitor, IN bypass capacitor) together near the
MAX1864/MAX1865.

4) All analog grounding must be done to a separate
solid copper ground plane, which connects to the
MAX1864/MAX1865 at the GND pin. This includes
the VL bypass capacitor, feedback resistors, com­pensation components (R

COMP

, C

COMP

), and
adjustable current-limit threshold resistors connect­ed to ILIM.







VVV

||

N

NEG

R

SNUB

LDO NEG SAT DIODE

≥




C

DIODE

t

SNUB

==

C

SNUB SNUB

++

()

V

It

×

ORR

=

V

RRM

C

OUT

ns

30






5) Ensure all feedback connections are short and
direct. Place the feedback resistors as close to the
MAX1864/MAX1865 as possible.

6) When trade-offs in trace lengths must be made, it’s
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and low-side
MOSFET or between the inductor and output filter
capacitor.

7) Route high-speed switching nodes away from sensi­tive analog areas (B_, FB_, COMP, ILIM).

Regulating High Voltage

The linear regulator controllers can be configured to
regulate high output voltages by adding a cascode
transistor to buffer the base-drive output. For example,
to generate an output voltage between 30V and 60V,
add a 2N5550 high-voltage NPN transistor as shown in
Figure 8a where V

BIAS

is a DC voltage between 3V and

20V that can source at least 1mA. R

DROP

protects the
cascode transistor by decreasing the voltage across
the transistor when the pass transistor saturates.
Similarly, to regulate a negative output voltage between

-20V and -120V, add a 2N5401 high-voltage PNP tran­sistor as shown in Figure 8b.

Chip Information

TRANSISTOR COUNT: 1617

PROCESS: BiCMOS

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output

Power Supplies

______________________________________________________________________________________ 23

Pin Configurations (continued)

TOP VIEW

1

POK

2

COMP

3

OUT

4

5

B2

6

FB2

7

B3

8

9

B4

10

20 QSOP

20

IN

19

VL

18

BST

17

DHFB

MAX1865

16

LX

15

DL

14

GND

13

ILIMFB3

12

FB5

11

B5FB4

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output
Power Supplies

24 ______________________________________________________________________________________

Table 1. Component Suppliers

Figure 8. High-Voltage Linear Regulation

V

V

BIAS

C

DROP

MAX1864
MAX1865

a) POSITIVE OUTPUT VOLTAGE WITH CASCODED BASE DRIVE

FB_

B_

Q

CASCODE

R1

R2

R

DROP

R

BE

Q

PASS

C

POS

SUP

C

BYP

V

POS

MAX1865

b) NEGATIVE OUTPUT VOLTAGE (MAX1865 ONLY)

WITH CASCODED BASE DRIVE

FB5

R4

R3

Q

CASCODE

B5

V

REF

V

R

DROP

C

DROP

Q

PASS

R

BE

NEG

C

NEG

V

SUP

C

BYP

SUPPLIER PHONE FAX INTERNET

INDUCTORS AND TRANSFORMERS

Coilcraft 847-639-6400 847-639-1469 http://www.coilcraft.com

Coiltronics 561-241-7876 561-241-9339 http://www.coiltronics.com

Sumida USA 847-956-0666 847-956-0702 http://www.sumida.com

Toko 847-297-0070 847-699-1194 http://www.toko.co.jp

CAPACITORS

AVX 803-946-0690 803-626-3123 http://www.avxcorp.com

Kemet 408-986-0424 408-986-1442 http://www.kemet.com

Panasonic 847-468-5624 847-468-5815 http://www.panasonic.com

Sanyo 619-661-6835 619-661-1055 http://www.sanyo.com

Taiyo Yuden 408-573-4150 408-573-4159 http://www.t-yuden.com

DIODES

Central Semiconductor 516-435-1110 516-435-1824 http://www.centralsemi.com

International

Nihon 847-843-7500 847-843-2798 http://www.niec.co.jp

On Semiconductor 602-303-5454 602-994-6430 http://www.onsemi.com

Zetex 516-543-7100 516-864-7630 http://www.zetex.com

310-322-3331 310-322-3332 http://www.irf.com

MAX1864/MAX1865

xDSL/Cable Modem Triple/Quintuple Output

Power Supplies

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25

© 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Package Information

QSOP.EPS