The MAX1813 step-down controller is intended for core
CPU DC-DC converters in notebook computers. The
controller features a dynamically adjustable output (5bit DAC), ultra-fast transient response, high DC accuracy, and high efficiency necessary for leading-edge
CPU core power supplies. Maxim’s proprietary QuickPWM™ quick-response, constant-on-time PWM control
scheme handles wide input/output voltage ratios with
ease and provides 100ns “instant-on” response to load
transients while maintaining a relatively constant switching frequency.
The MAX1813 is designed specifically for CPU core
applications requiring a voltage-positioned supply. The
voltage-positioning input (VPCS), combined with a
high-DC-accuracy control loop, is used to implement a
power supply that modifies its output set point in
response to the load current. This arrangement
decreases full-load power dissipation and reduces the
required number of output capacitors.
The output voltage can be dynamically adjusted
through the 5-bit digital-to-analog converter (DAC)
inputs over a 0.600V to 2V range. The MAX1813
includes an internal multiplexer that selects between
three different DAC code settings. The first two inputs
are controlled by five digital input pins (D0–D4). The
third input is used for the suspend mode and controlled
by two 4-level input pins (S0, S1). Output voltage transitions are accomplished with a proprietary precision
slew-rate control that minimizes surge currents to and
from the battery while guaranteeing “just-in-time” arrival
at the new DAC setting.
The MAX1813’s 28V input range enables single-stage
buck conversion from high-voltage batteries for the
maximum possible efficiency. Alternatively, the controller’s high-frequency capability combined with twostage conversion (stepping down the +5V system
supply instead of the battery) allows the smallest possible physical size.
The MAX1813 is available in a 28-pin QSOP package.
Applications
Notebook Computers
(Intel IMVP–II™/Coppermine™)
Docking Stations
CPU Core Supply
Single-Stage (BATT to V
CORE
) Converters
Two-Stage (+5V to V
CORE
) Converters
Features
♦ High-Efficiency Voltage Positioning
♦ Quick-PWM Architecture
♦ ±1% V
OUT
Accuracy Over Line
♦ Adjustable Output Slew Rate
♦ 0.600V to 2V Adjustable Output Range (5-Bit DAC)
= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: SKP/SDN may be forced to 12V, temporarily exceeding the absolute maximum rating, for the purpose of debugging proto-
type breadboards, using the no-fault test mode.
V+ to GND ..............................................................-0.3V to +30V
V
CC
, VDDto GND .....................................................-0.3V to +6V
PGND to GND.....................................................................±0.3V
D0–D4, CODE, ZMODE, SUS, PGOOD to GND ......-0.3V to +6V
SKP/SDN to GND (Note 1) .....................................-0.3V to +16V
ILIM, FB, CC, REF,
TON, TIME, S0, S1 to GND......................-0.3V to (V
CC
+ 0.3V)
VPCS to GND ............................................................-2V to +30V
DL to PGND................................................-0.3V to (VDD+ 0.3V)
BST to PGND..........................................................-0.3V to +36V
DH to LX....................................................-0.3V to (V
BST
+ 0.3V)
LX to BST..................................................................-6V to +0.3V
REF Short Circuit to GND ...........................................Continuous
Note 2: Output voltage accuracy specifications apply to DAC voltages from 0.6V to 2.0V.
Note 3: When the inductor is in continuous conduction, the output voltage will have a DC regulation level higher than the error-com-
parator threshold by 50% of the ripple. In discontinuous conduction (SKP/SDN = V
CC
, light load), the output voltage will
have a DC regulation level higher than the trip level by approximately 1.5% due to slope compensation.
Note 4: On-time and off-time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0, BST forced to 5V,
and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be different due to MOSFET switching speeds.
Note 5: Specifications to -40°C are guaranteed by design, not production tested.
5FBFeed b ack Inp ut. C onnect FB to the j uncti on of the exter nal i nd uctor and outp ut cap aci tor ( Fi g ur e 1) .
6CC
7, 8S0, S1
9V
10TON
CC
Battery Voltage Sense Connection. Connect V+ to the input power source. V+ is used only for PWM
one-shot timing. DH on-time is inversely proportional to the input voltage over a 2V to 28V range.
Current-Sense Input. Connect a current-sense resistor (R
voltage on VPCS controls both the voltage-positioning and current-limit circuits. The slope of the
voltage-positioned output is controlled with the current-sense resistor and the gain resistor connected
between CC and REF. See Setting Voltage Positioning. The current-limit threshold is set by ILIM. If the
current-sense signal (inductor current × R
will not initiate a new cycle. VPCS can also be connected to LX to reduce component count, but CC
must be connected to REF to disable the voltage positioning.
Combined Shutdown and Skip-Mode Control. Drive SKP/SDN to GND for shutdown, leave SKP/SDN
open for low-noise forced-PWM mode, or drive to V
Shutdown mode: SKP/SDN = GND
Low-noise forced-PWM mode: SKP/SDN = open
Normal pulse-skipping operation: SKP/SDN = V
Low-noise forced PWM mode causes inductor current recirculation at light loads and suppresses
pulse-skipping operation. Forcing SKP/SDN with 12V to 15V clears the fault latch and disables
undervoltage protection, overvoltage protection, and thermal shutdown with otherwise normal pulseskipping operation. Exiting shutdown clears the fault latch.
Do not connect SKP/SDN to voltages over 15V.
Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A
470kΩ to 47kΩ resistor sets the clock from 38kHz to 380kHz, respectively:
= 150kHz x 120kΩ / R
f
SLEW
Compensation Capacitor and Voltage-Positioning Gain Adjustment. Connect a 47pF to 1000pF (47pF
typ) capacitor from CC to GND to adjust the loop’s response time. Connect a resistor (R
CC to REF to set the gain of the voltage positioning amplifier.
VV
OUTOUT PROG
where the voltage-positioning amplifer’s transconductance (G
Suspend-Mode Voltage Select Inputs. S0 and S1 are 4-level logic inputs that select the suspendmode VID code for for the suspend-mode multiplexer inputs. If SUS is high, the suspend-mode VID
code is delivered to the DAC. See Suspend-Mode Internal Mux.
Analog Supply Voltage Input for PWM Core. Connect VCC to the system supply voltage (4.5V to 5.5V)
through a series 20Ω resistor. Bypass to GND with a 0.22µF or greater capacitor as close to the
MAX1813 as possible.
On-Time Selection-Control Input. This is a 4-level input used to determine DH on-time. Connect to
GND, REF, or V
1000kHz, REF = 600kHz, floating = 300kHz, and V
, or leave TON unconnected to set the following switching frequencies: GND =
CC
.
TIME
=+
()
) exceeds the current-limit threshold, the MAX1813
SENSE
for normal pulse-skipping operation:
CC
CC
GRV
m AVPS VPCS
1
= 200kHz.
CC
) between VPCS and PGND. The
SENSE
V
REF
m
) is typically 20µS.
AVPS
) from
Loading...
+ 26 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.