Rainbow Electronics MAX17480 User Manual

General Description

The MAX17480 is a triple-output, step-down, fixedfrequency controller for AMD’s serial VID interface (SVI) CPU and northbridge (NB) core supplies. The MAX17480 consists of two high-current SMPSs for the CPU cores and one 4A internal switch SMPS for the NB core. The two CPU core SMPSs run 180° out-of-phase for true interleaved operation, minimizing input capacitance. The 4A internal switch SMPS runs at twice the switching frequency of the core SMPS, reducing the size of the external components.

The MAX17480 is fully AMD SVI compliant. Output voltages are dynamically changed through a 2-wire SVI, allowing the SMPSs to be individually programmed to different voltages. A slew-rate controller allows controlled transitions between VID codes and controlled soft-start. SVI also allows each SMPS to be individually set into a low-power pulse-skipping state.

Transient phase repeat improves the response of the fixed-frequency architecture, reducing the total output capacitance for the CPU core. A thermistor-based temperature sensor provides a programmable thermal-fault output (VRHOT).

The MAX17480 includes output overvoltage protection (OVP), undervoltage protection (UVP), and thermal protection. When any of these protection features detect a fault, the controller shuts down. True differential current sensing improves current limit and load-line accuracy. The MAX17480 has an adjustable switching frequency, allowing 100kHz to 600kHz operation per core SMPS, and twice that for the NB SMPS.

Applications

Mobile AMD SVI Core Supplies

Multiphase CPU Core Supplies

Voltage-Positioned, Step-Down Converters

Notebook/Desktop Computers

Features

o Dual-Output Fixed-Frequency Core Supply

Controller

Split or Combinable Outputs Detected at Power-Up

Dynamic Phase Selection Optimizes Active/Sleep Efficiency

Transient Phase Repeat Reduces Output Capacitance

True Out-of-Phase Operation Reduces Input Capacitance

Programmable AC and DC Droop Accurate Current Balance and Current Limit Integrated Drivers for Large Synchronous-

Rectifier MOSFETs Programmable 100kHz to 600kHz Switching

Frequency 4V to 26V Battery Input Voltage Range

o 4A Internal Switch Northbridge SMPS

2.7V to 5.5V Input Voltage Range 2x Programmable Switching Frequency 75mΩ/40mΩ Power Switches

o ±0.5% V

OUT

Accuracy over Line, Load, and

Temperature

o AMD SVI-Compliant Serial Interface with

Switchable Address

o 7-Bit On-Board DAC: 0 to +1.550V Output Adjust

Range

o Integrated Boost Switches o Adjustable Slew-Rate Control o Power-Good (PWRGD) and Thermal-Fault

(VRHOT) Outputs

o System Power-OK (PGD_IN) Input o Overvoltage, Undervoltage, and Thermal-Fault

Protection

o Voltage Soft-Startup and Passive Shutdown o < 1µA Typical Shutdown Current

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

________________________________________________________________

Maxim Integrated Products

Ordering Information

19-4443; Rev 0; 2/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE

MAX17480GTL+ -40°C to +105°C 40 TQFN-EP*

Denotes a lead(Pb)-free/RoHS-compliant package.

EP = Exposed pad.

Pin Configuration appears at end of data sheet.

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

(Note 1)

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 2, V

= 12V, V

= V

IN3

= SHDN = PGD_IN = 5V, V

DDIO

= 1.8V, OPTION = GNDS_ = AGND = PGND,

FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, T

= 0°C to +85°C, unless otherwise noted.

Typical values are at T

= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DD,VIN3,VCC

, V

DDIO

to AGND ..............................-0.3V to +6V

PWRGD to AGND .....................................................-0.3V to +6V

SHDN to AGND ........................................................-0.3V to +6V

GNDS1, GNDS2, THRM, VRHOT to AGND..............-0.3V to +6V

CSP_, CSN_, ILIM12 to AGND .................................-0.3V to +6V

SVC, SVD, PGD_IN to AGND ...................................-0.3V to +6V

FBDC_, FBAC_, OUT3 to AGND ..............................-0.3V to +6V

OSC, TIME, OPTION, ILIM3 to AGND........-0.3V to (V

+ 0.3V)

BST1, BST2 to AGND .............................................-0.3V to +36V

BST1, BST2 to V

.................................................-0.3V to +30V

BST3 to AGND...................................(V

- 0.3V) to (V

LX3

+ 6V)

LX1 to BST1..............................................................-6V to +0.3V

LX3 RMS Current (Note 2) .....................................................±4A

LX2 to BST2..............................................................-6V to +0.3V

LX3 to PGND (Note 2) ..............................................-0.6V to +6V

DH1 to LX1 ..............................................-0.3V to (V

BST1

+ 0.3V)

DH2 to LX2 ..............................................-0.3V to (V

BST2

+ 0.3V)

DL1 to PGND..............................................-0.3V to (V

+ 0.3V)

DL2 to PGND..............................................-0.3V to (V

+ 0.3V)

Continuous Power Dissipation (T

= +70°C)

40-Pin TQFN (derate 22.2mW/°C above +70°C) .......1778mW

Operating Temperature Range .........................-40°C to +105°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Note 1: Absolute Maximum Ratings measured with 20MHz scope bandwidth. Note 2: LX3 has clamp diodes to PGND and IN3. If continuous current is applied through these diodes, thermal limits must be observed.

INPUT SUPPLIES

Input Voltage Range

VCC Undervoltage-Lockout Threshold

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VIN Drain of external high-side MOSFET 4 26

BIAS

IN3

DDIO

UVLO

VCC, VDD 4.5 5.5

2.7 5.5

1.0 2.7

VCC rising, 50mV typical hysteresis, latched, UV fault

4.10 4.25 4.45 V

Fal ling edge, typica l h ysteresis = 1.1V,

VCC Power-On Reset Thresho ld

Undervoltage-Lockout

DDIO

Threshold

Undervoltage-Lockout

IN3

Threshold

Quie sc ent Supply Current (VCC) I

Quiescent Supply Currents (VDD) I

Quiescent Supply Current (V

Quiescent Supply Current (IN3) I

Shutdown Supply C urrent (VCC) SHDN = GND, TA = +25°C 0.01 1 µA

DDI O

) I

DDI O

IN3

faults cleared and DL_ forced high when

falls be low th is le vel

rising, 100mV typical hysteresis,

DDIO

latched, UV fault

rising, 100mV typical hystere sis 2.5 2.6 2.7 V

IN3

Skip mode, FBDC_ and OUT3 forced above their regulation points

Skip mode, FBDC_ and OUT3 forced above their regulation points, T

10 25 µA

Skip mode, OUT3 forced above its regulation point

= +25°C

1.8 V

0.7 0.8 0.9 V

5 10 mA

0.01 1 µA

50 200 µA

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 2, V

= 12V, V

= V

IN3

= SHDN = PGD_IN = 5V, V

DDIO

= 1.8V, OPTION = GNDS_ = AGND = PGND,

FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, T

= 0°C to +85°C, unless otherwise noted.

Typical values are at T

= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Shutdown Supply Currents (VDD) SHDN = GND, TA = +25°C 0.01 1 µA

Shutdown Supply C urrent (V

) SHDN = GND, TA = +25°C 0.01 1 µA

DDIO

Shutdown Supply C urrent (IN3) SHDN = GND, TA = +25°C 0.01 1 µA

INTERNAL DACs, SLEW RATE, PHAS E SHIFT

Measured at FBDC_ for the core SMPSs;

DAC codes from

0.8375V to 1.5500V

-0.5 +0.5 %

measured at OUT3 DC Output Voltage Accuracy (Note 1)

OUT

for the NB SMPS;

30% duty cycle, no

load, ILIM3 = V

= V

OUT3

DAC3

12.5mV (Note 3)

DAC codes from

0.5000V to 0.8250V

DAC codes from

12.5mV to 0.4875V

-5 +5

-10 +10

OUT3 Offset 12.5 mV

SMPS1 to SMPS2 Phase Shift SMPS2 starts after SMPS1

SMPS3 to SMPS1 and SMPS2 Phase Shift

Slew-Rate Accuracy

SMPS3 starts after SMPS1 or SMPS2 25 %

= 143k, SR = 6.25mV/µs -10 +10

During

transition

TIME

= 35.7k to 357k,

TIME

SR = 25mV/µs to 2.5mV/µs

50 %

180 Degrees

-15 +15

Startup 1 mV/µs

FBAC_ Input Bias Current I

FBDC_ Input Bias Current I

Switching Frequenc y Accuracy

_CSP_ = CSN_, TA = +25°C -3 +3 µA

FBAC

_TA = +25°C -250 +250 nA

FBDC

OSC1,

OSC2,

OSC3

= 143k (f

OSC

nominal, f

OSC

nominal, f

432k (f

OSC3

= 71.4k (f

OSC3

OSC1

= 199kHz nominal)

= f

OSC1

= f

OSC2

= 300kHz

= 600kHz nominal)

OSC1

= f

OSC2

= 600kHz

= 1.2MHz nominal) to

= 99kHz nominal,

OSC2

-7 +7

-9 +9

SMPS1 AND SMPS2 CONTROLLERS

DC Load Regulation

Either SMPS, PWM mode, droop disabled;

zero to full load

-0.1 %

Line Regulation Error Either SMPS, 4V < VIN < 26V 0.03 %/V

GNDS_ Input Range V

GNDS_ Gain A

GNDS_ Input B ia s Current I

GNDS_

GNDS

Separate mode -200 +200 mV

Separate: V

 +200mV; combined: V

-200mV  V

OUT

GNDS_

_/V

GNDS_,

 +200mV

-200mV  V /V

OUT

GNDS _,

GNDS

0.95 1.00 1.05 V/V

_TA = +25°C -2 +2 µA

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 2, V

= 12V, V

= V

IN3

= SHDN = PGD_IN = 5V, V

DDIO

= 1.8V, OPTION = GNDS_ = AGND = PGND,

FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, T

= 0°C to +85°C, unless otherwise noted.

Typical values are at T

= +25°C.)

Idle Mode is a trademark of Maxim Integrated Products, Inc.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Combined-Mode Detection Threshold

Maximum Duty Factor D

Minimum On-Time t

SMPS1 AND SMPS2 CURRENT LIMIT

Current-Limit Threshold Tolerance

Zero-Crossing Threshold V

Idle Mode™ Threshold

CS_ Input Leakage Current CSP_ and CSN_, TA = +25°C -0.2 +0.2 µA

CS_ Common-Mode Input Range CSP_ and CSN_ 0 2 V

SMPS1 AND SMPS2 DROOP, CURRENT BALANCE, AND TRANSIENT RESPONSE

AC Droop and Current Balance Ampl ifier Transconductance

AC Droop and Current Balance Amplifier Offset

No-Load Positive Offset OPTION = 2V or GND +12.5 mV

Transient Detection Threshold

SMPS3 INTERNAL 4A STEP-DOWN CONVERTER

OUT3 Load Regulat ion R

OUT3 Line Regulation 0 to 100% duty cycle 5 mV

OUT3 Input Current I

LX3 Leakage Current I

Internal MOSFET On-Resistance

LX3 Peak C urrent Lim it I

LX3 Idle-Mode Trip Level I

LX3 Zero-Crossing Trip Level I

Maximum Duty Factor D

Minimum On-Time t

MAX

ONMIN

LIMIT

IMIN

m(FBAC_)

GNDS1, GNDS2, detection after REFOK, latched, cleared by cycling SHDN

90 92 %

CSP

REF

GND

CSP

I

FBAC

CSP

FBAC

_ - V

_ - VLX_, skip mode 1 mV

_ - V

_/G

_ = 0.052 x (V

CSN

- V

) = 0.2V to 1.0V

ILM

_, skip mode, 0.15 x V

CSN

_/( VCS_), V

_ = 0 to +40mV

CSN

m(FBAC_)

-1.5 +1.5 mV

FBAC

_ = V

0.7 0.8 0.9 V

150 ns

- V

REF

CSN

ILIM

LIMIT

_ = 1.2V,

-3 +3 mV

-2 +2 mV

1.94 2.00 2.06 mS

Measured at FBDC_ with respect to steady-state FBDC_ regulation voltage,

-47 -41 -33 mV

10mV hysteresis (typ)

4 5.5 7 mV/A

DROOP3

TA = +25°C -100 -5 +100 nA

OUT3

LX3

ON(NH3)

ON(NL3)

LX3PK

LX3MIN

ZX3

MAX

ONMIN

SHDN = GND, V V

= 5.5V, TA = +25°C

IN3

High-side n-channe l 75 150

Low-side n-channel 40 75

ILIM3 = VCC 4.75 5.25 6

ILIM3 = GND 3.75 4.25 5

Percentage of I

Skip mode 20 mA

84 87 %

= GND or 5.5V,

LX3

25 %

LX3PK

-20 +20 µA

150 ns

m

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 2, V

= 12V, V

= V

IN3

= SHDN = PGD_IN = 5V, V

DDIO

= 1.8V, OPTION = GNDS_ = AGND = PGND,

FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, T

= 0°C to +85°C, unless otherwise noted.

Typical values are at T

= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

FAULT DETECTION

Output Overvoltage Tr ip Threshold (SMPS1 and SMPS2 Only)

Output Overvoltage Fault Propagation Delay (SMPS1 and SMPS2 Only)

Output Undervoltage Protection Trip Threshold

Output Undervoltage Fault Propagation Dela y

PWRGD Threshold

PWRGD Propagat ion Delay t

PWRGD, Output Low Voltage I

PWRGD Leakage Current I

PWRGD Startup Dela y and Transition B lan king Time

VRHOT Trip Threshold

VRHOT Delay t

VRHOT, Output Low Voltage I VRHOT Leakage Current High state, VRHOT forced to 5V, TA = +25°C 1 µA

THRM Input Leakage TA = +25°C -100 +100 nA

Thermal-Shutdown Threshold T

GATE DRIVERS

DH_ Gate-Driver On-Resistance R

DL_ Gate-Driver On-Resistance R

OVP_

OVP

UVP

PWRGD

BLANK

VRHOT

SHDN

ON(DH_)

ON(DL_)

PWM mode 250 300 350 mV

Measured at FBDC_, rising edge

FBDC_ forced 25mV above trip threshold 10 µs

Measured at FBDC_ or OUT3 with respect to unloaded output vo ltage

FBDC_ forced 25mV below trip threshold 10 µs

Measured at FBDC_ or OUT3 with respect to unloaded output voltage,15mV hysteresis (typ)

FBDC_ or OUT3 forced 25mV outside the PWRGD trip thresholds

= 4mA 0.4 V

SINK

High state, PWRGD forced to 5.5V, T

= +25°C

Measured from the time when FBDC_ and OUT3 reach the target voltage

Measured at THRM, with respect to V falling edge, 115mV hysteresis (typ)

THRM forced 25mV below the VRHOT trip threshold, fall ing edge

= 4mA 0.4 V

SINK

Hysteresis = 15°C +160 °C

BST_ - LX_ forced to 5V (Note 4)

DL_, high state 0.7 2.0

DL_, low state 0.25 0.6

Skip mode and output has not reached the regulation voltage

Minimum OVP threshold

Lower threshold, falling edge (undervolt age)

Upper threshold, rising edge (overvoltage)

High state (pullup) 0.9 2.5

Low state (pulldown) 0.7 2.5

1.80 1.85 1.90

0.8

-450 -400 -350 mV

-350 -300 -250

+150 +200 +250

10 µs

1 µA

20 µs

29.5 30 30.5 %

10 µ



MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 2, V

= 12V, V

= V

IN3

= SHDN = PGD_IN = 5V, V

DDIO

= 1.8V, OPTION = GNDS_ = AGND = PGND,

FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, T

= 0°C to +85°C, unless otherwise noted.

Typical values are at T

= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DH_ Gate-Driver Source/Sink Current

DL_ Gate-Driver Source Current

DL_ Gate-Driver Sink Current IDL_

Dead Time

Internal BST1, BST2 Switch R

Internal BST3 Switch R

2-WIRE I2C BUS LOGIC INTERFACE

SVI Logic-Input Current SVC, SVD, TA = +25°C -1 +1 µA

SVI Logic-Input Threshold

SVC Clock Frequenc y f

START Condit ion Hold Time t

Repeated START Condition Setup Time

STOP Condition Setup Time t

Data Hold t

Data Setup Time t

SVC Low Period t

SVC High Period t

SVC/SVD Rise and Fall Time tR, t

Pulse Width of Spike Suppression 20 ns

INPUTS AND OUTPUTS

Logic-Input Current

Logic-Input Leve ls SHDN, rising edge, hysteresis = 225mV 0.8 2.0 V

Input Logic Leve ls

PGD_IN Logic-Input Threshold PGD_IN, rising edge, hysteresis = 65mV

(SINK)

tDH_

DL_DH

_ DH_ forced to 2.5V, BST_ - LX_ forced to 5V 2.2 A

DL_ forced to 2.5V 2.7 A

DL_ forced to 2.5V 8 A

DH_ low to DL_ high 9 20 35

DL_ low to DH_ high 9 20 35

BST1, BST2 to VDD, I

BST3 to VDD, I

BST3

= I

BST1

= 10mA 10 20 

SVC, SVD, rising edge, hysteresis 0.14 x V

(V)

DDIO

SVC

HD; STA

SU;STA

SU;STO

3.4 MHz

160 ns

= 10mA 10 20 

BST2

0.3 x

DDIO

A master device must internally provide a hold time of at least 300ns for the SVD

HD;DAT

signal (referred to the V

of SVC signa l)

IHMIN

70 ns to bridge the undefined region of SVC’s falling edge

SU;DAT

LOW

HIGH

10 ns

160 ns

Measured from 10% to 90% of V

Input filter s o n SVD and SVC suppress

noise spike less than 50ns

60 ns

DDIO

40 ns

SHDN, PGD_IN, TA = +25°C -1 +1 µA

ILIM3, OPTION, T

High, OPTION, ILIM3

= +25°C -200 +200 nA

0.4

3.3V, OPTION 2.75 3.85

2V, OPTION 1.65 2.35

Low, OPTION, ILIM3 0.4

0.3 x

DDIO

0.7 x

DDIO

0.7 x

DDIO

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

_______________________________________________________________________________________ 7

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 2, V

= 12V, V

= V

IN3

= SHDN = PGD_IN = 5V, V

DDIO

= 1.8V, OPTION = GNDS_ = AGND = PGND,

FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, T

= -40°C to +105°C, unless otherwise

noted. Typical values are at T

= +25°C.) (Note 5)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

INPUT SUPPLIES

VIN Drain of external high-side MOSFET 4 26

Input Voltage Range

VCC Undervoltage-Lockout Threshold

Undervoltage-Lockout

DDIO

Threshold

Undervoltage-Lockout

IN3

Threshold

Quie sc ent Supply Current (VCC) I

Quiescent Supply Current

Quiescent Supply Current (IN3) I

BIAS

2.7 5.5

IN3

1.0 2.7

DDIO

UVLO

DDI O

IN3

VCC rising, 50mV typical hysteresis, latched, UV fault

rising, 100mV typical hysteresis,

DDIO

latched, UV fault

rising, 100mV typical hystere sis 2.5 2.7 V

IN3

Skip mode, FBDC_ and OUT3 forced above their regulation points

4.10 4.45 V

0.7 0.9 V

10 mA

25 µA

Skip mode, OUT3 forced above its regulation point

200 µA

VCC, VDD 4.5 5.5

INTERNAL DACs, SLEW RATE, PHAS E SHIFT

Measured at FBDC_ for the core SMPSs;

DAC codes from

0.8375V to 1.5500V

-0.7 +0.7 %

measured at OUT3

DC Output Voltage Accuracy V

OUT

for the NB SMPS; 30% duty cycle, no load, ILIM3 = V

, V

OUT3

= V

+ 12.5mV (Note 3)

DAC codes from

0.5000V to 0.8250V

DAC codes from

DAC3

12.5mV to 0.4875V

-7.5 +7.5

-15 +15

Slew-Rate Accuracy During transit ion

= 143k (f

OSC

Switching Frequenc y Accuracy

OSC1,

OSC2,

OSC3

nominal, f

= 71.4k (f

OSC

nominal, f 432k (f f

= 199kHz nominal)

OSC3

= 600kHz nominal)

OSC3

= 1.2MHz nominal) to

OSC3

= f

OSC1

= 143k,

TIME

SR = 6.25mV/µs

= 35.7k to

TIME

357k, SR = 25mV/µs to 2.5mV/µs

= f

OSC1

= 99kHz nominal,

OSC2

= f

OSC2

= 300 kHz

= 600 kHz

-10 +10

-15 +15

-9 +9

-12 +12

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

8 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 2, V

= 12V, V

= V

IN3

= SHDN = PGD_IN = 5V, V

DDIO

= 1.8V, OPTION = GNDS_ = AGND = PGND,

FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, T

= -40°C to +105°C, unless otherwise

noted. Typical values are at T

= +25°C.) (Note 5)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SMPS1 AND SMPS2 CONTROLLERS

GNDS_ Input Range V

GNDS_ Gain A

Combined-Mode Detection Threshold

Maximum Duty Factor D

Minimum On-Time t

SMPS1 AND SMPS2 CURRENT LIMIT

Current-Limit Threshold Tolerance

Idle-Mode Threshold Tolerance V

CS_ Common-Mode Input Range CSP_ and CSN_ 0 2 V

SMPS1 AND SMPS2 DROOP, CURRENT BALANCE, AND TRANSIENT RESPONSE

AC Droop and Current Balance Ampl ifier Transconductance

AC Droop and Current Balance Amplifier Offset

Transient Detection Threshold

SMPS3 INTERNAL 4A STEP-DOWN CONVERTER

OUT3 Load Regulat ion R

Internal MOSFET On-Resistance

LX3 Peak C urrent Lim it I

Maximum Duty Factor D

Minimum On-Time t

GNDS_

MAX

ONMIN

LIMIT

IMIN

m(FBAC_)

DROOP3

ON(NH3)

ON(NL3)

LX3PK

MAX

ONMIN

Separate mode -200 +200 mV

Separate: V V

_  +200mV; combined;

GNDS

/ V

V

OUT

GNDS1, GNDS2, detection after REFOK, latched, cleared by cycling SHDN

OUT

GNDS _,

_/V

GNDS_,

-200mV  V

-200mV 

GNDS _

0.95 1.05 V/V

 +200mV

0.7 0.9 V

90 %

150 ns

CSP

REF

CSP

I

FBAC

CSP

FBAC

_ - V

_/G

_ = 0.052 x (V

CSN

- V

) = 0.2V to 1.0V

ILM

_, skip mode, 0.15 x V

CSN

_/(VCS_), V

CSN

m(FBAC_)

FBAC

_ = 0 to +40mV

-1.5 +2.0 mV

_ = V

REF

CSN

- V

ILIM

LIMIT

_ = 1.2V,

-3 +3 mV

-2 +2 mV

1.94 2.06 mS

Measured at FBDC_ with respect to steady-state FBDC_ regulation voltage,

-47 -33 mV

10mV hysteresis (typ)

4 7 mV/A

High-side n-channel 150

Low-side n-channel 75

ILIM3 = V

skip mode 4.75 6 A

CC,

m

84 %

150 ns

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

_______________________________________________________________________________________ 9

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 2, V

= 12V, V

= V

IN3

= SHDN = PGD_IN = 5V, V

DDIO

= 1.8V, OPTION = GNDS_ = AGND = PGND,

FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, T

= -40°C to +105°C, unless otherwise

noted. Typical values are at T

= +25°C.) (Note 5)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

FAULT DETECTION

Output Overvoltage Tr ip Threshold (SMPS1 and SMPS2 Only)

Output Undervoltage Protection Trip Threshold

PWRGD Threshold

PWRGD, Output Low Voltage I

VRHOT Trip Threshold

VRHOT, Output Low Voltage I

GATE DRIVERS

DH_ Gate-Driver On-Resistance R

DL_ Gate-Driver On-Resistance R

Dead Time

Internal BST1, BST2 Switch R

Internal BST3 Switch R

2-WIRE I2C BUS LOGIC INTERFACE

SVI Logic-Input Threshold

SVC Clock Frequenc y f

START Condit ion Hold Time t

Repeated START Condition Setup Time

STOP Condition Setup Time t

Data Hold t

OVP_

UVP

ON(DH_)

ON(DL_)

tDH_

DL_DH

SVC

SU;STA

SU;STO

HD;DAT

PWM mode 250 350 mV

Measured at FBDC_, rising edge

Measured at FBDC_ or OUT3 with respect to unloaded output vo ltage

Measured at FBDC_ or OUT3 with respect to unloaded output voltage, 15mV hysteresis (typ)

= 4mA 0.4 V

SINK

Measured at THRM, with respect to V falling edge, 115mV hysteresis (typ)

= 4mA 0.4 V

SINK

BST_ - LX_ forced to 5V (Note 4)

DL_, high state 2.0

DL_, low state 0.6

DH_ low to DL_ high 9 35

DL_ low to DH_ high 9 35

BST1, BST2 to VDD, I

BST3 to VDD, I

SVC, SVD, rising edge, hy steresis = 0.14 x

(V)

DDIO

3.4 MHz

160 ns

A master device must internally provide a hold time of at least 300ns for the SVD signal (referred to the V the undefined region of SVC’s falling edge

BST3

Skip mode and output ha ve not reached the regulation voltage

Lower threshold, falling edge (undervolt age)

Upper threshold, rising edge (overvoltage)

High state (pullup) 2.5

Low state (pulldown) 2.5

= I

BST1

= 10mA 20 

of SVC signal) to bridge

IHMIN

= 10mA 20 

BST2

1.80 1.90 V

-450 -350 mV

-350 -250

+150 +250

CC,

29.5 30.5 %

0.3 x

DDIO

70 ns

0.7 x

DDIO



MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

10 ______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 2, V

= 12V, V

= V

IN3

= SHDN = PGD_IN = 5V, V

DDIO

= 1.8V, OPTION = GNDS_ = AGND = PGND,

FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, T

= -40°C to +105°C, unless otherwise

noted. Typical values are at T

= +25°C.) (Note 5)

Note 3: When the inductor is in continuous conduction, the output voltage has a DC regulation level lower than the error-comparator

threshold by 50% of the ripple. In discontinuous conduction, the output voltage has a DC regulation level higher than the error-comparator threshold by 50% of the ripple. The core SMPSs have an integrator that corrects for this error. The NB SMPS has an offset determined by the ILIM3 pin, and a -6.5mV/A load line.

Note 4: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the TQFN

package.

Note 5: Specifications to T

= -40°C to +105°C are guaranteed by design, not production tested.

SVC

HD;STA

HD;DAT

SU;DAT

SU;STO

BUF

LOW

HIGH

SVD

Figure 1. Timing Definitions Used in the Electrical Characteristics

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Data Setup Time t

SVC Low Period t

SVC High Period t

SVC/SVD Rise and Fall Time tR, t

INPUTS AND OUTPUTS Logic-Input Leve ls SHDN, rising edge, hysteresis = 225mV 0.8 2.0 V

Input Logic Leve ls

PGD_IN Logic-Input Threshold PGD_IN, rising edge, hysteresis = 65mV

SU;DAT

LOW

HIGH

10 ns

160 ns

Measured from 10% to 90% of V

Input filter s o n SVD and SVC suppress

noise spike less than 50ns

High, OPTION, ILIM3

3.3V, OPTION 2.75 3.85

60 ns

DDIO

40 ns

0.4

2V, OPTION 1.65 2.35

Low, OPTION, ILIM3 0.4

0.3 x

DDIO

0.7 x

DDIO

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 11

Typical Operating Characteristics

(Circuit of Figure 2, V

= 12V, VDD= VCC= 5V, V

DDIO

= 2.5V, TA = +25°C, unless otherwise noted.)

CORE SMPS 1-PHASE EFFICIENCY

vs. LOAD CURRENT (V

OUT

= 1.2V)

MAX17480 toc01

LOAD CURRENT (A)

EFFICIENCY (%)

101

100

0.1 100

SKIP MODE PWM MODE

12V

20V

CORE SMPS 2-PHASE EFFICIENCY

vs. LOAD CURRENT (V

OUT

= 1.2V)

MAX17480 toc02

LOAD CURRENT (A)

EFFICIENCY (%)

100

1100

12V

20V

PWM MODE

CORE SMPS OUTPUT VOLTAGE

vs. LOAD CURRENT (V

OUT

= 1.2V)

MAX17480 toc03

LOAD CURRENT (A)

OUTPUT VOLTAGE (V)

15105

1.195

1.200

1.205

1.190 020

SKIP MODE AND PWM MODE

VIN = 12V

CORE SMPS 1-PHASE EFFICIENCY

vs. LOAD CURRENT (V

OUT

= 0.8V)

MAX17480 toc04

LOAD CURRENT (A)

EFFICIENCY (%)

101

100

0.1 100

SKIP MODE PWM MODE

12V

20V

CORE SMPS OUTPUT VOLTAGE

vs. LOAD CURRENT (V

OUT

= 0.8V)

MAX17480 toc05

LOAD CURRENT (A)

OUTPUT VOLTAGE (V)

15105

0.795

0.800

0.805

0.790 020

SKIP MODE AND PWM MODE

VIN = 12V

NB SMPS EFFICIENCY

vs. LOAD CURRENT (1V)

MAX17480 toc06

LOAD CURRENT (A)

EFFICIENCY (%)

100

0.1 10

SKIP MODE PWM MODE

3.3V

NB SMPS 1V OUTPUT VOLTAGE

vs. LOAD CURRENT

MAX17480 toc07

LOAD CURRENT (A)

OUTPUT VOLTAGE (V)

0.97

0.99

1.01

1.03

1.05

0.95 043

SKIP MODE PWM MODE

VIN = 3.3V

VIN = 5V

CORE SMPS 1-PHASE SWITCHING

FREQUENCY vs. LOAD CURRENT

MAX17480 toc08

LOAD CURRENT (A)

SWITCHING FREQUENCY (kHz)

101

150

200

250

300

350

100

0.1 100

VIN = 20V SKIP VIN = 20V PWM

VIN = 12V SKIP VIN = 12V PWM

VIN = 7V SKIP VIN = 7V PWM

OUT

= 1.2V

NB SMPS SWITCHING FREQUENCY

vs. LOAD CURRENT

MAX17480 toc09

LOAD CURRENT (A)

SWITCHING FREQUENCY (kHz)

3.0 3.52.52.00.5 1.0 1.5

450

500

550

600

650

700

750

400

04.0

VIN = 3.3V SKIP VIN = 5V PWM VIN = 3.3V SKIP VIN = 5V PWM

OUT

= 1V

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

12 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(Circuit of Figure 2, V

= 12V, VDD= VCC= 5V, V

DDIO

= 2.5V, TA = +25°C, unless otherwise noted.)

MAXIMUM INDUCTOR CURRENT

vs. INPUT VOLTAGE

MAX17480 toc10

INPUT VOLTAGE (V)

INDUCTOR CURRENT (A)

20.017.512.5 15.010.07.5

5.0

OUT

= 1.2V

PEAK CURRENT

DC CURRENT

NO-LOAD SUPPLY CURRENT

vs. INPUT VOLTAGE

MAX17480 toc11

INPUT VOLTAGE (V)

SUPPLY CURRENT (mA)

242118151296

0.1

100

0.01 3

SKIP MODE PWM MODE

+ I

OUT

= 1.2V

CORE SMPS VID = 1.2V

OUTPUT VOLTAGE DISTRIBUTION

MAX17480 toc12

OUTPUT VOLTAGE (V)

SAMPLE PERCENTAGE (%)

1.195

1.196

1.197

1.198

1.199

1.200

1.201

1.202

1.203

1.204

1.205

TA = +85°C TA = +25°C

SAMPLE SIZE = 100

NB SMPS VID = 1.2V

OUTPUT VOLTAGE DISTRIBUTION

MAX17480 toc13

OUTPUT VOLTAGE (V)

SAMPLE PERCENTAGE (%)

1.195

1.196

1.197

1.198

1.199

1.200

1.201

1.202

1.203

1.204

1.205

SAMPLE SIZE = 100

TA = +85°C TA = +25°C

m(FBAC)

TRANSCONDUCTANCE

DISTRIBUTION

MAX17480 toc14

TRANSCONDUCTANCE (µS)

SAMPLE PERCENTAGE (%)

1985

1988

1991

1994

1997

2000

2003

2006

2009

2012

2015

SAMPLE SIZE = 100

+85°C +25°C

NB SMPS PEAK

CURRENT-LIMIT DISTRIBUTION

MAX17480 toc15

PEAK CURRENT LIMIT (A)

SAMPLE PERCENTAGE (%)

5.00

5.05

5.10

5.15

5.20

5.25

5.30

5.40

5.35

5.45

5.50

SAMPLE SIZE = 100

ILIM3 = V

TA = +85°C TA = +25°C

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 13

Typical Operating Characteristics (continued)

(Circuit of Figure 2, V

= 12V, VDD= VCC= 5V, V

DDIO

= 2.5V, TA = +25°C, unless otherwise noted.)

STARTUP WAVEFORMS

MAX17480 toc16

200µs/div

SHDN, 5V/div V

OUT1

, 0.5V/div

OUT2

, 0.5V/div

OUT3

, 0.5V/div

PWRGD, 5V/div

, 5A/div

LX3

, 1A/div

= 12V

BOOT

= 1V

LOAD1

= 3A

LOAD2

= 3A

LOAD3

= 0.5A

0 0

STARTUP SEQUENCE

MAX17480 toc17

400µs/div

SHDN, 5V/div V

OUT1

, 0.5V/div

OUT2

, 0.5V/div

OUT3

, 0.5V/div

PWRGD, 5V/div

PGD_IN, 2.5V/div

SVC, 2.5V/div

SVD, 2.5V/div

= 12V

BOOT

= 1V

SVID

= 1.2V

SHUTDOWN WAVEFORMS

MAX17480 toc18

100µs/div

3.3V

1.2V

5V 5V

SHDN, 5V/div

OUT1

, 0.5V/div

OUT2

, 0.5V/div

OUT3

, 0.5V/div

DL1, 10V/div

DL2, 10V/div

LX3, 10V/div

PWRGD, 10V/div

= 12V I

LOAD1

= 3A

SVID

= 1.2V I

LOAD2

= 3A

LOAD3

= 0.5A

CORE SMPS 1-PHASE LOAD-TRANSIENT

RESPONSE

MAX17480 toc19

20µs/div

1.2V

1.5A

13.5A

12V

OUT1

, 50mV/div

LX1

, 10A/div

LX1, 10V/div

= 12V I

LOAD1

= 1.5A TO 13.5A TO 1.5A

OUT1

= 1.2V PWM MODE

CORE SMPS 1-PHASE TRANSIENT

PHASE REPEAT

MAX17480 toc20

2µs/div

1.2V

1.5A

13.5A

12V

OUT1

50mV/div

LX1

10A/div

LX1 10V/div

= 12V I

LOAD1

= 1.5A TO 13.5A TO 1.5A

OUT1

= 1.2V PWM MODE

CORE SMPS 2-PHASE LOAD-TRANSIENT

RESPONSE

MAX17480 toc21

20µs/div

1.2V

1.5A

13.5A

13.5V

1.5A

OUT

50mV/div

LX1

10A/div

LX2

10A/div

= 12V I

LOAD

= 3A TO 27A TO 3A

OUT1

= 1.2V PWM MODE

CORE SMPS 2-PHASE TRANSIENT

PHASE REPEAT

MAX17480 toc22

2µs/div

1.2V

1.5A

13.5A

1.5A

OUT

50mV/div

LX1

10A/div

LX2

10A/div

= 12V I

LOAD

= 3A TO 27A TO 3A

OUT1

= 1.2V PWM MODE

NB SMPS LOAD-TRANSIENT

RESPONSE

MAX17480 toc23

20µs/div

0.4A

3.6A

OUT3

50mV/div

LX3

2A/div

LX3 5V/div

IN3

= 5V I

LOAD3

= 0.4A TO 3.6A TO 0.4A

OUT3

= 1V PWM MODE

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

14 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(Circuit of Figure 2, V

= 12V, VDD= VCC= 5V, V

DDIO

= 2.5V, TA = +25°C, unless otherwise noted.)

Typical Operating Characteristics (continued)

(Circuit of Figure 2, V

= 12V, VDD= VCC= 5V, V

DDIO

= 2.5V, TA = +25°C, unless otherwise noted.)

CORE SMPS OUTPUT OVERLOAD

WAVEFORM (SEPARATE MODE)

MAX17480 toc24

100µs/div

1.2V

= 12V I

LOAD1

= 3A TO 40A

SVID

= 1.2V I

LOAD2

= 3A

LOAD3

= 0.5A

SHDN, 5V/div

OUT1

, 1V/div

DL1, 10V/div

OUT2

, 1V/div

OUT3

, 1V/div

DL2, 10V/div

LX3, 10V/div

CORE SMPS OUTPUT OVERVOLTAGE

WAVEFORM (SEPARATE MODE)

MAX17480 toc25

100µs/div

1.2V

= 12V I

LOAD1

= NO LOAD

SVID

= 1.2V I

LOAD2

= 3A

LOAD3

= 0.5A

SHDN, 5V/div

OUT1

, 1V/div

DL1, 10V/div

OUT2

, 1V/div

OUT3

, 1V/div

DL2, 10V/div

LX3, 10V/div

DYNAMIC OUTPUT-VOLTAGE

TRANSITIONS (LIGHT LOAD)

MAX17480 toc26

100µs/div

0.6V

1.3V

2.5V

1.3V

= 12V

SVID

= 1.3V TO 0.6V TO 1.3V

OUT1

, 0.5V/div

OUT2

, 0.5V/div

OUT3

, 0.5V/div

SVC, 2.5V/div

SVD, 2.5V/div

PGD_IN TRANSITION (LIGHT LOAD)

MAX17480 toc27

10µs/div

0.8V

1.1V

1.2V

0.9V

= 12V

BOOT

= 1.1V

OUT1

= 0.8V

OUT2

= 1.2V

OUT3

= 0.9V

OUT

, 200mV/div,

OUT2

, 200mV/div

LX1, 20V/div

LX2, 20V/div

LX3, 5V/div

OUT3

, 200mV/div

PWRGD, 5V/div

PGD_IN, 5V/div

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

16 ______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

SMPS1 and SMPS2 Current-Limit Adjust Input. The positive current-limit threshold voltage is 0.052

1 ILIM12

2 ILIM3

3, 4 IN3

5, 6 LX3 Inductor Connection for SMPS3. Connect LX3 to the switched side of the inductor.

7 BST3

times the voltage between TIME and ILIM o ver a 0.2V to 1.0V range of V(TIME, ILIM). The I min imum current-limit threshold voltage in skip mode is precisel y 15% of the correspond ing positive current-limit threshold voltage.

SMPS3 Current-Limit Adjust Input. Two-leve l current-lim it setting for SMPS3. The I current-limit threshold in skip mode is preci sely 25% of the correspond ing positive current-lim it threshold.

ILIM3 I

VCC 5.25

Internal High-Side MOSFET Drain Connection for SMPS3. Bypass to PGND with a 10µF or greater ceramic capacitor close to the IC.

Boost Flying Capacitor Connection for SMPS3. An internal switch between V the fl ying capacitor during the time the low-side FET is on.

Active-Low Shutdown Control Input. This input cannot withstand the battery voltage. Connect to V

startup, the output vo ltage is ramped up to the vo ltage set by the SVC and SVD inputs at a slew rate of 1mV/µs. In shutdown, the outputs are discharged using a 20 switch through the CSN_ pin s for the core SMPSs and through the OUT3 pin for the northbridge SMPS. The MAX17480 powers up to the voltage set by the two SVI bit s.

GND 4.25

for normal operation. Connect to ground to put the IC into its 1µA max shutdown state. During

LX3PK

(A)

MIN12

minimum

LX3MIN

and BST3 charges

8 SHDN

The MAX17480 stores the boot VID when PWRGD first goes high. The stored boot VID is cleared by a rising SHDN signal.

9 OUT3

10 AGND Analog Ground

11 SVD Serial VID Data

12 SVC Serial VID Clock

13 V

14 GNDS2

DDIO

Feedback Input for SMPS3. A 20 discharge FET is enabled from OUT3 to PGND when SMPS3 is shut down.

CPU I/O Voltage (1.8V or 1.5V). Logic thresholds for SVD and SVC are relative to the voltage at V

SMPS2 Remote Ground-Sense Input. Normall y connected to GND directly at the load. GNDS2 internally connects to a transconductance amplifier that fine tunes the output voltage— compensating for voltage drops from the SMPS ground to the load ground.

Connect GNDS1 or GNDS2 above 0.9V combined-mode operation (unified core). When GNDS2 is pulled above 0.9V, GNDS1 is used as the remote ground-sense input.

SVC SVD

0 0 1.1

0 1 1.0

1 0 0.9

1 1 0.8

BOOT VOLTAGE

(V)

OUT

DDIO

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 17

Pin Description (continued)

PIN NAME FUNCTION

Output of the Voltage-Pos itioning Transconductance Amplifier for SMPS2. The RC network between this pin and the positive s ide of the remote-sensed output voltage sets the transient AC droop:

15 FBAC2

where R trade-off between stability and load-transient response, G value of the current-sense element that i s u sed to provide the (CSP2, CSN2) current-sense voltage, Z

CFB2

Feedback-Sense Input for SMPS2. Connect a resistor R of the feedback remote sense, and a capac itor from FBAC2 to couple the AC ripple from FBAC2 to FBDC2. An integrator on FBDC2 corrects for output ripple and ground-sense offset.

16 FBDC2

17 CSN2

To enable a DC load-line less than the AC load-line, add a resistor from FBAC2 to FBDC2.

To enable a DC load-line equal to the AC load-line, short FBAC2 to FBDC2. See the Core Steady- State Voltage Pos itioning (DC Droop) section.

FBDC2 i s high impedance in shutdown.

Negative Current-Sense Input for SMPS2. Connect to the negativ e side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.

A 20 discharge FET is enabled from CSN2 to PGND when the SMPS2 is sh ut down.

DROOP AC

DROOP_AC2

is the impedance of C

is the transient (AC) voltage-positioning slope that provides an acceptable

RRR

FB2

++

FBAC FBDC FB

222

, and FBAC2 i s high impedance in shutdown.

FBAC FBDC

××

SENSE m FBAC

CFB

m(FBAC2)

FBDC2

= 2mS (typ), and R

between FBDC2 and the pos itive side

()

SENSE2

is the

Positive Current-Sense Input for SMPS2. Connect to the pos itive side of the output current-sensing

18 CSP2

19 PGD_IN

resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.

System Power-Good Input PGD_IN is low when SHDN first goes high. The MAX17480 decodes the two SVI bits to determine

the boot voltage. The SVI bits can be changed dynamically during this time while PGD_IN rema in s low and PWRGD is still low.

PGD_IN goes high after the MAX17480 reaches the boot voltage. This indicates that the SVI block is active, and the MAX17480 starts to respond to the SVI commands. The MAX17480 stores the boot VID when PWRGD first goes high. The stored boot VID is cleared by rising SHDN.

After PGD_IN has gone high, if at any time PGD_IN goes low, the MAX17480 regulates to the previously stored boot VID. The slew rate during this transit ion is set by the resistor between the TIME and GND pins. PWRGD fol lows the blanking for normal VID transit ion.

The subsequent rising edge of PGD_IN does not change the stored VID.

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

18 ______________________________________________________________________________________

Pin Description (continued)

PIN NAME FUNCTION

Open-Drain Power-Good Output. PWRGD is the wired-OR open-drain output of all three SMPS outputs.

PWRGD is forced high impedance whenever the s lew-rate controller is active (output voltage transitions).

During startup, PWRGD is held low for an additional 20µs after the MAX17480 reaches the startup

20 PWRGD

21 DH2 SMPS2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown.

22 LX2

23 BST2

24 DL2

boot vo ltage set by the SVC and SVD pins. The MAX17480 stores the boot VID when PWRGD first goes high. The stored boot VID is cleared by rising SHDN.

PWRGD is forced low in shutdown.

When SMPS is in pulse-skipping mode, the upper PWRGD threshold comparator for the respective SMPS is blanked during a downward VID trans ition. The upper PWRGD threshold comparator is reenabled once the output is in regulation (Figure 6).

SMPS2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver. Also u sed as an input to SMPS2’s zero-crossing comparator.

Boost Flying Capacitor Connection for the DH2 High-Side Gate Driver. An internal switch between

and BST2 charges the flying capacitor during the time the low-side FET is on.

SMPS2 Low-Side Gate-Driver Output. DL2 swings from GND2 to V DL2 is al so forced high when an output over voltage fault is detected. DL2 is forced low in sk ip mode after an inductor current zero crossing (GND2 - LX2) is detected.

. DL2 is f orced low in shutdown.

Supply Voltage Input for the DL_ Drivers. V

25 V

26 DL1

27 BST1

28 LX1

29 DH1 SMPS1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown.

30 VRHOT

31 THRM

32 V

the BST _ flying capacitors during the off-time. Connect V voltage. Bypass V

SMPS1 Low-Side Gate-Driver Output. DL1 swings from GND1 to V DL1 is al so forced high when an output over voltage fault is detected. DL1 is forced low in sk ip mode after an inductor current zero crossing (GND1 - LX1) is detected.

Boost Flying Capacitor Connection for the DH1 High-Side Gate Driver. An internal switch between

and BST1 charges the flying capacitor during the time the low-side FET is on.

SMPS1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver. Also u sed as an input to SMPS1’s zero-crossing comparator.

Active-Low Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes below 1.5V (30% of V

Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between V and GND) to THRM. Select the component s so the voltage at THRM fa lls be low 1.5V (30% of V at the desired high temperature.

Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with a 1µF min imum capacitor. A V cleared by cycling V

to GND with a 2.2µF or greater ceramic capacitor.

). VRHOT is high impedance in shutdown.

UVLO event that occurs while the IC is functioning is latched, and can only be

power or by toggling SHDN.

is also the supply voltage used to internally recharge

to the 4.5V to 5.5V system supply

. DL1 is f orced low in shutdown.

)

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 19

Pin Description (continued)

PIN NAME FUNCTION

33 CSP1

34 CSN1

35 FBDC1

36 FBAC1

37 GNDS1

Positive Current-Sense Input for SMPS1. Connect to the positive s ide of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.

Negative Current-Sense Input for SMPS1. Connect to the negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.

A 20 discharge FET is enabled from CSN1 to PGND when the SMPS1 is sh ut down.

Feedback Sense Input for SMPS1. Connect a resistor R of the feedback remote sense, and a capac itor from FBAC1 to couple the AC ripple from FBAC1 to FBDC1. An integrator on FBDC1 corrects for output ripple and ground-sense offset.

To enable a DC load-line less than the AC load-line, add a resistor from FBAC1 to FBDC1.

To enable a DC load-line equal to the AC load-line, short FBAC1 to FBDC1. See the Core Steady- State Voltage Pos itioning (DC Droop) section.

FBDC1 i s high impedance in shutdown.

Output of the AC Voltage-Positioning Transconductance Amplifier for SMPS1. The RC network between this pin and the positi ve side of the remote-sensed output voltage sets the transient AC droop:

DROOP AC

where R trade-off between stability and load-transient response, G value of the current-sense element that i s u sed to provide the (CSP1, CSN1) current-sense voltage, Z

SMPS1 Remote Ground-Sense Input. Normall y connected to GND directly at the load. GNDS1 internally connects to a transconductance amplifier that fine tunes the output voltage— compensating for voltage drops from the SMPS ground to the load ground.

Connect GNDS1 or GNDS2 above 0.9V combined-mode operation (unified core). When GNDS1 is pulled above 0.9V, GNDS2 is used as the remote ground-sense input.

DROOP_AC1

is the impedance of C

CFB1

RRR

is the transient (AC) voltage-positioning slope that provides an acceptable

++

FBAC FBDC FB

111

, and FBAC1 i s high impedance in shutdown.

FB1

FBAC FBDC

between FBDC1 and the pos itive side

FBDC1

××

SENSE m FBAC

CFB

m(FBAC1)

= 2mS (typ), R

()

SENSE1

is the

Four-Leve l Input to Enable Offset and Change Core SMPS Address

38 OPTION

When OFFSET is enabled, the MAX17480 enables a fixed +12.5mV offset on SMPS1 and SMPS2 VID codes after PGD_IN goes high. This configuration is intended for applications that implement a load line. An external resistor at FBDC_ sets the load-line. The offset can be disabled by setting the PSI_L bit to 0 through the ser ial interface. Additionally, the OPTION level also allows core SMPS1 and SMPS2 to ta ke on either the VDD0 or VDD1 addresses. VDD0 refers to CORE0, and VDD1 refers to CORE1 for the AMD CPU. The NB SMPS is not affected by the OPTION setting.

OPTION

VCC 0 BIT 1 (VDD0) BIT 2 (VDD1)

3.3V 0 BIT 2 (VDD1) BIT 1 (VDD0)

2V 1 BIT 1 (VDD0) BIT 2 (VDD1)

GND 1 BIT 2 (VDD1) BIT 1 (VDD0)

OFFSET

ENABLED

SMPS1

ADDRESS

SMPS2

ADDRESS

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

20 ______________________________________________________________________________________

Pin Description (continued)

PIN NAME FUNCTION

Oscillator Adjustment Input. Connect a resistor (R frequency (per phase):

= 300kHz x 143k/R

OSC

39 OSC

A 71.4k to 432k res istor corresponds to switching frequencies of 600kHz to 100kHz, respectively, for SMPS1 and SMPS2. SMPS3 runs at twice the programmed switching frequency. Switching frequenc y selection is limited by the minimum on-time. See the Core Switching Frequency description in the SMPS Design Procedure section.

) between OSC and GND to set the switching

OSC

Slew-Rate Adjustment Pin. The total resistance R

PWM slew rate = (6.25mV/µs) x (143k/R

where R

40 TIME

EP PGND Exposed Pad. Power ground connection and source connection of the internal low-side MOSFET.

Thi s slew rate applies to both upward and downward VID transition s, and to the transition from boot mode to VID mode. Downward VID transition slew rate in skip mode can appear slower because the output transit ion is not forced by the SMPS.

The s lew rate for startup is fixed at 1mV/µs.

is between 35.7 k and 357k.

TIME

from TIME to GND sets the internal slew rate:

TIME

)

TIME

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 21

Table 1. Component Selection for Standard Applications

Note: Mobile applications should be designed for separate mode operation. Component selection is dependent on AMD CPU AC

and DC specifications.

Table 2. Component Suppliers

Standard Application Circuit

The MAX17480 standard application circuit (Figure 2) generates two independent 18A outputs and one 4A

output for AMD mobile CPU applications. See Table 1 for component selections. Table 2 lists the component manufacturers.

COMPONENT

Mode

Swit ch ing

Frequency

Input

IN_

Capacitor

Output

OUT_

Capacitor

NH_ High-Side

MOSFET

NL_ Low-Side

MOSFET

DL_ Schottky

Rectifier

(if needed)

L_ Inductor

= 7V TO 24V,

= V

OUT1

1.3V, 18A PER PHASE

Separate, 2-phase mobile (GNDS1 = GNDS2 = low)

300kHz 600kH z 500 kHz 1MHz

(2) 10µF, 25V Tai yo Yuden TMK432BJ106KM

(2) 330µF, 2V, 6m, low-ESR capacitor Panasonic EEFSX0D331XE SANYO 2TPE330M6

(1) Vishay/Siliconix SI7634DP

(2) Vishay/Siliconix SI7336ADP

3A, 40V Schottky diode Central Semiconductor CMSH3-40

0.45µH, 21A, 1.1m power inductor Panasonic ETQP4LR45WFC

OUT2

= 1.0V TO

OUT3

(1) 10µF, 6.3V TDK C2012X5R0J106M Tai yo Yuden JMK212BJ106M

(1) 220µF, 2V, 6m, low-ESR capacitor Panasonic EEFSD0D221R SANYO 2TPE220M6

None

1.5µH, 5A, 21m power inductor NEC/Tokin MPLCH0525LIR5 Toko FDV0530-1R5M

= 5V,

IN3

= 1.0V TO 1.3V,

—

OUT1

1.3V, 18A PER PHASE

Separate, 2-phase mobile (GNDS1 = GNDS2 = low)

(2) 10µF, 16V Tai yo Yuden TMK432BJ106KM

(2) 220µF, 2V, 6m, low-ESR capacitor Panasonic EEFSD0D221R SANYO 2TPE220M6

(1) International Rectifier IRF7811W

(2) Vishay/Siliconix SI7336ADP

3A, 40V Schottky diode Central Semiconductor CMSH3-40

0.36µH, 21A, 1.1m power inductor Panasonic ETQP4LR36WFC

= 4.5V TO 14V,

= V

OUT2

= 1.0V TO

= 3.3V,

IN3

= 1.0V TO 1.3V,

OUT3

(1) 10µF, 6.3V TDK C2012X5R0J106M Tai yo Yuden JMK212BJ106M

(1) 47µF, ceramic capacitor

None

0.6µH, 4.95A, 16m power inductor Sumida CDR6D23MN

—

MANUFACTURER WEBSITE

AVX Corporation www.avxcorp.com

BI Technologies www.bitechnologies.com

Central Semiconductor Corp.

Fairch ild Semiconductor www.fairchildsem i.com

Internationa l Rectifier www.irf.com

KEMET Corp. www.kemet.com

NEC TOKIN America, Inc. www.nec-tokinamerica.com

Panason ic Corp. www.panasonic.com

www.centralsemi.com

MANUFACTURER WEBSITE

Pulse Engineering www.pulseeng.com

Renesas Technology Corp. www.renesa s.com

SANYO Electric Co., Ltd. www.sanyodevice.com

Siliconix (Visha y) www.vi sha y.com

Sumida Corp. www.sumida.com

Taiyo Yuden www.t-yuden.com

TDK Corp. www.component.tdk.com

TOKO America, Inc. www.tokoam.com

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

22 ______________________________________________________________________________________

Figure 2. Griffin/Puma Standard Application Circuit

VCC

10Ω

1.5V OR 1.8V

SERIAL INPUT

5.25

4.25

0 0 1 1

(A)ILIM3

SMPS1

ADDR

BIT1 (VDD0) BIT2 (VDD1) BIT1 (VDD0) BIT2 (VDD1)

SMPS3

OFFSET (mV)

+12.5 +12.5

3.3V

GND

V GND

OFFSETOPTION

LX3_PK

2.7V TO 5.5V

/4A

OUT3

INTERNAL

4A NB

REGULATOR

NB SENSE_H

VCC

2.2µF

AGND

ON OFF

SMPS2

ADDR

BIT2 (VDD1) BIT1 (VDD0) BIT2 (VDD1) BIT1 (VDD0)

+3.3V

4-LEVEL ILIM3

IN_NB

OUT3

220µF

6mΩ

PWR

ILIM2

2x 100kΩ

1.5µH

OSC

THRM

IN_NB

BST3

0.1µF

0Ω

4700pF

ILIM1

NTC

AGND

PWR

AGND

OSC

TIME

ILIM12

DDIO

SVC

SVD

PGD_INSYSTEM POWER-GOOD

SHDN

OPTION

PWRGD

VRHOT

THRM

ILIM3V

3, 4

IN3

5, 6

LX3

BST3

OUT3

AGND

MAX17480

EP = PGND

PWR

BST1

DH1

DL1

CSP1

CSN1

0.22µF

LX1

AGND

CSP2

CSN2

AGND

BST2

FBAC1

FBDC1

GNDS1

DH2

DL2

0.22µF

LX2

C 2200pF

4700pF

AGND

FBAC2

FBDC2

GNDS2

C 2200pF

4700pF

AGND

PWR

BST1

CS1

CSN1

CS2

CSN2

BST2

FB1

FB2

FBAC1

2kΩ

FBDC1

2kΩ

100Ω

FBAC2

2kΩ

FBDC2

2kΩ

100Ω

C 1µF

CSP1

CSN1

CSP2

CSN2

PWR

CSP1

IN1

+5V

4V TO 26V

LX1RDCR1

LX1

CSP1

0.45µH

DCR1

CSN1

PWR

OUT1

2x 330µF 6mΩ

/18A

OUT1

TDC

CORE0 18A REGULATOR

VDD

NL1D

CSN1

CSP2

CSN2

PWR

NL2D

PWR

100Ω

IN2

4V TO 26V

LX2RDCR2

LX2

CSP2

CORE0 SENSE_H

0.45µH

DCR2

CSN2

PWR

OUT2

2x 330µF 6mΩ

OUT2

/18A

CORE1 18A REGULATOR

TDC

4700pF

AGND

CORE0 SENSE_L

100Ω

CORE1 SENSE_H

4700pF

AGND

POWER GROUND

ANALOG GROUND

CORE1 SENSE_L

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 23

Figure 3. Caspian/Tigris Standard Application Circuit

OPEN

REF

GND

OFFSETOPTION

0 0 1 1

LX3_PK

5.25

4.25

INTERNAL

4A NB

REGULATOR

(A)ILIM3

OFFSET (mV)

SERIAL INPUT

SMPS1

ADDR

BIT1 (VDD0) BIT2 (VDD1) BIT1 (VDD0) BIT2 (VDD1)

SMPS3

+12.50 +12.50

/4A

OUT3

VCC

2.2µF

AGND

1.5V OR 1.8V

ON OFF

SMPS2

ADDR

BIT2 (VDD1) BIT1 (VDD0) BIT2 (VDD1) BIT1 (VDD0)

+3.3V

4-LEVEL ILIM3

IN_NB

2.7V TO 5.5V

OUT3

220µF

6mΩ

NB SENSE_H

PWR

ILIM2

2x 100kΩ

1.5µH

100Ω

OSC

ILIM1

THRM

IN_NB

BST3

0.1µF

4700pF

VCC

10Ω

VDD

1µF

PWR

BST1

0.22µF

CS1

CSN1

AGND

CSP2

CS2

CSN2

AGND

BST2

0.22µF

FBAC1

2kΩ

FB1

2200pF

FBDC1

2kΩ

100Ω

4700pF

FBAC2

AGND

2kΩ

FB2

2200pF

FBDC2

2kΩ

FOR UNIFIED CORE OPERATION

NL1D

CSP1

NL2D

CONNECT GNDS2 TO V

MAX17480

BST1

DH1

DL1

CSP1

CSN1

CSP2

CSN2

BST2

DH2

DL2

FBAC1

FBDC1

LX1

LX2

OSC

TIME

ILIM12

DDIO

SVC

SVD

PGD_INSYSTEM POWER-GOOD

SHDN

OPTION

AGND

PWRGD

VRHOT

THRM

NTC

ILIM3V

3, 4

IN3

PWR

5, 6

LX3

BST3

OUT3

GNDS1

FBAC2

FBDC2

AGND

GNDS2

AGND

EP = PGND

PWR

IN1

PWR

CSP1

CSN1

CSP2

CSN2

IN2

PWR

100Ω

4700pF

AGND

CORE0 SENSE_L

100Ω

4700pF

AGND

DDIO

+5V

4V TO 26V

LX1RDCR1

LX1

4.5V TO 28V

LX2RDCR2

LX2

CORE0 SENSE_H

DDIO

CORE

CSP1

CSP2

0.45µH

DCR1

0.45µH

DCR2

CSN1

CSN2

/36A

CORE

TDC

OUT

3x330µF 6mΩ

PWR

POWER GROUND

ANALOG GROUND

36A CORE REGULATOR

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

24 ______________________________________________________________________________________

Figure 4. Functional Diagram

SHDN

AGND

OFS_EN

ADDR

PGD_IN

TIME

GNDS2

GNDS1

DDIO

SVC

SVD

FAULT1 FAULT2 FAULT3

SVI INTERFACE

7-BIT VID SKIP1

7-BIT VID SKIP2

7-BIT VID SKIP3

REF

(2.0V)

DAC1

DAC2

DAC3

REFOK

DACOUT1

DACOUT2

DACOUT3

DDIO

UVLO

COMBINE

DETECT

MAX17480

RUN

SMPS1 TARGET

AND SLEW

RATE BLOCK

SMPS2 TARGET

AND SLEW

RATE BLOCK

SMPS3 TARGET

AND SLEW

RATE BLOCK

GNDS MUX

BLANK1

TARGET1

GNDS1

BLANK2

TARGET2

GNDS2

BLANK3

TARGET3

COMBINE

0.3 x V

PWM_

SKIP_

PWM_

CSA_

TARGET_

IMAX_

IMIN_

SKIP_

CLOCK_

SLOPE_

COMBINE

SMPS1 AND

SMPS2 DRIVER

BLOCK

SMPS1 AND

SMPS2 PWM

BLOCK

PWR

VRHOT

THRM V

BST_

DH_

LX_

DL_

PGND

FBAC_

FBDC_

CSN_

CSP_

IMAX_

IMIN_

CSA_

REF

SKIP_

OFS_EN

ADDR

CLOCK1 CLOCK2 CLOCK3 I

SLOPE1

SLOPE2

SLOPE3

FBDC1

TARGET1

BLANK1

FBDC2

TARGET2

BLANK2

OUT3

TARGET3

BLANK3

SMPS1 FAULT

BLOCK

SMPS2 FAULT

BLOCK

SMPS3 FAULT

BLOCK

FAULT1

PGD1

PGD2

FAULT2

PGD3

FAULT3

TARGET3

SKIP3

CSP3

CSN3

SMPS3 DRIVER

BLOCK

ILIM12

OPTION

OSC

CURRENT

LIMIT

4-LEVEL DECODE

OSCILLATOR

OUT3 BST3

IN3

LX3

PGND

PWR

ILIM3 PWRGD

MAX17480

Detailed Description

The MAX17480 consists of a dual fixed-frequency PWM controller with external switches that generate the supply voltage for two independent CPU cores and one low-input-voltage internal switch SMPS for the separate NB SMPS. The CPU core SMPSs can be configured as independent outputs, or as a combined output by connecting the GNDS1 or GNDS2 pin-strap high (GNDS1 or GNDS2 pulled to 1.5V to 1.8V, which are the respective voltages for DDR3 and DDR2).

All three SMPSs can be programmed independently to any voltage in the VID table (see Table 4) using the serial VID interface (SVI). The CPU is the SVI bus master, while the MAX17480 is the SVI slave. Voltage transitions are commanded by the CPU as a single step command from one VID code to another. The MAX17480 slews the SMPS outputs at the slew rate programmed by the external R

TIME

resistor during VID transitions and the transi-

tion from boot mode to VID mode.

During startup, the MAX17480 SMPSs are always in pulse-skipping mode. After exiting the boot mode, the individual PSI_L bit sets the respective SMPS into pulse-skipping mode or forced-PWM mode, depending on the system power state, and adds the +12.5mV offset for core supplies if enabled by the OPTION pin. In combined mode, the PSI_L bit adds the +12.5mV offset if enabled by the OPTION pin, and switches from 1-phase pulse-skipping mode to 2-phase PWM mode. Figure 4 is the MAX17480 functional diagram.

+5V Bias Supply (VCC, VDD)

The MAX17480 requires an external 5V bias supply in addition to the battery. Typically, this 5V bias supply is the notebook’s main 95%-efficient 5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V linear SMPS that would otherwise be needed to supply the PWM circuit and gate drivers.

The 5V bias supply powers both the PWM controller and internal gate-drive power, so the maximum current drawn is:

BIAS

= ICC+ f

SW_COREQG_CORE

SW_NBQG_NB

= 50mA to 70mA (typ)

where ICCis provided in the

Electrical Characteristics

table, f

SW_CORE

and f

SW_NB

are the respective core

and NB SMPS switching frequencies, Q

G_CORE

is the

gate charge of the external MOSFETs as defined in the MOSFET data sheets, and Q

G_NB

is approximately

2nC. If the +5V bias supply is powered up prior to the battery supply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup.

Switching Frequency (OSC)

Connect a resistor (R

OSC

) between OSC and GND to

set the switching frequency (per phase):

fSW= 300kHz × 143kΩ/R

OSC

A 71.4kΩ to 432kΩ resistor corresponds to switching frequencies of 600kHz to 100kHz, respectively, for the core SMPSs, and 1.2MHz to 200kHz for the NB SMPS. Highfrequency (600kHz) operation for the core SMPS optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This might be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. Low-frequency (100kHz) operation offers the best overall efficiency at the expense of component size and board space.

The NB SMPS runs at twice the switching frequency of the core SMPSs. The low power of the NB rail allows for higher switching frequencies with little impact on the overall efficiency.

Minimum on-time (t

ON(MIN)

) must be taken into consideration when selecting a switching frequency. See the Core Switching Frequency description in the

SMPS

Design Procedure

section.

Interleaved Multiphase Operation

The MAX17480 interleaves both core SMPSs’ phases— resulting in 180° out-of-phase operation that minimizes the input and output filtering requirements, reduces electromagnetic interference (EMI), and improves efficiency. The high-side MOSFETs do not turn on simultaneously during normal operation. The instantaneous input current is effectively reduced by the number of active phases, resulting in reduced input-voltage ripple, effective series resistance (ESR) power loss, and RMS ripple current (see the

Core Input Capacitor Selection

section). Therefore, the controller achieves high performance while minimizing the component count—which reduces cost, saves board space, and lowers component power requirements—making the MAX17480 ideal for high-power, cost-sensitive applications.

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 25

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

26 ______________________________________________________________________________________

Transient Phase Repeat

When a transient occurs, the output voltage deviation depends on the controller’s ability to quickly detect the transient and slew the inductor current. A fixed-frequency controller typically responds only when a clock edge occurs, resulting in a delayed transient response. To minimize this delay time, the MAX17480 includes enhanced transient detection and transient phase repeat capabilities. If the controller detects that the output voltage has dropped by 41mV, the transient detection comparator immediately retriggers the phase that completed its on-time last. The controller triggers the subsequent phases as normal, on the appropriate oscillator edges. This effectively triggers a phase a full cycle early, increasing the total inductor-current slew rate and providing an immediate transient response.

Core SMPS Feedback

Adjustment Amplifiers

The MAX17480 provides an FBAC and FBDC pin for each SMPS to allow for flexible AC and DC droop settings. FBAC is the output of an internal transconductance amplifier that outputs a current proportional to the current-sense signal. FBDC is the feedback input that is compared against the internal target. Place resistors and capacitors at the FBAC and FBDC pins as shown in Figure 5. With this configuration, the DC droop is always less than or equal to the AC droop.

Core Steady-State Voltage Positioning (DC Droop)

FBDC is the feedback input to the error amplifier. Based on the configuration in Figure 5, the core SMPS output voltage is given by:

where the target voltage (V

TARGET

) is defined in the

Nominal Output-Voltage Selection

section, and the

FBAC amplifier’s output current (I

FBAC

) is determined

by each phase’s current-sense voltage:

where V

= V

CSP

- V

CSN

is the differential current-sense

voltage, and G

(FBAC)

is typically 2mS as defined in the

Electrical Characteristics

table. DC droop is typically used together with the +12.5mV offset feature to keep within the DC tolerance window of the application. See the

Offset

and Address Change for Core SMPSs (OPTION)

section. The ripple voltage on FBDC must be less than the -33mV (max) transient phase repeat threshold:

where ∆I

is the inductor ripple current, R

ESR

is the

effective output ESR at the remote sense point, R

SENSE

is the current-sense element, and G

(FBAC)

is 2.06mS

(max) as defined in the

Electrical Characteristics

table. The worst-case inductor ripple occurs at the maximum input-voltage and maximum output-voltage conditions:

To make the DC and AC load-lines the same, directly short FBAC to FBDC.

To disable DC voltage positioning, remove RFB, which connects FBAC to FBDC.

Core Transient Voltage-Positioning Amplifier

(AC Droop)

Each of the MAX17480 core supply SMPSs includes one transconductance amplifier for voltage positioning. The amplifiers’ inputs are generated by summing their respective current-sense inputs, which differentially sense the voltage across either current-sense resistor or the inductor’s DCR.

The voltage-positioning droop amplifier’s output (FBAC) connects to the remote-sense point of the output through an RC network that sets each phase’s AC voltage-positioning gain:

where the target voltage (V

TARGET

) is defined in the

Nominal Output-Voltage Selection

section, Z

CFB

is the effective impedance of CFB, and the FBAC amplifier’s output current (I

FBAC

) is determined by each phase’s

current-sense voltage:

Figure 5. Core SMPS Feedback Connection

MAX17480

ERROR

AMP

m(FBAC)

FBAC

FBDC

FBAC

FBDC

100Ω

4700pF

AGND

CSP

CSN

TARGET

=−

OUT TARGET

FBDC FBAC

RRR

FBAC FBDC FB

CORE SENSE_H

AAC

RRR

FBAC FBDC FB

OUT TARGET

IGV

FBAC m FBAC CS

()

FBAC

FBDC

∆I

LMAX

()

IR G R

L SENSE m FBAC FBDC

mV I R R R

66≤−

()

RIRG mV

∆−66

FBAC L SENSE m FBAC

()

∆

L ESR FBAC F

()

VVV

OUT MAX IN MAX OUT MAX

()

() () ()

AAX SW

)

IN M

(

+∆

−

∆∆IR

L ESR

)

33≤

=−

RR RZ

FBAC FBDC FB CF

FBAC FBDC

++

FBDC

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 27

where VCS= V

CSP

- V

CSN

is the differential current-

sense voltage, and G

(FBAC)

is 2.06mS (max) as

defined in the

Electrical Characteristics

table.

AC droop is required for stable operation of the MAX17480. A minimum of 1.5mV/A is recommended. AC droop must not be disabled.

Core Differential Remote Sense

The MAX17480 controller includes independent differential, remote-sense inputs for each CPU core to eliminate the effects of voltage drops along the PCB traces and through the processor’s power pins. The feedback-sense (FBDC_) input connects to the remote-sensed output through the resistance at FBDC_ (R

FBDC_

). The groundsense (GNDS_) input connects to an amplifier that adds an offset directly to the target voltage, effectively adjusting the output voltage to counteract the voltage drop in the ground path. Connect the feedback-sense (FBDC_) R

FBDC_

resistor and ground-sense (GNDS_) input directly to the respective CPU core’s remotesense outputs as shown in Figure 2.

GNDS1 and GNDS2 are dual-function pins. At power-on, the voltage levels on GNDS1 and GNDS2 configure the MAX17480 as two independent switching SMPSs, or one higher current 2-phase SMPS. Keep both GNDS1 and GNDS2 low during power-up to configure the MAX17480 in separate mode. Connect GNDS1 or GNDS2 to a voltage above 0.8V (typ) for combined-mode operation. In the AMD mobile system, this is automatically done by the CPU that is plugged into the socket that pulls GNDS1 or GNDS2 the V

DDIO

voltage level.

When GNDS1 is pulled high to indicate combinedmode operation, the remote ground sense is automatically switched to GNDS2. When GNDS2 is pulled high to indicate combined-mode operation, the remote ground sense is automatically switched to GNDS1. GNDS1 and GNDS2 do not dynamically switch in the real application. It is only switched when one CPU is removed (e.g., split-core CPU), and another is plugged in (e.g., combined-core CPU). This should not be done when the socket is “hot” (i.e., powered).

The MAX17480 checks the GNDS1 and GNDS2 levels at the time when the internal REFOK signal goes high, and latches the operating mode information (separate or combined mode). This latch is cleared by cycling the SHDN pin.

Core Integrator Amplifier

An internal integrator amplifier forces the DC average of the FBDC_ voltage to equal the target voltage. This transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure 4), allowing accurate DC output-voltage regulation regardless of the output ripple voltage.

The MAX17480 disables the integrator during downward VID transitions done in pulse-skipping mode. The integrator remains disabled until the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator).

The integrator amplifier can shift the output voltage by ±80mV (min). The maximum difference between transient AC droop and DC droop should not exceed ±80mV at the maximum allowed load current to guarantee proper DC output-voltage accuracy over the full load conditions.

NB SMPS Feedback Adjustment Amplifiers

NB Steady-State Voltage Positioning (DC Droop)

The NB SMPS has a built-in load-line that is -5.5mV/A. The output peak voltage (V

OUT3_PK+

) is set to:

where the target voltage (V

TARGET3

) is defined in the

Nominal Output-Voltage Selection

section, f

SW3

is the

NB switching frequency, and I

LOAD3

is the output load

current of the NB SMPS.

2-Wire Serial Interface (SVC, SVD)

The MAX17480 supports the 2-wire, write-only, serialinterface bus as defined by the AMD serial VID interface specification. The serial interface is similar to the high-speed 3.4MHz I2C bus, but without the master mode sequence. The bus consists of a clock line (SVC) and a data line (SVD). The CPU is the bus master, and the MAX17480 is the slave. The MAX17480 serial interface works from 100kHz to 3.4MHz. In the AMD mobile application, the bus runs at 3.4MHz.

The serial interface is active only after PGD_IN goes high in the startup sequence. The CPU sets the VID voltage of the three internal DACs and the PSI_L bit through the serial interface.

During the startup sequence, the SVC and SVD inputs serve an alternate function to set the 2-bit boot VID for all three DACs while PWRGD is low.

IGV

FBAC m FBAC CS

()

V V mV/A (I

OUT3_PK TARGET3 LOAD3

=−×+55

−

VV V

()

IN OUT OUT

33 3

××

LV f

33 3

IN SW

∆∆I

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

28 ______________________________________________________________________________________

Nominal Output-Voltage Selection

Core SMPS Output Voltage

The nominal no-load output voltage (V

TARGET

) for each SMPS is defined by the selected voltage reference (VID DAC) plus the remote ground-sense adjustment (V

GNDS

) and the offset voltage (V

OFFSET

) as defined in

the following equation:

where V

DAC

is the selected VID voltage of the core

SMPS DAC, V

GNDS

is the ground-sense correction volt-

age for core supplies, and V

OFFSET

is the +12.5mV offset enabled by the OPTION pin when the PSI_L is set high for core supplies.

NB SMPS Output Voltage

The nominal output voltage (V

TARGET

) for the NB is defined by the selected voltage reference (VID DAC) plus the offset voltage (V

OFFSET_NB

) as defined in the

following equation:

where V

DAC

is the selected VID voltage of the NB DAC,

and V

OFFSET_NB

is +12.5mV.

7-Bit DAC

Inside the MAX17480 are three 7-bit digital-to-analog converters (DACs). Each DAC can be individually programmed to different voltage levels by the serial-interface bus. The DAC sets the target for the output voltage for the core and NB SMPSs. The available DAC codes and resulting output voltages are compatible with the AMD SVI (Table 4) specifications.

Boot Voltage

On startup, the MAX17480 slews the target for all three DACs from ground to the boot voltage set by the SVC and SVD pin-voltage levels. While the output is still below regulation, the SVC and SVD levels can be changed, and the MAX17480 sets the DACs to the new boot voltage. Once the programmed boot voltage is reached and PWRGD goes high, the MAX17480 stores the boot VID. Changes in the SVC and SVD settings do not change the output voltage once the boot VID is stored. When PGD_IN goes high, the MAX17480 exits boot mode, and the three DACs can be independently set to any voltage in the VID table by the serial interface.

If PGD_IN goes from high to low any time after the boot VID is stored, the MAX17480 sets all three DACs back to the voltage of the stored boot VID.

Table 3 is the boot voltage code table.

Core SMPS Offset

A +12.5mV offset can be added to both core SMPS DAC voltages for applications that include DC droop. The offset is applied only after the MAX17480 exits boot mode (PGD_IN going from low to high), and the MAX17480 enters the serial-interface mode. The offset is disabled when the PSI_L bit is set, saving more power when the load is light.

The OPTION pin setting enables or disables the +12.5mV offset. Connect OPTION to OSC (2V) or GND to enable the offset. Keep OPTION connected to 3.3V or VCCto disable the offset. See the

Offset and

Address Change for Core SMPSs (OPTION)

section.

NB SMPS Offset

The NB SMPS output has a -5.5mV/A load line. A +12.5mV offset is added to keep the output within regulation over the full load. See the

Offset and Current-

Limit Setting for NB SMPS (ILIM3)

section.

Output-Voltage Transition Timing

SMPS Output-Voltage Transition

The MAX17480 performs positive voltage transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-intime arrival at the new output-voltage level with the lowest possible peak currents for a given output capacitance. The slew rate (set by resistor R

TIME

) must be set fast enough to ensure that the transition is completed within the maximum allotted time for proper CPU operation. R

TIME

is between 35.7kΩ and 357kΩ for cor-

responding slew rates between 25mV/µs to 2.5mV/µs, respectively, for the SMPSs.

At the beginning of an output-voltage transition, the MAX17480 blanks both PWRGD comparator thresholds, preventing the PWRGD open-drain output from changing states during the transition. At the end of an upward VID transition, the controller enables both PWRGD thresholds approximately 20µs after the slew-rate controller reaches the target output voltage. At the end

Table 3. Boot Voltage Code Table

VVVVV

TARGET FBDC DAC GNDS OFFSET

==++

VVVV

TARGET OUT DAC OFFSET NB33

==+

SVC SVD

0 0 1.1

0 1 1.0

1 0 0.9

1 1 0.8

BOOT VOLTAGE

(V)

OUT

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 29

of a downward VID transition, the upper PWRGD threshold is enabled only after the output reaches the lower VID code setting. Figure 6 shows VID transition timing.

The MAX17480 automatically controls the current to the minimum level required to complete the transition in the calculated time. The slew-rate controller uses an internal capacitor and current source programmed by R

TIME

to transition the output voltage. The total transi-

tion time depends on R

TIME

, the voltage difference, and

the accuracy of the slew-rate controller (C

SLEW

accuracy). The slew rate is not dependent on the total output capacitance, as long as the surge current is less than the current limit set by ILIM12 for the core SMPSs and ILIM3 for the NB SMPS. For all dynamic positive VID transitions or negative VID transitions in forcedPWM mode (PSI_L set to 1), the transition time (t

TRAN

)

is given by:

where dV

TARGET

/dt = 6.25mV/µs × 143kΩ/R

TIME

is the

slew rate, V

OLD

is the original output voltage, and V

NEW

is the new target voltage. See the Slew-Rate Accuracy in the

Electrical Characteristics

table for slew-rate limits.

The output voltage tracks the slewed target voltage, making the transitions relatively smooth. The average inductor current per phase required to make an output voltage transition is:

where dV

TARGET

/dt is the required slew rate and C

OUT

is the total output capacitance of each phase.

If the SMPS is in a pulse-skipping mode (PSI_L set to

0), the discharge rate of the output voltage during downward transitions is then dependent on the load current and total output capacitance for loads less than a minimum current, and dependent on the R

TIME

programmed slew rate for heavier loads. The critical load current (I

LOAD(CRIT)

) where the transition time is depen-

dent on the load is:

For load currents less than I

LOAD(CRIT)

, the transition

time is:

For soft-start, the controller uses a fixed slew rate of 1mV/µs. In shutdown, the outputs are discharged using a 20Ω switch through the CSN_ pins for the core SMPSs and through the OUT3 pin for the NB SMPS.

Forced-PWM Operation

After exiting the boot mode and if the PSI_L bit is set to 1, the MAX17480 operates with the low-noise, forcedPWM control scheme. Forced-PWM operation disables the zero-crossing comparator, forcing the low-side gate-drive waveforms to constantly be the complement of the high-side gate-drive waveforms. This keeps the switching frequency constant and allows the inductor current to reverse under light loads, providing fast, accurate negative output-voltage transitions by quickly discharging the output capacitors.

Forced-PWM operation comes at a cost: the no-load +5V bias supply current remains between 50mA to 70mA,

Figure 6. VID Transition Timing

SVC/SVD BUS IDLE BUS IDLEBUS IDLE

SMPS LOAD LIGHT LOAD HEAVY LOAD

PWRGD UPPER THRESHOLD

SMPS VOLTAGE (SMPS TARGET)

PWRGD LOWER

THRESHOLD

PWRGD

UPPER THRESHOLD BLANKED

SMPS TARGET

BLANK

HIGH-Z

s20

−

⎡

NEW OLD

TRAN

⎣

dV d t

()

TARGET

⎤

⎦

IC dV dt

≅×

L OUT TARGET

()

BLANK

HIGH-Z

s20

BLANK HIGH-Z

ICdVdt

LOAD CRIT OUT TARGET()

()

/≅×

CdV

TRAN

OUT TARGET

≅

LOAD

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

30 ______________________________________________________________________________________

depending on the external MOSFETs and switching frequency. To maintain high efficiency under light load conditions, the processor could switch the controller to a low-power pulse-skipping control scheme.

Pulse-Skipping Operation

During soft-start and in power-saving mode—when the PSI_L bit is set to 0—the MAX17480 operates in pulseskipping mode. Pulse-skipping mode enables the driver’s zero-crossing comparator, so the driver pulls its DL low when “zero” inductor current is detected (V

GND

- VLX=

0). This keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under light load conditions to avoid overcharging the output.

In pulse-skipping operation, the controller terminates the on-time when the output voltage exceeds the feedback threshold and when the current-sense voltage exceeds the idle-mode current-sense threshold (V

IDLE

= 0.15 x V

LIMIT

for the core SMPS and I

LX3MIN

= 0.25 x

LX3PK

setting for the NB SMPS). Under heavy load conditions, the continuous inductor current remains above the idle-mode current-sense threshold, so the on-time depends only on the feedback voltage threshold. Under light load conditions, the controller remains above the feedback voltage threshold, so the on-time duration depends solely on the idle-mode currentsense threshold, which is approximately 15% of the fullload peak current-limit threshold set by ILIM12 for the core SMPSs and 25% of the full-load peak current-limit threshold set by ILIM3 for the NB SMPS.

During downward VID transitions, the controller temporarily sets the OVP threshold of the SMPSs to 1.85V (typ), preventing false OVP faults. Once the error amplifier detects that the output voltage is in regulation, the OVP threshold tracks the selected VID DAC code.

Each SMPS can be individually set to operate in pulseskipping mode when its PSI_L bit is set to 0, or set to operate in forced-PWM mode when its PSI_L bit is set to 1.

When the core SMPSs are configured for combinedmode operation, core supplies operate in 1-phase pulse-skipping mode when PSI_L = 0, and core supplies are in 2-phase forced-PWM mode when PSI_L = 1.

Idle-Mode Current-Sense Threshold

The idle-mode current-sense threshold forces a lightly loaded SMPS to source a minimum amount of power with each on-time since the controller cannot terminate the on-time until the current-sense voltage exceeds the idle-mode current-sense threshold (V

IDLE

= 0.15 x

LIMIT

for the core SMPS and I

LX3MIN

= 0.25 x I

LX3PK

setting for the NB SMPS). Since the zero-crossing comparator prevents the switching SMPS from sinking

current, the controller must skip pulses to avoid overcharging the output. When the clock edge occurs, if the output voltage still exceeds the feedback threshold, the controller does not initiate another on-time. This forces the controller to actually regulate the valley of the output voltage ripple under light load conditions.

Automatic Pulse-Skipping Crossover

In skip mode, the MAX17480 zero-crossing comparators are active. Therefore, an inherent automatic switchover to PFM takes place at light loads, resulting in a highly efficient operating mode. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current’s zero crossing. The driver’s zero-crossing comparator senses the inductor current across the low-side MOSFET. Once V

GND

- VLXdrops below the zero-crossing threshold, the driver forces DL low. This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). The load-current level at which the PFM/PWM crossover occurs, I

LOAD(SKIP)

, is given by:

The switching waveforms can appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-off in PFM noise vs. light-load efficiency is made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels).

Current Sense

Core SMPS Current Sense

The output current of each phase is sensed differentially. A low offset voltage and high-gain differential current amplifier at each phase allows low-resistance currentsense resistors to be used to minimize power dissipation. Sensing the current at the output of each phase offers advantages, including less noise sensitivity, more accurate current sharing between phases, and the flexibility of using either a current-sense resistor or the DC resistance of the output inductor.

LOAD SKIP

()

VVV

OUT IN OUT

−

()

Vf L

IN SW

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 31

When using a current-sense resistor for accurate outputvoltage positioning, the circuit requires a differential RC filter to eliminate the AC voltage step caused by the equivalent series inductance (L

ESL

) of the current-sense resistor (see Figure 7). The ESL-induced voltage step does not affect the average current-sense voltage, but

results in a significant peak current-sense voltage error that results in unwanted offsets in the regulation voltage and early current-limit detection. Similar to the inductor DCR sensing method above, the RC filter’s time constant should match the L/R time constant formed by the current-sense resistor’s parasitic inductance:

Table 4. Output-Voltage VID DAC Codes

Note: The NB SMPS output voltage has an offset of +12.5mV.

SVID[6:0]

000_0000 1.5500 010_0000 1.1500 100_0000 0.7500 110_0000 0.3500

000_0001 1.5375 010_0001 1.1375 100_0001 0.7375 110_0001 0.3375

000_0010 1.5250 010_0010 1.1250 100_0010 0.7250 110_0010 0.3250

000_0011 1.5125 010_0011 1.1125 100_0011 0.7125 110_0011 0.3125

000_0100 1.5000 010_0100 1.1000 100_0100 0.7000 110_0100 0.3000

000_0101 1.4875 010_0101 1.0875 100_0101 0.6875 110_0101 0.2875

000_0110 1.4750 010_0110 1.0750 100_0110 0.6750 110_0110 0.2750

000_0111 1.4625 010_0111 1.0625 100_0111 0.6625 110_0111 0.2625

000_1000 1.4500 010_1000 1.0500 100_1000 0.6500 110_1000 0.2500

000_1001 1.4375 010_1001 1.0375 100_1001 0.6375 110_1001 0.2375

000_1010 1.4250 010_1010 1.0250 100_1010 0.6250 110_1010 0.2250

000_1011 1.4125 010_1011 1.0125 100_1011 0.6125 110_1011 0.2125

000_1100 1.4000 010_1100 1.0000 100_1100 0.6000 110_1100 0.2000

000_1101 1.3875 010_1101 0.9875 100_1101 0.5875 110_1101 0.1875

000_1110 1.3750 010_1110 0.9750 100_1110 0.5750 110_1110 0.1750

000_1111 1.3625 010_1111 0.9625 100_1111 0.5625 110_1111 0.1625

001_0000 1.3500 011_0000 0.9500 101_0000 0.5500 111_0000 0.1500

001_0001 1.3375 011_0001 0.9375 101_0001 0.5375 111_0001 0.1375

001_0010 1.3250 011_0010 0.9250 101_0010 0.5250 111_0010 0.1250

001_0011 1.3125 011_0011 0.9125 101_0011 0.5125 111_0011 0.1125

001_0100 1.3000 011_0100 0.9000 101_0100 0.5000 111_0100 0.1000

001_0101 1.2875 011_0101 0.8875 101_0101 0.4875 111_0101 0.0875

001_0110 1.2750 011_0110 0.8750 101_0110 0.4750 111_0110 0.0750

001_0111 1.2625 011_0111 0.8625 101_0111 0.4625 111_0111 0.0625

001_1000 1.2500 011_1000 0.8500 101_1000 0.4500 111_1000 0.0500

001_1001 1.2375 011_1001 0.8375 101_1001 0.4375 111_1001 0.0375

001_1010 1.2250 011_1010 0.8250 101_1010 0.4250 111_1010 0.0250

001_1011 1.2125 011_1011 0.8125 101_1011 0.4125 111_1011 0.0125

001_1100 1.2000 011_1100 0.8000 101_1100 0.4000 111_1100 OFF

001_1101 1.1875 011_1101 0.7875 101_1101 0.3875 111_1101 OFF

001_1110 1.1750 011_1110 0.7750 101_1110 0.3750 111_1110 OFF

001_1111 1.1625 011_1111 0.7625 101_1111 0.3625 111_1111 OFF

OUTPUT

VOLTAGE

(V)

SVID[6:0]

OUTPUT

VOLTAGE

(V)

SVID[6:0]

OUTPUT

VOLTAGE

(V)

SVID[6:0]

OUTPUT

VOLTAGE

(V)

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

32 ______________________________________________________________________________________

where L

ESL

is the equivalent series inductance of the

current-sense resistor, R

SENSE

is current-sense resis-

tance value, and C

SENSE

and REQare the time-con-

stant matching components.

Using the DC resistance (R

DCR

) of the output inductor allows higher efficiency. In this configuration, the initial tolerance and temperature coefficient of the inductor’s DCR must be accounted for in the output-voltage droop-error budget and power monitor. This currentsense method uses an RC filtering network to extract the current information from the output inductor (see Figure 7). The time constant of the RC network should match the inductor’s time constant (L/R

DCR

where C

SENSE

and REQare the time-constant matching

components. To minimize the current-sense error due to

the current-sense inputs’ bias current (I

CSP

and I

CSN

), choose REQless than 2kΩ and use the above equation to determine the sense capacitance (C

SENSE

). Choose capacitors with 5% tolerance and resistors with 1% tolerance specifications. Temperature compensation is recommended for this current-sense method. See the

Core Voltage Positioning and Loop Compensation

sec-

tion for detailed information.

Additional RLXand CLXare always added between the LX_ and CSP_ pins if DCR sensing is used, and they provide additional overdrive to the current-sense signal to improve the noise immunity; otherwise, there might be too much jitter or the system could be unstable.

NB SMPS Current Sense

The NB current sense is achieved by sensing the voltage across the high-side internal MOSFET during the on-time. The current information is computed by dividing the sensed voltage by the MOSFET’s on-resistance, R

ON(NH3)

Figure 7. Current-Sense Configurations

INPUT (VIN)

A) OUTPUT SERIES RESISTOR SENSING

MAX17480

DH_

LX_

DL_

CSP_

CSN_

DH_

LX_

DL_

CSP_

CSN_

NLD

INPUT (VIN)

SENSE RESISTOR

ESL

INDUCTOR

SENSE

DCR

ESL

CEQREQ =

R2R1

OUT

FOR THERMAL COMPENSATION: R2 SHOULD CONSIST OF AN NTC RESISTOR IN SERIES WITH A STANDARD THIN-FILM RESISTOR.

SENSE

RCS = × R

R1 + R2

= +×

DCR

1R11

B) LOSSLESS INDUCTOR DCR SENSING

ESL

SENSE

EQ SENSE

DCR

EQ SENSE

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 33

Combined-Mode Current Balance

When the core SMPSs are configured in combined mode (GNDS1 or GNDS2 pulled to V

DDIO

), the MAX17480 current-mode architecture automatically forces the individual phases to remain current balanced. SMPS1 is the main voltage-control loop, and SMPS2 maintains the current balance between the phases. This control scheme regulates the peak inductor current of each phase, forcing them to remain properly balanced. Therefore, the average inductor current variation depends mainly on the variation in the currentsense element and inductance value.

Peak Current Limit

The MAX17480 current-limit circuit employs a fast peak inductor current-sensing algorithm. Once the currentsense signal of the SMPS exceeds the peak current-limit threshold, the PWM controller terminates the on-time. See the

Core Peak Inductor Current Limit (ILIM12)

sec-

tion in the

Core SMPS Design Procedure

section.

Power-Up Sequence (POR, UVLO, PGD_IN)

Power-on reset (POR) occurs when VCCrises above approximately 3V, resetting the fault latch and preparing the controller for operation. The VCCundervoltage-lockout (UVLO) circuitry inhibits switching until V

rises above

4.25V (typ). The controller powers up the reference once the system enables the controller V

above 4.25V and

SHDN is driven high. With the reference in regulation, the controller ramps the SMPS and NB voltages to the boot voltage set by the SVC and SVD inputs:

The soft-start circuitry does not use a variable current limit, so full output current is available immediately. PWRGD becomes high impedance approximately 20µs after the SMPS outputs reach regulation. The boot VID is stored the first time PWRGD goes high. The MAX17480 is in pulse-skipping mode during soft-start. Figure 8 shows the MAX17480 startup sequence.

Figure 8. Startup Sequence

DC_IN

DDIO

1234 5 6

START

BOOT

1/µ

mV s

()

SVC/SVD

SHDN

GNDS1 OR GNDS2

(VDD_PLANE_STRAP)

SMPS V

OUT

PWRGD

PGD_IN

RESET_L

2-BIT BOOT VID SERIAL MODE

20µs

10µs

BUS IDLE

BLANK HIGH-Z

20µs

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

34 ______________________________________________________________________________________

For automatic startup, the battery voltage should be present before VCC. If the controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. The controller remains shut down until the fault latch is cleared by toggling SHDN or cycling the V

power supply below 0.5V.

If the V

voltage drops below 4.25V, the controller assumes that there is not enough supply voltage to make valid decisions and could also result in the stored boot VIDs being corrupted. As such, the MAX17480 immediately stops switching (DH_ and DL_ pulled low), latches off, and discharges the outputs using the internal 20Ω switches from CSN_ to GND.

Notes for Figure 8:

1) The relationship between DC_IN and V

DDIO

is not

guaranteed. It is possible to have V

DDIO

powered when DC_IN is not powered, and it is possible to have DC_IN power up before V

DDIO

powers up.

2) As the V

DDIO

power rail comes within specification, VDD_Plane_Strap becomes valid and SVC and SVD are driven to the boot VID value by the processor. The system guarantees that V

DDIO

is in specifica-

tion and SVC and SVD are driven to the boot VID value for at least 10µs prior to SHDN being asserted to the MAX17480.

3) After SHDN is asserted, the MAX17480 samples and

latches the VDD_Plane_Strap level at its GNDS1 and GNDS2 pins when REF reaches the REFOK threshold, and ramps up the voltage plane outputs to the level indicated by the 2-bit boot VID. The boot VID is stored in the MAX17480 for use when PGD_IN deasserts. The MAX17480 soft-starts the output rails to limit inrush current from the DC_IN rail. The MAX17480 operates in pulse-skipping mode in the boot mode regardless of PSI_L settings.

4) The MAX17480 asserts PWRGD. After PWRGD is asserted and all system-wide voltage planes and free-running clocks are within specification, then the system asserts PGD_IN.

5) The processor holds the 2-bit boot VID for at least 10µs after PGD_IN is asserted.

6) The processor issues the set VID command through SVI.

7) The MAX17480 transitions the voltage planes to the set VID. The set VID can be greater than or less than the boot VID voltage. The MAX17480 operates in pulse-skipping mode or forced-PWM mode according to the PSI_L setting.

8) The chipset enforces a 1ms delay between PGD_IN assertion and RESET_L deassertion.

PWRGD

The MAX17480 features internal power-good fault comparators for each SMPS. The outputs of these individual power-good fault comparators are logically ORed to drive the gate of the open-drain PWRGD output transistor. Each SMPS’s power-good fault comparator has an upper threshold of +200mV (typ) and a lower threshold of -300mV (typ). PWRGD goes low if the output of either SMPS exceeds its respective threshold.

PWRGD is forced low during the startup sequence up to 20µs after the output is in regulation. The 2-bit boot VID is stored when PWRGD goes high during the startup sequence. PWRGD is immediately forced low when SHDN goes low.

PWRGD is blanked high impedance while any of the internal SMPS DACs are slewing during a VID transition, plus an additional 20µs after the DAC transition is completed. For downward VID transitions, the upper threshold of the particular power-good fault comparators remains blanked until the output reaches regulation again.

PWRGD is blanked high impedance for each SMPS whose internal DAC is in off mode, and is pulled low if all three SMPS DACs are in off mode.

PGD_IN

After the SMPS outputs reach the boot voltage, the MAX17480 switches to the serial-interface mode when PGD_IN goes high. Anytime during normal operation, a high-to-low transition on PGD_IN causes the MAX17480 to slew all three internal DACs back to the stored boot VIDs. The SVC and SVD inputs are disabled during the time that PGD_IN is low. The serial interface is reenabled when PGD_IN goes high again. Figure 9 shows PGD_IN timing.

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 35

Shutdown

When SHDN goes low, the MAX17480 enters shutdown mode. PWRGD is pulled low immediately and forces all DH and DL low, and all three outputs are discharged through the 20Ω internal discharge FETs through the CSN pin for core SMPSs and through the OUT3 pin for NB SMPSs.

VRHOT

Temperature Comparator

The MAX17480 features an independent comparator with an accurate threshold (V

HOT

) that tracks the analog sup-

ply voltage (V

HOT

= 0.3VCC). Use a resistor- and thermis-

tor-divider between VCCand GND to generate a

voltage-SMPS overtemperature monitor. Place the thermistor as close as possible to the MOSFETs and inductors.

Place three individual thermistors near to each SMPS to monitor the temperature of the respective SMPS. When core SMPSs are in combined-mode operation, the current-balance circuit balances the currents between core SMPS phases. As such, the power loss and heat in each phase should be identical, apart from the effects of placement and airflow over each phase. Single thermistors can be placed near either of the phases and still be effective for core SMPS temperature monitoring, and one thermistor can be saved. See Figure 10.

MAX17480

THRM

NTC

GND

PLACE R

NTC

NEXT TO THE

HOTTEST POWER COMPONENT.

MAX17480

THRM

PTC2

THRM

GND

PLACE R

PTC1

, R

PTC2

, AND R

PTC3

NEXT TO THE RESPECTIVE SMPS'S POWER COMPONENT.

PTC1

PTC3

Figure 10. THRM Configuration

20µs

2-BIT BOOT VID, SVC/SVD INPUTS DISABLED

PSI_L

PGD_IN

PWRGD

SMPS V

OUT

(HIGH DAC TARGET)

(LOW DAC TARGET)

SMPS V

OUT

SVC/SVD BUS IDLE BUS IDLE

PULSE-SKIPPING MODE

TARGET

OUT

BLANK HIGH-Z

BLANK

HIGH-Z

Figure 9. PGD_IN Timing

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

36 ______________________________________________________________________________________

Fault Protection (Latched)

Output Overvoltage Protection (OVP)

The overvoltage protection (OVP) circuit is designed to protect the CPU against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The MAX17480 continuously monitors the output for an overvoltage fault. The controller detects an OVP fault if the output voltage exceeds the set VID DAC voltage by more than 300mV. The OVP threshold tracks the VID DAC voltage except during a downward VID transition. During a downward VID transition, the OVP threshold is set at 1.85V (typ) until the output reaches regulation, when the OVP threshold is reset back to 300mV above the VID setting.

When the OVP circuit detects an overvoltage fault in core SMPSs, it immediately sets the fault latch and forces the external low-side driver high on the faulted SMPS. The nonfaulted SMPSs are also shut down by turning on the internal passive discharge MOSFET. The synchronous-rectifier MOSFETs of the faulted side are turned on with 100% duty, which rapidly discharges the output filter capacitor and forces the output low. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse blows. Toggle SHDN or cycle the VCCpower supply below

0.5V to clear the fault latch and reactivate the controller.

When the core SMPSs are configured in combined mode, the synchronous-rectifier MOSFETs of both phases are turned on with 100% duty in response to an overvoltage fault. Passive shutdown is initiated for the NB SMPS.

The NB SMPS has no OVP.

Output Undervoltage Protection (UVP)

If any of the MAX17480 output voltages are 400mV below the target voltage, the controller sets the fault latch, shuts down all the SMPSs, and activates the internal passive discharge MOSFET. Toggle SHDN or cycle the VCCpower supply below 0.5V to clear the fault latch and reactivate the controller.

VCCUndervoltage-Lockout (UVLO) Protection

If the VCCvoltage drops below 4.2V (typ), the controller assumes that there is not enough supply voltage to make valid decisions and sets a fault latch. During a UVLO fault, the controller shuts down all the SMPSs immediately, forces DL and DH low, and pulls CSN1, CSN2, and OUT3 low through internal 20Ω discharge FETs. If the VCCfalls below the POR threshold (1.8V, typ), DL is forced low even if it was previously high due to a latched overvoltage fault.

Toggle SHDN or cycle the VCCpower supply below

0.5V to clear the fault latch and reactivate the controller.

DDIO

Undervoltage-Lockout (UVLO) Protection

If the V

DDIO

voltage drops below 0.7V (typ), the controller assumes that there is not enough supply voltage to make valid decisions and sets a UV fault latch. During V

DDIO

UVLO, as with UVP, the controller shuts down all the SMPSs immediately, forces DL and DH low, and pulls CSN1, CSN2, and OUT3 low through internal 20Ω discharge FETs. If the VCCfalls below the POR threshold (1.8V, typ), DL is forced low even if it was previously high due to a latched overvoltage fault.

Toggle SHDN or cycle the VCCpower supply below

0.5V to clear the fault latch and reactivate the controller.

Thermal Fault Protection

The MAX17480 features a thermal fault protection circuit. When the junction temperature rises above +160°C, a thermal sensor sets the fault latch and shuts down immediately, forcing DH and DL low and turning on the 20Ω discharge FETs for all SMPSs. Toggle SHDN or cycle the VCCpower supply below 0.5V to clear the fault latch and reactivate the controller after the junction temperature cools by 15°C.

Other Fault Protection (Nonlatched)

IN3

Undervoltage-Lockout (UVLO) Protection

If the V

IN3

voltage drops below 2.5V (typ), the controller assumes that there is not enough input voltage for NB SMPSs. If V

IN3

UVLO happens before or just after softstart, the NB SMPS is disabled and the internal target voltage stays off. When the V

IN3

subsequently rises past its UVLO rising threshold 2.6V (typ), NB goes through the soft-start sequence with a 1mV/µs slew rate.

If V

IN3

UVLO happens while the MAX17480 is running, the NB SMPS is stopped, the NB target is reset to 0 immediately, and PWRGD is forced low. When V

IN3

subsequently rises above the UVLO rising threshold

2.6V (typ), the NB SMPS restarts with 1mV/µs slew rate to the previous DAC target.

Core SMPS MOSFET Gate Drivers

The DH and DL drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications where a large VIN- V

OUT

differential exists. The high-side gate drivers (DH) source and sink 2.2A, and the low-side gate drivers (DL) source 2.7A and sink 8A. This ensures robust gate drive for high-current applications. The DH floating high-side MOSFET drivers are powered by internal boost switch charge pumps at BST, while the DL synchronous-rectifier drivers are powered directly by the 5V bias supply (VDD).

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 37

Adaptive dead-time circuits monitor the DL and DH drivers and prevent either FET from turning on until the other is fully off. The adaptive driver dead time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency.

There must be a low-resistance, low-inductance path from the DL and DH drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17480 interprets the MOSFET gates as “off” while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver).

The internal pulldown transistor that drives DL low is robust, with a 0.25Ω (typ) on-resistance. This helps prevent DL from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX) quickly switches from ground to VIN. Applications with high input voltages and long inductive driver traces could require rising LX edges that do not pull up the low-side MOSFET’s gate, causing shoot-through currents. The capacitive coupling between LX and DL created by the MOSFET’s gate-todrain capacitance (C

RSS

), gate-to-source capacitance

ISS

- C

RSS

), and additional board parasitics should not

exceed the following minimum threshold:

Typically, adding a 4700pF capacitor between DL and power ground (CNLin Figure 11), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays.

Alternatively, shoot-through currents can be caused by a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually turned off. Adding a resistor less than 5Ω in series with BST slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading the turn-off time (R

BST

in Figure 11). Slowing down the high-side MOSFET also reduces the LX node rise time, thereby reducing EMI and high-frequency coupling responsible for switching noise.

Offset and Address Change

for Core SMPSs (OPTION)

The +12.5mV offset and the address change features of the MAX17480 can be selectively enabled and disabled by the OPTION pin setting. When the offset is

enabled, setting the PSI_L bit to 0 disables the offset, reducing power consumption in the low-power state. See the

Core SMPS Offset

section for a detailed

description of this feature.

In addition, the address of the core SMPSs can be exchanged, allowing for flexible layout of the MAX17480 with respect to the CPU placement on the same or opposite sides of the PCB. Table 5 shows the OPTION pin voltage levels and the features that are enabled.

Figure 11. Gate-Drive Circuit

Table 5. OPTION Pin Settings

Note: VDD0 refers to CORE0 and VDD1 refers to CORE1 for

the AMD CPU.

⎛

⎞

GS TH IN

()

RSS

⎜

⎟

⎝

⎠

ISS

MAX17480

)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING

BST

)* OPTIONAL—THE CAPACITOR REDUCES LX-TO-DL CAPACITIVE

THE SWITCHING NODE RISE TIME.

COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.

BST

PGND

BST

BYP

(CNL)*

INPUT (V

)

OPTION

VCC 0 BIT 1 (VDD0) BIT 2 (VDD1)

3.3V 0 BIT 2 (VDD1) BIT 1 (VDD0)

2V 1 BIT 1 (VDD0) BIT 2 (VDD1)

GND 1 BIT 2 (VDD1) BIT 1 (VDD0)

OFFSET

ENABLES

SMPS1

ADDRESS

SMPS2

ADDRESS

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

38 ______________________________________________________________________________________

Offset and Current-Limit Setting

for NB SMPS (ILIM3)

The offset and current-limit settings of the NB SMPS can be set by the ILIM3 pin setting. Table 6 shows the ILIM3 pin voltage levels and the corresponding settings for the offset and current limit of the NB SMPS. The NB offset is always present regardless of PSI_L setting.

The I

LX3MIN

minimum current-limit threshold in skip mode is precisely 25% of the corresponding positive current-limit threshold.

SMPS Design Procedure

Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design:

• Input Voltage Range: The maximum value (V

IN(MAX)

) must accommodate the worst-case high AC adapter voltage. The minimum value (V

IN(MIN)

) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency.

• Maximum Load Current: There are two values to consider. The peak load current (I

LOAD(MAX)

) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (I

LOAD

) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit I

LOAD

LOAD(MAX)

x 80%.

For multiphase systems, each phase supports a fraction of the load, depending on the current balancing. When properly balanced, the load current is evenly distributed among each phase:

where ηPHis the total number of active phases.

• Core Switching Frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and V

. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical.

When selecting a switching frequency, the minimum on-time at the highest input voltage and lowest output voltage must be greater than the 150ns (max) minimum on-time specification in the

Electrical

Characteristics

table:

OUT(MIN)/VIN(MAX)

x tSW> t

ON(MIN)

A good rule is to choose a minimum on-time of at least 200ns.

When in pulse-skipping operation (PSI_L = 0), the minimum on-time must take into consideration the time needed for proper skip-mode operation. The ontime for a skip pulse must be greater than the 170ns (max) minimum on-time specification in the

Electrical

Characteristics

table:

• Inductor Operating Point: This choice provides trade-offs between size vs. efficiency and transient response vs. output noise. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current.

Table 6. ILIM3 Setting

ILIM3

VCC 5.25 1.3 4.75 -26.13 12.5

GND 4.25 1.05 3.75 -20.63 12.5

PEAK CURRENT

LIMIT (A)

SKIP CURRENT

LIMIT (A)

LOAD PHASE

()

LOAD

MAX DC

CURRENT (A)

ON MIN

()

FULL-LOAD

DROOP (mV)

≤

RV V

SENSE IN MA X OUT MIN

()

() ()

IDLE

−

OFFSET

(mV)

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 39

Core SMPS Design Procedure

Core Inductor Selection

By design, the AMD mobile serial VID application should regard each of the MAX17480 SMPSs as independent, single-phase SMPSs. The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows:

where I

LOAD(MAX)

is the maximum current per phase,

and fSWis the switching frequency per phase.

Find a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. If using a swinging inductor (where the inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. For the selected inductance value, the actual peak-to-peak inductor ripple current (∆I

INDUCTOR

) is defined by:

Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (I

PEAK

Core Peak Inductor Current Limit (ILIM12)

The MAX17480 overcurrent protection employs a peak current-sensing algorithm that uses either currentsense resistors or the inductor’s DCR as the currentsense element (see the

Current Sense

section). Since the controller limits the peak inductor current, the maximum average load current is less than the peak current-limit threshold by an amount equal to half the inductor ripple current. Therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and input-to-output voltage difference. When combined with the output undervoltage-protection circuit, the system is effectively protected against excessive overload conditions.

The peak current-limit threshold is set by the voltage difference between ILIM and REF using an external resistor-divider:

CS(PK)

= V

CSP

_ - V

CSN

_ = 0.052 x (V

REF

- V

ILIM12

)

LIMIT(PK)

= V

CS(PK)/RSENSE

where R

SENSE

is the resistance value of the currentsense element (inductors’ DCR or current-sense resistor), and I

LIMIT(PK)

is the desired peak current limit (per phase). The peak current-limit threshold voltage adjustment range is from 10mV to 50mV.

Core Output Capacitor Selection

The output filter capacitor must have low enough ESR to meet output ripple and load-transient requirements. In CPU V

CORE

converters and other applications where the output is subject to large load transients, the output capacitor’s size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance:

In non-CPU applications, the output capacitor’s size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor’s ESR. When operating multiphase systems out-ofphase, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage (V

RIPPLE

) by reducing the total inductor ripple current.

For nonoverlapping, multiphase operation (VIN≥ V

OUT

), the maximum ESR to meet the output-ripple-voltage requirement is:

where fSWis the switching frequency per phase. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor selection is usually limited by ESR and voltage rating rather than by capacitance value (this is true of polymer types).

The capacitance value required is determined primarily by the output transient-response requirements. Low inductor values allow the inductor current to slew faster, replenishing charge removed from or added to the output filter capacitors by a sudden load step. Therefore, the amount of output soar when the load is removed is a function of the output voltage and inductor value. The minimum output capacitance required to prevent overshoot (V

SOAR

) due to stored inductor energy can be

calculated as:

⎛

−

IN OUT

⎜

fI LIRVV

SW LOA D MAX

⎝

()

⎞

⎛

OUT

⎟

⎜⎜

⎟

⎝

⎠

⎞ ⎟ ⎠

∆I

INDUCTOR

VVV

OUT IN OUT

−

()

Vf L

IN SW

⎛

PEAK

LOAD MAX

⎜ ⎝

()

⎞

⎟ ⎠

⎛

∆

INDUCTOR

⎜ ⎝

⎞ ⎟

⎠

()

ESR PCB

≤

∆

STEP

()

LOAD MAX

⎡

Vf L

ESR

⎢

≤

⎢

⎣

IN SW

VV V

−

()

IN OUT OUT

⎤ ⎥

RI PPLE

⎥

⎦

()

∆

()

LOAD MAX

≥

OUT

OUT SOAR

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

40 ______________________________________________________________________________________

When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent V

SOAR

from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem.

Core Input Capacitor Selection

The input capacitor must meet the ripple-current requirement (I

RMS

) imposed by the switching currents.

For a dual 180° interleaved controller, the out-of-phase operation reduces the RMS input ripple current, effectively lowering the input capacitance requirements. When both outputs operate with a duty cycle less than 50% (VIN> 2V

OUT

), the RMS input ripple current is

defined by the following equation:

where IINis the average input current:

In combined mode (GNDS1 = V

DDIO

or GNDS2 =

DDIO

) with both phases active, the input RMS current

simplifies to:

For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. If the MAX17480 is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than +10°C temperature rise at the RMS input current for optimal circuit longevity.

Core Voltage Positioning and Loop Compensation

Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the output capacitance and processor’s power-dissipation requirements. The controller uses a transconductance amplifier to set the transient AC and DC output-voltage droop (Figure 5). The FBAC and FBDC configuration adjusts the steady-state regulation voltage as a function of the load. This adjustability allows flexibility in the selected current-sense resistor value or inductor DCR, and allows smaller current-sense resistance to be used, reducing the overall power dissipated.

Core Transient Droop and Stability

The inductor current ripple sensed across the currentsense inputs (CSP_ - CSN_) generates a proportionate current out of the FBAC pin. This AC current flowing across the effective impedance at FBAC generates an AC ripple voltage. Actual stability, however, depends on the AC voltage at the FBDC pin, and not on the FBAC pin. Based on the configuration shown in Figure 5, the ripple voltage at the FBDC pin can only be less than, or equal to, the ripple at the FBAC pin.

With the requirement that R

FBDC

= R

FBAC

, and

CFB

//RFB) < 10% of R

FBAC

, then:

where G

(FBAC_)

is typically 2mS as defined in the

Electrical Characteristics

table, R

SENSE_

is the effective value of the current-sense element that is used to provide the (CSP_, CSN_) current-sense voltage, and f

is the selected switching frequency.

Based on the above requirement for R

FBAC

and R

FBDC

and with the other requirement for R

FBDC

defined in the

Core Steady-State Voltage Positioning (DC Droop)

sec-

tion, R

FBAC

and R

FBDC

can be chosen. The resultant

AC droop is:

Capacitor CFBis required when the R

DROOP_DC

is less

than R

DROOP_AC

. Choose CFBaccording to the following

equation:

Core Steady-State Voltage Positioning

With R

DROOP_AC

defined, the steady-state voltage-

positioning slope, R

DROOP_DC

, can only be less than,

or at most equal to, R

DROOP_AC

Choose the R

FBDC

and R

FBAC

already previously cho-

sen, then select RFBto give the desired droop.

DC droop is typically used together with the +12.5mV offset feature to keep within the DC tolerance window of the application. See the

Offset and Address Change for

Core SMPSs (OPTION)

section.

RMS

⎛

⎞

OUT

⎜ ⎝

II I

OUT OUT IN

⎟

⎠

()

⎛

⎞

OUT

−

⎜ ⎝

II I

OUT OUT IN

⎟

⎠

()

⎛

⎜ ⎝

RMS OUT

OUT

⎞

OUT

⎟ ⎠

⎛ ⎜ ⎝

OUT

⎛

⎜ ⎝

⎞

⎛

⎟

⎜

⎠

⎝

OUT

−

OUT

⎞

OUT

⎟ ⎠

⎞ ⎟ ⎠

−

=≥

FBAC FBDC

CfR G

OUT SW SENSE m FBAC

_( )

RRR

DROOP AC

FBDC FBAC SENSE

≈

FBAC FBDC

mFBA_(

CC)

CRR R t

×+

⎡

FB FB FBAC FBDC SW

⎣

⎤

⎦

=×//( ) 3

DROOP DC

RRR

FBDC FBAC SENSE

RRR

FBAC FBDC FB

(()FBAC

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 41

Core Power-MOSFET Selection

Most of the following MOSFET guidelines focus on the challenge of obtaining high-load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention.

The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both V

IN(MIN)

and V

IN(MAX)

. Calculate both of these sums.

Ideally, the losses at V

IN(MIN)

should be roughly equal to

losses at V

IN(MAX)

, with lower losses in between. If the

losses at V

IN(MIN)

are significantly higher than the losses

at V

IN(MAX)

, consider increasing the size of NH(reducing

DS(ON)

but with higher C

GATE

). Conversely, if the loss-

es at V

IN(MAX)

are significantly higher than the losses at

IN(MIN)

, consider reducing the size of NH(increasing

DS(ON)

to lower C

GATE

). If VINdoes not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses.

Choose a low-side MOSFET that has the lowest possible on-resistance (R

DS(ON)

), comes in a moderate-sized package (i.e., one or two 8-pin SOs, DPAK, or D2PAK), and is reasonably priced. Make sure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-todrain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems might occur (see the

Core SMPS MOSFET Gate Drivers

section).

Core MOSFET Power Dissipation

Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage:

where I

LOAD

is the per-phase current.

Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the R

DS(ON)

required to stay within package power dissipation often limits how small the MOSFET can be. Again, the optimum occurs when the switching losses equal the conduction (R

DS(ON)

) losses. Highside switching losses do not usually become an issue until the input is greater than approximately 15V.

Calculating the power dissipation in the high-side MOSFET (NH) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very

rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on N

where C

RSS

is the reverse transfer capacitance of NH,

GATE

is the peak gate-drive source/sink current (1A,

typ), and I

LOAD

is the per-phase current.

Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the C x V

x fSWswitching-loss equation. If the high-side

MOSFET chosen for adequate R

DS(ON)

at low battery voltages becomes extraordinarily hot when biased from V

IN(MAX)

, consider choosing another MOSFET with

lower parasitic capacitance.

For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage:

The worst case for MOSFET power dissipation occurs under heavy overloads that are greater than I

LOAD(MAX)

, but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, the circuit can be “overdesigned” to tolerate:

where I

PEAK(MAX)

is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good-sized heatsink to handle the overload power dissipation.

Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 the load current per phase. This diode is optional and can be removed if efficiency is not critical.

Core Boost Capacitors

The boost capacitors (C

BST

) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1µF ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1µF. For these applications,

⎛

⎞

PD (N Resistive) =

OUT

⎜

⎟

⎝

⎠

LOAD DS O

(NN)

PD (N Switching) =HV

()

IN MAX

()

⎛

⎜ ⎝

RSS SW

GAT

⎞ ⎟

⎠

LOAD

⎡

PD (N Resistive) =L1−

⎢ ⎢⎢

⎣

⎛

⎜ ⎜

IN MAX()

⎝

OUT

⎤

⎞

⎛

LOAD

⎥

⎟

⎜

⎟

⎥

⎝

TOTAL

⎠

⎦

⎞ ⎟ ⎠

DS ON

()

LOAD MAX PEAK MAX

=− =

∆

INDUCTO R

PEAK MAX() () (

⎛

ILIR

LOAD MAX

()

⎜

−

))

⎜

⎝

⎞ ⎟

⎟ ⎠

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

42 ______________________________________________________________________________________

select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs’ gates:

where N is the number of high-side MOSFETs used for one SMPS, and Q

GATE

is the gate charge specified in the MOSFET’s data sheet. For example, assume two IRF7811W n-channel MOSFETs are used on the high side. According to the manufacturer’s data sheet, a single IRF7811W has a maximum gate charge of 24nC (VGS= 5V). Using the above equation, the required boost capacitance would be:

Selecting the closest standard value, this example requires a 0.22µF ceramic capacitor.

NB SMPS Design Procedure

NB Inductor Selection

The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows:

where I

LOAD3(MAX)

is the maximum current and f

SW3

the switching frequency of the NB regulator.

Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. If using a swinging inductor (where the inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. For the selected inductance value, the actual peak-to-peak inductor ripple current (∆I

INDUCTOR

) is defined by:

Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (I

PEAK3

NB Peak Inductor Current Limit (ILIM3)

The MAX17480 NB regulator overcurrent protection employs a peak current-sensing algorithm that uses the high-side MOSFET R

ON(NH3)

as the current-sense element. Since the controller limits the peak inductor current, the maximum average load current is less than the peak current-limit threshold by an amount equal to half the inductor ripple current. Therefore, the maximum load capability is a function of the current-limit setting, inductor value, switching frequency, and input-to-output voltage difference. When combined with the output undervoltage-protection circuit, the system is effectively protected against excessive overload conditions.

The peak current-limit threshold is set by the ILIM3 pin setting (see the

Offset and Current-Limit Setting for NB

SMPS (ILIM3)

section).

NB Output Capacitor Selection

The output filter capacitor must have low enough ESR to meet output ripple and load-transient requirements. In CPU V

CORE

The output capacitor’s size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor’s ESR. For single-phase operation, the maximum ESR to meet the output-ripple-voltage requirement is:

where f

SW3

is the switching frequency. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, capacitor selection is usually limited by ESR and voltage rating rather than by capacitance value (this is true of polymer types).

⎛

⎞

⎝

⎠

BST

200

GATE

BST

224

200

= .

024µ

⎛

−

IN OUT

⎜

fI LIR

SW LOAD MAX

()

⎞

⎛

⎟

⎜

⎟

⎝

OUT

⎞

⎟ ⎠

∆I

INDUCTOR

VVV

OUT IN OUT

33 3

Vf L

−

()

IN SW

333

PEAK LOAD MAX

()

∆

INDUCTOR

⎜ ⎝

⎟

⎠

()

ESR PCB

≤

∆

STEP

()

LOAD MAX

⎡

Vf L

333

ESR

⎢

≤

⎢

⎣

IN SW

VV V

−

()

333

IN OUT OUT

⎤ ⎥

⎥

⎦

PPPLE3

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 43

The capacitance value required is determined primarily by the stability requirements. However, the soar and sag calculations are still provided here for reference. Low inductor values allow the inductor current to slew faster, replenishing charge removed from or added to the output filter capacitors by a sudden load step. Therefore, the amount of output soar and sag when the load is applied or removed is a function of the output voltage and inductor value. The soar and sag voltages are calculated as:

where D

MAX

is the maximum duty cycle of the NB

SMPS as listed in the

Electrical Characteristics

table,

SW3

is the NB switching period programmed by the

OSC pin, and ∆t equals V

OUT/VIN

x tSWwhen in forced-

PWM mode, or L x I

LX3MIN

/(VIN- V

OUT

) when in pulse-

skipping mode. When using low-capacity ceramic filter capacitors,

capacitor size is usually determined by the capacity needed to prevent V

SOAR

from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem.

NB Input Capacitor Selection

The input capacitor must meet the ripple-current requirement (I

RMS

) imposed by the switching currents. The I

RMS

requirements can be determined by the following equation:

The worst-case RMS current requirement occurs when operating with V

IN3

= 2V

OUT3

. At this point, the above

equation simplifies to I

RMS

= 0.5 x I

LOAD3

For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. The MAX17480 NB regulator is operated as the second stage of a two-stage power-conversion system. Tantalum input capacitors are acceptable. Choose an input capacitor that exhibits less than 10°C temperature rise at the RMS input current for optimal circuit longevity.

NB Steady-State Voltage Positioning

ON(NH3)

), and is internally preset to -5.5mV/A (typ). This guarantees the output voltage to stay in the static regulation window over the maximum load conditions per AMD specifications. See Table 6 for full-load voltage droop according to different ILIM3 settings.

NB Transient Droop and Stability

The voltage-positioned load-line of the NB SMPS also provides the AC ripple voltage required for stability. To maintain stability, the output capacitive ripple must be kept smaller than the internal AC ripple voltage. Hence, a minimum NB output capacitance is required as calculated below:

where R

DROOP3(MIN)

is 4mV/A as defined in the

Electrical Characteristics

table, and f

SW3

is the NB

switching frequency programmed by the OSC pin.

SVI Applications Information

I2C Bus-Compatible Interface

The MAX17480 is a receive-only device. The 2-wire serial bus (pins SVC and SVD) is designed to attach on a low-voltage I2C-like bus. In the AMD mobile application, the CPU directly drives the bus at a speed of 3.4MHz. The CPU has a push-pull output driving to the V

DDIO

voltage level. External pullup resistors are not required.

When not used in the specific AMD application, the serial interface can be driven to as high as 2.5V, and can operate at the lower speeds (100kHz, 400kHz, or

1.7MHz). At lower clock speeds, external pullup resistors can be used for open-drain outputs. Connect both SVC and SVD lines to V

DDIO

through individual pullup resistors. Calculate the required value of the pullup resistors using:

where tRis the rise time, and should be less than 10% of the clock period. C

BUS

is the total capacitance on the bus.

The MAX17480 is compatible with the standard SVI interface protocol as defined in the following subsections. Figure 12 shows the SVI bus START, STOP, and data change conditions.

⎛

⎞

∆

()

SOA R

∆

()

LLOAD MAX

SAG

CVDV

OUT IN MAX OUT

×−

()

33 3

LOAD MAX

OUT OUT

()

∆

LLOAD MAX SW

()

OUT

−

∆

RMS

LOAD

⎜

⎝

VVV

⎟ ⎠

()

33 3

OUT IN OUT

−

OUT

21>××

SW DROOP MIN

3333

⎛ ⎜

⎝

()

OUT

⎞ ⎟

⎠

PULLUP

≤

BUS

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

44 ______________________________________________________________________________________

Bus Not Busy

The SVI bus is not busy when both data and clock lines remain high. Data transfers can be initiated only when the bus is not busy. Figure 13 shows the SVI bus acknowledge.

Start Data Transfer (S)

Starting from an idle bus state (both SVC and SVD are high), a high-to-low transition of the data (SVD) line while the clock (SVC) is high determines a START condition. All commands must be preceded by a START condition.

Stop Data Transfer (P)

A low-to-high transition of the SDA line while the clock (SVC) is high determines a STOP condition. All operations must be ended with a STOP condition.

Slave Address

After generating a START condition, the bus master transmits the slave address consisting of a 7-bit device code (110xxxx) for the MAX17480. Since the MAX17480 is a write-only device, the eighth bit of the

slave address is 0. The MAX17480 monitors the bus for its corresponding slave address continuously. It generates an acknowledge bit if the slave address was true and it is not in a programming mode.

SVD Data Valid

The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data.

Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. The device that acknowledges has to pull down the SVD line during the acknowledge clock pulse so that the SVD line is stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. See Figure 13.

DATA OUTPUT

BY MASTER

DATA OUTPUT

BY MAX17480

SVC FROM

MASTER

START

CONDITION

CLK1

CLK2

CLK8

CLK9

D6 D0

NOT ACKNOWLEDGE

ACKNOWLEDGE

CLOCK PULSE

Figure 13. SVI Bus Acknowledge

Figure 12. SVI Bus START, STOP, and Data Change Conditions

SVD

SVC

START

CONDITION

DATA LINE

STABLE

DATA VALID

CHANGE OF DATA

ALLOWED

STOP

CONDITION

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 45

Command Byte

A complete command consists of a START condition (S) followed by the MAX17480’s slave address and a data phase, followed by a STOP condition (P). For the slave address, bits 6:4 are always 110 and bit 3 is X (don’t care). The WR bit should always be 1 since read functions are not supported. Figure 14 is the SVI bus data-transfer summary. Table 7 is a description of the SVI send byte address and Table 8 describes serial VID 8-bit field encoding.

SMPS Applications Information

Duty-Cycle Limits

Minimum Input Voltage

The minimum input operating voltage (dropout voltage) is restricted by stability requirements, not the minimum off-time (t

OFF(MIN)

). The MAX17480 does not include slope compensation, so the controller becomes unstable with duty cycles greater than 50% per phase:

IN(MIN)

≥ 2V

OUT(MAX)

However, the controller can briefly operate with duty cycles over 50% during heavy load transients.

Table 7. SVI Send Byte Address Description Table 8. Serial VID 8-Bit Field Encoding

Figure 14. SVI Bus Data Transfer Summary

S P

VDD1 (CORE1)

FIXED VALUES

VDD0 (CORE0)

SET DAC AND PSI_LSLAVE ADDRESS

ACK

WR (WRITE) = 0

PSI_L

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

STOPSTART

ACK

BIT0

BIT DESCRIPTION

6:4 Always 110b.

3 X—don’t care.

VDD1, if set then the fo llowing data byte contains the VID for VDD1. Bit 2 is ignored in

combined mode (GNDS1 or GNDS2 = V VDD1 refers to CORE1 of the AMD CPU.

VDD0, if set then the fo llowing data byte contains the VID for VDD0 in separate mode, and

the unified VDD in combined mode. VDD0 refers to CORE0 of the AMD CPU.

VDDNB, if set then the following data byte

contains the VID for VDDNB.

DDI O

BIT DESCRIPTION

PSI_L: Power-Save Indicator

0 mean s the processor i s at an optimal load and the SMPS(s) can enter power-saving mode. The SMPS operates in pulse-skipping mode after exiting the boot mode. Offset is disabled if previous ly enabled by the OPTION pin. The MAX17480 enters 1-phase operation if in

combined mode (GNDS1 or GNDS2 = H).

1 mean s the processor i s in a high currentconsumption state. The SMPS operates in forcedPWM mode after exiting the boot mode. Offset is enabled if previou sl y enabled by the OPTION pin. The MAX17480 returns to 2-phase operation if in combined mode (GNDS1 or GNDS2 = H).

6:0 SVID[6:0] as defined in Table 7.

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

46 ______________________________________________________________________________________

Maximum Input Voltage

The MAX17480 controller has a minimum on-time, which determines the maximum input operating voltage that maintains the selected switching frequency. With higher input voltages, each pulse delivers more energy than the output is sourcing to the load. At the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trigger an on-time pulse, resulting in pulse-skipping operation regardless of the operating mode selected by PSI_L. This allows the controller to maintain regulation above the maximum input voltage, but forces the controller to effectively operate with a lower switching frequency. This results in an input threshold voltage at which the controller begins to skip pulses (V

IN(SKIP)

where fSWis the per-phase switching frequency set by the OSC resistor, and t

ON(MIN)

is 150ns (max) minus the driver’s turn-on delay (DL low to DH high). For the best high-voltage performance, use the slowest switching frequency setting (100kHz per phase, R

OSC

= 432kΩ).

PCB Layout Guidelines

Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 15). If possible, mount all the power components on the top side of the board with their ground terminals flush against one another, and mount the controller and analog components on the bottom layer so the internal ground layers shield the analog components from any noise generated by the power components. Follow these guidelines for good PCB layout:

• Keep the high-current paths short, especially at the

ground terminals. This is essential for stable, jitterfree operation.

• Connect all analog grounds to a separate solid cop-

per plane; then connect the analog ground to the GND pins of the controller. The following sensitive components connect to analog ground: VCCand V

DDIO

bypass capacitors, remote sense and GNDS bypass capacitors, and the resistive connections (ILIM12, OSC, TIME).

• Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PCB (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single mΩ of excess trace resistance causes a measurable efficiency penalty.

• Connections for current limiting (CSP, CSN) and voltage positioning (FBS, GNDS) must be made using Kelvin-sense connections to guarantee the currentsense accuracy. Place current-sense filter capacitors and voltage-positioning filter capacitors as close as possible to the IC.

• Route high-speed switching nodes and driver traces away from sensitive analog areas (REF, V

, FBAC,

FBDC, OUT3, etc.). Make all pin-strap control input connections (SHDN, PGD_IN, OPTION) to analog ground or VCCrather than power ground or VDD.

• Route the high-speed serial-interface signals (SVC, SVD) in parallel, keeping the trace lengths identical. Keep the SVC and SVD away from the high-current switching paths.

• Keep the drivers close to the MOSFET, with the gatedrive traces (DL, DH, LX, and BST) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require lowimpedance gate drivers to avoid shoot-through currents.

• When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET rather than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.

Layout Procedure

1) Place the power components first, with ground ter-

minals adjacent (low-side MOSFET source, CIN, C

OUT

, and DL anode). If possible, make all these connections on the top layer with wide, copperfilled areas. For the NB SMPS, place CIN3 and L3 as near as possible to the MAX17480, using multiple vias to reduce inductance when connecting the different layers.

2) Use multiple vias to connect the exposed backside to the power ground plane (PGND) to allow for a lowimpedance path for the SMPS3 internal low-side MOSFET.

3) Mount the MAX17480 close to the low-side MOSFETs. The DL gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the driver IC).

4) Group the gate-drive components (BST capacitors, V

bypass capacitor) together near the

MAX17480.

⎛

⎝

⎞

⎠

IN SKIP OUT

()

⎜ ⎜

SW ON MI N

()

⎟ ⎟

MAX17480

AMD 2-/3-Output Mobile Serial

VID Controller

______________________________________________________________________________________ 47

5) Make the DC-DC controller ground connections as shown in the standard application circuit (Figure 2). This diagram can be viewed as having three separate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the PGND, V

bypass capacitor, and driver IC ground connection go; and the controller’s analog ground plane, where sensitive analog components, the MAX17480’s AGND pin, and V

bypass capacitor go. The controller’s analog

ground plane (AGND) must meet the power ground

plane (PGND) only at a single point directly beneath the IC. The power ground plane should connect to the high-power output ground with a short, thick metal trace from PGND to the source of the low-side MOSFETs (the middle of the star ground).

6) Connect the output power planes (V

CORE

, V

OUT3

, and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the CPU as is practical.

DDNB

CORE1

CORE0

OUT

INDUCTOR

POWER

GROUND

INDUCTOR

OUT

SPLIT CORE CPU SOCKET

AGND PIN

CONNECT THE EXPOSED

PAD TO POWER GND

USING MULTIPLE VIAS

VCC

VDD

IN3

OUT3

NTC

R2 R1

CSP CSN

KELVIN-SENSE VIAS TO

INDUCTOR PAD

KELVIN-SENSE VIAS UNDER THE INDUCTOR

(REFER TO EVALUATION KIT)

INDUCTOR DCR SENSING

Figure 15. PCB Layout Example

MAX17480

AMD 2-/3-Output Mobile Serial VID Controller

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Pin Configuration

MAX17480

PGND

THIN QFN

(5mm

× 5mm)

TOP VIEW

ILIM3

IN3

LX3

BST3

ILIM12

BST1

DL2

LX1

DH1

VRHOT

BST2

LX2

CSN1

4567

27282930 26 24 23 22

FBDC1

FBAC1

CSP2

CSN2

FBDC2

FBAC2

IN3

DL1

GNDS1

GNDS2

OPTION

OSC

TIME

DDIO

SVC

SVD

CSP1

PGD_IN

PWRGD

SHDN

OUT3

AGND

DH2

*EP

*EXPOSED PAD.

THRM

Chip Information

TRANSISTOR COUNT: 24,311

PROCESS: BiCMOS

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

40 TQFN-EP T4055-2

21-0140

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages

Rainbow Electronics MAX17480 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual