Rainbow Electronics MAX17409 User Manual

General Description
The MAX17409 is a 1-phase Quick-PWM™ step-down VID power-supply controller for high-performance graph­ics processors. The Quick-PWM control provides instan­taneous response to fast-load current steps. Active voltage positioning reduces power dissipation and bulk output capacitance requirements and allows ideal posi­tioning compensation for tantalum, polymer, or ceramic bulk output capacitors.
The MAX17409 is intended for two different notebook processor core applications: either bucking down the bat­tery directly to create the core voltage, or bucking down the +5V system supply. The single-stage conversion method allows this device to directly step down high-volt­age batteries for the highest possible efficiency. Alternatively, 2-stage conversion (stepping down the +5V system supply instead of the battery) at higher switching frequency provides the minimum possible physical size.
A slew-rate controller allows controlled transitions between VID codes. A thermistor-based temperature sensor provides programmable thermal protection.
The MAX17409 is available in a 28-pin, 4mm x 4mm TQFN package.
Applications
Graphics Core (GPU) Power Supplies
Voltage-Positioned Step-Down Converters
2-to-4 Li+ Cells Battery to Processor Core Supply Converters
Notebooks/Desktops/Servers
Features
o 1-Phase Quick-PWM Controller
o ±6mV V
OUT
Accuracy Over Line, Load, and
Temperature
o 6-Bit Graphics DAC (12.5mV LSB)
o Active Voltage Positioning with Adjustable Gain
o Accurate Droop and Current Limit
o Remote Output and Ground Sense
o Buffered 2V Reference Output for Offsets
o Power-Good Window Comparator
o Temperature Comparator
o Drives Large Synchronous Rectifier FETs
o 2V to 26V Power Input Range
o Adjustable Switching Frequency (600kHz max)
o Output Overvoltage and Undervoltage Protection
o Soft-Startup and Soft-Shutdown
o Internal Boost Diodes
MAX17409
1-Phase Quick-PWM GPU Controller
________________________________________________________________
Maxim Integrated Products
1
Pin Configuration
Ordering Information
19-4590; Rev 1; 7/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE
MAX17409GTI+ -40°C to +105°C 28 TQFN-EP*
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
TOP VIEW
GND
VRHOT
ILIM
CCV
REF
V
DD
V
BST
DL
PGNDLXG5
G4
2021 19 17 16 15
18
SKIP
THRM
14
G3
G2
13
12
G1
G0
11
10
SHDN
PWRGD
9
8
TON
DH
22
23
24
25
26
27
CC
28
12
IMON
GNDS/OFSP
MAX17409
PAD GND
4567
3
FB
CSN
THIN QFN
CSP
MAX17409
1-Phase Quick-PWM GPU Controller
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN= 12V, VDD= VCC= 5V, SHDN = ILIM = VCC, SKIP = GNDS = PGND = GND, VFB= V
CSP
= V
CSN
= 1.05V;
G5–G0 set for 1.05V (G0–G5 = 100110); T
A
= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.) (Note 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VCC, VDDto GND .....................................................-0.3V to +6V
G0–G5 to GND .........................................................-0.3V to +6V
CSP, CSN to GND ....................................................-0.3V to +6V
ILIM, THRM, VRHOT, PWRGD to GND ....................-0.3V to +6V
SKIP to GND.............................................................-0.3V to +6V
CCV, FB, IMON, REF to GND.....................-0.3V to (V
CC
+ 0.3V)
SHDN to GND (Note 1)...........................................-0.3V to +30V
TON to GND ...........................................................-0.3V to +30V
GNDS/OFSP, PGND to GND (Note 2) ...................-0.3V to +0.3V
Internal Driver (Note 2)
DL to PGND.............................................-0.3V to (V
DD
+ 0.3V)
BST to GND .........................................................-0.3V to +36V
LX to BST...............................................................-6V to +0.3V
BST to V
DD
..........................................................-0.3V to +30V
DH to LX .................................................-0.3V to (V
BST
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C) 28-Pin 4mm x 4mm TQFN
(derate 21.3mW/°C above +70°C) ............................1702mW
Operating Temperature Range .........................-40°C to +105°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +165°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1: SHDN might be forced to 12V for the purpose of debugging prototype breadboards using the no-fault test mode, which dis-
ables fault protection.
Note 2: Measurements valid using a 20MHz bandwidth limit.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PWM CONTROLLER
Input Voltage Range VCC, VDD 4.5 5.5 V
DC Output-Voltage Accuracy
Line Regulation Error VCC = 4.5V to 5.5V, VIN = 4.5V to 26V 0.1 %
GNDS Input Range -200 +200 mV
GNDS/OFSP Gain A
GNDS/OFSP Input Bias Current I
REF Voltage V
Dynamic VID Slew-Rate Accuracy 11.0 12.5 14.0 mV/µs
Soft-Start/Soft-Shutdown Slew-Rate Accuracy
On-Time (Note 5) t
Minimum Off-Time t TON Shutdown Input Current SHDN = GND, VIN = 26V, VCC = VDD = 0 or 5V 0.01 0.1 µA
Measured at FB with respect to GNDS; inc lude s load-regulation error (Note 4)
V
GNDS
-2 +2 µA
GNDS
REF
1.248 1.56 1.872 mV/µs
ON
OFF(MIN)
Measured at DH (Note 5) 300 375 ns
/V
OUT
GNDS
VCC = 4.5V to 5.5V, I
= 0 to 1mA 1.97 2.000 2.02
I
REF
VIN = 12V, VFB = 1.2V
, -200mV  V
= 100µA 1.98 2.000 2.02
REF
R
R
R
-6 +6 mV
+200mV 0.97 1.00 1.03 V/V
GNDS
= 96.75k 142 167 192
TON
= 200k 300 333 366
TON
= 303.25k 425 500 575
TON
V
ns
MAX17409
1-Phase Quick-PWM GPU Controller
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN= 12V, VDD= VCC= 5V, SHDN = ILIM = VCC, SKIP = GNDS = PGND = GND, VFB= V
CSP
= V
CSN
= 1.05V;
G5–G0 set for 1.05V (G0–G5 = 100110); T
A
= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
BIAS CURRENTS
Quie scent Supply Current (VCC) I
Quie scent Supply Current (VDD) I
Shutdown Supply C urrent (VCC) Measured at VCC, SHDN = GND, TA = +25°C 0.01 1 µA
Shutdown Supply C urrent (VDD) Measured at VDD, SHDN = GND, TA = +25°C 0.01 1 µA
FAULT PROTECTION
Output Overvoltage Protect ion Threshold
Output Overvoltage Propagation Delay
Output Undervoltage Protection Threshold
Output Undervoltage Propagation Dela y
PWRGD Startup Delay
PWRGD Threshold
PWRGD Transition Blanking Time
PWRGD Delay
PWRGD Output Low Voltage I
PWRGD Leakage Current High state, PWRGD forced to 5V 1 µA
VCC Undervoltage-Lockout Threshold
CSN Discharge Resistance in UVLO
CC
DD
V
OVP
t
OVP
V
UVP
t
UVP
t
BLANK
V
UVLO(VCC)
Measured at VCC, SKIP = 5V, FB forced above the regulation point
Measured at VDD, SKIP = 0V, FB forced above the regulation point, T
Skip mode after output reaches the regulation voltage or PWM mode; measured at FB with respect to unloaded output vo ltage
Soft-start, soft-shutdown, skip mode, and output have not reached the regulation voltage; mea sured at FB
Min imum OVP threshold; measured at FB 0.8
FB forced 25mV above trip thresho ld 10 µs
Measured at FB with respect to unloaded output vo ltage
FB forced 25mV below trip threshold 10 µs
Measured at startup from the time when SHDN goes high
Measured at FB with respect to unloaded output voltage, 15mV hysteresis (typ)
Measured from the time when FB reaches the target voltage (Note 4) based on the slew rate FB forced 25mV out side the PWRGD trip thresholds
= 3mA 0.4 V
SINK
Risi ng edge, 50mV typical hysteresis, controller disabled below this level
= VDD = 4.0V 8
V
CC
Lower threshold, falling edge (undervoltage)
Upper threshold, rising edge (overvoltage)
= +25°C
A
1.5 3 mA
0.02 1 µA
250 300 350 mV
1.45 1.50 1.55
-450 -400 -350 mV
3 5 8 ms
-350 -300 -250
+150 +200 +250
20 µs
10 µs
4.05 4.25 4.48 V
V
mV
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN= 12V, VDD= VCC= 5V, SHDN = ILIM = VCC, SKIP = GNDS = PGND = GND, VFB= V
CSP
= V
CSN
= 1.05V;
G5–G0 set for 1.05V (G0–G5 = 100110); T
A
= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.) (Note 3)
MAX17409
1-Phase Quick-PWM GPU Controller
4 _______________________________________________________________________________________
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
THERMAL COMPARATOR AND PROTECTION
VRHOT Trip Threshold
VRHOT Delay t
VRHOT Output On-Resistance R VRHOT Leakage Current I
THRM Input Leakage I
Thermal-Shutdown Threshold T
VRHOT
VRHOT
VRHOT
THRM
SHDN
Measured at THRM with respect to V falling edge; typical hysteresis = 100mV
THRM forced 25mV below the VRHOT trip threshold; falling edge
Low state 2 8 High state, VRHOT forced to 5V, TA = +25°C 1 µA
V
= 0 to 5V, TA = +25°C -100 +100 nA
THRM
Typical hysteresis = 15°C 160 °C
CC
;
29.2 30 30.8 %
10 µs
VALLEY CURRENT LIMIT AND DROOP
V
- V
Current-Limit Threshold Voltage (Positive Adjustable)
Current-Limit Threshold Voltage (Positive Default)
Current-Limit Threshold Voltage (Negative) Accuracy
Current-Limit Threshold Voltage (Zero Crossing)
CSP, CS N Comm on- Mode Input Range
V
LIMIT
V
ILIM = V
V
LIMIT(NEG) VCSP
V
ZERO VPGND
0 1.9 V
CSP
- V
V
REF
REF
CSN
CSP
- V
CSN
, V
CC
- V
, nominally -125% of V
CSN
- VLX 1 mV
= 100mV 7 10 13
ILIM
- V
= 500mV 45 50 55
ILIM
20 22.5 25 mV
LIMIT
-4 +4 mV
CSP, CSN Input Current TA = +25°C -0.2 +0.2 µA
ILIM Input Current TA = +25°C -100 +100 nA
Droop Amplifier (GMD) Offset (V
Droop Amplifier (GMD) Transconductance
- V
CSP
I
/(V
FB
) at IFB = 0 -0.75 +0.75 mV
CSN
- V
CSN
);
CSP
FB = CSN = 0.45V to 2.0V, and (V
CSP
- V
) = -15.0mV to +15.0mV
CSN
592 600 608 µS
GATE DRIVERS
DH Gate-Driver On-Resistance R
DL Gate-Driver On-Resistance R
DH Gate-Driver Source Current I
DH(S OURC E)
DH Gate-Driver Sink Current I
DL Gate-Driver Source Current I
DL(SOURCE)
DL Gate-Driver Sink Current I
Internal BST Switch On-Resistance
ON(DH)
ON(DL)
DH(S INK)
DL(S INK)
R
BST IBST
BST - LX forced to 5V
High state (pullup) 0.7 2.0
Low state (pulldown) 0.25 0.7
DH forced to 2.5V, BST - LX forced to 5V 2.2 A
DH forced to 2.5V, BST - LX forced to 5V 2.7 A
DL forced to 2.5V 2.7 A
DL forced to 2.5V 8 A
= 10mA, VDD = 5V 10 20
High state (pullup) 0.9 2.5
Low state (pulldown) 0.7 2.0
mV
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN= 12V, VDD= VCC= 5V, SHDN = ILIM = VCC, SKIP = GNDS = PGND = GND, VFB= V
CSP
= V
CSN
= 1.05V;
G5–G0 set for 1.05V (G0–G5 = 100110); T
A
= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.) (Note 3)
MAX17409
1-Phase Quick-PWM GPU Controller
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN= 12V, VDD= VCC= 5V, SHDN = ILIM = VCC, SKIP = GNDS = PGND = GND, VFB= V
CSP
= V
CSN
= 1.05V;
G5–G0 set for 1.05V (G0–G5 = 100110); T
A
= -40°C to +105°C, unless otherwise specified.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CURRENT MONITOR
Current-Monitor Transconductance G
Current-Monitor Offset Referred to V(CSP,CSN)
IMON Clamp Voltage V
m(IMON)IIMON
I
I
IMON
/(V
- V
), V
CSP
CSN
= 0 -1.0 +1.0 mV
IMON
= -1.0mA 1.05 1.10 1.15 V
IMON
= 0.5V to 1.0V 4.9 5.0 51 mS
CSN
LOGIC AND I/O
Logic-Input High Voltage V
Logic-Input Low Voltage V
Low-Voltage Logic-Input High Voltage
Low-Voltage Logic-Input Low Voltage
V
V
IHLV
ILLV
SHDN, SKIP 2.3 V
IH
SHDN, SKIP 1.0 V
IL
G0–G5 0.67 V
G0–G5 0.33 V
Logic-Input Current TA = +25°C, S HDN, SKIP, G0–G5 = 0 or 5V -1 +1 µA
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PWM CONTROLLER
Input Voltage Range VCC, VDD 4.5 5.5 V
DC Output-Voltage Accuracy
Measured at FB with respect to GNDS, inc lude s load regulation error (Note 4)
-10 +10 mV
GNDS Input Range For positive offset and remote-sen se errors -200 +200 mV
GNDS/OFSP Gain A
REF Voltage V
GNDS
REF
V
/V
OUT
V
= 4.5V to 5.5V, I
CC
= 0 to 1mA 1.95 2.03
I
REF
GNDS
, -200mV  V
= 100µA 1.97 2.03
REF
+200mV 0.95 1.05 V/V
GNDS
Dynamic VID Slew-Rate Accuracy 10 15 mV/µs
Soft-Start/Soft-Shutdown Slew-Rate Accuracy
On-Time (Note 5) t
Minimum Off-Time t
1.248 1.872 mV/µs
R
= 96.75k 142 192
TON
ON
OFF(MIN)
VIN = 12V, VFB = 1.2V
Measured at DH (Note 5) 400 ns
R
= 200k 300 366
TON
= 303.25k 425 575
R
TON
BIAS CURRENTS
Quie scent Supply Current (VCC) I
CC
Measured at VCC, SKIP = 5V, FB forced above the regulation point
3 mA
V
ns
MAX17409
1-Phase Quick-PWM GPU Controller
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN= 12V, VDD= VCC= 5V, SHDN = ILIM = VCC, SKIP = GNDS = PGND = GND, VFB= V
CSP
= V
CSN
= 1.05V;
G5–G0 set for 1.05V (G0–G5 = 100110); T
A
= -40°C to +105°C, unless otherwise specified.) (Note 3)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FAULT PROTECTION
Output Overvoltage-Protection Threshold
Output Undervoltage-Protection Threshold
PWRGD Startup Delay
PWRGD Threshold
PWRGD Output Low Voltage I
VCC Undervoltage-Lockout Threshold
THERMAL COMPARATOR AND PROTECTION
VRHOT Trip Threshold
VRHOT Output On-Resistance R
VALLEY CURRENT LIMIT AND DROOP
Current-Limit Threshold Voltage (Positive Adjustable)
Current-Limit Threshold Voltage (Positive Default)
Current-Limit Threshold Voltage (Negative) Accuracy
CSP, CS N Comm on- Mode Input Range
Droop Amplifier GMD) Offset (V
Droop Amplifier (GMD) Transconductance
Skip mode after output reaches the regulation voltage or PWM mode; measured at FB with respect to unloaded
V
OVP
output vo ltage
Soft-start, soft-shutdown, skip mode, and output have not reached the regulation voltage, mea sured at FB
V
UVP
Measured at FB with respect to unloaded output vo ltage
Measured at startup from the time when SHDN goes high
Measured at FB with respect to
Lower threshold, falling edge (undervoltage)
unloaded output
Upper threshold, rising edge (overvoltage)
V
UVLO(VCC)
voltage; 15mV hysteresis (typ)
= 3mA 0.4 V
SINK
Risi ng edge, 50mV typical hysteresis, controller disabled below this level
Measured at THRM with respect to V falling edge; typical hysteresis = 100mV
VRHOT
V
LIMIT
V
LIMIT(NEG) VCSP
Low state 8
V
- V
V
- V
CSP
ILIM = V
- V
CSP
- V
V
REF
REF
CSN
CSN
, V
CC
, nominally -125% of V
CSN
= 100mV 7 13
ILIM
- V
= 500mV 45 55
ILIM
20 25 mV
LIMIT
0 1.9 V
- V
CSP
/(V
I
FB
) at IFB = 0 -1.0 +1.0 mV
CSN
- V
CSN
);
CSP
FB = CSN = 0.45V to 2.0V, and (V
CSP
- V
) = -15.0mV to +15.0mV
CSN
CC
250 350 mV
1.45 1.55 V
-450 -350 mV
3 8 ms
-350 -250 mV
+150 +250 mV
4.0 4.5 V
;
29.2 30.8 %
-5 +5 mV
588 612 µS
mV
MAX17409
1-Phase Quick-PWM GPU Controller
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN= 12V, VDD= VCC= 5V, SHDN = ILIM = VCC, SKIP = GNDS = PGND = GND, VFB= V
CSP
= V
CSN
= 1.05V;
G5–G0 set for 1.05V (G0–G5 = 100110); T
A
= -40°C to +105°C, unless otherwise specified.) (Note 3)
Note 3: Limits are 100% production tested at TA= +25°C. Maximum and minimum limits over temperature are guaranteed by design
and characterization.
Note 4: The equation for the target voltage V
TARGET
is:
V
TARGET
= the slew-rate-controlled version of V
DAC
, where V
DAC
= 0 for shutdown, V
DAC
= V
VID
otherwise (the V
VID
volt­ages for all possible VID codes are given in Table 4). In pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load.
Note 5: On-time and minimum off-time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0V, BST forced
to 5V, and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times might be different due to MOSFET switching speeds.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GATE DRIVERS
DH Gate-Driver On-Resistance R
DL Gate-Driver On-Resistance R
Internal BST Switch On-Resistance
CURRENT MONITOR
Current-Monitor Transconductance G
Current-Monitor Offset Referred to V(CSP,CSN)
IMON Clamp Voltage V
LOGIC AND I/O
Logic-Input High Voltage V
Logic-Input Low Voltage V
Low-Voltage Logic-Input High Voltage
Low-Voltage Logic-Input Low Voltage
ON(DH)
ON(DL)
R
BST IBST
m(IMON)IIMON
IMON IIMON
V
IHLV
V
ILLV
BST - LX forced to 5V
High state (pullup) 2.0
Low state (pulldown) 0.7
= 10mA, VDD = 5V 20
I
IH
IL
IMON
SHDN, SKIP 2.3 V SHDN, SKIP 1.0 V
G0–G5 0.67 V
G0–G5 0.33 V
/(V
CSP
= 0 -1.0 +1.0 mV
= -1.0mA 1.05 1.15 V
High state (pullup) 2.5
Low state (pulldown) 2.0
- V
) V
CSN
= 0.5V to 1.0V 4.9 5.1 mS
CSN
MAX17409
1-Phase Quick-PWM GPU Controller
8 _______________________________________________________________________________________
Typical Operating Characteristics
(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN = VCC, G0–G5 set for 1.05V (G0–G5 = 100110), TA= +25°C, unless other­wise specified.)
100
90
80
70
EFFICIENCY (%)
60
50
40
0.01 100
0.9V OUTPUT EFFICIENCY vs. LOAD CURRENT
7V
12V
20V
SKIP MODE PWM MODE
1010.1
LOAD CURRENT (A)
MAX17409 toc01
0.92
0.91
0.90
OUTPUT VOLTAGE (V)
0.89
0.88
0.9V OUTPUT VOLTAGE vs. LOAD CURRENT
SKIP MODE
PWM MODE
016
LOAD CURRENT (A)
12 14108642
MAX17409 toc02
SWITCHING FREQUENCY
vs. LOAD CURRENT
350
VIN = 12V
300
250
200
150
100
SWITCHING FREQUENCY (kHz)
50
0
0.01 100 LOAD CURRENT (A)
0.8125V OUTPUT
VOLTAGE DISTRIBUTION
90
+85°C
80
+25°C
70
60
50
40
30
SAMPLE PERCENTAGE (%)
20
10
0
0.8085
0.8095
0.8075 OUTPUT VOLTAGE (V)
0.8105
SAMPLE SIZE = 100
0.8115
0.8125
0.8135
0.8145
SKIP MODE PWM MODE
1010.1
0.8155
0.8165
0.8175
MAX17409 toc03
MAX17409 toc05
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE
100
I
IN
10
1
0.1
SWITCHING FREQUENCY (kHz)
0.01 514
ICC + I
DD
I
IN
INPUT VOLTAGE (V)
Gm
TRANSCONDUCTANCE
(FB)
ICC + I
SKIP MODE PWM MODE
12 1311109876
MAX17409 toc04
DD
DISTRIBUTION
50
+85°C
45
+25°C
40
35
30
25
20
15
SAMPLE PERCENTAGE (%)
10
5
0
592
594
590
TRANSCONDUCTANCE (µS)
596
SAMPLE SIZE = 100
598
600
602
604
606
608
MAX17409 toc06
610
MAX17409
1-Phase Quick-PWM GPU Controller
_______________________________________________________________________________________
9
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN = VCC, G0–G5 set for 1.05V (G0–G5 = 100110), TA= +25°C, unless other­wise specified.)
SAMPLE PERCENTAGE (%)
100
Gm
TRANSCONDUCTANCE
(IMON)
DISTRIBUTION
MAX17409 toc07
0.95V
5V
0
0
0
0
0
4.96
4.98
SAMPLE SIZE = 100
5.00
5.02
5.04
5.06
5.08
5.10
+85°C
90
+25°C
80
70
60
50
40
30
20
10
0
4.92
4.94
4.90 TRANSCONDUCTANCE (mS)
LOAD-TRANSIENT RESPONSE
(PWM MODE)
SOFT-START WAVEFORM
A. SHDN, 5V/div
, 10A/div
B. I
LX
, 500mV/div
C. V
OUT
MAX17409 toc10
1ms/div
MAX17409 toc08
D. PWRGD, 5V/div E. DL, 5V/div
= 0A, SKIP MODE
I
OUT
SOFT-SHUTDOWN WAVEFORM
5V
A
0
B
C
D
E
0
0.95V
0
0
0
A. SHDN, 5V/div
, 10A/div
B. I
LX
, 500mV/div
C. V
OUT
LOAD-TRANSIENT RESPONSE
(SKIP MODE)
100µs/div
MAX17409 toc11
MAX17409 toc09
D. PWRGD, 5V/div E. DL, 5V/div
= 0A, SKIP MODE
I
OUT
A
B
C
D
E
0.95V
A
1A
0
A. V B. I
OUT
, 20A/div
LX
, 50mV/div
20µs/div
C. LX, 10V/div
= 1A - 11A
I
OUT
B
C
0.95V
1A
0
A. V B. I
OUT
, 20A/div
LX
, 50mV/div
20µs/div
C. LX, 10V/div
= 1A - 11A
I
OUT
A
B
C
MAX17409
1-Phase Quick-PWM GPU Controller
10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
Current Monitor Output. The MAX17409 IMON output sources a current that is directl y proportional to the current-sen se vo ltage as defined by:
I
1 IMON
2 GNDS/OFSP
3 FB
4 CSN
5 CSP
6 SKIP
= G
IMON
where G
The IMON current is unidirectional (sources current out of IMON only) for positive current-sense values. For negative current-sense vo ltages, the IMON current is zero.
Connect an e xternal resistor between IMON and GNDS to create the desired IMON gain based on the following equation:
where I
LOAD(MAX)
The IMON voltage is internall y clamped to 1.1V. The transconductance amplifier and voltage clamp are internally compensated, so IMON cannot drive large external capacitance values. To filter the IMON signal, use an RC filter as shown in Figure 1.
Remote Ground-Sense Input/Positi ve Offset Input. Connect directl y to the ground-sense pin or ground connect ion of the load. GNDS internally connects to a transconductance amplifier that adjusts the feedback vo ltage—compen sating for voltage drops between the regulator’s ground and the processor’s ground.
Remote-Sense Feedback Input and Voltage-Position ing Transconductance Amplifier Output. Connect resistor R pin of the load) for best accurac y and to set the steady-state droop based on the voltage­positioning gain requirement:
where R current-sen se resi stance w ith respect to CSP to CSN current-sen se inputs. See the Current Sense section for details on designing with sense resistors or inductor DCR sensi ng.
Shorting FB directly to the output effectively disab les voltage posit ioning, but impacts the stability requirement s. Designs that disable vo ltage positioning require a h igher minimum output capacitance ESR to maintain stabil ity (see the Output Capacitor Selection section).
FB enters a high-impedance state in shutdown.
Negative Inductor Current-Sense Input. Connect CSN to the negative terminal of the inductor current-sen sing resistor or directly to the negati ve terminal of the inductor if the loss less DCR sen si ng method is used (see Figure 3).
Positive Inductor Current-Sense Input. Connect CSP to the positive terminal of the inductor current­sen si ng resistor or direct ly to the pos itive terminal of the filtering capacitor used when the loss less DCR sensing method is used (see Figure 3).
Pulse-Skipping Control Input. The SKIP signal indicate s the power usage and sets the operating mode of the MAX17409. When the system forces SKIP high, the MAX17409 immediately enters automatic pulse-skipping mode. The controller returns to continuous forced-PWM mode when SKIP is pulled low and the output is in regulat ion. SKIP determines the operating mode and output­voltage transition slew rate as shown in the truth table below:
SKIP 0 Normal slew rate, forced-PWM mode 1 Normal slew rate, s kip mode
The SKIP state is ignored during soft-start and shutdown. The MAX17409 alway s uses pulse­sk ipping mode during startup to ensure a monotonic power-up. During shutdown, the controller always uses forced-PWM mode so the output can be actively discharged.
DROOP_DC
Functionality
m(IMON)
= 5mS (typ).
= 1.0V/(I
R
IMON
is the maximum load current, and R
between FB and the output remote-sense pin (or Kelvi n-sensed to the supply
FB
is the desired voltage-positioning slope, GMD = 600µS (typ), and R
R
FB
LOAD(MAX)
= R
DROO P
m(IMON)
/(R
x (V
x R
SENSE
CSP
SENSE
SENSE
- V
)
CSN
x G
is the current-sense voltage.
x GMD)
m(IMON)
)
SENSE
is the
MAX17409
1-Phase Quick-PWM GPU Controller
______________________________________________________________________________________ 11
Pin Description (continued)
PIN NAME FUNCTION
Comparator Input for Thermal Protection. THRM connects to the positi ve input of an internal comparator. The comparator’s negative input connects to an internal resistive voltage-divider that
7 THRM
8 TON
9 PWRGD
10 SHDN
11–16 G0–G5
17 PGND
18 DL
19 V
20 BST
21 LX
DD
accurately sets the THRM threshold to 30% of the VCC voltage. Connect the output of a resistor­div ider and thermistor-div ider (between V voltage at THRM fall s below 30% of V
Switching Frequenc y-Setting Input. An external res istor (R TON sets the switching frequenc y (f determine the nominal switching period:
t
SW
TON enters a high impedance in shutdown to reduce the input quiescent current. If the TON current is les s than 10µA, the MAX17409 disables the controller, sets the TON OPEN fault latch, and pulls DH and DL low.
Open-Drain Power-Good Output. The MAX17409 forces PWRGD low when SHDN is pulled low. After the controller is properly powered up, PWRGD become s a high-impedance output as long as the feedback voltage i s in regulation and the startup blanking time has expired.
PWRGD becomes active 5ms after the MAX17409 reaches the VID target. The MAX17409 pulls PWRGD low when shutdown (SHDN = GND) is pulled low, during startup, and during shutdown transitions.
The PWRGD upper threshold i s blanked during an y downward output-voltage transition that occurs when the MAX17409 is in skip mode (SKIP = V related PWRGD blanking period expires and the controller detects the output is in regulation (error­amplifier edge occurs).
Note: The pullup res istance on PWRGD causes additional shutdown current.
Shutdown Control Input. Connect to V controller into the low-power 1µA (max) shutdown state. During startup, the controller ramps up the output voltage with a 1.56mV/µs slew rate to the se lected target vo ltage. During the shutdown transition, the MAX17409 softly ramps down the output voltage with a 1.56mV/µs s lew rate. Forcing SHDN to 11V ~ 13V disable s overvoltage protection, undervoltage protection, and thermal shutdown, and clears the fault latches.
Low-Voltage (1.0V Logic) VID DAC Code Inputs. The G0–G5 inputs do not have internal pullups. These 1.0V logic inputs are designed to interface directly with the µP. The output voltage is set by the DAC code indicated by the logic-level voltages on G0–G5.
Power Ground. Ground connect ion for the DL driver.
Low-Side Gate-Driver Output. DL swings from V also forced low when an output overvoltage fault is detected, overriding any negati ve current-limit condition that might be present. DL is forced low in skip mode after detectin g an inductor current zero cross ing.
Driver-Supply Voltage Input. V BST switch used to refresh the BST capacitor. Connect V voltage. Bypass V
Boost Flying Capacitor Connection. BST provides the upper supply rail for the DH high-side gate driver. An internal switch between V MOSFET is on (DL pulled h igh and LX pulled to ground).
Inductor Connection. LX serves as the lower supply rail for the DH high-side gate driver. The MAX17409 al so u se s LX as the input to the zero-cross ing comparator.
to PGND with a 1µF or greater ceramic capacitor.
DD
supplies power to the low- side gate driver (DL) and to the internal
DD
and GND) to THRM with the valu es se lected so the
CC
(1.5V when VCC = 5V) at the desired high temperature.
CC
= 1/tSW) according to the following equation used to
SW
= 16.3pF x (R
). PWRGD remains blanked until the transition-
CC
for normal operation. Connect to ground to put the
CC
to PGND. DL is forced low in shutdown. DL is
DD
and BST charges the flying capacitor while the low-side
DD
) between the i nput power source and
TON
+ 6.5k)
TON
to the 4.5V to 5.5V sy stem supply
DD
MAX17409
1-Phase Quick-PWM GPU Controller
12 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
22 DH High-Side Gate-Driver Output. DH sw ings from LX to BST. The controller pulls DH low in shutdown.
23 GND Analog Ground. Internally connected to GND.
24 VRHOT
25 REF Buffered 2V Reference Output. Bypass REF with a 100pF to 1000pF capacitor. Do not exceed 1000pF.
26 ILIM
27 VCC Analog Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with a 1µF minimum capacitor.
28 CCV
— EP
Thermal Comparator’s Open-Drain Output. The comparator pulls VRHOT low when the voltage at THRM drops below 30% of V
Valley Current-Limit Adjustment Input. The valley current-limit threshold voltage at CSP to CSN equals precise ly 1/10 of the differential REF to ILIM voltage over a 0.1V to 0.5V range (10mV to 50mV current-sen se range). The negative current-lim it threshold is nom ina lly -125% of the corresponding valley current-limit threshold. Connect ILIM directly to V
Integrator Capacitor Connection. Connect a capacitor (C time constant. Choose the capacitor value according to:
where G frequency set by the R The integrator is internally disabled during any downward output-voltage transition that occurs in pulse-skipp ing mode, and remains disabled unti l the transit ion blan king period expire s and the output reaches regulation (error-amplifier transit ion detected).
Exposed Pad (Backside). Internally connected to the substrate. Connect to the ground plane through a thermally enhanced via.
= 320S (max) is the integrator’s transconductance and fSW is the switching
m(CCV)
TON
(1.5V with 5V VCC). VRHOT is high impedance in shutdown.
CC
to set the default 22.5mV current-limit threshold setting.
CC
CCV
16 x [C
resistance.
CCV/Gm(CCV)
] x f
) from CCV to GND to set the integration
>> 1
SW
MAX17409
1-Phase Quick-PWM GPU Controller
______________________________________________________________________________________ 13
Figure 1. MAX17409 Application Circuit
(VRON)
OFF
VID INPUTS
VALLEY CURRENT LIMIT SET BY THE TIME TO ILIM
SLEW RATE SET BY TIME BIAS CURRENT
V
CC
= 0.2V x R2/(R2 + R3)
V
LIMIT
dV/dt = 12.5mV/µs x 71.5k/(R2 + R3)
R3 R2
V
R6
R8
10k
10k
NTC2
100k
B = 4700
AGND
R
IMON
AGND
REF
C
REF
100pF
R5
AGND
3.3V
R4
10k
7.87k
C4
0.1µF AGND
R1
10
SHDNON
6
SKIP
11
G0
12
G1
13
G2
14
G3
15
G4
16
G5
MAX17409
26
ILIM
25
REF
9
PWRGD
24
VRHOT
7
THRM
1
IMON
GNDS/OFSP
GND (EP)
27
V
CC
19
V
DD
SWITCHING FREQUENCY (f
= 16.3pF x (R
t
SW
8
TON
R
20
BST
22
DH
21
LX
18
DL
17
PGND
5
CSP
4
CSN
C3
3
FB
2
R20
OPEN
28
CCV
23
AGND
BST
0
C
0.1µF
BST
C
CCV
100pF
R
C1
1.0µF AGND
TON
TON
C5
OPEN AGND
C6
OPEN AGND
V
R
GND
0
REF
10
= 1/tSW):
SW
+ 6.5kΩ)
N
HI
N
LO
PWR
LOAD LINE ADJUSTMENT: R
R
FB
AGND
PWR
C2
1.0µF
PWR
C
IN
PWR
L1
D1
R10
R11
C7
DCR THERMAL COMPENSATION
= R
/(R
FB
DROOP
1000pF
AGND
1000pF
AGND
REMOTE-SENSE FILTERS
x 600µS)
SENSE
C8
C9
R13
10
R14
10
5V BIAS
INPUT
INPUT
7V TO 24V
NTC1
CATCH RESISTORS
REQUIRED WHEN
CPU NOT POPULATED
R15 10
R16 10
PWR
C
OUT
PWR
CORE
OUTPUT
OUTPUT SENSE
GROUND SENSE
MAX17409
1-Phase Quick-PWM GPU Controller
14 ______________________________________________________________________________________
Figure 2. Functional Diagram
CSP
CSN
ILIM
REF
V
CC
REF (2.0V)
GND
G0–G5
SHDN
FAULT
REF
SLEW
CONTROL
DAC
TAR GET
MINIMUM OFF-TIME
TRIGQ
ONE-SHOT
FB
PGND
LX
1mV
ON-TIME
ONE SHOT
Q
TRIG
R
Q
S
SKIP
IMON
TON
BST
DH
S
Q
R
LX
V
DD
DL
CCV
G
FB
GNDS
G
m(CCV)
m(FB)
G
m(GNDS)
R7R
CSP
CSN
TARGET
+200mV
TARGET
-300mV
TARGET
+300mV
TARGET
-400mV
MAX17409
BLANK
FAULT
5ms
STARTUP
DELAY
0.3 x V
CC
PGND
SKIP
PWRGD
THRM
VRHOT
MAX17409
1-Phase Quick-PWM GPU Controller
______________________________________________________________________________________ 15
Table 1. Component Selection for Standard Applications
Table 2. Component Suppliers
DESIGN PARAMETERS 14A DESIGN 9A DESIGN 5A DESIGN
Input Voltage Range 8V to 20V 8V to 20V 8V to 20V
Maximum Load Current 14A 9A 5A
Transient Load Current 10A 7A 4A
COMPONENTS
TON Resistance (R
Inductance
(L1)
High-Side MOSFET (NHI)
Low-Side MOSFET (NLO)
Output Capacitors
(C
)
OUT
Input Capacitors
(C
)
IN
REF/ILIM Resistance (R2) 10k 17.8k 20 k
ILIM/GND Resistance (R3) 63.4k 60.4k 54.9k
FB Resistance (RFB) 100 100 100
Feedforward Capacitance
(C3)
LX/CSP Resistance (R10) 1.3k 1.3k 1.3k
CSP/CSN Series Resistance
(R11 + NTC1)
DCR Sense Capacitance
(C7)
IMON Resistance (R
)
TON
NEC-TOKIN MPC0750LR60C
9.4m/12.0m (typ/max)
4.2m/5.0m (typ/max)
2x 10µF, 25V ceramic (1210) 1x 10µF, 25V ceramic (1210) 1x 10µF, 25V ceramic (1210)
2k + 10k NTC (B = 3380) 2k + 10k NTC (B = 3380) 2k + 10 NTC (B = 3380)
0.22µF, 6V ceram ic (0603) 0.1µF, 6V ceramic (0603) 0.1µF, 6V ceramic (0603)
) 6.81 k 3.92 k 3.24 k
IMON
200k
(f
= 300kHz)
SW
0.6µH, 17A, 2.3m TOKO FDVE0630-R75M
11m/13.75m (typ/max)
Fairch ild FDS6298
Fairch ild FDS8670
1x 470µF, 6m, 2V SANYO 2TPE470M6
0.22µF 0.15µF 0.1µF
Internationa l Rectifier IRF7822
170k
(fSW = 350kHz)
0.75µH, 10.7A, 6.2m
Vishay Si7392DP
5m/6.5m (typ/max)
1x 330µF, 6m, 2V
SANYO 2TPE330M6
(fSW = 390kHz)
1.50µH, 8A, 12.1m
TOKO FDVE0630-1R5M
14.5m/20.5m (typ/max)
Internationa l Rectifier IRF7904
10m/13m (typ/max)
Internationa l Rectifier IRF7904
1x 220µF, 6m, 2V SANYO 2TPE220M6
150k
MANUFACTURER WEBSITE
AVX Corporation www.av xcorp.com
Fairch ild Semiconductor www.fairchildsem i.com
NEC-TOKIN America, Inc. www.nec-tokinamerica.com
Panason ic Corp. www.panasonic.com
SANYO Electric Co., Ltd. www.sanyodevice.com
MANUFACTURER WEBSITE
Taiyo Yuden www.t-yuden.com
TDK Corp. www.component.tdk.com
TOKO America, Inc. www.tokoam.com
Toshiba America Electronic Component s, Inc.
Vishay www.vishay.com
www.tosh iba.com/taec
MAX17409
1-Phase Quick-PWM GPU Controller
16 ______________________________________________________________________________________
Detailed Description
Free-Running, Constant On-Time PWM
Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixed­frequency, constant-on-time, current-mode regulator with voltage feed-forward (Figure 2). This architecture relies on the output filter capacitor’s ESR to act as the current-sense resistor, so the output ripple voltage pro­vides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to input voltage, and directly proportional to output volt­age (see the
On-Time One-Shot
section). Another one­shot sets a minimum off-time. The on-time one-shot triggers when the error comparator goes low, the induc­tor current is below the valley current-limit threshold, and the minimum off-time one-shot times out.
+5V Bias Supply (VCCand VDD)
The Quick-PWM controller requires an external +5V bias supply in addition to the battery. Typically, this +5V bias supply is the notebook’s 95% efficient +5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associat­ed with the +5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the +5V bias supply can be generated with an external linear regulator.
The +5V bias supply must provide VCC(PWM con­troller) and VDD(gate-drive power), so the maximum current drawn is:
where ICCis provided in the
Electrical Characteristics
table, fSWis the switching frequency, and Q
G(LOW)
and
Q
G(HIGH)
are the MOSFET data sheet’s total gate-
charge specification limits at VGS= 5V.
VINand VDDcan be connected together if the input power source is a fixed +4.5V to +5.5V supply. If the +5V bias supply is powered up prior to the battery sup­ply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup.
Switching Frequency (TON)
Connect a resistor (R
TON
) between TON and VINto set
the switching period (tSW= 1/fSW):
tSW= 16.3pF x (R
TON
+ 6.5kΩ)
A 96.75kto 303.25kcorresponds to switching peri­ods of 167ns (600kHz) to 500ns (200kHz), respectively.
High-frequency (600kHz) operation optimizes the appli­cation for the smallest component size, trading off effi­ciency due to higher switching losses. This might be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. Low-frequency (200kHz) opera­tion offers the best overall efficiency at the expense of component size and board space.
On-Time One-Shot
The core contains a fast, low-jitter, adjustable one-shot that sets the high-side MOSFET’s on-time. The one-shot varies the on-time in response to the input and feed­back voltages. The main high-side switch on-time is inversely proportional to the input voltage as measured by the R
TON
input, and proportional to the feedback
voltage (VFB):
where the switching period (tSW= 1/fSW) is set by the resistor at the TON pin and 0.075V is an approximation to accommodate the expected drop across the low­side MOSFET switch.
This algorithm results in a nearly constant switching fre­quency and balanced inductor currents despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: first, the fre­quency can be selected to avoid noise-sensitive regions such as the 455kHz IF band; second, the induc­tor ripple-current operating point remains relatively con­stant, resulting in easy design methodology and predictable output-voltage ripple. The on-time one­shots have good accuracy at the operating points specified in the
Electrical Characteristics
table. On­times at operating points far removed from the condi­tions specified in the
Electrical Characteristics
table
can vary over a wider range.
On-times translate only roughly to switching frequen­cies. The on-times guaranteed in the
Electrical
Characteristics
table are influenced by switching delays in the external high-side MOSFET. Resistive losses, including the inductor, both MOSFETs, output capacitor ESR, and PCB copper losses in the output and ground tend to raise the switching frequency at higher output currents. Also, the dead-time effect increases the effective on-time, reducing the switching frequency. It occurs only during forced-PWM operation and dynamic output-voltage transitions when the induc­tor current reverses at light or negative load currents. With reversed inductor current, the inductor’s EMF causes LX to go high earlier than normal, extending the
IIfQ Q
=+ +
BIAS CC SW G LOW G HIGH
()
() ( )
t
ON MAIN
()
tV V
()
SW FB
V
IN
.=+
0 075
MAX17409
1-Phase Quick-PWM GPU Controller
______________________________________________________________________________________ 17
on-time by a period equal to the DH rising dead time. For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is:
where V
DROP1
is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PCB resistances; V
DROP2
is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and PCB resis­tances; and tONis the on-time as determined above.
Current Sense
The output current is differentially sensed by the high­impedance current-sense inputs (CSP and CSN). Low­offset amplifiers are used for voltage-positioning gain, current-limit protection, and power monitoring. Sensing the current at the output offers advantages, including less noise sensitivity and the flexibility to use either a current-sense resistor or the DC resistance of the out­put inductor.
Using the DC resistance (R
DCR
) of the output inductor allows higher efficiency. In this configuration, the initial tolerance and temperature coefficient of the inductor’s DCR must be accounted for in the output-voltage droop­error budget and power monitor. This current-sense method uses an RC filtering network to extract the cur­rent information from the inductor (see Figure 3). The resistive divider used should provide a current-sense resistance (RCS) low enough to meet the current-limit requirements, and the time constant of the RC network should match the inductor’s time constant (L/RCS):
and:
where RCSis the required current-sense resistance, and R
DCR
is the inductor’s series DC resistance. Use
the worst-case inductance and R
DCR
values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. To minimize the current-sense error due to the current­sense inputs’ bias current (I
CSP
and I
CSN
), choose
R1//R2 to be less than 2kand use the above equation to determine the sense capacitance (CEQ). Choose capacitors with 5% tolerance and resistors with 1% tol­erance specifications. Temperature compensation is
recommended for this current-sense method. See the
Voltage Positioning and Loop Compensation
section.
When using a current-sense resistor for accurate output­voltage positioning, the circuit requires a differential RC filter to eliminate the AC voltage step caused by the equivalent series inductance (L
ESL
) of the current-sense resistor (see Figure 3). The ESL-induced voltage step does not affect the average current-sense voltage, but results in a significant peak current-sense voltage error that results in unwanted offsets in the regulation voltage and results in early current-limit detection. Similar to the inductor DCR sensing method above, the RC filter’s time constant should match the L/R time constant formed by the current-sense resistor’s parasitic inductance:
where L
ESL
is the equivalent series inductance of the
current-sense resistor, R
SENSE
is the current-sense resis­tance value, CEQand R1 are the time-constant matching components.
Current Limit
The current-limit circuit employs a “valley” current­sensing algorithm that uses current-sense inputs (CSP to CSN) as the current-sensing elements. If the current­sense signal exceeds the current-limit threshold, the PWM controller does not initiate a new cycle until the inductor current drops below the valley current-limit threshold.
Since only the valley current level is actively limited, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple cur­rent. Therefore, the exact current-limit characteristic and maximum load capability are a function of the cur­rent-sense resistance, inductor value, and battery volt­age. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance.
The positive current-limit threshold is fixed internally at
22.5mV (typ). There is also a negative current limit that prevents excessive reverse inductor currents when V
OUT
is sinking current. The negative current-limit threshold is 130% of the nominal valley current-limit threshold. When the inductor current drops below the negative current limit, the controller immediately acti­vates an on-time pulse—DL turns off and DH turns on— allowing the inductor current to remain above the negative current threshold.
Carefully observe the PCB layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signals seen by the current-sense inputs (CSP, CSN).
f
=
SW
VV
+
()
OUT DROP
tVV V
ON IN DROP DROP
+
()
1
-
12
R
=
CS DCR
R
=+
CS
CRR
2
R
R
⎟ ⎠
+
12
RR
L
111
EQ
⎡ ⎢
⎤ ⎥
2
L
R
SENSE
ESL
= 1
CR
EQ
MAX17409
1-Phase Quick-PWM GPU Controller
18 ______________________________________________________________________________________
Figure 3. Current-Sense Methods
Feedback Adjustment Amplifiers
Voltage-Positioning Amplifier
(Steady-State DC Droop)
The MAX17409 includes a transconductance amplifier for adding gain to the voltage-positioning sense path. The amplifier’s input is generated by the differential cur­rent-sense inputs, which sense the inductor current by measuring the voltage across either current-sense resistors or the inductor’s DCR. The amplifier’s output connects directly to the regulator’s voltage-positioned feedback input (FB), so the resistance between FB and the output-voltage sense point determines the voltage­positioning gain:
where the target voltage (V
TARGET
) is defined in the
Nominal Output-Voltage Selection
section, and the FB amplifier’s output current (IFB) is determined by the cur­rent-sense voltages:
IFB= G
m(FB)
x (V
CSP
- V
CSN
)
where V
CSP
- V
CSN
is the differential current-sense volt-
age, and G
m(FB)
is typically 600µS, as defined in the
Electrical Characteristics
table.
Differential Remote Sense
The MAX17409 includes differential, remote-sense inputs to eliminate the effects of voltage drops along the PCB traces and through the processor’s power pins. The feedback-sense node connects to the voltage-posi­tioning resistor (RFB). The ground-sense (GNDS) input connects to an amplifier that adds an offset directly to the target voltage, effectively adjusting the output volt­age to counteract the voltage drop in the ground path. Connect the voltage-positioning resistor (RFB) and ground-sense (GNDS) input directly to the processor’s remote-sense outputs as shown in Figure 1.
Integrator Amplifier
An integrator amplifier forces the DC average of the FB voltage to equal the target voltage. This transconduc­tance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage
INPUT (VIN)
C
IN
L
D
L
SENSE RESISTOR
L
ESL
R1
R
C
SENSE
EQ
MAX17409
DH
PGND
N
H
LX
DL
N
L
L
SENSE
CEQR1 =
C
OUT
R
SENSE
A) OUTPUT SERIES RESISTOR SENSING
MAX17409
B) LOSSLESS INDUCTOR SENSING
CSP
CSN
DH
PGND
CSP
CSN
N
H
LX
DL
N
L
C
D
VV RI
= -
OUT TARGET FB FB
INPUT (VIN)
IN
L
INDUCTOR
L
R
1
R
DCR
C
R
2
C
EQ
OUT
FOR THERMAL COMPENSATION: R2 SHOULD CONSIST OF AN NTC RESISTOR IN SERIES WITH A STANDARD THIN-FILM RESISTOR.
RCS = R2 R
R1 + R2
L
R
=
DCR
[
CEQ R1 R2
DCR
1 + 1
]
MAX17409
1-Phase Quick-PWM GPU Controller
______________________________________________________________________________________ 19
(Figure 2), allowing accurate DC output-voltage regula­tion regardless of the output ripple voltage. The integra­tor amplifier has the ability to shift the output voltage by ±80mV (typ). The differential input voltage range is at least ±60mV total, including DC offset and AC ripple. The integration time constant can be set easily with an external compensation capacitor between CCV and analog ground, with the minimum recommended CCV capacitor value determined by:
where G
m(CCV)
is the integrator’s maximum transcon-
ductance (320µs) and f
SW
is the switching frequency
set by the TON resistance.
The MAX17409 disables the integrator by connecting the amplifier inputs together at the beginning of all VID transitions done in pulse-skipping mode (SKIP = high). The integrator remains disabled until 20µs after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator).
Nominal Output-Voltage Selection
The nominal no-load output voltage (V
TARGET
) is defined by the selected voltage reference (VID DAC) plus the remote ground-sense adjustment (V
GNDS
) as
defined in the following equation:
where V
DAC
is the selected VID voltage. On startup, the MAX17409 slews the target voltage from ground to the selected VID voltage.
DAC Inputs (G0–G5)
The digital-to-analog converter (DAC) programs the output voltage using the G0–G5 inputs. G0–G5 are low­voltage (1.0V) logic inputs, designed to interface direct­ly with the CPU. Do not leave G0–G5 unconnected. Changing G0–G5 initiates a transition to a new output­voltage level. Change G0–G5 together, avoiding greater than 20ns skew between bits. Otherwise, incor­rect DAC readings could cause a partial transition to the wrong voltage level followed by the intended transi­tion to the correct voltage level, lengthening the overall transition time (Table 4).
Table 3. MAX17409 Operating Mode Truth Table
VVVV
TARGET FB DAC GNDS
C
CCV
G
m CCV
()
>>
f
×
16π
SW
SHDN SKIP OPERATING MODE DESCRIPTION
GND X DISABLED
Rising X
High Low
High High
Fal ling X
High X DISABLED
Pulse-Skipping
1.56mV/µs Slew Rate
Forced-PWM
12.5mV/µ s Slew Rate
Pulse-Skipping
12.5mV/µ s Slew Rate
Forced-PWM
1.56mV/µs Slew Rate
Low-Power Shutdown Mode. DL forced low, and the controller is disabled. The supply current drops to 10µA (max).
Startup. When SHDN is pulled high, the MAX17409 begins the startup sequence. The controller enables the PWM controller and ramps the output voltage up to the selected VID voltage.
Ful l Power. The no-load output voltage is determined by the selected VID DAC code (G0–G5, Table 4).
Suspend Mode. The no-load output voltage i s determined by the selected VID DAC code (G0–G5, Table 4). When SKIP is pulled high, the MAX17409 immediately enters pulse-skipping operation, allowing automatic PWM/PFM switchover under light loads. The PWRGD upper threshold is blan ked during the transit ion.
Shutdown. When SHDN is pulled low, the MAX17409 immediately pull s PWRGD low, and the output vo ltage is ramped down to ground. Once the output reache s 0V, the controller enters the low-power shutdown state.
Fault Mode. The fault latch has been set by the MAX17409 UVP or thermal-shutdown protection, or by the OVP protection. The controller remains in fault mode until V
power is cycled or SHDN toggled.
CC
== +
MAX17409
1-Phase Quick-PWM GPU Controller
20 ______________________________________________________________________________________
Table 4. Output Voltage VID DAC Codes
G5 G4 G3 G2 G1 G0
1 0 0 0 0 0 1.1250
1 0 0 0 0 1 1.1125
1 0 0 0 1 0 1.1000
1 0 0 0 1 1 1.0875
1 0 0 1 0 0 1.0750
1 0 0 1 0 1 1.0675
1 0 0 1 1 0 1.0500
1 0 0 1 1 1 1.0375
1 0 1 0 0 0 1.0250
1 0 1 0 0 1 1.0125
1 0 1 0 1 0 1.0000
1 0 1 0 1 1 0.9875
1 0 1 1 0 0 0.9750
1 0 1 1 0 1 0.9625
1 0 1 1 1 0 0.9500
1 0 1 1 1 1 0.9275
1 1 0 0 0 0 0.9250
1 1 0 0 0 1 0.9125
1 1 0 0 1 0 0.9000
1 1 0 0 1 1 0.8875
1 1 0 1 0 0 0.8750
1 1 0 1 0 1 0.8625
1 1 0 1 1 0 0.8500
1 1 0 1 1 1 0.8375
1 1 1 0 0 0 0.8250
1 1 1 0 0 1 0.8125
1 1 1 0 1 0 0.8000
1 1 1 0 1 1 0.7875
1 1 1 1 0 0 0.7750
1 1 1 1 0 1 0.7625
1 1 1 1 1 0 0.7500
1 1 1 1 1 1 0.7375
VOLTAGE (V)
OUTPUT
G5 G4 G3 G2 G1 G0
0 0 0 0 0 0 0.7250
0 0 0 0 0 1 0.7125
0 0 0 0 1 0 0.7000
0 0 0 0 1 1 0.6875
0 0 0 1 0 0 0.6750
0 0 0 1 0 1 0.6625
0 0 0 1 1 0 0.6500
0 0 0 1 1 1 0.6275
0 0 1 0 0 0 0.6250
0 0 1 0 0 1 0.6125
0 0 1 0 1 0 0.6000
0 0 1 0 1 1 0.5875
0 0 1 1 0 0 0.5750
0 0 1 1 0 1 0.5625
0 0 1 1 1 0 0.5500
0 0 1 1 1 1 0.5275
0 1 0 0 0 0 0.5250
0 1 0 0 0 1 0.5125
0 1 0 0 1 0 0.5000
0 1 0 0 1 1 0.4875
0 1 0 1 0 0 0.4750
0 1 0 1 0 1 0.4625
0 1 0 1 1 0 0.4500
0 1 0 1 1 1 0.4275
0 1 1 0 0 0 0.4250
0 1 1 0 0 1 0.4125
0 1 1 0 1 0 0.4000
0 1 1 0 1 1 0.3875
0 1 1 1 0 0 0.3750
0 1 1 1 0 1 0.3625
0 1 1 1 1 0 0.3500
0 1 1 1 1 1 0.3375
OUTPUT
VOLTAGE (V)
MAX17409
1-Phase Quick-PWM GPU Controller
______________________________________________________________________________________ 21
Output-Voltage Transition Timing
The MAX17409 performs mode transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output voltage level with the lowest possible peak currents for a given output capacitance.
At the beginning of an output-voltage transition, the MAX17409 blanks both PWRGD thresholds, preventing the PWRGD open-drain output from changing states during the transition. The controller enables the PWRGD thresholds approximately 20µs after the slew­rate controller reaches the target output voltage. The slew rate is set to 12.5mV/µs to ensure that the transi­tion can be completed within a reasonable time period.
The MAX17409 automatically controls the current to the minimum level required to complete the transition in the calculated time. The slew-rate controller uses an inter­nal capacitor and current source to transition the target voltage. The total transition time depends on the
12.5mV/µs slew rate, the voltage difference, and the accuracy of the slew-rate controller, C
SLEW
, accuracy).
The slew rate is not dependent on the total output capacitance, as long as the surge current is less than the current limit. For all dynamic VID transitions, the transition time (t
TRAN
) is given by:
where V
OLD
is the original output voltage, and V
NEW
is
the new target voltage. See Slew-Rate Accuracy in the
Electrical Characteristics
for slew-rate limits. For soft­start and shutdown, the controller automatically reduces the slew rate to 1.56mV/µs (1/8 of the nominal slew rate).
The output voltage tracks the slewed target voltage, making the transitions relatively smooth. The average inductor current required to make an output voltage transition is:
where C
OUT
is the total output capacitance.
Figure 4. VID Transition
t
TRAN
VV
-
NEW OLD
=
12 5.
mVµs
IC mVµs
≅×12 5.
LOUT
OVP LEVEL
HIGH VID
CPU CORE
VOLTAGE
VID (G0–G5)
SKIP
INTERNAL
PWM CONTROL
DH
PWRGD
INTERNAL
TARGET
BLANK HIGH-Z
OVP = 1.45V MIN
NO PULSES: V
t
BLANK
20µs TYP
ACTUAL V
SLEEP VID
PULSE-SKIPPING MODE
> V
OUT
TARGET
LOW THRESHOLD ONLY
OUT
OVP TRACKS INTERNAL TARGET
FORCED-PWM MODE
BLANK HIGH-Z
t
BLANK
20µs TYP
NEW ACTIVE VID LOW VID
MAX17409
1-Phase Quick-PWM GPU Controller
22 ______________________________________________________________________________________
Forced-PWM Operation (Normal Mode)
During soft-shutdown and normal operation—when the CPU is actively running (SKIP = low, Table 3)—the MAX17409 operates with the low-noise, forced-PWM control scheme. Forced-PWM operation disables the zero-crossing comparator, forcing the low-side gate­drive waveforms to constantly be the complement of the high-side gate-drive waveforms. This keeps the switching frequency constant and allows the inductor current to reverse under light loads, providing fast, accurate negative-output-voltage transitions by quickly discharging the output capacitors.
Forced-PWM operation comes at a cost: the no-load +5V bias supply current remains between 10mA to 50mA, depending on the external MOSFETs and switching frequency. To maintain high efficiency under light-load conditions, the processor might switch the controller to a low-power pulse-skipping control scheme after entering suspend mode. The MAX17409 automatically uses pulse-skipping operation during soft-start, regardless of the SKIP configuration.
Light-Load Pulse-Skipping Operation
During soft-start and sleep states—SKIP is pulled high—the MAX17409 operates in pulse-skipping mode. The pulse-skipping mode enables the driver’s zero­crossing comparator, so the controller pulls DL low when its current-sense inputs detect “zero” inductor current. This keeps the inductor from sinking current and discharging the output capacitors and forces the controller to skip pulses under light-load conditions to avoid overcharging the output.
Upon entering pulse-skipping operation, the controller temporarily blanks the upper PWRGD thresholds, and sets the OVP threshold to 1.80V to prevent false OVP faults when the transition to pulse-skipping operation coincides with a VID DAC code. The MAX17409 auto­matically uses forced-PWM operation during soft-shut­down, regardless of the SKIP configuration.
Automatic Pulse-Skipping Switchover
In skip mode (SKIP = high), an inherent automatic switchover to PFM takes place at light loads. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current’s zero crossing. The zero-crossing comparator senses the inductor current across the low-side MOSFETs.
Once VLXdrops below the zero-crossing comparator threshold (see the
Electrical Characteristics
table), the comparator forces DL low (Figure 2). This mechanism causes the threshold between pulse-skipping PFM and nonskipping-PWM operation to coincide with the boundary between continuous and discontinuous induc­tor-current operation. The PFM/PWM crossover occurs when the load current is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (Figure 5). For a 7V to 20V battery input range, this threshold is relatively constant, with only a minor depen­dence on the input voltage due to the typically low duty cycles. The total load current at the PFM/PWM crossover threshold (I
LOAD(SKIP)
) is approximately:
The switching waveforms might appear noisy and asyn­chronous when light loading activates pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs between PFM noise and light-load efficiency are made by varying the inductor value. Generally, low inductor values pro­duce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output volt­age ripple. Penalties for using higher inductor values include larger physical size and degraded load-tran­sient response, especially at low input-voltage levels.
Figure 5. Pulse-Skipping/Discontinuous Crossover Point
I
LOAD SKIP
()
tVLVV
1
=
⎜ ⎝
2
-
SW OUT IN OUT
⎞ ⎟
V
IN
⎞ ⎟
⎠⎠
I
V
- V
BATT
=
t
INDUCTOR CURRENT
ON-TIME0 TIME
OUT
L
I
PEAK
I
= I
PEAK
/2
LOAD
MAX17409
1-Phase Quick-PWM GPU Controller
______________________________________________________________________________________ 23
Power-Up Sequence (POR, UVLO)
The MAX17409 is enabled when SHDN is driven high (Figure 6). The reference powers up first. Once the ref­erence exceeds its UVLO threshold, the internal analog blocks are turned on and masked by a 150µs one-shot delay. The PWM controller then begins switching.
Power-on reset (POR) occurs when VCCrises above approximately 2V, resetting the fault latch and prepar­ing the controller for operation. The V
CC
UVLO circuitry
inhibits switching until V
CC
rises above 4.25V. The con­troller powers up the reference once the system enables the controller, VCCis above 4.25V, and SHDN is driven high. With the reference in regulation, the con­troller ramps the output voltage to the selected VID volt­age with a 1.56mV/µs slew rate:
where V
BOOT
is the initial VID target. The soft-start cir­cuitry does not use a variable current limit, so full output current is available immediately. PWRGD becomes high impedance approximately 5ms after the target out­put voltage is reached. The MAX17409 automatically uses pulse-skipping mode during soft-start and uses forced-PWM mode during soft-shutdown, regardless of the SKIP configuration.
For automatic startup, the battery voltage should be present before VCC. If the controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. The controller remains shut down until the fault latch is cleared by toggling SHDN or cycling the VCCpower supply below 0.5V.
If the VCCvoltage drops below 4.25V, the controller assumes that there is not enough supply voltage to make valid decisions. To protect the output from over­voltage faults, the controller shuts down immediately and forces a high-impedance output (DL and DH pulled low).
Figure 6. Power-Up and Shutdown Sequence Timing Diagram
t
TRAN START
()
V
CC
SHDN
V
=
./
156
()
BOOT
mV µs
INVALID VID INVALID VID CODE
G0–G5
OVP LEVEL
SOFT-START =
1.56mV/µs SLEW RATE
INITIAL TARGET
V
CORE
INTERNAL
PWM CONTROL
PWRGD
OVP = 1.45V MIN OVP = 1.45V MIN
PULSE SKIPPING
t
BLANK
60µs TYP
OVP TRACKS INTERNAL TARGET
t
BLANK
5ms TYP
t
BLANK
20µs TYP
FORCED-PWM
t
BLANK
20µs TYP
SOFT-SHUTDOWN =
1.56mV/µs SLEW RATE
MAX17409
1-Phase Quick-PWM GPU Controller
24 ______________________________________________________________________________________
Shutdown
When SHDN goes low, the MAX17409 enters low-power shutdown mode. PWRGD is pulled low immediately, and the output voltage ramps down with a 1.56mV/µs slew rate:
Slowly discharging the output capacitors by slewing the output over a long period of time keeps the average negative inductor current low (damped response), thereby eliminating the negative output-voltage excur­sion that occurs when the controller discharges the out­put quickly by permanently turning on the low-side MOSFET (underdamped response). This eliminates the need for the Schottky diode normally connected between the output and ground to clamp the negative output-voltage excursion. After the controller reaches the zero target, the MAX17409 shuts down completely— the drivers are disabled (DL driven high, DH pulled low)—the reference turns off, and the supply currents drop to approximately 1µA (max).
When a fault condition—output UVLO or thermal shut­down—activates the shutdown sequence, the protec­tion circuitry sets the fault latch to prevent the controller from restarting. To clear the fault latch and reactivate the controller, toggle SHDN or cycle V
CC
power below
0.5V typ.
Temperature Comparator (
VRHOT
)
The MAX17409 also features an independent compara­tor with an accurate threshold (V
HOT
) that tracks the
analog supply voltage (V
HOT
= 0.3VCC). This makes the thermal trip threshold independent of the VCCsupply voltage tolerance. Use a resistor- and thermistor-divider between VCCand GND to generate a voltage-regulator overtemperature monitor. Place the thermistor as close to the MOSFETs and inductors as possible.
Fault Protection (Latched)
Output Overvoltage (OVP) Protection
The OVP circuit is designed to protect the processor against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The MAX17409 continuously monitors the output for an overvoltage fault. The controller detects an OVP fault if the output voltage exceeds the set VID DAC voltage by more than 300mV, subject to a minimum OVP threshold of 0.8V. During pulse-skipping operation (SKIP = high), the controller initially sets the OVP threshold to a fixed 1.8V threshold.
Once the output is in regulation (the first on-time is trig­gered) and the PWRGD blanking time expires, the con­troller tightens the OVP threshold, tracking the OVP threshold by 300mV, subject to a minimum OVP thresh­old of 0.8V. The controller also uses the fixed 1.8V OVP threshold during soft-start and soft-shutdown.
When the OVP circuit detects an overvoltage fault, the MAX17409 immediately forces DL high and pulls DH low. This action turns on the synchronous-rectifier MOSFETs with 100% duty and, in turn, rapidly discharges the output filter capacitor and forces the output low. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse blows. Toggle SHDN or cycle the VCCpower supply below 0.5V to clear the fault latch and reactivate the controller.
OVP protection can be disabled through the no-fault test mode (see the
No-Fault Test Mode
section).
Output Undervoltage Protection (UVP)
The output UVP function is similar to foldback current limiting, but employs a timer rather than a variable cur­rent limit. If the MAX17409 output voltage is 400mV below the target voltage, the controller activates the shutdown sequence and sets the fault latch. Once the controller ramps down to zero, it forces the DL high, and pulls DH low. Toggle SHDN or cycle the VCCpower supply below 0.5V to clear the fault latch and reactivate the controller.
UVP protection can be disabled through the no-fault test mode (see the
No-Fault Test Mode
section).
Thermal-Fault Protection
The MAX17409 features a thermal-fault protection cir­cuit. When the junction temperature rises above +160°C, an internal thermal sensor sets the fault latch and forces the DL high and the DH low. Toggle SHDN or cycle the VCCpower supply below 0.5V to clear the fault latch and reactivate the controller after the junction temperature cools by 15°C. Thermal shutdown can be disabled through the no-fault test mode (see the
No-
Fault Test Mode
section).
No-Fault Test Mode
The latched fault protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to deter­mine what went wrong. Therefore, a “no-fault” test mode is provided to disable the fault protection—over­voltage protection, undervoltage protection, and ther­mal shutdown. Additionally, the test mode clears the fault latch if it has been set. The no-fault test mode is entered by forcing 11V to 13V on SHDN.
t
TRAN SHDN
()
V
OUT
=
mV µs
./
156
()
MAX17409
1-Phase Quick-PWM GPU Controller
______________________________________________________________________________________ 25
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moder­ate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications, where a large V
IN
-
V
OUT
differential exists. The high-side gate drivers (DH) source and sink 2.2A, and the low-side gate drivers (DL) source 2.7A and sink 8A. This ensures robust gate drive for high-current applications. The DH floating high-side MOSFET drivers are powered by internal boost switch charge pumps at BST, while the DL syn­chronous-rectifier drivers are powered directly by the 5V bias supply (V
DD
).
Adaptive dead-time circuits monitor the DL and DH dri­vers and prevent either FET from turning on until the other is fully off. The adaptive driver dead-time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency.
There must be a low-resistance, low-inductance path from the DL and DH drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; other­wise, the sense circuitry in the MAX17409 interprets the MOSFET gates as “off” while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver).
The internal pulldown transistor that drives DL low is robust, with a 0.25(typ) on-resistance. This helps DL from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX) quickly switches from ground to V
IN
. Applications with high input voltages and long inductive driver traces might require that rising LX edges do not pull up the low-side MOSFETs’ gate, causing shoot­through currents. The capacitive coupling between LX and DL created by the MOSFET’s gate-to-drain capaci­tance (C
RSS
), gate-to-source capacitance (C
ISS
-
C
RSS
), and additional board parasitics should not
exceed the following minimum threshold:
Typically, adding a 4700pF between DL and power ground (CNLin Figure 7), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays.
Alternatively, shoot-through currents could be caused by a combination of fast high-side MOSFETs and slow low-side MOSFETs. If the turn-off delay time of the low­side MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually
turned off. Adding a resistor less than 5in series with BST slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrad­ing the turn-off time (R
BST
in Figure 7). Slowing down the high-side MOSFET also reduces the LX node rise time, thereby reducing EMI and high-frequency cou­pling responsible for switching noise.
Quick-PWM Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switch­ing frequency and inductor operating point, and the fol­lowing four factors dictate the rest of the design:
Input voltage range: The maximum value
(V
IN(MAX)
) must accommodate the worst-case high
AC adapter voltage. The minimum value (V
IN(MIN)
) must account for the lowest input voltage after drops due to connectors, fuses, and battery selec­tor switches. If there is a choice at all, lower input voltages result in better efficiency.
Maximum load current: There are two values to consider. The peak load current (I
LOAD(MAX)
) deter­mines the instantaneous component stresses and filtering requirements, and thus drives output
Figure 7. Gate-Drive Circuit
VV
GS TH IN
()
>
⎜ ⎝
C
RSS
C
ISS
(R
)*
C
BYP
(CNL)*
BST
C
BST
N
N
(R
BST
SWITCHING NODE RISE TIME.
)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
(C
NL
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
MAX17409
)* OPTIONAL—THE RESISTOR LOWERS EMI, DECREASING THE
BST
DH
V
PGND
LX
DD
DL
INPUT (VIN)
H
L
L
MAX17409
1-Phase Quick-PWM GPU Controller
26 ______________________________________________________________________________________
capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continu­ous load current (I
LOAD
) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-con­tributing components. Modern notebook CPUs gen­erally exhibit I
LOAD
= I
LOAD(MAX)
x 80%.
Switching frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and V
IN
2
. The opti­mum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical.
Inductor operating point: This choice provides trade-offs between size vs. efficiency and transient response vs. output noise. Low inductor values pro­vide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduc­tion (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction bene­fit. The optimum operating point is usually found between 20% and 50% ripple current.
Inductor Selection
The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows:
Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite and molded iron cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (I
PEAK
):
Transient Response
The inductor ripple current impacts transient-response performance, especially at low VIN- V
OUT
differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output fil­ter capacitors by a sudden load step. The amount of
output sag is also a function of the maximum duty fac­tor, which can be calculated from the on-time and mini­mum off-time. The worst-case output sag voltage can be determined by:
where t
OFF(MIN)
is the minimum off-time (see the
Electrical Characteristics
table).
The amount of overshoot due to stored inductor energy can be calculated as:
Current-Limit Control (ILIM)
REF and ILIM are used to set the current limit. REF reg­ulates to a fixed 2.0V and the REF-to-ILIM voltage determines the valley current-sense threshold. When ILIM = VCC, the controller uses the preset 22.5mV cur­rent-limit threshold. In an adjustable design, ILIM is connected to a resistive voltage-divider connected between REF and ground. The differential voltage between REF and ILIM sets the current-limit threshold (V
LIMIT
), so the valley current-sense threshold is:
This allows design flexibility since the DCR sense circuit or sense resistor does not have to be adjusted to meet the current limit as long as the current-sense voltage never exceeds 50mV. Keeping V
LIMIT
between 20mV to
40mV leaves room for future current-limit adjustment.
The minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. The val­ley of the inductor current occurs at I
LOAD(MAX)
minus
half the ripple current; therefore:
VV
-
L
=
IN OUT
fI LIRVV
SW LOAD MAX
()
⎜ ⎝
OUT
IN
⎞ ⎟
⎠⎠
()
LOAD(MA X)
V
=
SAG
CV
2
OUT OUT
⎡ ⎢ ⎢
2
Vt
OUT SW
⎜ ⎝
VV t
-
()
IN OUT SW
⎜ ⎝
V
IN
+LI
t
OFF
V
IN
tt
-
OFF MIN()
⎟ ⎠
(MMIN
⎤ ⎥
)
⎤ ⎥ ⎥
V
SOA R
IL
()
LOAD MAX
2
CV
OUT OUT
2
()
VV
-
V
LIMIT
REF ILIM
=
10
II
=+
PEAK L OAD MAX
1
()
LIR
2
⎞ ⎟
II
VALLEY LOAD MAX
>
()
LIR
12-
MAX17409
1-Phase Quick-PWM GPU Controller
______________________________________________________________________________________ 27
where:
where R
SENSE
is the sensing resistor and R
CSP-CSN
/
R
LX-CSN
is the ratio of resistor-divider with DCR-sensing
approach.
Voltage Positioning and
Loop Compensation
Voltage positioning dynamically lowers the output volt­age in response to the load current, reducing the out­put capacitance and processor’s power dissipation requirements. The controller uses a transconductance amplifier to set the transient and DC output voltage droop (Figure 2) as a function of the load. This adjusta­bility allows flexibility in the selected current-sense resistor value or inductor DCR, and allows smaller cur­rent-sense resistance to be used, reducing the overall power dissipated.
Steady-State Voltage Positioning
Connect a resistor (RFB) between FB and V
OUT
to set the DC steady-state droop (load line) based on the required voltage positioning slope (R
DROOP
):
where the effective current-sense resistance (R
SENSE
)
depends on the current-sense method (see the
Current
Sense
section), and the voltage-positioning amplifier’s
transconductance (G
m(FB)
) is typically 600µS as
defined in the
Electrical Characteristics
table. When the inductors’ DCR is used as the current-sense element (R
SENSE
= R
DCR
), each current-sense input should include an NTC thermistor to minimize the temperature dependence of the voltage-positioning slope.
Output Capacitor Selection
The output filter capacitor must have low enough effec­tive equivalent series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements.
In processor core supplies and other applications where the output is subject to large load transients, the output capacitor’s size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance:
In nonprocessor applications, the output capacitor’s size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor’s ESR. The maximum ESR to meet rip­ple requirements is:
where f
SW
is the switching frequency. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usu­ally selected by ESR and voltage rating rather than by capacitance value (this is true of polymer types).
When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent V
SAG
and V
SOAR
from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the V
SAG
and V
SOAR
equations
in the
Transient Response
section).
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching fre­quency. The boundary of instability is given by the fol­lowing equation:
where:
and:
where C
OUT
is the total output capacitance, R
ESR
is the
total ESR, R
SENSE
is the current-sense resistance (R
CM
= RCS), R
DROOP(AC)
is the AC component of the droop,
and R
PCB
is the parasitic board resistance between the
output capacitors and sense resistors.
V
I
VALLEY
LIMIT
==
R
SENSE
DCR
V
×
LIMIT
R
R
-
CSP CSN
LX
-CCSN
R
R
FB
DROOP
=
RG
SENSE m FB
()
V
RR
+
()
ESR PCB
I
LOAD MAX
STEP
()
V
⎥ ⎥
RI PPLE
Vf L
R
ESR
IN SW
-
VV V
()
IN OUT OUT
f
ESR
RRR R
=+ +
EFF ESR DRO OP AC PCB
f
ESR
=
2π
f
SW
π
1
RC
EFF OUT
()
MAX17409
1-Phase Quick-PWM GPU Controller
28 ______________________________________________________________________________________
In applications that require DC droop, R
DROOP(AC)
is
the same as the DC droop setting (R
DROOP(AC)
=
R
DROOP(DC)
). In applications that do not require DC droop, this AC signal is generated by capacitively cou­pling the inductor ripple current signal to the FB pin. In this case, R
DROOP(AC)
= R
SENSE
, where R
SENSE
is the
effective sense resistance seen at the CSP-CSN pins.
In Figure 1, C3 couples the inductor ripple current signal to the FB pin. C3 can be connected to the CSN pin or the CSP pin. Connecting to the CSN pin only couples the out­put capacitor ESR to the FB pin. Connecting to the CSP pin adds the R
SENSE
component to the effective resis­tance in addition to the output capacitor ESR. This is use­ful for applications using all ceramic output capacitors.
Keep the C3 x RFBtime constant between 3x and 5x of the switching period. Practical values for C3 range from
0.1µF to 1µF. Calculate RFBafter selecting C3. Keeping RFBbelow 100minimizes any residual DC droop.
In the standard application circuit (Figure 1), the effec­tive resistance for stability is the sum of the ~ 2mDCR and the 6mESR of the 470µF output capacitor. The ESR zero frequency is 42kHz, well within the require­ment of fSW/π.
Ceramic capacitors have a high-ESR zero frequency, but applications with significant voltage positioning can take advantage of their size and low ESR. Do not put high-value ceramic capacitors directly across the out­put without verifying that the circuit contains enough voltage positioning and series PCB resistance to ensure stability. When only using ceramic output capacitors, output overshoot (V
SOAR
) typically deter­mines the minimum output capacitance requirement. Their relatively low capacitance value can cause output overshoot when stepping from full-load to no-load con­ditions, unless a small inductor value is used (high switching frequency) to minimize the energy transferred from inductor to capacitor during load-step recovery.
Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output-voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. Double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits.
The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage ripple envelope for over­shoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (I
RMS
) imposed by the switching currents.
The I
RMS
requirements can be determined by the fol-
lowing equation:
The worst-case RMS current requirement occurs when operating with VIN= 2V
OUT
. At this point, the above
equation simplifies to I
RMS
= 0.5 x I
LOAD
.
For most applications, nontantalum chemistries (ceram­ic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. If the Quick-PWM controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either con­figuration, choose an input capacitor that exhibits less than +10°C temperature rise at the RMS input current for optimal circuit longevity.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Low­current applications usually require less attention.
The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both V
IN(MIN)
and V
IN(MAX)
. Calculate both of these sums. Ideally, the
losses at V
IN(MIN)
should be roughly equal to losses at
V
IN(MAX)
, with lower losses in between. If the losses at
V
IN(MIN)
are significantly higher than the losses at
V
IN(MAX)
, consider increasing the size of NH(reducing
R
DS(ON)
but with higher C
GATE
). Conversely, if the losses
at V
IN(MAX)
are significantly higher than the losses at
V
IN(MIN)
, consider reducing the size of NH(increasing
R
DS(ON)
to lower C
GATE
). If VINdoes not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses.
Choose a low-side MOSFET that has the lowest possible on-resistance (R
DS(ON)
), comes in a moderate-sized package (i.e., one or two 8-pin SOs, DPAK, or D2PAK), and is reasonably priced. Make sure that the DL gate
I
RMS
=
⎜ ⎝
I
LOAD
V
IN
VVV
()
OUT IN OUT
⎟ ⎠
-
MAX17409
1-Phase Quick-PWM GPU Controller
______________________________________________________________________________________ 29
driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate­to-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems could occur (see the
MOSFET Gate Drivers
section).
MOSFET Power Dissipation
Worst-case conduction losses occur in the high-side MOSFET (NH) is a function of the duty factor, with the worst-case power dissipation occurring at the minimum input voltage:
Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the R
DS(ON)
required to stay within package power dissipation often limits how small the MOSFET can be. Again, the optimum occurs when the switching losses equal the conduction (R
DS(ON)
) losses. High­side switching losses do not usually become an issue until the input is greater than approximately 15V.
Calculating the switching losses in a high-side MOSFET (NH) is difficult since it must allow for difficult quantify­ing factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss cal­culation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably includ­ing verification using a thermocouple mounted on NH:
where C
OSS
is the NHMOSFET’s output capacitance,
Q
G(SW)
is the charge needed to turn on the NHMOSFET,
and I
GATE
is the peak gate-drive source/sink current
(2.2A typ).
Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the C x V
IN
2
x fSWswitching-loss equation. If the high-side
MOSFET chosen for adequate R
DS(ON)
at low battery voltages becomes extraordinarily hot when biased from V
IN(MAX)
, consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage:
The worst case for MOSFET power dissipation occurs under heavy overloads that are greater than I
LOAD(MAX)
, but are not quite high enough to exceed the current limit and cause the fault latch to trip. To pro­tect against this possibility, the circuit can be overde­signed to tolerate:
where I
VALLEY(MAX)
is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good size heatsink to handle the overload power dissipation.
Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. Select a diode that can handle the load current during the dead times. This diode is optional and can be removed if effi­ciency is not critical.
Boost Capacitors
The boost capacitors (C
BST
) must be selected large enough to handle the gate charging requirements of the high-side MOSFETs. However, high-current appli­cations driving large high-side MOSFETS require boost capacitors larger than 0.1µF. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the high­side MOSFETs’ gates:
where N is the number of high-side MOSFETs used for one regulator, and Q
GATE
is the gate charge specified in the MOSFET’s data sheet. For example, assume (2) IRF7811W n-channel MOSFETs are used on the high side. According to the manufacturer’s data sheet, a sin­gle IRF7811W has a maximum gate charge of 24nC (VGS= 5V). Using the above equation, the required boost capacitance would be:
Selecting the closest standard value, this example requires a 0.22µF ceramic capacitor.
PD (NH Res istive) =
⎛ ⎜
V
OUT
V
IN
⎞ ⎟
2
IR
LOAD DS
(OON)
Q
PD (NH Switching) = V I f
IN LOAD SW
CV
OSS IN
+
⎛ ⎜
⎝⎝
22
f
SW
2
GSW
()
I
GATE
⎞ ⎟
PD (NL R esist iv e) = 1 -
⎢ ⎢
V
OUT
V
IN MAX()
⎤⎤
IR
()
LOAD DS ON2()
II
=+
LOAD VALLEY MAX
=+
⎛ ⎜
I
VALLEY MAX
()
()
I
INDUCTOR
ILIR
LOAD MAX
⎜ ⎝
⎞ ⎟
2
()
2
⎞ ⎟
C
BST
C
=
BST
NQ
×
200
GATE
mV
=
nC
×=224
mV
200
µF
024.
MAX17409
1-Phase Quick-PWM GPU Controller
30 ______________________________________________________________________________________
Applications Information
Positive Offset
Some applications require a positive offset to shift the output voltage to a different level. This might be neces­sary to obtain a voltage not supported by the VID code, or to allow a shift in the VID code mapping.
A positive offset is generated by raising the voltage at the GNDS/OFSP pin using a resistor-divider from REF. Refer to R14 and R20 in Figure 1. The voltage at the GNDS/OFSP pin relative to the analog ground of the IC sets the offset voltage that is added to the programmed VID voltage:
and:
V
TARGET
= V
DAC
+ V
OFFSET
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 8). If possible, mount all the power components on the top side of the board with their ground terminals flush against one another. Follow the MAX17409 Evaluation Kit layout and use the following guidelines for good PCB layout:
Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitter­free operation.
Connect all analog grounds to a separate solid cop­per plane, which connects to the GND pin of the Quick-PWM controller. This includes the V
CC
bypass capacitor, REF, GNDS bypass capacitors, and compensation (CCV) components.
Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PCBs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a mea­surable efficiency penalty.
Keep the high-current, gate-driver traces (DL, DH, LX, and BST) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shoot-through currents.
CSP and CSN connections for current limiting and voltage positioning must be made using Kelvin-sense connections to guarantee the current-sense accuracy.
When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the low­side MOSFET or between the inductor and the out­put filter capacitor.
Route high-speed switching nodes away from sen­sitive analog areas (CCV, FB, CSP, CSN, etc.).
Layout Procedures
1) Place the power components first, with ground ter­minals adjacent (low-side MOSFET source, CIN, C
OUT
, and D1 anode). If possible, make all these connections on the top layer with wide, copper­filled areas.
2) Mount the controller IC adjacent to the low-side MOSFET. The DL gate traces must be short and wide (50mils to 100mils wide if the MOSFET is 1in from the controller IC).
3) Group the gate-drive components (BST capacitors, VDDbypass capacitor) together near the controller IC.
4) Make the DC-DC controller ground connections as shown in Figure 1. This diagram can be viewed as having four separate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the PGND pin and VDDbypass capacitor go; the master’s analog ground plane where sensitive analog components go, the master’s GND pin and VCCbypass capaci­tor go; and the slave’s analog ground plane where the slave’s GND pin and VCCbypass capacitor go. The master’s GND plane must meet the PGND plane only at a single point directly beneath the IC. Similarly, the slave’s GND plane must meet the PGND plane only at a single point directly beneath the IC. The respective master and slave ground planes should connect to the high-power output ground with a short metal trace from PGND to the source of the low-side MOSFET (the middle of the star ground). This point must also be very close to the output capacitor ground terminal.
5) Connect the output power planes (V
CORE
and sys­tem ground planes) directly to the output filter capacitor positive and negative terminals with multi­ple vias. Place the entire DC-DC converter circuit as close to the CPU as is practical.
14
R
⎛ ⎜
RR
20 14
VV
==
GNDS OFFSET REF
+
V
⎟ ⎠
MAX17409
1-Phase Quick-PWM GPU Controller
______________________________________________________________________________________ 31
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages
.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
28 TQFN T2844-1
21-0139
Chip Information
PROCESS: BiCMOS
Figure 8. PCB Layout Example
KELVIN SENSE VIAS UNDER
THE INDUCTOR
(SEE MAX17409 EVALUATION KIT)
POWER STAGE LAYOUT (TOP SIDE OF PCB)
OUTPUT
CSP CSN
C
EQ
KELVIN SENSE VIAS TO
INDUCTOR PAD
INDUCTOR DCR SENSING
R
NTC
R2 R1
INDUCTOR L
INPUT
SMPS
C
C
OUT
OUT
POWER GROUND
C
IN1
MAX17409
1-Phase Quick-PWM GPU Controller
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
0 4/09 Initial release
1 7/09 Remove all NVIDIA references; change CPU to GPU 1–32
REVISION
DATE
DESCRIPTION PAGES CHANGED
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