The MAX17030/MAX17036 are 3/2-phase interleaved
Quick-PWM™ step-down VID power-supply controllers
for IMVP-6.5 notebook CPUs. Two integrated drivers and
the option to drive a third phase using an external driver
such as the MAX8791 allow for a flexible 3/2-phase configuration depending on the CPU being supported.
True out-of-phase operation reduces input ripple-current
requirements and output-voltage ripple while easing
component selection and layout difficulties. The QuickPWM control provides instantaneous response to fast
load-current steps. Active voltage positioning reduces
power dissipation and bulk output capacitance requirements and allows ideal positioning compensation for tantalum, polymer, or ceramic bulk output capacitors.
The MAX17030/MAX17036 are intended for bucking
down the battery directly to create the core voltage.
The single-stage conversion method allows this device
to directly step down high-voltage batteries for the
highest possible efficiency.
A slew-rate controller allows controlled transitions
between VID codes. A thermistor-based temperature
sensor provides programmable thermal protection. An
output current monitor provides an analog current output proportional to the sum of the inductor currents,
which in steady state is the same as the current consumed by the CPU.
3 to 4 Li+ Cells Battery to CPU Core Supply
Converters
Notebooks/Desktops/Servers
Features
o Triple/Dual-Phase Quick-PWM Controllers
o 2 Internal Drivers + 1 External Driver
o ±0.5% V
OUT
Accuracy Over Line, Load, and
Temperature
o 7-Bit IMVP-6.5 DAC
o Dynamic Phase Selection Optimizes Active/Sleep
Efficiency
o Transient Phase Overlap Reduces Output
Capacitance
o Transient Suppression Feature (MAX17036 Only)
o Integrated Boost Switches
o Active Voltage Positioning with Adjustable Gain
o Accurate Lossless Current Balance and
Current Limit
o Remote Output and Ground Sense
o Adjustable Output Slew-Rate Control
o Power-Good (IMVPOK), Clock Enable (CLKEN),
and Thermal-Fault (VRHOT) Outputs
o IMVP-6.5 Power Sequencing and Timing
Compliant
o Output Current Monitor (IMON)
o Drives Large Synchronous Rectifier FETs
o 7V to 26V Battery Input Range
o Adjustable Switching Frequency (600kHz max)
o Undervoltage, Overvoltage, and Thermal-Fault
= 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; TA= 0°C to +85°C, unless otherwise noted.
Typical values are at T
A
= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC, VDDto GND .....................................................-0.3V to +6V
D0–D6, PGD_IN, PSI, DPRSLPVR to GND ...............-0.3V to +6V
CSP_, CSN_, THRM, ILIM to GND............................-0.3V to +6V
PWRGD, CLKEN, VR_HOT to GND..........................-0.3V to +6V
FB, FBAC, IMON, TIME to GND .................-0.3V to (V
CC
+ 0.3V)
SHDN to GND (Note 2)...........................................-0.3V to +30V
TON to GND ...........................................................-0.3V to +30V
GNDS to GND .......................................................-0.3V to +0.3V
DL1, DL2, PWM3, DRSKP to GND .............-0.3V to (V
DD
+ 0.3V)
BST1, BST2 to GND ...............................................-0.3V to +36V
BST1, BST2 to V
DD
.................................................-0.3V to +30V
LX1 to BST1..............................................................-6V to +0.3V
LX2 to BST2..............................................................-6V to +0.3V
DH1 to LX1 ..............................................-0.3V to (V
BST1
+ 0.3V)
DH2 to LX2 ..............................................-0.3V to (V
BST2
+ 0.3V)
Continuous Power Dissipation (40-pin, 5mm x 5mm TQFN)
Up to +70°C ..............................................................1778mW
Storage Temperature Range .............................-65°C to +165°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1: Absolute Maximum Ratings valid using 20MHz bandwidth limit.
Note 2: SHDN might be forced to 12V for the purpose of debugging prototype breadboards using the no-fault test mode. Internal
BST switches are disabled as well. Use external BST diodes when SHDN is forced to 12V.
PWM CONTROLLER
Input Voltage Range
FB Output Voltage Accuracy V
Boot Voltage V
Line Regulation Error VCC = 4.5V to 5.5V, VIN = 4.5V to 26V 0.1 %
FB Input Bias Current TA = +25°C -0.1 +0.1 µA
GNDS Input Range -200 +200 mV
GNDS Gain A
GNDS Input Bia s Current I
TIME Regulation Voltage V
TIME Slew-Rate Accurac y
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
FB
BOOT
GNDS
TA = +25°C -0.5 +0.5 µA
GNDS
R
TIME
VCC, V
V
Measured at FB
with respect to
GNDS;
includes loadregulation error
(Note 3)
1.094 1.100 1.106 V
V
R
R
178k (5mV/µs nominal)
Soft-start and soft-shutdown:
R
178k (1.25mV/µs nominal)
= 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; TA= 0°C to +85°C, unless otherwise noted.
Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
On-Time Accuracyt
Minimum Off-Time t
TON Shutdown Input Current I
BIAS CURRENTS
Quie sc ent Supply Current (VCC) I
Quie sc ent Supply Current (VDD) I
Shutdown Supply C urrent (VCC) I
Shutdown Supply C urrent (VDD) I
FAULT PROTECTION
Output Overvoltage-Protection
Threshold
Output OvervoltagePropagation Dela y
Output UndervoltageProtection Threshold
Output UndervoltagePropagation Dela y
CLKEN Startup Delay and
Boot Time Period
ON
OFF(MIN)
TON,SDN
CC
DD
CC, SDN
DD, SDN
V
OVP
t
OVP
V
UVP
t
UVP
t
BOOT
VIN = 10V,
= 1.0V,
V
FB
measured at
DH1, DH2,
and PWM3
(Note 4)
Measured at DH1, DH2, and PWM3 (Note 4) 300 375 ns
SHDN = GND, VIN = 26V, VCC = VDD = 0
or 5V, T
A
Measured at VCC, V
forced above the regulation point
Mea sured at VDD, V
above the regulation point, T
Mea sured at VCC, SHDN = GND, TA = +25°C 0.01 1 µA
Mea sured at VDD, SHDN = GND, TA = +25°C 0.01 1 µA
Skip mode after output reache s the
regulation voltage or PWM mode;
measured at FB with respect to the voltage
target set by the VID code (see Table 4)
Soft-start, soft-shutdown, skip mode, and
output have not reached the regulation
voltage; measured at FB
Min imum OVP threshold; measured at FB 0.8
FB forced 25mV above trip thresho ld 10 µs
Measured at FB with respect to the voltage
target set by the VID code (see Table 4)
FB forced 25mV below trip threshold 10 µs
Measured from the time when FB reaches
the boot target vo ltage (Note 3)
= 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; TA= -40oC to +105°C, unless otherwise noted.)
(Note 5)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
On-Time Accuracy t
Minimum Off-Time t
BIAS CURRENTS
Quie sc ent Supply Current (VCC) I
FAULT PROTECTION
Output Overvoltage-Protection
Threshold
Output Undervoltage-Protection
Threshold
CLKEN Startup Delay and Boot
Time Period
PWRGD Startup Dela y
CLKEN and PWRGD Threshold
CLKEN, PWRGD Output
Low Voltage
VCC Undervoltage-Lockout
Threshold
THERMAL PROTECTION
VRHOT Trip Threshold
VRHOT Output On-Resistance R
ON
OFF(MIN)
CC
V
OVP
V
UVP
t
BOOT
V
UVLO(VCC)
ON(VRHOT)
VIN = 10V,
= 1.0V,
V
FB
measured at
DH1, DH2,
and PWM3
(Note 4)
Measured at DH1, DH2, and PWM3 (Note 4) 400 ns
Measured at VCC, DPRSLPVR = 5V, FB
forced above the regulation point
Skip mode after output reache s the
regulation voltage or PWM mode;
measured at FB with respect to the voltage
target set by the VID code (see Table 4)
Soft-start, soft-shutdown, skip mode, and
output have not reached the regulation
voltage; measured at FB
Measured at FB with respect to the voltage
target set by the VID code (see Table 4)
Measured from the time when FB reaches
the boot target vo ltage (Note 3)
Measured at startup from the time when
CLKEN goes low
Mea sured at FB
with respect to the
vo ltage target set
by the VID code
(see Table 4),
20mV hysteresi s
(typ)
Low state, I
Rising edge, 65mV typical hy steresi s,
controller disabled below this level
Measured at THRM with respect to V
falling edge, typical hysteresis = 75mV
VALLEY CURRENT LIMIT, DROOP, CURRENT BALANCE, AND CURRENT MONITOR
V
TIME
- V
ILIM
= 100mV 7 13
V
TIME
- V
ILIM
= 500mV 45 55
Current-Limit Threshold Voltage
(Positive)
V
LIMIT
V
CSP_
- V
CSN_
ILIM = V
CC
20 25
mV
Current-Limit Threshold Voltage
(Negative) Accuracy
V
LIMIT(NEG) VCSP_
- V
CSN_
, nominally -125% of V
LIMIT
-4 +4 mV
CSP_, CSN_ Common-Mode
Input Range
0 2 V
Phase s 2, 3 Di sable Thresho ld Measured at CSP2, CSP3 3
V
CC
-
0.4
V
Droop Amplifier Offset
(1/N) x (V
CSP_
- V
CSN_
) at I
FBAC
= 0;
indicates summation over all power-up
enabled phases from 1 to N, N = 3
-1 +1
mV/
phase
Droop Amplifier
Transconductance
G
m(FBAC)
I
FBAC
/[(V
CSP_
- V
CSN_
)]; indicates
summation over all power-up enabled
phase s from 1 to N, N = 3,
V
FBAC
= V
CSN_
= 0.45V to 1.5V
390 407 μS
Current-Monitor Offset
(1/N) x (V
CSP_
- V
CSN_
) at I
FBAC
= 0;
indicates summation over all power-up
enabled phases from 1 to N, N = 3
-1.5 +1.5
mV/
phase
Current-Monitor
Transconductance
G
m(IMON)
I
IMON
/[(V
CSP_
- V
CSN_
)]; indicates
summation over all power-up enabled phase s
from 1 to N, N = 3, V
CSN_
= 0.45V to 1.5V
1.536 1.664 mS
GATE DRIVERS
High state (pullup) 2.5
DH_ Gate-Driver On-Resistance R
ON(DH)
BST_ – LX_
forced to 5V
Low state (pulldown) 2
High state (pullup) 2
DL_ Gate-Driver On-Resistance R
ON(DL)
Low state (pulldown) 0.7
Internal BST_ Switch
On-Resistance
R
ON(BST) IBST-
= 10mA 20
PWM3, DRSKP OUTPUTS
PWM3, DRSKP Output
High Voltages
I
SOURCE
= 3mA
V
DD
-
0.4V
V
PWM3, DRSKP Output
Low Voltages
I
SINK
= 3mA 0.4 V
LOGIC AND I/O
Logic-Input High Voltage V
IH
SHDN, PGD_IN 2.3 V
Logic-Input Low Voltage V
IL
SHDN, PGD_IN 1.0 V
Low-Voltage Logic-Input
High Voltage
V
IHLV
PSI, D0–D6, DPRSLPVR 0.67 V
Low-Voltage Logic-Input
Low Voltage
V
ILLV
PSI, D0–D6, DPRSLPVR 0.33 V
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN= 10V, VCC= VDD= V
SHDN
= V
PGD_IN
= V
PSI
= V
ILIM
= 5V, V
DPRSLPVR
= V
GNDS
= 0, V
CSP_
= V
CSN_
=
1.0000V, FB = FBAC, R
FBAC
= 3.57kΩ from FBAC to CSN_, [D6–D0] = [0101000]; TA= -40oC to +105°C, unless otherwise noted.)
(Note 5)
Note 3: The equation for the target voltage V
TARGET
is:
V
TARGET
= The slew-rate-controlled version of V
DAC
, where V
DAC
= 0 for shutdown
V
DAC
= V
BOOT
during IMVP-6.5 startup
V
DAC
= V
VID
otherwise (the V
VID
voltages for all possible VID codes are given in Table 4).
In pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load.
Note 4: On-time and minimum off-time specifications are measured from 50% to 50% at the DH_ pin, with LX_ forced to 0V, BST_
forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in-circuit times
might be different due to MOSFET switching speeds.
Note 5: Specifications to -40°C and +105°C are guaranteed by design, not production tested.
Negative Input of the Output Current Sense of Phase 3. This pin should be connected to the
1CSN3
2CSP3
3 THRM
4 IMON
5 ILIM
6 TIME
7 VCC Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypa ss to GND with 1µF minimum.
8 FB
negative side of the output current-sensing resistor or the filtering capacitor if the DC resistance of
the output inductor is utilized for current sensing.
Positive Input of the Output Current Sense of Phase 3. This pin should be connected to the positive
side of the output current-sensing resistor or the filtering capacitor if the DC resistance of the
output inductor is utilized for current sensing.
To disable phase 3, connect CSP3 to VCC and CSN3 to GND.
Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between V
and GND) to THRM. Select the component s such that the voltage at THRM fall s below 1.5V (30% of
V
) at the desired high temperature.
CC
Current Monitor Output Pin. The output current at this pin is:
where G
An external resistor R
where R
Choose R
IMON is high impedance when the MAX17030/MAX17036 are in shutdown.
Current-Limit Adju st Input. The va lley positive current-lim it threshold voltages at V(CSP_,CSN_) are
precise ly 1/10 the different ial voltage V(TIME,ILIM) over a 0.1V to 0.5V range of V(TIME,ILIM). The
valley negative current-limit thresholds are typically -125% of the corresponding valley positive
current-limit thresholds. Connect ILIM to V
22.5mV typ.
Slew-Rate Adjustment Pin. The total resistance R
where R
Thi s “normal” slew rate applies to transitions into and out of the low-power pulse-skipping modes
and to the transition from boot mode to VID. The slew rate for startup and for entering shutdown is
always 1/4 of normal. If the VID DAC inputs are clocked, the slew rate for all other VID transitions
is set by the rate at which they are clocked, up to a maximum slew rate equal to the normal slew
rate defined above.
Feedback Voltage Input. The voltage at the FB pin i s compared with the sle w-rate-controlled target
voltage by the error comparator (fast regulation loop), as well as by the internal voltage integrator
(slow, accurate regulation loop). Having sufficient ripple signal at FB that is in phase with the sum
of the inductor currents is e ss ential for cycle-by-cycle stability.
The external connection s and compensation at FB depend on the desired DC and transient (AC)
droop values. If DC droop = AC droop, then short FB to FBAC. To d isable DC droop, connect FB to the
remote-sensed output voltage through a resistor R and feed forward the FBAC ripple to FB through
capacitor C, where the R x C time constant should be at least 3x the switching period per phase.
M(IMON)
SENSE
TIME
= 1.6mS typical and denotes summation over al l enabled phases.
IMON
is the value of the effective current-sense res istance.
such that V
IMON
is between 35.7 k and 178k.
IMON
I
= G
IMON
between IMON and GNDS sets the current-monitor output voltage:
= I
V
IMON
does not exceed 900mV at the maximum expected load current I
Slew rate = (12.5mV/µs) x (71.5k/R
LOAD
x R
x V(CSP_,CSN_)
M(IMON)
x G
SENSE
to get the default current-lim it threshold setting of
CC
from TIME to GND sets the internal slew rate:
TIME
M(IMON)
x R
TIME
IMON
)
CC
MAX
.
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