The MAX17031 is a dual Quick-PWM™ step-down
power-supply (SMPS) controller with synchronous rectification, intended for main 5V/3.3V power generation in
battery-powered systems. Low-side MOSFET sensing
provides a simple low-cost, highly efficient current
sense for valley current-limit protection. Combined with
the output overvoltage and undervoltage protection features, this current limit ensures robust output supplies.
The 5V/3.3V SMPS outputs can save power by operating in pulse-skipping mode or in ultrasonic mode to
avoid audible noise. Ultrasonic mode forces the controller to maintain switching frequencies greater than
20kHz at light loads. The SKIP input also has an accurate logic threshold, allowing it to be used as a secondary feedback input to refresh an external charge
pump or secondary winding without overcharging the
output voltages.
An internal 100mA linear regulator generates the 5V
bias needed for power-up or other low-power “alwayson” suspend supplies. An internal bypass circuitry
allows automatic bypassing of the linear regulator when
the 5V SMPS is active.
The device includes independent shutdown controls
with well-defined logic thresholds to simplify power-up
and power-down sequencing. To prevent current
surges at startup, the internal voltage target is slowly
ramped up from zero to the final target over a 1ms period. To prevent the output from ringing below ground in
shutdown, the internal voltage target is ramped down
from its previous value to zero over a 1ms period. A
combined power-good (PGOOD) output simplifies the
interface with external controllers. The MAX17031 is
available in a 24-pin thin QFN (4mm x 4mm) package.
(Circuit of Figure 2, no load on LDO5, RTC, OUT1, OUT2, and REF, VIN= 12V, VDD= VCC= V
SKIP
= 5V, ONLDO = RTC, ON1 = ON2
= V
CC
, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN to GND ...............................................................-0.3V to +28V
V
DD
, VCCto GND .....................................................-0.3V to +6V
RTC, LDO5, ONLDO to GND ...................................-0.3V to +6V
OUT2 to GND ...........................................................-0.3V to +6V
ON1, ON2, PGOOD to GND.....................................-0.3V to +6V
OUT1 to GND..........................................-0.3V to (V
LDO5
+ 0.3V)
SKIP to GND...............................................-0.3V to (V
CC
+ 0.3V)
REF, ILIM1, ILIM2 to GND..........................-0.3V to (V
CC
+ 0.3V)
DL_ to GND ................................................-0.3V to (V
DD
+ 0.3V)
BST_ to GND ..........................................................-0.3V to +36V
BST_ to V
DD
............................................................-0.3V to +30V
DH1 to LX1 ..............................................-0.3V to (V
BST1
+ 0.3V)
BST1 to LX1..............................................................-0.3V to +6V
DH2 to LX2 ..............................................-0.3V to (V
BST2
+ 0.3V)
BST2 to LX2..............................................................-0.3V to +6V
LDO5, RTC, REF Short Circuit to GND.......................Momentary
RTC Current Continuous.....................................................+5mA
LDO5 Current (Internal Regulator) Continuous ..............+100mA
LDO5 Current (Switched Over) Continuous ...................+200mA
(Circuit of Figure 2, no load on LDO5, RTC, OUT1, OUT2, and REF, VIN= 12V, VDD= VCC= V
SKIP
= 5V, ONLDO = RTC, ON1 = ON2
= V
CC
, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
Note 1: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = GND, V
BST
= 5V, and
a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times might be different
due to MOSFET switching speeds.
Note 2: Specifications to T
A
= -40°C are guaranteed by design and not production tested.
Note 3: Specification increased by 1Ω to account for test measurement error.
Note 4: Production tested for functionality only.
A. LOAD CURRENT, 2A/div
B. 5V SMPS OUTPUT,
100mV/div
C. INDUCTOR CURRENT,
2A/div
A. LOAD CURRENT, 2A/div
B. 3.3V SMPS OUTPUT,
100mV/div
40µs/div
C. INDUCTOR CURRENT,
2A/div
PINNAMEFUNCTION
2V Reference Voltage Output. Bypas s REF to analog ground with a 0.22µF or greater ceramic
1 REF
capacitor. The reference can source up to 50µA for external loads. Loading REF degrades output
voltage accuracy according to the REF load regulation error (see Typical Operating Characteristics).
The reference shuts down when ON1, ON2, and ONLDO are all pulled low.
Enable Input for LDO5. Drive ONLDO high (pull up to RTC) to enable the linear regulator (LDO5)
2 ONLDO
3 V
CC
4 RTC
output. Drive ONLDO low to shut down the linear regulator output. When ONLDO i s high, LDO5
must supply V
Analog Supply Voltage Input. Connect V
and VDD.
CC
to the system supply voltage with a series 50
CC
resistor, and bypass to analog ground using a 1µF or greater ceramic capacitor.
3.3V Alwa ys-On Linear Regulator Output for RTC Power. Bypass RTC with a 1µF or greater ceramic
capacitor to analog ground. RTC can source up to 5mA for external loads.
Power Input Supply. Bypas s IN with a 0.1µF or greater ceramic capacitor to GND. IN powers the
5 IN
linear regulators (RTC and LDO5) and sense s the input vo ltage for the Quick-PWM on-time oneshot timer. The DH on-time is inversel y proportiona l to input vo ltage.
6 LDO5
5V Linear Regulator Output. Bypass LDO5 with a 4.7µF or greater ceramic capacitor to GND. LDO5
can source 100mA for external load support. LDO5 is powered from IN.
Output-Voltage Sense Input for SMPS1 and Linear Regulator Bypass Input. OUT1 is an input to the
Quick-PWM on-time one-shot timer. OUT1 also serves as the feedback input for the SMPS1.
7 OUT1
When OUT1 exceeds 93.5% of the LDO5 voltage, the controller bypas ses the LDO5 output to
OUT1. The bypass sw itch is disab led if the OUT1 voltage drops by 8.5% from LDO5 nomina l
regulation threshold.
Valley Current-Limit Adjustment for SMPS1. The GND - LX1 current-limit threshold is 1/10 the
8 ILIM1
voltage present on ILIM1 over a 0.2V to 2V range. An internal 5µA current source allow s thi s
voltage to be set w ith a single resi stor between ILIM1 and analog ground.
Open-Drain Power-Good Output for SMPS1 and SMPS2. PGOOD is low when either output voltage is
9 PGOOD
10 ON1 Enable Input for SMPS1. Drive ON1 high to enable SMPS1. Drive ON1 low to shut down SMPS1.
11 DH1 High-Side Gate-Driver Output for SMPS1. DH1 swings from LX1 to BST1.
12 LX1
13 BST1
14 DL1 Low-Side Gate-Driver Output for SMPS1. DL1 sw ings from power GND to V
15 V
16 GND Analog and Power Ground
17 DL2 Low-Side Gate-Driver Output for SMPS2. DL2 sw ings from power GND to V
18 BST2
19 LX2
20 DH2 High-Side Gate-Driver Output for SMPS2. DH2 swings from LX2 to BST2.
21 ON2 Enable Input for SMPS2. Drive ON2 high to enable SMPS2. Drive ON2 low to shut down SMPS2.
22 SKIP
23 OUT2
24 ILIM2
— EP Exposed Pad. Connect backside exposed pad to analog GND and power GND.
DD
more than 15% (typ) below the nominal regulation threshold, during soft-start, in shutdown, when either SMPS is disabled, and after the fault latch ha s been tripped. After the soft-start circuit ha s
terminated, PGOOD becomes high impedance if both output s are in regulation.
Inductor Connection for SMPS1. Connect LX1 to the switched side of the inductor. LX1 is the lower
suppl y rail for the DH1 high-side gate driver.
Boost Flying Capacitor Connection for SMPS1. Connect to an external capacitor as shown in
Figure 1. An optional resistor in series with BST1 allows the DH1 turn-on current to be adjusted.
DD.
Supply Voltage Input for the DL_ Gate Drivers. V
BST diode sw itch. Connect to a 5V supply, and bypass V
ceramic capacitor.
Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor as shown in
Figure 1. An optional resistor in series with BST2 allows the DH2 turn-on current to be adjusted.
Inductor Connection for SMPS2. Connect LX2 to the switched side of the inductor. LX2 is the lower
suppl y rail for the DH2 high-side gate driver.
Pulse-Skipping Control Input. This three-leve l input determines the operating mode for the
switching regulators:
Output-Voltage Sense Input for SMPS2. OUT2 is an input to the Quick-PWM on-time one-shot timer.
OUT2 also serves as the feedback input for the preset 3.3V.
Valley Current-Limit Adjustment for SMPS2. The GND - LX2 current-limit threshold is 1/10 the
voltage present on ILIM2 over a 0.2V to 2V range. An internal 5µA current source allow s thi s
voltage to be set w ith a single resi stor between ILIM2 and analog ground.
is internally connected to the drain of the HVPV
DD
to power GND with a 1µF or greater
DD
DD.
MAX17031
Dual Quick-PWM Step-Down Controller with LowPower LDO and RTC Regulator for MAIN Supplies
Figure 1. Standard Application Circuit—Main Supply
)*
INPUT (V
IN
7V TO 24V
C
IN_PIN
0.1µF
C
IN
4x 10µF
25V
5V OUTPUT
C
OUT1
12V TO 15V
CHARGE PUMP
C8
0.1µF
5V LDO OUTPUT
POWER GROUND
ANALOG GROUND
C6
0.1µF
D1
1MΩ
R4
L1
200kΩ
1.0µF
47Ω
C2
N
H1
C
BST1
0.1µF
N
L1
DH1
BST1
LX1
DL1
IN
DH2
BST2
LX2
DL2D2
C
BST2
0.1µF
N
H2
L2
N
L2
C
OUT2
3.3V OUTPUT
MAX17031
C5
C7
C1
ILIM1
OUT1
SKIP
V
DD
LDO5
V
CC
ILIM1
D
X1
10nF
D
X2
10nF
R5
R1
4.7µF
R
PAD
OUT2
PGOOD
RTC
REF
GND
ON1
ON2
ONLDO
ILIM2
C4
0.1µF
R
C3
1µF
ILIM2
R6
100kΩ
COMBINED POWER-GOOD
RTC SUPPLY
ON OFF
*NOTE: LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE. IF OPERATING NEAR DROPOUT, COMPONENT SELECTION MUST BE
CAREFULLY DONE TO ENSURE PROPER OPERATION.
Detailed Description
The MAX17031 step-down controller is ideal for highvoltage, low-power supplies for notebook computers.
Maxim’s Quick-PWM pulse-width modulator in the
MAX17031 is specifically designed for handling fast
load steps while maintaining a relatively constant operating frequency and inductor operating point over a
wide range of input voltages. The Quick-PWM architecture circumvents the poor load-transient timing problems of fixed-frequency current-mode PWMs, while also
avoiding the problems caused by widely varying
switching frequencies in conventional constant-on-time
and constant-off-time PWM schemes. Figure 2 is the
functional diagram overview and Figure 3 is the QuickPWM core functional diagram
Table 1. Component Selection for
Standard Applications
Table 2. Component Suppliers
400kHz/300kH z
COMPONENT
Input Voltage VIN = 7V to 24V
Input Capacitor
)
(C
IN
SMPS 1
Output Capac itor
(C
)
OUT1
Inductor
(L1)
High-Side MOSFET
)
(N
H1
Low-Side MOSFET
)
(N
L1
Current-Limit Res istor
)
(R
ILIM1
SMPS 2
Output Capac itor
(C
)
OUT2
Inductor
(L2)
High-Side MOSFET
(N
)
H2
Low-Side MOSFET
(N
)
L2
Current-Limit Res istor
(R
)
ILIM2
SMPS1: 5V AT 5A
SMPS2: 3.3V AT 8A
4X 10µF, 25V
Taiyo Yuden TMK432BJ106KM
2x 100µF, 6V, 35m
SANYO 6TPE100MAZB
4.3µH, 11.4m, 11A
Sumida CEP125U
Siliconix
Si4800BDY
23m/30m 30V
Siliconix
Si4812BDY
16.5m/20m 30V
71k
2x 150µF, 4V, 35m
SANYO 4TPE150MAZB
2.2µH, 5.4m, 14A
Sumida CEP125U
Siliconix
Si4684DY
9.2m/11.5m, 30V
Siliconix
Si4430BDY
4.8m/6.0m, 30V
71k
SUPPLIERWEBSITE
AVX Corp. www.avx.com
Central Semiconductor
Corp.
Fairch ild Semiconductor www.fairchildsem i.com
International Rect ifier www.irf.com
KEMET Corp. www.kemet.com
NEC/TOKIN America, Inc. www.nec-tokinamerica.com
Panason ic Corp. www.panasonic.coml
The MAX17031 includes several features for multipurpose notebook functionality, and is specifically
designed for 5V/3.3V main power-supply rails. The
MAX17031 includes a 100mA, 5V linear regulator
(LDO5) ideal for initial power-up of the notebook and
main supply. Additionally, the MAX17031 includes a
3.3V, 5mA RTC supply that remains always enabled,
which can be used to power the RTC supply and system pullups when the notebook shuts down. The
MAX17031 also includes a SKIP mode control input
with an accurate threshold that allows an unregulated
charge pump or secondary winding to be automatically
refreshed—ideal for generating the low-power 12V to
15V load switch supply.
3.3V RTC Power
The MAX17031 includes a low-current (5mA) linear regulator that remains active as long as the input supply
(IN) exceeds 2V (typ). The main purpose of this
“always-enabled” linear regulator is to power the RTC
when all other notebook regulators are disabled. The
RTC regulator sources at least 5mA for external loads.
Preset 5V, 100mA Linear Regulator
The MAX17031 includes a high-current (100mA) 5V linear regulator. This LDO5 is required to generate the 5V
bias supply necessary to power up the switching regulators. Once the 5V switching regulator (MAX17031 OUT1)
is enabled, LDO5 is bypassed to OUT1. The MAX17031
LDO5 sources at least 100mA of supply current.
Bypass Switch
The MAX17031 includes an LDO5 bypass switch that
allows the LDO5 to be bypassed to OUT1. When OUT1
exceeds 93.5% of the LDO5 output voltage for 500µs,
then the MAX17031 reduces the LDO5 regulation
threshold and turns on an internal p-channel MOSFET to
short OUT1 to LDO5. Instead of disabling the LDO5
when the MAX17031 enables the bypass switch, the
controller reduces the LDO5 regulation voltage, which
effectively places the linear regulator in a standby state
while switched over, allowing a fast recovery if the OUT1
drops by 8.5% from LDO5 nominal regulation threshold.
5V Bias Supply (VCC/VDD)
The MAX17031 requires an external 5V bias supply
(VDDand VCC) in addition to the battery. Typically, this
5V bias supply is generated by the internal 100mA
LDO5 or from the notebook’s 95%-efficient 5V main
supply. Keeping these bias supply inputs independent
improves the overall efficiency. When ONLDO is
enabled, VDDand VCCmust be supplied from LDO5.
The VDDbias supply input powers the internal gate drivers and the VCCbias supply input powers the analog
control blocks. The maximum current required is dominated by the switching losses of the drivers and can be
estimated as follows:
I
BIAS(MAX)
= I
CC(MAX)
+ fSWQG≈ 30mA to 60mA (typ)
Free-Running Constant-On-Time PWM
Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixedfrequency, constant on-time, current-mode regulator
with voltage feed-forward. This architecture relies on
the output filter capacitor’s ESR to act as a currentsense resistor, so the feedback ripple voltage provides
the PWM ramp signal. The control algorithm is simple:
the high-side switch on-time is determined solely by a
one-shot whose pulse width is inversely proportional to
input voltage and directly proportional to output voltage. Another one-shot sets a minimum off-time (400ns
typ). The on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the
valley current-limit threshold, and the minimum off-time
one-shot has timed out.
On-Time One-Shot
The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to battery and output voltage. The high-side
switch on-time is inversely proportional to the battery
voltage as sensed by IN, and proportional to the feedback voltage:
where K (switching period) is set 2.5µs for side 1 and
3.3µs for side 2. For continuous conduction operation,
the actual switching frequency can be estimated by:
where V
DROP1
is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PCB resistances; V
DROP2
is the
sum of the parasitic voltage drops in the charging path,
including the high-side switch, inductor, and PCB resistances; and tONis the on-time calculated by the
MAX17031.
Dual Quick-PWM Step-Down Controller with LowPower LDO and RTC Regulator for MAIN Supplies
= 1.8V) disables the zero-crossing comparator, which controls the
low-side switch on-time. This forces the low-side gatedrive waveform to constantly be the complement of the
high-side gate-drive waveform, so the inductor current
reverses at light loads while DH maintains a duty factor
of V
OUT/VIN
. The benefit of forced-PWM mode is to
keep the switching frequency fairly constant. However,
forced-PWM operation comes at a cost: the no-load 5V
bias current remains between 20mA to 60mA depending on the switching frequency and MOSFET selection.
The MAX17031 automatically uses forced-PWM operation
during shutdown regardless of the SKIP configuration.
Automatic Pulse-Skipping Mode (V
SKIP
> 2V)
In skip mode (V
SKIP
> 2V), an inherent automatic
switchover to PFM takes place at light loads. This
switchover is affected by a comparator that truncates
the low-side switch on-time at the inductor current’s
zero crossing. The zero-crossing comparator output is
set by the differential voltage across LX and GND.
DC output-accuracy specifications refer to the integrated
threshold of the error comparator. When the inductor is
in continuous conduction, the MAX17031 regulates the
valley of the output ripple and the internal integrator
removes the actual DC output-voltage error caused by
the output-ripple voltage and internal slope compensation. In discontinuous conduction (V
SKIP
> 2V and I
OUT
< I
LOAD(SKIP)
), the integrator cannot correct for the lowfrequency output ripple error, so the output voltage has
a DC regulation level higher than the error comparator
threshold by approximately 1.5% due to slope compensation and output ripple voltage.
Ultrasonic Mode (V
SKIP
= GND)
Shorting SKIP to ground activates a unique pulseskipping mode with a guaranteed minimum switching
frequency of 20kHz. This ultrasonic pulse-skipping
mode eliminates audio-frequency modulation that would
otherwise be present when a lightly loaded controller
automatically skips pulses. In ultrasonic mode, the controller automatically transitions to fixed-frequency PWM
operation when the load reaches the same critical conduction point (I
LOAD(SKIP)
) that occurs when normally
pulse skipping.
An ultrasonic pulse occurs (Figure 4) when the controller detects that no switching has occurred within the
last 37µs. Once triggered, the ultrasonic circuitry pulls
DL high, turning on the low-side MOSFET to induce a
negative inductor current. After the inductor current
reaches the negative ultrasonic current threshold, the
controller turns off the low-side MOSFET (DL pulled
low) and triggers a constant on-time (DH driven high).
When the on-time has expired, the controller reenables
the low-side MOSFET until the inductor current drops
below the zero-crossing threshold. Starting with a DL
pulse greatly reduces the peak output voltage when
compared to starting with a DH pulse.
The output voltage at the beginning of the ultrasonic
pulse determines the negative ultrasonic current threshold, corresponding to:
where RCSis the current-sense resistance seen across
LX to GND.
> 2V), the long
time between pulses (especially if the output is sinking
current) allows the external charge-pump voltage or
transformer secondary winding voltage to drop.
Connecting a resistor-divider between the secondary
output to SKIP to ground sets up a minimum refresh
threshold. When the SKIP voltage drops below its 2V
threshold, the MAX17031 enters forced-PWM mode.
This forces the controller to begin switching, allowing
the external unregulated charge pump (or transformer
secondary winding) to be refreshed.
Valley Current-Limit Protection
The current-limit circuit employs a unique “valley” current-sensing algorithm that senses the inductor current
through the low-side MOSFET—across LX to analog
GND. If the current through the low-side MOSFET
exceeds the valley current-limit threshold, the PWM
controller is not allowed to initiate a new cycle. The
actual peak current is greater than the valley currentlimit threshold by an amount equal to the inductor ripple
current. Therefore, the exact current-limit characteristic
and maximum load capability are a function of the
inductor value and battery voltage. When combined
with the undervoltage protection circuit, this currentlimit method is effective in almost every circumstance.
In forced-PWM mode, the MAX17031 also implements
a negative current limit to prevent excessive reverse
inductor currents when V
OUT
is sinking current. The
negative current-limit threshold is set to approximately
120% of the positive current limit.
POR, UVLO
When VCCrises above the power-on reset (POR) threshold, the MAX17031 clears the fault latches, forces the
low-side MOSFET to turn on (DL high), and resets the
soft-start circuit, preparing the controller for power-up.
However, the VCCundervoltage lockout (UVLO) circuitry
inhibits switching until VCCreaches 4.2V (typ). When
VCCrises above 4.2V and the controller has been
enabled (ON_ pulled high), the controller activates the
enabled PWM controllers and initializes soft-start.
When VCCdrops below the UVLO threshold (falling
edge), the controller stops switching, and DH and DL
are pulled low. When the 2V POR falling-edge threshold
is reached, the DL state no longer matters since there
is not enough voltage to force the switching MOSFETs
into a low on-resistance state, so the controller pulls DL
high, allowing a soft discharge of the output capacitors
(damped response). However, if the VCCrecovers
before reaching the falling POR threshold, DL remains
low until the error comparator has been properly powered up and triggers an on-time.
Soft-Start and Soft-Shutdown
The MAX17031 includes voltage soft-start and softshutdown—slowly ramping up and down the target voltage. During startup, the slew-rate control softly slews
the target voltage over a 1ms startup period. This long
startup period reduces the inrush current during startup.
When ON1 or ON2 is pulled low or the output undervoltage fault latch is set, the respective output automatically
enters soft-shutdown; the regulator enters PWM mode
and ramps down its output voltage over a 1ms period.
After the output voltage drops below 0.1V, the
MAX17031 pulls DL high, clamping the output and LX
switching node to ground, preventing leakage currents
from pulling up the output and minimizing the negative
output voltage undershoot during shutdown.
Output Voltage
DC output-accuracy specifications in the
Electrical
Characteristics
table refer to the error comparator’s
threshold. When the inductor continuously conducts, the
MAX17031 regulates the valley of the output ripple, so the
actual DC output voltage is lower than the slope-compensated trip level by 50% of the output ripple voltage. For
PWM operation (continuous conduction), the output voltage is accurately defined by the following equation:
where V
NOM
is the nominal feedback voltage, A
CCV
is
the integrator’s gain, and V
RIPPLE
is the output ripple
voltage (V
RIPPLE
= ESR x ∆I
INDUCTOR
, as described in
the
Output Capacitor Selection
section).
In discontinuous conduction (I
OUT
< I
LOAD(SKIP)
), the
longer off-times allow the slope compensation to
increase the threshold voltage by as much as 1%, so
the output voltage regulates slightly higher than it would
in PWM operation.
Internal Integrator
The internal integrator improves the output accuracy by
removing any output accuracy errors caused by the
slope compensation, output ripple voltage, and erroramplifier offset. Therefore, the DC accuracy (in forcedPWM mode) depends on the integrator’s gain, the integrator’s offset, and the accuracy of the integrator’s reference input.
Dual Quick-PWM Step-Down Controller with LowPower LDO and RTC Regulator for MAIN Supplies
PGOOD is the open-drain output that continuously
monitors both output voltages for undervoltage and
overvoltage conditions. PGOOD is actively held low in
shutdown (ON1 or ON2 = GND), during soft-start, and
soft-shutdown. Approximately 20µs (typ) after the softstart terminates, PGOOD becomes high impedance as
long as both output voltages exceed 85% of the nominal fixed-regulation voltage. PGOOD goes low if the
output voltage drops 15% below the regulation voltage,
or if the SMPS controller is shut down. For a logic-level
PGOOD output voltage, connect an external pullup
resistor between PGOOD and the logic power supply.
A 100kΩ pullup resistor works well in most applications.
Overvoltage Protection (OVP)
When the output voltage rises 15% above the fixedregulation voltage, the controller immediately pulls
PGOOD low, sets the overvoltage fault latch, and immediately pulls the respective DL_ high—clamping the
output fault to GND. Toggle either ON1 or ON2 input, or
cycle VCCpower below its POR threshold to clear the
fault latch and restart the controller.
Undervoltage Protection (UVP)
When the output voltage drops 30% below the fixedregulation voltage, the controller immediately pulls the
PGOOD low, sets the undervoltage fault latch, and
begins the shutdown sequence. After the output voltage drops below 0.1V, the synchronous rectifier turns
on, clamping the output to GND regardless of the output voltage. Toggle either ON1 or ON2 input, or cycle
VCCpower below its POR threshold to clear the fault
latch and restart the controller.
Thermal-Fault Protection (T
SHDN
)
The MAX17031 features a thermal-fault protection circuit. When the junction temperature rises above
+160°C, a thermal sensor activates the fault latch, pulls
PGOOD low, enables the 10Ω discharge circuit, and
disables the controller—DH and DL pulled low. Toggle
ONLDO or cycle IN power to reactivate the controller
after the junction temperature cools by 15°C.
Design Procedure
Firmly establish the input-voltage range and maximum
load current before choosing an inductor operating
point (ripple-current ratio). The primary design goal is
choosing a good inductor operating point, and the following three factors dictate the rest of the design:
•Input Voltage Range: The maximum value (V
IN(MAX)
)
must accommodate the worst-case, high ACadapter voltage. The minimum value (V
IN(MIN)
)
must account for the lowest battery voltage after
drops due to connectors, fuses, and battery-selector switches. If there is a choice at all, lower input
voltages result in better efficiency.
•Maximum Load Current: There are two values to
consider. The peak load current (I
LOAD(MAX)
) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor
selection, inductor saturation rating, and the design of
the current-limit circuit. The continuous load current
(I
LOAD
) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and
other critical heat-contributing components.
Table 3. Fault Protection and Shutdown Operation Table
MODECONTROLLER STATEDRI VER STATE
Shutdown (ON_ = High to Low)
Output UVP (Latched)
Output OVP (Latched)
UVLO (VCC Falling-Edge)
Thermal Fault (Latched)
UVLO (VCC Ri s ing Edge)
VCC Below POR SMPS inactive, 10 output discharge active.
Voltage soft-shutdown initiated. Internal error-amplifier
target slowly ramped down to GND and output activel y
discharged (automaticall y enters forced-PWM mode).
Controller shuts down and EA target internally slewed
down. Controller remains off until ON_ toggled or V
power cycled.
DL driven high and DH pulled low
after soft-shutdown completed
(output < 0.1V).
DL immediately
DH pulled low.
DL and DH pulled low.
DL driven high,
DH pulled low.
DL driven high,
DH pulled low.
driven high,
MAX17031
Inductor Operating Point: This choice provides
trade-offs between size vs. efficiency and transient
response vs. output ripple. Low inductor values provide better transient response and smaller physical
size, but also result in lower efficiency and higher
output ripple due to increased ripple currents. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduction (where the inductor current just touches zero
with every cycle at maximum load). Inductor values
lower than this grant no further size-reduction benefit. The optimum operating point is usually found
between 20% and 50% value at which PFM/PWM
switchover occurs.
Inductor Selection
The switching frequency and inductor operating point
determine the inductor value as follows:
For example: I
LOAD(MAX)
= 4A, VIN= 12V, V
OUT2
=
2.5V, f
SW
= 355kHz, 30% ripple current or LIR = 0.3:
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
inductor current (I
PEAK
):
Most inductor manufacturers provide inductors in standard values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc.
Also look for nonstandard values, which can provide a
better compromise in LIR across the input voltage
range. If using a swinging inductor (where the no-load
inductance decreases linearly with increasing current),
evaluate the LIR with properly scaled inductance values.
Transient Response
The inductor ripple current also impacts transientresponse performance, especially at low VIN- V
OUT
differentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The amount of output sag is also a function of the maximum duty factor, which can be calculated from the ontime and minimum off-time:
where t
OFF(MIN)
is the minimum off-time (see the
Electrical Characteristics
table).
The amount of overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as:
Setting the Current Limit
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The valley of the inductor current occurs at I
LOAD(MAX)
minus
half the ripple current; therefore:
where I
LIM(VAL)
equals the minimum valley current-limit
threshold voltage divided by the current-sense resistance (R
SENSE
). When using a 100kΩ ILIM resistor, the
minimum valley current-limit threshold is 40mV.
Connect a resistor between ILIM_ and analog ground to
set the adjustable current-limit threshold. The valley
current-limit threshold is approximately 1/10 the ILIM
voltage formed by the external resistance and internal
5µA current source. The 40kΩ to 400kΩ adjustment
range corresponds to a 20mV to 200mV valley currentlimit threshold. When adjusting the current limit, use 1%
tolerance resistors to prevent significant inaccuracy in
the valley current-limit tolerance.
Output Capacitor Selection
The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
For processor core voltage converters and other applications where the output is subject to violent load transients, the output capacitor’s size depends on how
much ESR is needed to prevent the output from dipping
too low under a load transient. Ignoring the sag due to
finite capacitance:
Dual Quick-PWM Step-Down Controller with LowPower LDO and RTC Regulator for MAIN Supplies
In applications without large and fast load transients,
the output capacitor’s size often depends on how much
ESR is needed to maintain an acceptable level of output voltage ripple. The output ripple voltage of a stepdown controller equals the total inductor ripple current
multiplied by the output capacitor’s ESR. Therefore, the
maximum ESR required to meet ripple specifications is:
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tantalums, OS-CONs, polymers, and other electrolytics).
When using low-capacity filter capacitors, such as
ceramic capacitors, size is usually determined by the
capacity needed to prevent V
SAG
and V
SOAR
from
causing problems during load transients. Generally,
once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge
is no longer a problem (see the V
SAG
and V
SOAR
equa-
tions in the
Transient Response
section). However, lowcapacity filter capacitors typically have high ESR zeros
that might affect the overall stability (see the
Output
Capacitor Stability Considerations
section).
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation:
where:
For a typical 300kHz application, the ESR zero frequency
must be well below 95kHz, preferably below 50kHz.
Tantalum and OS-CON capacitors in widespread use at
the time of publication have typical ESR zero frequencies of 25kHz. In the design example used for inductor
selection, the ESR needed to support 25mV
P-P
ripple is
25mV/1.2A = 20.8mΩ. One 220µF/4V SANYO polymer
(TPE) capacitor provides 15mΩ (max) ESR. This results
in a zero at 48kHz, well within the bounds of stability.
Do not put high-value ceramic capacitors directly on
OUT1 and OUT2 pins to ensure stability. Large ceramic
capacitors can have a high-ESR zero frequency and
cause erratic, unstable operation. However, it is easy to
add enough series resistance by placing the capacitors
a couple of inches downstream from the feedback
sense point, which should be as close as possible to
the inductor.
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and fast-feedback loop instability. Double-pulsing occurs due to
noise on the output or because the ESR is so low that
there is not enough voltage ramp in the output-voltage
signal. This “fools” the error comparator into triggering
a new cycle immediately after the 400ns minimum offtime period has expired. Double-pulsing is more annoying than harmful, resulting in nothing worse than
increased output ripple. However, it can indicate the
possible presence of loop instability due to insufficient
ESR. Loop instability results in oscillations at the output
after line or load steps. Such perturbations are usually
damped, but can cause the output voltage to rise
above or fall below the tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output-voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (I
RMS
) imposed by the switching currents:
For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their
resistance to power-up surge currents typical of systems with a mechanical switch or connector in series
with the input. If the MAX17031 is operated as the second stage of a two-stage power conversion system,
tantalum input capacitors are acceptable. In either configuration, choose a capacitor that has less than 10°C
temperature rise at the RMS input current for optimal
reliability and lifetime.
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention.
The high-side MOSFET (NH) must be able to dissipate
the resistive losses plus the switching losses at both
V
IN(MIN)
and V
IN(MAX)
. Ideally, the losses at V
IN(MIN)
should be roughly equal to the losses at V
IN(MAX)
, with
lower losses in between. If the losses at V
IN(MIN)
are
significantly higher, consider increasing the size of NH.
Conversely, if the losses at V
IN(MAX)
are significantly
higher, consider reducing the size of N
H
. If VINdoes
not vary over a wide range, maximum efficiency is
achieved by selecting a high-side MOSFET (N
H
) that
has conduction losses equal to the switching losses.
Choose a low-side MOSFET (N
L
) that has the lowest
possible on-resistance (R
DS(ON)
), comes in a moderate-sized package (i.e., 8-pin SO, DPAK, or D2PAK),
and is reasonably priced. Ensure that the MAX17031
DL_ gate driver can supply sufficient current to support
the gate charge and the current injected into the parasitic drain-to-gate capacitor caused by the high-side
MOSFET turning on; otherwise, cross-conduction problems could occur. Switching losses are not an issue for
the low-side MOSFET since it is a zero-voltage switched
device when used in the step-down topology.
Power-MOSFET Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at
minimum input voltage:
Generally, use a small high-side MOSFET to reduce
switching losses at high input voltages. However, the
R
DS(ON)
required to stay within package power-dissipation limits often limits how small the MOSFET can be.
The optimum occurs when the switching losses equal
the conduction (R
DS(ON)
) losses. High-side switching
losses do not become an issue until the input is greater
than approximately 15V.
Calculating the power dissipation in high-side
MOSFETs (NH) due to switching losses is difficult, since
it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors
include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PCB layout
characteristics. The following switching loss calculation
provides only a very rough estimate and is no substitute
for breadboard evaluation, preferably including verification using a thermocouple mounted on NH:
where C
OSS
is the high-side MOSFET’s output capaci-
tance, Q
G(SW)
is the charge needed to turn on the high-
side MOSFET, and I
GATE
is the peak gate-drive
source/sink current (1A typ).
Switching losses in the high-side MOSFET can become
a heat problem when maximum AC adapter voltages
are applied due to the squared term in the switchingloss equation provided above. If the high-side MOSFET
chosen for adequate R
DS(ON)
at low battery voltages
becomes extraordinarily hot when subjected to
V
IN(MAX)
, consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (NL), the worst-case power
dissipation always occurs at maximum battery voltage:
The absolute worst case for MOSFET power dissipation
occurs under heavy overload conditions that are
greater than I
LOAD(MAX)
but are not high enough to
exceed the current limit and cause the fault latch to trip.
To protect against this possibility, “overdesign” the circuit to tolerate:
where I
VALLEY(MAX)
is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and sense-resistance variation. The
MOSFETs must have a relatively large heatsink to handle the overload power dissipation.
Choose a Schottky diode (DL) with a forward voltage
drop low enough to prevent the low-side MOSFET’s
body diode from turning on during the dead time. As a
general rule, select a diode with a DC current rating
equal to 1/3 the load current. This diode is optional and
can be removed if efficiency is not critical.
Dual Quick-PWM Step-Down Controller with LowPower LDO and RTC Regulator for MAIN Supplies
The output voltage-adjustable range for continuousconduction operation is restricted by the nonadjustable
minimum off-time one-shot. When working with low
input voltages, the duty-factor limit must be calculated
using worst-case values for on- and off-times.
Manufacturing tolerances and internal propagation
delays introduce an error to the TON K-factor. This error
is greater at higher frequencies. Also, keep in mind that
transient response performance of buck regulators
operated too close to dropout is poor, and bulk output
capacitance must often be added (see the V
SAG
equa-
tion in the
Design Procedure
section).
The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆I
DOWN
)
as much as it ramps up during the on-time (∆IUP). The
ratio h = ∆IUP/∆I
DOWN
indicates the controller’s ability
to slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
each switching cycle, and V
SAG
greatly increases
unless additional output capacitance is used.
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows trade-offs between V
SAG
, output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
where V
DROP2
is the parasitic voltage drop in the
charge path (see the
On-Time One-Shot
section),
t
OFF(MIN)
is from the
Electrical Characteristics
table,
and K (1/fSW) is the switching period. The absolute minimum input voltage is calculated with h = 1.
If the calculated V
IN(MIN)
is greater than the required minimum input voltage, then operating frequency must be
reduced or output capacitance added to obtain an
acceptable V
SAG
. If operation near dropout is anticipated,
calculate V
SAG
to be sure of adequate transient response.
Dropout Design Example:
V
OUT2
= 2.5V
fSW= 355kHz
K = 3.0µs, worst-case K
MIN
= 3.3µs
t
OFF(MIN)
= 500ns
V
DROP2
= 100mV
h = 1.5:
Calculating again with h = 1 and the typical K-factor
value (K = 3.3µs) gives the absolute limit of dropout:
Therefore, VINmust be greater than 3.06V, even with
very large output capacitance, and a practical input voltage with reasonable output capacitance would be 3.47V.
PCB Layout Guidelines
Careful PCB layout is critical to achieving low switching
losses and clean, stable operation. The switching
power stage requires particular attention. If possible,
mount all the power components on the top side of the
board, with their ground terminals flush against one
another. Follow these guidelines for good PCB layout:
•Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable, jitter-free operation.
•Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PCBs (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing
PCB traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
•Minimize current-sensing errors by connecting LX_
directly to the drain of the low-side MOSFET.
•When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.
•Route high-speed switching nodes (BST_, LX_,
DH_, and DL_) away from sensitive analog areas
(REF, and OUT_).
A sample layout is available in the MAX17031 Evaluation
Kit data sheet.
Dual Quick-PWM Step-Down Controller with LowPower LDO and RTC Regulator for MAIN Supplies
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
1) Place the power components first, with ground terminals adjacent (NL_source, CIN, C
OUT_
, and D
L_
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET, preferably on the back side opposite N
L_
and NH_in order to keep LX_, GND, DH_, and the
DL_ gate-drive lines short and wide. The DL_ and
DH_ gate traces must be short and wide (50 mils to
100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for
proper adaptive dead-time sensing.
3) Group the gate-drive components (BST_ capacitor,
V
DD
bypass capacitor) together near the controller IC.
4) Make the DC-DC controller ground connections as
shown in Figure 1. This diagram can be viewed as
having two separate ground planes: power ground,
where all the high-power components go; and an analog ground plane for sensitive analog components.
The analog ground plane and power ground plane
must meet only at a single point directly at the IC.
5) Connect the output power planes directly to the output filter capacitor positive and negative terminals
with multiple vias. Place the entire DC-DC converter
circuit as close to the load as is practical.
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
.
PACKAGE TYPEPACKAGE CODEDOCUMENT NO.
24 TQFNT2444-3
21-0139
Chip Information
TRANSISTOR COUNT: 12,197
PROCESS: BiCMOS
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