Rainbow Electronics MAX16071 User Manual

19-5003; Rev 0; 10/09
12-Channel/8-Channel, Flash-Configurable System
Monitors with Nonvolatile Fault Registers
General Description
The MAX16070/MAX16071 flash-configurable sys­tem monitors supervise multiple system voltages. The MAX16070/MAX16071 can also accurately monitor (Q2.5%) one current channel using a dedicated high­side current-sense amplifier. The MAX16070 monitors up to twelve system voltages simultaneously, and the MAX16071 monitors up to eight supply voltages. These devices integrate a selectable differential or single-end­ed analog-to-digital converter (ADC). Device configura­tion information, including overvoltage and undervoltage limits and timing settings are stored in nonvolatile flash memory. During a fault condition, fault flags and channel voltages can be automatically stored in the nonvolatile flash memory for later read-back.
Because the MAX16070/MAX16071 support a power­supply voltage of up to 14V, they can be powered directly from the 12V intermediate bus in many systems.
The MAX16070/MAX16071 include eight/six program­mable general-purpose inputs/outputs (GPIOs). GPIOs are flash configurable as dedicated fault outputs, as a watchdog input or output, or as a manual reset.
The MAX16070/MAX16071 feature nonvolatile fault mem­ory for recording information during system shutdown events. The fault logger records a failure in the internal flash and sets a lock bit protecting the stored fault data from accidental erasure. An SMBus™ or a JTAG serial interface configures the MAX16070/MAX16071. The MAX16070/MAX16071 are available in a 40-pin, 6mm x 6mm, TQFN package. Both devices are fully specified from -40NC to +85NC.
Features
S Operate from 2.8V to 14V
S ±2.5% Current-Monitoring Accuracy
S 1% Accurate 10-Bit ADC Monitors 12/8 Voltage
Inputs
S Single-Ended or Differential ADC for System
Voltage/Current Monitoring
S Integrated High-Side, Current-Sense Amplifier
S 12/8 Monitored Inputs with Overvoltage/
Undervoltage/Early Warning Limit
S Nonvolatile Fault Event Logger
S Two Programmable Fault Outputs and One Reset
Output
S Eight General-Purpose Inputs/Outputs
Configurable as: Dedicated Fault Outputs Watchdog Timer Function Manual Reset Margin Enable
S SMBus (with Timeout) or JTAG Interface
S Flash Configurable Time Delays and Thresholds
S -40NC to +85NC Operating Temperature Range
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX16070ETL+ MAX16071ETL+
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
-40NC to +85NC
-40NC to +85NC
40 TQFN-EP* 40 TQFN-EP*
MAX16070/MAX16071
Applications
Networking Equipment
Telecom Equipment (Base Stations, Access)
Storage/Raid Systems
Servers
Pin Configuration and Typical Operating Circuits appear at end of data sheet.
SMBus is a trademark of Intel Corp.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers
ABSOLUTE MAXIMUM RATINGS
VCC, CSP, CSM to GND ........................................-0.3V to +15V
CSP to CSM .......................................................... -0.7V to +0.7V
MON_, GPIO_, SCL, SDA, A0, RESET to GND
(programmed as open-drain outputs) .................-0.3V to +6V
EN, TCK, TMS, TDI to GND ....................................-0.3V to +4V
DBP, ABP to GND ...-0.3V to the lower of +3V and (VCC + 0.3V) TDO, GPIO_, RESET
(programmed as push-pull outputs) .... -0.3V to (V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DBP
+ 0.3V)
ELECTRICAL CHARACTERISTICS
(VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at ABP = DBP = VCC = 3.3V, TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX16070/MAX16071
Operating Voltage Range V
Undervoltage Lockout (Rising) V
Undervoltage Lockout Hysteresis V
Minimum Flash Operating Voltage
Supply Current I
ABP Regulator Voltage V DBP Regulator Voltage V Boot Time t Flash Writing Time 8-byte word 122 ms Internal Timing Accuracy (Note 3) -8 +8 %
EN Input Voltage
EN Input Current I Input Voltage Range 0 5.5 V
CC
UVLO
UVLO_HYS
V
flash
CC
ABP
DBP
BOOT
V
TH_EN_R
V
TH_EN_F
EN
Reset output asserted low 1.2 (Note 2) 2.8 14
Minimum voltage on VCC to ensure the device is flash configurable
Minimum voltage on VCC to ensure flash erase and write operations
No load on output pins 4.5 7 During flash writing cycle 10 14 C
= 1μF, no load, VCC = 5V 2.85 3 3.15 V
ABP
C
= 1μF, no load, VCC = 5V 2.8 3 3.1 V
ABP
VCC > V
EN voltage rising 1.41 EN voltage falling 1.365 1.39 1.415
UVLO
Input/Output Current .........................................................20mA
Continuous Power Dissipation (TA = +70NC)
40-Pin TQFN (derate 26.3mW/NC above +70NC) .......2105mW
Operating Temperature Range .......................... -40NC to +85NC
Junction Temperature ....................................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
V
2.7 V
100 mV
2.7 V
mA
200 350 μs
V
-0.5 +0.5 μA
2 ______________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at ABP = DBP = VCC = 3.3V, TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ADC DC ACCURACY
Resolution 10 Bits
Gain Error ADC
Offset Error ADC Integral Nonlinearity ADC Differential Nonlinearity ADC ADC Total Monitoring Cycle Time t
ADC IN_ Ranges
CURRENT SENSE
CSP Input-Voltage Range V
Input Bias Current
CSP Total Unadjusted Error CSP
Overcurrent Differential Threshold
V
Fault Threshold
SENSE
Hysteresis
Secondary Overcurrent Threshold Timeout
V
Ranges
SENSE
ADC Current Measurement Accuracy
Gain Accuracy
Common-Mode Rejection Ratio CMRR Power-Supply Rejection Ratio PSRR
CYCLE
I
I
CSM
OVC
OVC
OVC
CSP
CSP
GAIN
TA = +25°C 0.35 TA = -40°C to +85°C 0.70
OFF
INL
DNL
No MON_ fault detected 40 50 μs 1 LSB = 5.43mV 5.56
1 LSB = 1.36mV 1.39
3 14 V
14 25
V
= V
CSP
(Note 4) 2 %FSR
ERR
V
TH
HYS
DEL
SNSVCSP
SNS
CSP
V
CSM
r73h[6:5] = ‘00’ 0 r73h[6:5] = ‘01’ 3 4 5 r73h[6:5] = ‘10’ 12 16 20 r73h[6:5] = ‘11’ 50 64 60 Gain = 6 232 Gain = 12 116 Gain = 24 58 Gain = 48 29 V
SENSE
V
SENSE
V
SENSE
V
SENSE
V
SENSE
gain = 6
CSM
Gain = 48 21.5 25 30.5 Gain = 24 46 51 56
­Gain = 12 94 101 108 Gain = 6 190 202 210
= 150mV (gain = 6 only) -2.5 = 50mV, gain = 12 -4 = 25mV, gain = 24 = 10mV, gain = 48
= 20mV to 100mV, V
> 4V 80 dB
CSP
= 5V,
-1.5 +1.5 %
3 5
0.5 % OVC
Q0.2 Q0.2 Q0.5
Q1
80 dB
1 LSB 1 LSB 1 LSB
+2.5
+4
%
V1 LSB = 2.72mV 2.78
μA
mV
TH
ms
mV
%
MAX16070/MAX16071
_______________________________________________________________________________________ 3
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at ABP = DBP = VCC = 3.3V, TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OUTPUTS (RESET, GPIO_)
I
= 2mA 0.4
SINK
I
Output-Voltage Low V
Maximum Output Sink Current
Output-Voltage High (Push-Pull) I
Output Leakage (Open Drain) 1 μA
SMBus INTERFACE
Logic-Input Low Voltage V Logic-Input High Voltage V Input Leakage Current IN = GND or V Output Sink Current V
MAX16070/MAX16071
Input Capacitance C SMBus Timeout t
INPUTS (A0, GPIO_)
Input Logic-Low V Input Logic-High V WDI Pulse Width t
MR Pulse Width MR to RESET Delay MR Glitch Rejection
SMBus TIMING
Serial Clock Frequency f
Bus Free Time Between STOP and START Condition
START Condition Setup Time t START Condition Hold Time t STOP Condition Setup Time t Clock Low Period t Clock High Period t Data Setup Time t
OL
IL
IH
OL
IN
TIMEOUT
IL
IH
WDI
t
MR
SCL
t
BUF
SU:STA
HD:STA
SU:STO
LOW
HIGH
SU:DAT
= 10mA, GPIO_ only 0.7
SINK
VCC = 1.2V, I Total current into RESET, GPIO_,
VCC = 3.3V
SOURCE
Input voltage falling 0.8 V Input voltage rising 2.0 V
I
SINK
SCL time low for reset 25 35 ms
= 100μA 2.4 V
= 3mA 0.4 V
= 100μA (RESET only)
SINK
CC
-1 +1 μA
5 pF
2.0 V
100 ns
1 μs
0.5 μs
100 ns
1.3 μs
0.6 μs
0.6 μs
0.6 μs
1.3 μs
0.6 μs
100 ns
0.3
30 mA
0.8 V
400 kHz
V
4 ______________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at ABP = DBP = VCC = 3.3V, TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Fall Time t Data Hold Time t Pulse Width of Spike Suppressed t
JTAG INTERFACE
TDI, TMS, TCK Logic-Low Input Voltage
TDI, TMS, TCK Logic-High Input Voltage
TDO Logic-Output Low Voltage V TDO Logic-Output High Voltage V TDI, TMS Pullup Resistors R I/O Capacitance C TCK Clock Period t TCK High/Low Time t2, t TCK to TMS, TDI Setup Time t TCK to TMS, TDI Hold Time t TCK to TDO Delay t TCK to TDO High-Z Delay t
OF
HD:DAT
V
V
SP
IL
IH
OL
OH
PU
I/O
1
4
5
6
7
C
= 10pF to 400pF 250 ns
BUS
From 50% SCL falling to SDA change 0.3 0.9 μs
30 ns
Input voltage falling 0.8 V
Input voltage rising 2 V
I
= 3mA 0.4 V
SINK
I
SOURCE
Pullup to DBP 40 50 60
3
= 200μA 2.4 V
5 pF
50 500 ns 15 ns 10 ns
1000 ns
500 ns 500 ns
MAX16070/MAX16071
Note 1: Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at TA =
+25NC and TA = +85NC. Specifications at TA = -40NC are guaranteed by design.
Note 2: For 3.3V VCC applications, connect VCC, DBP, and ABP together. For higher supply applications, connect VCC only to the
supply rail.
Note 3: Applies to RESET, fault, autoretry, sequence delays, and watchdog timeout. Note 4: Total unadjusted error is a combination of gain, offset, and quantization error.
_______________________________________________________________________________________ 5
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers
SDA
t
BUF
SCL
t
HD:STA
t
SU:DAT
t
t
t
LOW
t
HIGH
t
R
HD:DAT
t
F
SU:STA
t
HD:STA
t
SU:STO
START
CONDITION
MAX16070/MAX16071
Figure 1. SMBus Timing Diagram
t
2
TCK
TDI, TMS
t
6
t
7
t
4
REPEATED START
CONDITION
t
1
t
5
STOP
CONDITION
t
3
START
CONDITION
TDO
Figure 2. JTAG Timing Diagram
6 ______________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
VCC SUPPLY CURRENT
NORMALIZED MON_ THRESHOLD
NORMALIZED EN THRESHOLD
NORMALIZED EN THRESHOLD
TRANSIENT DURATION
µ
NORMALIZED TIMING ACCURACY
MON_ DEGLITCH
µ
DELAY (µs)
OUTPUT VOLTAGE
OUTPUT-VOLTAGE HIGH vs.
V
(V)
Managers with Nonvolatile Fault Registers
Typical Operating Characteristics
(Typical values are at VCC = 3.3V, T
= +25°C, unless otherwise noted.)
A
MAX16070/MAX16071
6
ABP AND DBP CONNECTED TO V
5
4
(mA)
3
CC
I
2
1
0
ABP AND DBP REGULATORS ACTIVE
FOR LOW-VOLTAGE APPLICATIONS VCC < 3.6V CONNECT ABP AND DBP TO V
0 14
+25NC
-40NC
CC
VCC (V)
vs. THRESHOLD OVERDRIVE (EN)
160
140
s)
120
100
80
60
TRANSIENT DURATION (
40
20
vs. VCC SUPPLY VOLTAGE
0
1 100
10
EN OVERDRIVE (mV)
CC
+85NC
12108642
1.2
1.0
MAX16070 toc01
0.8
0.6
0.4
NORMALIZED MON_ THRESHOLD
0.2
0
-40 80
5.6V RANGE, HALF SCALE, PUV THRESHOLD
6040200-20
TEMPERATURE (NC)
MAX16070 toc02
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
-40
vs. TEMPERATURE
vs. TEMPERATURE
0.986
0.984
MAX16070 toc04
0.982
0.980
0.978
0.976
NORMALIZED SLOT DELAY
0.974
0.972
-40
806040200-20
TEMPERATURE (NC)
MAX16070 toc05
120
100
s)
80
60
40
TRANSIENT DURATION (
20
0
vs. TEMPERATURE
TEMPERATURE (NC)
vs. TRANSIENT DURATION
2
4 8 16
DEGLITCH VALUE
MAX16070 toc03
806040200-20
MAX16070 toc06
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
MR TO RESET PROPAGATION DELAY
vs. TEMPERATURE
MAX
MIN
-40 TEMPERATURE (NC)
_______________________________________________________________________________________ 7
806020 400-20
MAX16070 toc07
vs. SINK CURRENT (OUT = LOW)
0.45
0.40
0.35
0.30
0.25
(V)
OUT
V
0.20
0.15
0.10
0.05
0
0 20
GPIO_
I
OUT
RESET
(mA)
SOURCE CURRENT (PUSH-PULL OUTPUT)
3.4
3.3
3.2
MAX16070 toc08
3.1
3.0
2.9
OUT
2.8
2.7
2.6
2.5
2.4
15105
0 1500
RESET
GPIO_
1000500
I
(µA)
OUT
MAX16070 toc09
12-Channel/8-Channel Flash-Configurable System
INL (LSB)
NORMALIZED CURRENT-SENSE
CURRENT-SENSE ACCURACY
CURRENT-SENSE TRANSIENT DURATION
RESET OUTPUT CURRENT
Monitors with Nonvolatile Fault Registers
Typical Operating Characteristics (continued)
(Typical values are at VCC = 3.3V, T
= +25°C, unless otherwise noted.)
A
INTEGRAL NONLINEARITY vs. CODE
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0 0 1024
CODE (LSB)
MAX16070/MAX16071
1.05
1.03
1.01
0.99
0.97
NORMALIZED CURRENT-SENSE ACCURACY
0.95
ACCURACY vs. TEMPERATURE
200mV
100mV
-40 TEMPERATURE (NC)
25mV
6010
DIFFERENTIAL NONLINEARITY vs. CODE
1.0
0.8
MAX16070 toc10
896768512 640256 384128
0.6
0.4
0.2
0
DNL (LSB)
-0.2
-0.4
-0.6
-0.8
-1.0 0 1024
CODE (LSB)
MAX16070 toc11
896768512 640256 384128
vs. CSP-CSM VOLTAGE
1.0
0.8
MAX16070 toc12
0.6
0.4
0.2
0
ERROR (mV)
-0.2
-0.4
-0.6
-0.8
-1.0 0 30
CSP-CSMs VOLTAGE (mV)
MAX16070 toc13
252015105
8 ______________________________________________________________________________________
1.8
vs. CSP-CSM OVERDRIVE
1.6
1.4
1.2
1.0
0.8
0.6
TRANSIENT DURATION (Fs)
0.4
0.2
0
0 100
CSP-CSM OVERDRIVE (mV)
18
16
MAX16070 toc14
80604020
14
12
10
8
6
OUTPUT CURRENT (mA)
4
2
0
0 14
ABP AND DBP CONNECTED TO V
ABP AND DBP
REGULATORS ACTIVE
SUPPLY VOLTAGE (V)
V
CC
RESET
MAX16070 toc15
= 0.3V
12106 842
vs. SUPPLY VOLTAGE
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Pin Description
MAX16070/MAX16071
PIN
MAX16070 MAX16071
1–5, 34, 35, 401–5, 37, 38,
40
6 6 CSP
7 7 CSM
8 8 RESET Configurable Reset Output
9 9 TMS JTAG Test Mode Select 10 10 TDI JTAG Test Data Input 11 11 TCK JTAG Test Clock 12 12 TDO JTAG Test Data Output 13 13 SDA SMBus Serial-Data Open-Drain Input/Output 14 14 A0 Four-State SMBus Address. Address sampled upon POR. 15 15 SCL SMBus Serial Clock Input
16, 33 16, 36 GND Ground
17, 18 GPIO7, GPIO8
19–24 17–22 GPIO1–GPIO6
25, 26, 27, 29
28 29 EN
30 31, 32 DBP
31 33, 34 V
32 35 ABP Analog Bypass. Bypass ABP with a 1FF ceramic capacitor to GND.
36–39
EP
23–28, 30, 39
NAME FUNCTION
MON2–MON6, MON7, MON8,
MON1
N.C. No Connection. Not internally connected.
CC
MON9– MON12
Monitor Voltage Input 1–Monitor Voltage Input 8. Set monitor voltage range through configuration registers. Measured value written to the ADC register can be read back through the SMBus or JTAG interface.
Current-Sense Amplifier Positive Input. Connect CSP to the source side of the external sense resistor.
Current-Sense Amplifier Negative Input. Connect CSM to the load side of the external sense resistor.
General-Purpose Input/Output 7 and General-Purpose Input/Output 8. GPIO_s can be configured to act as a TTL input, a push-pull, open-drain, or high-impedance output or a pulldown circuit during a fault event or reverse sequencing.
General-Purpose Input/Output 1–General-Purpose Input/Output 6. GPIO_s can be configured to act as a TTL input, a push-pull, open-drain, or high­impedance output or a pulldown circuit during a fault event.
Analog Enable Input. All outputs deassert when VEN is below the enable threshold.
Digital Bypass. All push-pull outputs are referenced to DBP. Bypass DBP with a 1FF capacitor to GND.
Device Power Supply. Connect VCC to a voltage from 2.8V to 14V. Bypass VCC with a 10FF capacitor to GND.
Monitor Voltage Input 9–Monitor Voltage Input 12. Set monitor voltage range through configuration registers. Measured value written to the ADC register can be read back through the SMBus or JTAG interface.
Exposed Pad. Internally connected to GND. Connect to ground, but do not use as the main ground connection.
_______________________________________________________________________________________ 9
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers
Functional Diagram
V
CC
MAX16070 MAX16071
EN
1.4V
CSP
CSM
A
V
V
CSTH
MAX16070/MAX16071
REF
MON1–
MON12
VOLTAGE SCALING
AND MUX
10-BIT ADC
(SAR)
REGISTERS
ADC
ABP DBP
DIGITAL
COMPARATORS
DECODE
LOGIC
WATCHDOG
TIMER
OVERC
RESET
ANYFAULT
FAULT1
FAULT2
MR
MARGIN
WDI
WDO
GPIO1–GPIO8
RESET
G P
I
O
C O N
T R O
L
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
RAM
REGISTERS
SMBus INTERFACE
AO
SCL SDA
FLASH
MEMORY
GND
TDO TDI TCK TMS
JTAG
INTERFACE
10 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Detailed Description
The MAX16070 monitors up to twelve system power sup­plies and the MAX16071 can monitor up to eight system power supplies. After boot-up, if EN is high and the soft­ware enable bit is set to ‘1,’ monitoring begins based on the configuration stored in flash. An internal multiplexer cycles through each MON_ input. At each multiplexer stop, the 10-bit ADC converts the monitored analog volt­age to a digital result and stores the result in a register. Each time a conversion cycle (50Fs, max) completes, internal logic circuitry compares the conversion results to the overvoltage and undervoltage thresholds stored in memory. When a result violates a programmed threshold, the conversion can be configured to generate a fault. GPIO_ can be programmed to assert on combinations of faults. Additionally, faults can be configured to shut off the system and trigger the nonvolatile fault logger, which writes all fault information automatically to the flash and write-protects the data to prevent accidental erasure.
The MAX16070/MAX16071 contain both SMBus and JTAG serial interfaces for accessing registers and flash. Use only one interface at any given time. For more infor­mation on how to access the internal memory through these interfaces, see the SMBus-Compatible Interface and JTAG Serial Interface sections. The memory map is divided into three pages with access controlled by special SMBus and JTAG commands.
The factory-default values at POR (power-on reset) for all RAM registers are ‘0’s. POR occurs when VCC reaches the undervoltage-lockout threshold (UVLO) of 2.8V (max). At POR, the device begins a boot-up sequence. During the boot-up sequence, all monitored inputs are masked
from initiating faults and flash contents are copied to the respective register locations. During boot-up, the MAX16070/MAX16071 are not accessible through the serial interface. The boot-up sequence takes up to 150Fs, after which the device is ready for normal opera­tion. RESET is asserted low up to the boot-up phase and remains asserted for its programmed timeout period once sequencing is completed and all monitored channels are within their respective thresholds. Up to the boot-up phase, the GPIO_s are high impedance.
Power
Apply 2.8V to 14V to VCC to power the MAX16070/ MAX16071. Bypass VCC to ground with a 10FF capaci­tor. Two internal voltage regulators, ABP and DBP, supply power to the analog and digital circuitry within the device. For operation at 3.6V or lower, disable the regulators by connecting ABP and DBP to VCC.
ABP is a 3.0V (typ) voltage regulator that powers the inter­nal analog circuitry. Bypass ABP to GND with a 1FF ceram­ic capacitor installed as close to the device as possible.
DBP is an internal 3.0V (typ) voltage regulator. DBP pow­ers flash and digital circuitry. All push-pull outputs refer to DBP. Bypass the DBP output to GND with a 1FF ceramic capacitor installed as close as possible to the device.
Do not power external circuitry from ABP or DBP.
Enable
To enable monitoring, the voltage at EN must be above
1.4V and the software enable bit in r73h[0] must be set to ‘1.’ To power down and disable monitoring, either pull EN below 1.35V or set the Software Enable bit to ‘0.’ See Table 1 for the software enable bit configurations. Connect EN to ABP if not used.
MAX16070/MAX16071
Table 1. Software Enable Configurations
REGISTER
ADDRESS
73h 273h
FLASH
ADDRESS
______________________________________________________________________________________ 11
BIT RANGE DESCRIPTION
[0] Software enable [1] Reserved [2] 1 = Margin mode enabled
Early warning threshold select
[3]
[4]
0 = Early warning is undervoltage 1 = Early warning is overvoltage
Independent watchdog mode enable 1 = Watchdog timer is independent of sequencer 0 = Watchdog timer boots after sequence completes
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers
When in the monitoring state, a register bit, ENRESET, is set to a ‘1’ when EN falls below the undervoltage threshold. This register bit latches and must be cleared through software. This bit indicates if RESET asserted low due to EN going under the threshold. The POR state of ENRESET is ‘0’. The bit is only set on a falling edge of the EN comparator output or the software enable bit.
Voltage/Current Monitoring
The MAX16070/MAX16071 feature an internal 10-bit ADC that monitors the MON_ voltage inputs. An internal multiplexer cycles through each of the enabled inputs, taking less than 40Fs for a complete monitoring cycle. Each acquisition takes approximately 3.2Fs. At each multiplexer stop, the 10-bit ADC converts the analog input to a digital result and stores the result in a register. ADC conversion results are stored in registers r00h to r1Ah (see Table 6). Use the SMBus or JTAG serial inter­face to read ADC conversion results.
The MAX16070 provides twelve inputs, MON1 to MON12,
MAX16070/MAX16071
for voltage monitoring. The MAX16071 provides eight inputs, MON1 to MON8, for voltage monitoring. Each input voltage range is programmable in registers r43h to r45h (see Table 5). When MON_ configuration registers are set to ’11,’ MON_ voltages are not monitored, and the multiplexer does not stop at these inputs, decreasing the total cycle time. These inputs cannot be configured to trigger fault conditions.
The three programmable thresholds for each monitored voltage include an overvoltage, an undervoltage, and a secondary warning threshold that can be set in r73h[3] to be either an undervoltage or overvoltage threshold. See the Faults section for more information on setting overvoltage and undervoltage thresholds. All voltage thresholds are 8 bits wide. The 8 MSBs of the 10-bit ADC conversion result are compared to these overvoltage and undervoltage thresholds.
Inputs that are not enabled are not converted by the ADC; they contain the last value acquired before that channel was disabled.
The ADC conversion result registers are reset to 00h at boot-up. These registers are not reset when a reboot command is executed.
Configure the MAX16070/MAX16071 for differential mode in r46h (Table 5). The possible differential pairs are MON1/MON2, MON3/MON4, MON5/MON6, MON7/ MON8, MON9/MON10, MON11/MON12 with the first input always being at a higher voltage than the second. Use differential voltage sensing to eliminate voltage off­sets or measure supply current. See Figure 3. In differ­ential mode, the odd-numbered MON_ input measures the absolute voltage with respect to GND while the result of the even input is the difference between the odd and even inputs. See Figure 3 for the typical differential mea­surement circuit.
POWER
SUPPLY
POWER
SUPPLY
MON
ODD
MAX16070 MAX16071
MON
S
ODD
LOAD
MON
EVEN
MON
EVEN
I
LOAD
R
SENSE
V
MON
LOAD
CS+
CS-
OVERC
*ADJUSTABLE BY r47h [1:0]
-
+
MAX16070
-
+
R
Figure 3. Differential Measurement Connections Figure 4. Current-Sense Amplifier
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TO ADC MUX
*A
V
+
*V
CSTH
-
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Boot-Up Delay
Once EN is above its threshold and the software-enable bit is set, a boot-up delay occurs before monitoring begins. This delay is configured in register 77h[3:0] as shown in Tables 2 and 3.
Internal Current-Sense Amplifier
The current-sense inputs, CSP/CSM, and a current­sense amplifier facilitate power monitoring (see Figure
4). The voltage on CSP relative to GND is also monitored by the ADC when the current-sense amplifier is enabled with r47h[0]. The conversion results are located in regis­ters r19h and r1Ah (see Table 6). There are two select­able voltage ranges for CSP set by r47h[1], see Table
4. Although the voltage can be monitored over SMBus or JTAG, this voltage has no threshold comparators and cannot trigger any faults. Regarding the current-sense amplifier, there are four selectable ranges and the ADC output for a current-sense conversion is:
X
where X r18h, V
= (V
ADC
is the 8-bit decimal ADC result in register
ADC
is V
SENSE
CSP
x AV)/1.4V x (28 - 1)
SENSE
- V
and AV is the current-
CSM,
sense voltage gain set by r47h[3:2].
In addition, there are two programmable current-sense trip thresholds: primary overcurrent and secondary over­current. For fast fault detection, the primary overcurrent threshold is implemented with an analog comparator connected to the internal OVERC signal. The OVERC signal can be output on one of the GPIO_s. See the General-Purpose Inputs/Outputs section for configur­ing the GPIO_ to output the OVERC signal. The primary threshold is set by:
ITH = V
where ITH is the current threshold to be set, V the threshold set by r47h[3:2], and R
CSTH/RSENSE
SENSE
is
CSTH
is the value
of the sense resistor. See Table 4 for a description of r47h. OVERC depends only on the primary overcurrent threshold. The secondary overcurrent threshold is imple­mented through ADC conversions and digital compari­son set by r6Ch. The secondary overcurrent threshold includes programmable time delay options located in r73h[6:5]. Primary and secondary current-sense faults are enabled/disabled through r47h[0].
MAX16070/MAX16071
Table 2. Boot-Up Delay Register
REGISTER
ADDRESS
77h 277h
FLASH
ADDRESS
BIT RANGE DESCRIPTION
Table 3. Boot-Up Delay Values
CODE VALUE
0000 0001 0010 1ms 0011 2ms 0100 3ms 0101 4ms 0110 6ms 0111 8ms 1000 10ms 1001 12ms 1010 25ms 1011 100ms 1100 200ms 1101 400ms 1110 800ms 1111 1.6s
[3:0] Boot-up delay [7:0] Reserved
25Fs
500Fs
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12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers
Table 4. Overcurrent Primary Threshold and Current-Sense Control
REGISTER ADDRESS
47h 247h
73h 273h [6:5]
FLASH
ADDRESS
BIT
RANGE
[0]
[1]
[3:2]
1 = Current sense is enabled 0 = Current sense is disabled
1 = CSP full-scale range is 14V 0 = CSP full-scale range is 7V
Overcurrent primary threshold and current-sense gain setting 00 = 200mV threshold, AV = 6V/V 01 = 100mV threshold, AV = 12V/V 10 = 50mV threshold, AV = 24V/V 11 = 25mV threshold, AV = 48V/V
Overcurrent secondary threshold deglitch 00 = No delay 01 = 14ms 10 = 15ms 11 = 60ms
MAX16070/MAX16071
Table 5. ADC Configuration Registers
REGISTER ADDRESS
43h 243h
FLASH
ADDRESS
BIT RANGE DESCRIPTION
[1:0]
[3:2]
[5:4]
[7:6]
DESCRIPTION
ADC1 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted
ADC2 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted
ADC3 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted
ADC4 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted
14 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 5. ADC Configuration Registers (continued)
MAX16070/MAX16071
REGISTER ADDRESS
44h 244h
45h 245h
FLASH
ADDRESS
BIT RANGE DESCRIPTION
ADC5 full-scale range 00 = 5.6V
[1:0]
[3:2]
[5:4]
[7:6]
[1:0]
[3:2]
[5:4]
[7:6]
01 = 2.8V 10 = 1.4V 11 = Channel not converted
ADC6 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted
ADC7 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted
ADC8 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted
ADC9 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted
ADC10 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted
ADC11 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted
ADC12 full-scale range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted
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12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers
Table 5. ADC Configuration Registers (continued)
REGISTER ADDRESS
46h 246h
FLASH
ADDRESS
BIT RANGE DESCRIPTION
[0]
[1]
[2]
[3]
[4]
MAX16070/MAX16071
[5]
Differential conversion ADC1, ADC2 0 = Disabled 1 = Enabled
Differential conversion ADC3, ADC4 0 = Disabled 1 = Enabled
Differential conversion ADC5, ADC6 0 = Disabled 1 = Enabled
Differential conversion ADC7, ADC8 0 = Disabled 1 = Enabled
Differential conversion ADC9, ADC10 0 = Disabled 1 = Enabled
Differential conversion ADC11, ADC12 0 = Disabled 1 = Enabled
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