The MAX16070/MAX16071 flash-configurable system monitors supervise multiple system voltages. The
MAX16070/MAX16071 can also accurately monitor
(Q2.5%) one current channel using a dedicated highside current-sense amplifier. The MAX16070 monitors
up to twelve system voltages simultaneously, and the
MAX16071 monitors up to eight supply voltages. These
devices integrate a selectable differential or single-ended analog-to-digital converter (ADC). Device configuration information, including overvoltage and undervoltage
limits and timing settings are stored in nonvolatile flash
memory. During a fault condition, fault flags and channel
voltages can be automatically stored in the nonvolatile
flash memory for later read-back.
The internal 1% accurate 10-bit ADC measures each
input and compares the result to one overvoltage, one
undervoltage, and one early warning limit that can be
configured as either undervoltage or overvoltage. A fault
signal asserts when a monitored voltage falls outside the
set limits. Up to three independent fault output signals
are configurable to assert under various fault conditions.
Because the MAX16070/MAX16071 support a powersupply voltage of up to 14V, they can be powered
directly from the 12V intermediate bus in many systems.
The MAX16070/MAX16071 include eight/six programmable general-purpose inputs/outputs (GPIOs). GPIOs
are flash configurable as dedicated fault outputs, as a
watchdog input or output, or as a manual reset.
The MAX16070/MAX16071 feature nonvolatile fault memory for recording information during system shutdown
events. The fault logger records a failure in the internal
flash and sets a lock bit protecting the stored fault data
from accidental erasure. An SMBus™ or a JTAG serial
interface configures the MAX16070/MAX16071. The
MAX16070/MAX16071 are available in a 40-pin, 6mm x
6mm, TQFN package. Both devices are fully specified
from -40NC to +85NC.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
ABSOLUTE MAXIMUM RATINGS
VCC, CSP, CSM to GND ........................................-0.3V to +15V
CSP to CSM .......................................................... -0.7V to +0.7V
MON_, GPIO_, SCL, SDA, A0, RESET to GND
(programmed as open-drain outputs) .................-0.3V to +6V
EN, TCK, TMS, TDI to GND ....................................-0.3V to +4V
DBP, ABP to GND ...-0.3V to the lower of +3V and (VCC + 0.3V)
TDO, GPIO_, RESET
(programmed as push-pull outputs) .... -0.3V to (V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DBP
+ 0.3V)
ELECTRICAL CHARACTERISTICS
(VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at ABP = DBP = VCC = 3.3V, TA = +25NC.)
(Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
MAX16070/MAX16071
Operating Voltage RangeV
Undervoltage Lockout (Rising)V
Undervoltage Lockout HysteresisV
Minimum Flash Operating
Voltage
Supply CurrentI
ABP Regulator Voltage V
DBP Regulator VoltageV
Boot Time t
Flash Writing Time 8-byte word122ms
Internal Timing Accuracy(Note 3)-8+8%
EN Input Voltage
EN Input CurrentI
Input Voltage Range 05.5V
CC
UVLO
UVLO_HYS
V
flash
CC
ABP
DBP
BOOT
V
TH_EN_R
V
TH_EN_F
EN
Reset output asserted low1.2
(Note 2)2.814
Minimum voltage on VCC to ensure the
device is flash configurable
Minimum voltage on VCC to ensure flash
erase and write operations
No load on output pins4.57
During flash writing cycle1014
C
= 1μF, no load, VCC = 5V2.8533.15V
ABP
C
= 1μF, no load, VCC = 5V2.833.1V
ABP
VCC > V
EN voltage rising1.41
EN voltage falling1.3651.391.415
UVLO
Input/Output Current .........................................................20mA
(VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at ABP = DBP = VCC = 3.3V, TA = +25NC.)
(Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Output Fall Timet
Data Hold Timet
Pulse Width of Spike Suppressedt
JTAG INTERFACE
TDI, TMS, TCK Logic-Low Input
Voltage
TDI, TMS, TCK Logic-High Input
Voltage
TDO Logic-Output Low VoltageV
TDO Logic-Output High VoltageV
TDI, TMS Pullup ResistorsR
I/O CapacitanceC
TCK Clock Periodt
TCK High/Low Timet2, t
TCK to TMS, TDI Setup Timet
TCK to TMS, TDI Hold Timet
TCK to TDO Delayt
TCK to TDO High-Z Delayt
OF
HD:DAT
V
V
SP
IL
IH
OL
OH
PU
I/O
1
4
5
6
7
C
= 10pF to 400pF250ns
BUS
From 50% SCL falling to SDA change0.30.9μs
30ns
Input voltage falling0.8V
Input voltage rising2V
I
= 3mA0.4V
SINK
I
SOURCE
Pullup to DBP405060kω
3
= 200μA2.4V
5pF
50500ns
15ns
10ns
1000ns
500ns
500ns
MAX16070/MAX16071
Note 1: Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at TA =
+25NC and TA = +85NC. Specifications at TA = -40NC are guaranteed by design.
Note 2: For 3.3V VCC applications, connect VCC, DBP, and ABP together. For higher supply applications, connect VCC only to the
supply rail.
Note 3: Applies to RESET, fault, autoretry, sequence delays, and watchdog timeout.
Note 4: Total unadjusted error is a combination of gain, offset, and quantization error.
99TMSJTAG Test Mode Select
1010TDIJTAG Test Data Input
1111TCKJTAG Test Clock
1212TDOJTAG Test Data Output
1313SDASMBus Serial-Data Open-Drain Input/Output
1414A0Four-State SMBus Address. Address sampled upon POR.
1515SCLSMBus Serial Clock Input
16, 3316, 36GNDGround
17, 18—GPIO7, GPIO8
19–2417–22GPIO1–GPIO6
25, 26, 27, 29
2829EN
3031, 32DBP
3133, 34V
3235ABPAnalog Bypass. Bypass ABP with a 1FF ceramic capacitor to GND.
36–39—
——EP
23–28,
30, 39
NAMEFUNCTION
MON2–MON6,
MON7, MON8,
MON1
N.C.No Connection. Not internally connected.
CC
MON9–
MON12
Monitor Voltage Input 1–Monitor Voltage Input 8. Set monitor voltage range
through configuration registers. Measured value written to the ADC register
can be read back through the SMBus or JTAG interface.
Current-Sense Amplifier Positive Input. Connect CSP to the source side of the
external sense resistor.
Current-Sense Amplifier Negative Input. Connect CSM to the load side of the
external sense resistor.
General-Purpose Input/Output 7 and General-Purpose Input/Output 8.
GPIO_s can be configured to act as a TTL input, a push-pull, open-drain, or
high-impedance output or a pulldown circuit during a fault event or reverse
sequencing.
General-Purpose Input/Output 1–General-Purpose Input/Output 6. GPIO_s
can be configured to act as a TTL input, a push-pull, open-drain, or highimpedance output or a pulldown circuit during a fault event.
Analog Enable Input. All outputs deassert when VEN is below the enable
threshold.
Digital Bypass. All push-pull outputs are referenced to DBP. Bypass DBP with
a 1FF capacitor to GND.
Device Power Supply. Connect VCC to a voltage from 2.8V to 14V. Bypass
VCC with a 10FF capacitor to GND.
Monitor Voltage Input 9–Monitor Voltage Input 12. Set monitor voltage range
through configuration registers. Measured value written to the ADC register
can be read back through the SMBus or JTAG interface.
Exposed Pad. Internally connected to GND. Connect to ground, but do not
use as the main ground connection.
The MAX16070 monitors up to twelve system power supplies and the MAX16071 can monitor up to eight system
power supplies. After boot-up, if EN is high and the software enable bit is set to ‘1,’ monitoring begins based on
the configuration stored in flash. An internal multiplexer
cycles through each MON_ input. At each multiplexer
stop, the 10-bit ADC converts the monitored analog voltage to a digital result and stores the result in a register.
Each time a conversion cycle (50Fs, max) completes,
internal logic circuitry compares the conversion results
to the overvoltage and undervoltage thresholds stored in
memory. When a result violates a programmed threshold,
the conversion can be configured to generate a fault.
GPIO_ can be programmed to assert on combinations
of faults. Additionally, faults can be configured to shut off
the system and trigger the nonvolatile fault logger, which
writes all fault information automatically to the flash and
write-protects the data to prevent accidental erasure.
The MAX16070/MAX16071 contain both SMBus and
JTAG serial interfaces for accessing registers and flash.
Use only one interface at any given time. For more information on how to access the internal memory through
these interfaces, see the SMBus-Compatible Interface
and JTAG Serial Interface sections. The memory map
is divided into three pages with access controlled by
special SMBus and JTAG commands.
The factory-default values at POR (power-on reset) for all
RAM registers are ‘0’s. POR occurs when VCC reaches
the undervoltage-lockout threshold (UVLO) of 2.8V (max).
At POR, the device begins a boot-up sequence. During
the boot-up sequence, all monitored inputs are masked
from initiating faults and flash contents are copied to
the respective register locations. During boot-up, the
MAX16070/MAX16071 are not accessible through the
serial interface. The boot-up sequence takes up to
150Fs, after which the device is ready for normal operation. RESET is asserted low up to the boot-up phase and
remains asserted for its programmed timeout period once
sequencing is completed and all monitored channels
are within their respective thresholds. Up to the boot-up
phase, the GPIO_s are high impedance.
Power
Apply 2.8V to 14V to VCC to power the MAX16070/
MAX16071. Bypass VCC to ground with a 10FF capacitor. Two internal voltage regulators, ABP and DBP,
supply power to the analog and digital circuitry within
the device. For operation at 3.6V or lower, disable the
regulators by connecting ABP and DBP to VCC.
ABP is a 3.0V (typ) voltage regulator that powers the internal analog circuitry. Bypass ABP to GND with a 1FF ceramic capacitor installed as close to the device as possible.
DBP is an internal 3.0V (typ) voltage regulator. DBP powers flash and digital circuitry. All push-pull outputs refer to
DBP. Bypass the DBP output to GND with a 1FF ceramic
capacitor installed as close as possible to the device.
Do not power external circuitry from ABP or DBP.
Enable
To enable monitoring, the voltage at EN must be above
1.4V and the software enable bit in r73h[0] must be set
to ‘1.’ To power down and disable monitoring, either pull
EN below 1.35V or set the Software Enable bit to ‘0.’
See Table 1 for the software enable bit configurations.
Connect EN to ABP if not used.
0 = Early warning is undervoltage
1 = Early warning is overvoltage
Independent watchdog mode enable
1 = Watchdog timer is independent of sequencer
0 = Watchdog timer boots after sequence completes
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
When in the monitoring state, a register bit, ENRESET,
is set to a ‘1’ when EN falls below the undervoltage
threshold. This register bit latches and must be cleared
through software. This bit indicates if RESET asserted
low due to EN going under the threshold. The POR state
of ENRESET is ‘0’. The bit is only set on a falling edge
of the EN comparator output or the software enable bit.
Voltage/Current Monitoring
The MAX16070/MAX16071 feature an internal 10-bit
ADC that monitors the MON_ voltage inputs. An internal
multiplexer cycles through each of the enabled inputs,
taking less than 40Fs for a complete monitoring cycle.
Each acquisition takes approximately 3.2Fs. At each
multiplexer stop, the 10-bit ADC converts the analog
input to a digital result and stores the result in a register.
ADC conversion results are stored in registers r00h to
r1Ah (see Table 6). Use the SMBus or JTAG serial interface to read ADC conversion results.
The MAX16070 provides twelve inputs, MON1 to MON12,
MAX16070/MAX16071
for voltage monitoring. The MAX16071 provides eight
inputs, MON1 to MON8, for voltage monitoring. Each
input voltage range is programmable in registers r43h to
r45h (see Table 5). When MON_ configuration registers
are set to ’11,’ MON_ voltages are not monitored, and
the multiplexer does not stop at these inputs, decreasing
the total cycle time. These inputs cannot be configured
to trigger fault conditions.
The three programmable thresholds for each monitored
voltage include an overvoltage, an undervoltage, and a
secondary warning threshold that can be set in r73h[3]
to be either an undervoltage or overvoltage threshold.
See the Faults section for more information on setting
overvoltage and undervoltage thresholds. All voltage
thresholds are 8 bits wide. The 8 MSBs of the 10-bit ADC
conversion result are compared to these overvoltage
and undervoltage thresholds.
Inputs that are not enabled are not converted by the
ADC; they contain the last value acquired before that
channel was disabled.
The ADC conversion result registers are reset to 00h at
boot-up. These registers are not reset when a reboot
command is executed.
Configure the MAX16070/MAX16071 for differential
mode in r46h (Table 5). The possible differential pairs
are MON1/MON2, MON3/MON4, MON5/MON6, MON7/
MON8, MON9/MON10, MON11/MON12 with the first
input always being at a higher voltage than the second.
Use differential voltage sensing to eliminate voltage offsets or measure supply current. See Figure 3. In differential mode, the odd-numbered MON_ input measures
the absolute voltage with respect to GND while the result
of the even input is the difference between the odd and
even inputs. See Figure 3 for the typical differential measurement circuit.
Once EN is above its threshold and the software-enable
bit is set, a boot-up delay occurs before monitoring
begins. This delay is configured in register 77h[3:0] as
shown in Tables 2 and 3.
Internal Current-Sense Amplifier
The current-sense inputs, CSP/CSM, and a currentsense amplifier facilitate power monitoring (see Figure
4). The voltage on CSP relative to GND is also monitored
by the ADC when the current-sense amplifier is enabled
with r47h[0]. The conversion results are located in registers r19h and r1Ah (see Table 6). There are two selectable voltage ranges for CSP set by r47h[1], see Table
4. Although the voltage can be monitored over SMBus
or JTAG, this voltage has no threshold comparators and
cannot trigger any faults. Regarding the current-sense
amplifier, there are four selectable ranges and the ADC
output for a current-sense conversion is:
X
where X
r18h, V
= (V
ADC
is the 8-bit decimal ADC result in register
ADC
is V
SENSE
CSP
x AV)/1.4V x (28 - 1)
SENSE
- V
and AV is the current-
CSM,
sense voltage gain set by r47h[3:2].
In addition, there are two programmable current-sense
trip thresholds: primary overcurrent and secondary overcurrent. For fast fault detection, the primary overcurrent
threshold is implemented with an analog comparator
connected to the internal OVERC signal. The OVERC
signal can be output on one of the GPIO_s. See the
General-Purpose Inputs/Outputs section for configuring the GPIO_ to output the OVERC signal. The primary
threshold is set by:
ITH = V
where ITH is the current threshold to be set, V
the threshold set by r47h[3:2], and R
CSTH/RSENSE
SENSE
is
CSTH
is the value
of the sense resistor. See Table 4 for a description of
r47h. OVERC depends only on the primary overcurrent
threshold. The secondary overcurrent threshold is implemented through ADC conversions and digital comparison set by r6Ch. The secondary overcurrent threshold
includes programmable time delay options located in
r73h[6:5]. Primary and secondary current-sense faults
are enabled/disabled through r47h[0].