Rainbow Electronics MAX16068 User Manual
19-5040; Rev 0; 10/09
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
General Description
The MAX16068 flash-configurable system manager
monitors and manages up to six system voltages
simultaneously. The MAX16068 integrates an analogto-digital converter (ADC). Device configuration information, including overvoltage and undervoltage limits,
time delay settings is stored in nonvolatile flash memory.
During a fault condition, fault flags and channel voltages can be automatically stored in the nonvolatile flash
memory for later readback.
The internal 1% accurate, 10-bit ADC measures each
input and compares the result to one overvoltage and
one undervoltage limit. A fault signal asserts when a
monitored voltage falls outside the set limits.
The MAX16068 supports a power-supply voltage of up to
14V and can be powered directly from the 12V intermediate bus in many systems.
The MAX16068 includes six programmable generalpurpose inputs/outputs (GPIOs). GPIOs are flash configurable as a fault output, as a watchdog input or output,
or as a manual reset.
The MAX16068 features nonvolatile fault memory for
recording information during system shutdown events.
The fault logger records a failure in the internal flash
and sets a lock bit protecting the stored fault data from
accidental erasure.
An SMBus™ or a JTAG serial interface configures the
MAX16068. The MAX16068 is available in a 28-pin, 5mm
x 5mm, TQFN package and is fully specified over the
-40NC to +85NC extended temperature range.
Features
S Operates from 2.8V to 14V
S 1% Accurate, 10-Bit ADC Monitors 6 Voltage
Inputs
S Analog EN Monitoring Input
S 6 Monitored Inputs with Overvoltage and
Undervoltage Limits
S Nonvolatile Fault Event Logger
S Six General-Purpose Inputs/Outputs Configurable
as:
Dedicated Fault Output
Watchdog Timer Function
Manual Reset
SMBus Alert
Fault Propagation Input/Output
S SMBus and JTAG Interface
S Supports Cascading with MAX16065/MAX16066
S Flash-Configurable Time Delays and Thresholds
S -40NC to +85NC Extended Operating Temperature
Range
Applications
Networking Equipment
Telecom Equipment (Base Stations, Access)
Storage/Raid Systems
Servers
Typical Operating Circuit appears at end of data sheet.
MAX16068
Ordering Information/Selector Guide
PART PIN-PACKAGE VOLTAGE-DETECTOR INPUTS
MAX16068ETI+ 28 TQFN-EP* 6 6
Note: This device is specified over the -40NC to +85NC extended temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
SMBus is a trademark of Intel Corp.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
GENERAL-PURPOSE INPUTS/
OUTPUTS
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
ABSOLUTE MAXIMUM RATINGS
V
to GND ...............……………………………….-0.3V to +15V
CC
MON_, SCL, SDA, A0 to GND ................................-0.3V to +6V
EN, TCK, TMS, TDI to GND ....................................-0.3V to +4V
TDO to GND ............................................-0.3V to (V
RESET, GPIO_
(configured as open-drain) to GND. ....................-0.3V to +6V
RESET, GPIO_ (configured as push-pull)
to GND .................................................-0.3V to (V
DBP, ABP to GND .......................................-0.3V to minimum of
MAX16068
(4V and (VCC + 0.3V))
*As per JEDEC 51 Standard, Multilayer Board (PCB).
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DBP
DBP
+ 0.3V)
+ 0.3V)
ELECTRICAL CHARACTERISTICS
(VCC = 2.8V to 14V, TA = TJ = -40NC to +85NC, unless otherwise specified. Typical values are at V
TA = +25NC.) (Note 2)
Continuous Current (all pins) .......................................... Q20mA
Continuous Power Dissipation (TA = +70NC)
28-Pin TQFN (derate 34.5mW/NC above +70NC) ..... 2759mW*
Thermal Resistance (Note 1)
BJA ................................................................................29NC/W
BJC ........................…………………………….………… 2NC/W
Operating Temperature Range .......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
ABP
= V
= VCC = 3.3V,
DBP
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Voltage Range V
Undervoltage Lockout V
Undervoltage Lockout Hysteresis UVLO
Minimum Flash Operating Voltage V
Supply Current
DBP Regulator Voltage V
ABP Regulator Voltage V
Boot Time t
Flash Writing Time 8-byte word 122 ms
Internal Timing Accuracy (Note 4) -10 +10 %
ADC
Resolution 10 Bits
Gain Error ADC
Offset Error ADC
CC
UVLO
FLASH
I
CC1
CC2
DBP
ABP
BOOT
RESET output asserted low 1.2
2.8 14
Minimum voltage on VCC to ensure the
device is flash configurable
HYS
Minimum voltage on VCC to ensure flash
erase and write operations
No load on any output 2.8 4
No load on any output, during flash writing
cycle
VCC = V
VCC = 5V, C
VCC = 5V, C
V
CC
TA = +25NC
GAIN
TA = -40NC to +85NC
OFF
> V
ABP
UVLO
= V
DBP
= 1FF, no load
DBP
= 1FF, no load
ABP
= 3.6V (Note 3) 5
2.7 V
2.8 3 3.2 V
2.85 3 3.15 V
2.7 V
55 mV
7.7 14
100 200
0.35
0.75
1.5 LSB
V
mAI
Fs
%
2 ______________________________________________________________________________________
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.8V to 14V, TA = TJ = -40NC to +85NC, unless otherwise specified. Typical values are at V
TA = +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Integral Nonlinearity ADC
Differential Nonlinearity ADC
ADC Total Monitoring Cycle Time t
ADC MON_ Ranges ADC
ADC LSB Step Size ADC
ADC Input Leakage Current 1
ENABLE INPUT (EN)
EN Input-Voltage Threshold
EN Input Current I
EN Input-Voltage Range 0 3.6 V
OUTPUTS (RESET, GPIO_)
Output-Voltage Low V
Maximum Output Sink Current
CYCLE
V
TH_EN_R
V
TH_EN_F
EN
OL
INL
DNL
Monitoring all 6 inputs, no MON_ fault
detected
MON_ range set to ‘00’ 5.552
RNG
MON_ range set to ‘10’ 1.388
MON_ range set to ‘00’ 5.42
LSB
MON_ range set to ‘10’ 1.35
EN voltage rising 1.24
EN voltage falling 1.195 1.215 1.235
-0.5 +0.5
I
= 2mA 0.4
SINK
= 10mA, GPIO_ only 0.7
SINK
VCC = 1.2V, I
Total current into RESET, GPIO_,
VCC = 3.3V
= 100FA (RESET only)
SINK
= V
ABP
24 30
18 mA
= VCC = 3.3V,
DBP
1 LSB
1 LSB
0.3
Fs
VMON_ range set to ‘01’ 2.776
mVMON_ range set to ‘01’ 2.71
FA
V
FA
VI
MAX16068
Output-Voltage High (Push-Pull) V
Output Leakage Current
(Open-Drain)
INPUTS (A0, GPIO_)
Input Logic-Low V
Input Logic-High V
WDI Pulse Width t
MR Pulse Width
SMBus INTERFACE
Logic-Input Low Voltage V
Logic-Input High Voltage V
Input Leakage Current VCC shorted to GND, V
Output Sink Current V
Input Capacitance C
_______________________________________________________________________________________ 3
OH
I
OUT_LKG
WDI
t
MR
OL
I
SOURCE
IL
IH
Input voltage falling 0.8 V
IL
Input voltage rising 2.0 V
IH
I
SINK
IN
=100FA
= 3mA 0.4 V
2.4 V
20 V
100 ns
2
= 0 or 6V -1 +1
MON_
1
0.8 V
5 pF
FA
Fs
FA
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.8V to 14V, TA = TJ = -40NC to +85NC, unless otherwise specified. Typical values are at V
TA = +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SMBus TIMING
Serial Clock Frequency f
Bus Free Time Between STOP
and START Condition
MAX16068
START Condition Setup Time t
START Condition Hold Time t
STOP Condition Setup Time t
Clock Low Period t
Clock High Period t
Data Setup Time t
Output Fall Time t
Data Hold Time t
Pulse Width of Spike Suppressed t
SMBus Timeout t
JTAG INTERFACE
TDI, TMS, TCK Logic-Low Input
Voltage
TDI, TMS, TCK Logic-High Input
Voltage
TDO Logic-Output Low Voltage V
TDO Logic-Output High Voltage V
TDI, TMS Pullup Resistors R
I/O Capacitance C
TCK Clock Period t
TCK High/Low Time t
TCK to TMS, TDI Setup Time t
TCK to TMS, TDI Hold Time t
TCK to TDO Delay t
TCK to TDO High-Z Delay t
Note 2: Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at TA =
+25NC and TA = +85NC. Specifications at TA = -40NC are guaranteed by design.
Note 3: For VCC of 3.6V or lower, connect VCC, DBP, and ABP together. For higher supply applications, connect only VCC to the
supply rail.
Note 4: Applies to RESET (except for a reset timeout period of 25Fs), fault, autoretry, sequence delays, and watchdog timeout.
SCL
t
BUF
SU:STA
HD:STA
SU:STO
LOW
HIGH
SU:DAT
OF
HD:DAT
SP
TIMEOUT
V
V
OL_TDOISINK
OH_TDO
JPU
2, t3
10pF P C
From 50% SCL falling to SDA
change
SMBCLK time low for reset 22 35 ms
Input voltage falling 0.8 V
IL
Input voltage rising 2.0 V
IH
I
SOURCE
Pullup to DBP 30 50 65
I/O
1
4
5
6
7
1.3
0.6
0.6
0.6
1.3
0.6
100 ns
P 400pF
BUS
Receive 0.15
Transmit 0.3 0.9
= 3mA 0.4 V
= 200FA
2.4 V
50 500 ns
15 ns
15 ns
= V
ABP
250 ns
5 pF
= VCC = 3.3V,
DBP
400 kHz
250 ns
1000 ns
500 ns
500 ns
Fs
Fs
Fs
Fs
Fs
Fs
Fs
kI
4 ______________________________________________________________________________________
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
SDA
t
STOP
BUF
START
CONDITION
t
SU:DAT
t
LOW
SCL
t
HIGH
t
HD:STA
t
R
START
CONDITION
Figure 1. SMBus Timing Diagram
t
t
HD:DAT
t
F
SU:STA
REPEATED START
CONDITION
t
HD:STA
t
SU:STO
CONDITION
MAX16068
TCK
TDI, TMS
t
6
t
7
TDO
Figure 2. JTAG Timing Diagram
t
1
t
2
t
4
t
5
t
3
_______________________________________________________________________________________ 5
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
Typical Operating Characteristics
(Typical values are at VCC = 3.3V, TA = +25NC.)
4.0
3.5
MAX16068
3.0
2.5
(mA)
2.0
CC
I
1.5
1.0
0.5
0
0 14
1.055
1.040
1.025
1.010
0.995
0.980
NORMALIZED EN THRESHOLD
0.965
0.950
-40
VCC SUPPLY CURRENT
vs. V
SUPPLY VOLTAGE
CC
ABP AND DBP CONNECTED
TO V
CC
TA = -40°C
ABP AND DBP
REGULATORS ACTIVE
VCC (V)
NORMALIZED EN THRESHOLD
vs. TEMPERATURE
TEMPERATURE (°C)
TA = +85°C
TA = +25°C
12102 4 6 8
806040200-20
MAX16068 toc01
MAX16068 toc03
NORMALIZED MON_THRESHOLD
vs. TEMPERATURE
1.055
1.040
1.025
1.010
0.995
0.980
NORMALIZED MON_ THRESHOLD
0.965
0.950
-40
TEMPERATURE (°C)
5.6V RANGE
HALF-SCALE
PUV THRESHOLD
TRANSIENT DURATION
vs. THRESHOLD OVERDRIVE (EN)
35
30
25
20
15
10
TRANSIENT DURATION (µs)
5
0
1 100
10
EN OVERDRIVE (mV)
MAX16068 toc02
806040200-20
MAX16068 toc04
NORMALIZED TIMING ACCURACY
vs. TEMPERATURE
1.055
1.040
1.025
1.010
0.995
0.980
NORMALIZED SLOT DELAY
0.965
0.950
-40
TEMPERATURE (°C)
806040200-20
MAX16068 toc05
90
80
70
60
50
40
30
TRANSIENT DURATION (us)
20
10
0
TRANSIENT DURATION
vs. MON_ DEGLITCH
2
DEGLITCH VALUE
1684
6 ______________________________________________________________________________________
MAX16068 toc06
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
Typical Operating Characteristics (continued)
(Typical values are at VCC = 3.3V, TA = +25NC.)
MAX16068
MR TO RESET PROPAGATION DELAY
vs. TEMPERATURE
1100
1000
900
800
700
600
DELAY (ns)
500
400
300
200
100
MAX
MIN
TEMPERATURE (°C)
OUTPUT-VOLTAGE HIGH vs.
SOURCE CURRENT (PUSH-PULL OUTPUT)
3.4
3.3
3.2
3.1
3.0
(V)
2.9
OUT
V
2.8
2.7
2.6
2.5
2.4
0 1200
RESET
I
SOURCE
GPIO_
(µA)
DIFFERENTIAL NONLINEARITY vs. CODE
1.0
0.8
0.6
0.4
0.2
0
DNL (LSB)
-0.2
-0.4
-0.6
-0.8
-1.0
0 1024
CODE (LSB)
OUTPUT VOLTAGE vs. SINK CURRENT
(OUT = LOW)
0.40
806040200-20-40
MAX16068 toc07
0.35
0.30
0.25
(V)
0.20
OUT
V
0.15
0.10
0.05
0
0 20
I
SINK
RESET, GPIO_
(mA)
15105
MAX16068 toc08
INTEGRAL NONLINEARITY vs. CODE
1.0
0.8
MAX16068 toc09
1000800600400200
0.6
0.4
0.2
0
INL (LSB)
-0.2
-0.4
-0.6
-0.8
-1.0
0 1024
CODE (LSB)
MAX16068 toc10
896768512 640256 384128
RESET OUTPUT CURRENT
vs. V
SUPPLY VOLTAGE
25
MAX16068 toc11
896768512 640256 384128
20
15
10
OUTPUT CURRENT (mA)
5
0
0 14
CC
ABP AND DBP CONNECTED TO V
ABP AND DBP
REGULATORS ACTIVE
V
RESET
VCC (V)
CC
MAX16068 toc12
= 0.3V
12108642
_______________________________________________________________________________________ 7
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
Pin Configuration
MAX16068
TOP VIEW
MON3
MON4
MON5
MON6
RESET
GPIO1
GPIO2
MON2
MON1
2021 19 17 16 15
22
23
24
25
26
27
28
1 2 4 5 6 7
+
GPIO3
GPIO4
MAX16068
3
GPIO5
GND
18
ABP
GPIO6
CC
V
GND
EP*
DBP
AO
EN
SCL
N.C.
14
N.C.
13
12
TMS
11
TCK
10
TDI
9
TDO
8
SDA
THIN QFN
(5mm x 5mm)
*CONNECT EXPOSED PAD TO GND.
Pin Description
PIN NAME FUNCTION
GPIO3–
1–4, 27, 28
GPIO6,
GPIO1,
General-Purpose Inputs/Outputs. Each GPIO_ can be configured to act as an input, a push-pull
output, an open-drain output, or a special function.
GPIO2
5, 19 GND Ground. Connect all GNDs together.
6 A0 Four-State SMBus Address. Address is sampled upon POR.
7 SCL SMBus Serial-Clock Input
8 SDA SMBus Serial-Data Open-Drain Input/Output
9 TDO JTAG Test Data Output
10 TDI JTAG Test Data Input
11 TCK JTAG Test Clock
12 TMS JTAG Test Mode Select
13, 14 N.C. No Connection. Not internally connected.
15 EN Analog Enable Input. All outputs deassert when VEN is below the enable threshold.
8 ______________________________________________________________________________________
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
Pin Description (continued)
PIN NAME FUNCTION
16 DBP
17 V
CC
18 ABP
20–25
MON1–
MON6
26 RESET Configurable Reset Output
— EP
Functional Diagram
EN
MON1
Digital Bypass. All push-pull outputs are referenced to DBP. Bypass DBP with a 1FF capacitor to
GND.
Power-Supply Input. Bypass VCC to GND with a 10FF ceramic capacitor.
Analog Bypass. Bypass ABP to GND with a 1FF ceramic capacitor.
Monitor Voltage Inputs. Set the monitor voltage range through the configuration registers.
Measured values are written to the ADC registers and can be read back through the SMBus or
JTAG interface.
Exposed Pad. Internally connected to GND. Connect to ground, but do not use EP as the main
ground connection.
ABP
V
V
REF REG
TH_EN
DBP
CC
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
DECODE
LOGIC
WATCHDOG
TIMER
ALERT
EXTFAULT
FAULT
MR
WDI
WDO
GPIO
CONTROL
MAX16068
MON2
MON3
MON4
MON5
MON6
VOLTAGE
AND
SCALING
MUX
10-BIT ADC
SMBus
INTERFACE
AO SCL SDA
(SAR)
MAX16068
ADC
REGISTERS
RAM
REGISTERS
FLASH
REGISTERS
DIGITAL
COMPARATORS
INTERFACE
TDI TCK TMSGND GND
TDO
JTAG
RESET
OUTPUT
LOGIC
RESET
_______________________________________________________________________________________ 9
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
Detailed Description
The MAX16068 monitors up to six system power supplies. The monitoring phase begins after boot-up if EN is
high and the software enable bit is set to ‘1’. An internal
multiplexer cycles through each MON_ input. At each
multiplexer stop, the 10-bit ADC converts the monitored
analog voltage to a digital result and stores the result in
a register. Each time a conversion cycle (5Fs, max) completes, internal logic circuitry compares the conversion
MAX16068
results to the overvoltage and undervoltage thresholds
stored in memory. When a result violates a programmed
threshold, the conversion can be configured to generate
a fault. GPIO_ can be programmed to assert on combinations of faults. Additionally, faults can be configured to
trigger the nonvolatile fault logger, which writes all fault
information automatically to the flash and write-protects
the data to prevent accidental erasure.
The MAX16068 contains both SMBus and JTAG serial
interfaces for accessing registers and flash. Use only
one interface at any given time. For more information
on how to access the internal memory through these
interfaces, see the SMBus-Compatible Serial Interface
and JTAG Serial Interface sections. The memory map
is divided into three pages with access controlled by
special SMBus and JTAG commands.
The factory-default values at POR (power-on reset) for all
RAM registers are ‘0’s. POR occurs when VCC reaches
the undervoltage-lockout threshold (UVLO) of 2.7V
(max). At POR, the device begins a boot-up sequence.
During the boot-up sequence, all monitored inputs are
masked from initiating faults and flash contents are
copied to the respective register locations. During bootup, the MAX16068 is not accessible through the serial
interface. The boot-up sequence takes up to 150Fs, after
which the device is ready for normal operation. RESET
is asserted low up to the boot-up phase after which it
assumes its programmed active state. RESET remains
active for its programmed timeout period once all monitored channels are within their respective thresholds. Up
to the boot-up phase, the GPIO_s are high impedance.
Power
Apply 2.8V to 14V to VCC to power the MAX16068.
Bypass VCC to ground with a 10FF capacitor. Two internal voltage regulators, ABP and DBP, supply power to
the analog and digital circuitry within the device. For
operation at 3.6V or lower, disable the regulators by connecting ABP and DBP to VCC.
ABP is a 3.0V (typ) voltage regulator that powers the internal analog circuitry. Bypass ABP to GND with a 1FF ceramic capacitor installed as close as possible to the device.
DBP is an internal 3.0V (typ) voltage regulator. DBP
powers flash and digital circuitry. All push-pull outputs
refer to DBP. DBP supplies the input voltage to the internal charge pump when the programmable outputs are
configured as charge-pump outputs. Bypass the DBP
output to GND with a 1FF ceramic capacitor installed as
close as possible to the device.
Do not power external circuitry from ABP or DBP.
Enable Input (EN)
To enable monitoring, the voltage at EN must be above
1.24V (typ) and the software enable bit in r73h[0] must
be set to ‘1.’ To disable monitoring, either pull EN
below 1.215V (typ) or set the software enable bit to ‘0.’
See Table 1 for the software enable bit configurations.
Connect EN to ABP if not used.
Table 1. Software Enable Configurations
REGISTER
ADDRESS
73h 273h
10 _____________________________________________________________________________________
FLASH
ADDRESS
BIT RANGE DESCRIPTION
Software Enable
[0]
[1] Reserved
[2] 1 = Margin mode enabled
[3] Reserved
[4]
1 = Sequencing enabled
0 = Power-down
Independent watchdog mode enable
1 = Watchdog timer is independent of EN input
0 = Watchdog timer boots after EN goes high and the boot-up delay completes
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
When in the monitoring state, and when EN falls below
the undervoltage threshold, a register bit, ENRESET
(r20h[2]), is set to a ‘1.’ This register bit latches and must
be cleared through software. This bit indicates if RESET
asserted low due to EN going under the threshold. The
POR state of ENRESET is ‘0.’ The bit is only set on a falling edge of the EN comparator output or the software
enable bit. If operating in latch-on fault mode, toggle
EN or toggle the software enable bit to clear the latch
condition and restart the device once the fault condition
has been removed.
Set r73h[2] to ‘1’ to enable monitoring functionality.
Faults are not recorded when the device is in margining
mode. Set r73h[2] to ‘0’ for normal functionality.
Voltage Monitoring
The MAX16068 features an internal 10-bit ADC that monitors the MON_ voltage inputs. An internal multiplexer
cycles through each of the enabled inputs, taking less
than 24Fs for a complete monitoring cycle. Each acquisition takes approximately 4Fs. At each multiplexer stop,
the 10-bit ADC converts the analog input to a digital
result and stores the result in a register. ADC conversion
results are stored in registers r00h–r0Bh (see Table 2).
Use the SMBus or JTAG serial interface to read ADC
conversion results.
The MAX16068 provides six inputs, MON1–MON6, for
voltage monitoring. Each input-voltage range is programmable in registers r43h–r44h (see Table 3). When
MON_ configuration registers are set to ’11,’ MON_ voltages are not monitored and the multiplexer does not stop
at these inputs, decreasing the total cycle time. These
inputs cannot be configured to trigger fault conditions.
The two programmable thresholds for each monitored
voltage include an overvoltage and an undervoltage
threshold. See the Faults section for more information
on setting overvoltage and undervoltage thresholds. All
voltage thresholds are 8 bits wide. The 8 MSBs of the
10-bit ADC conversion result are compared to these
overvoltage and undervoltage thresholds.
For any undervoltage or overvoltage condition to be
monitored and any faults detected, the MON_ input must
be assigned to monitoring mode. Inputs that are not
enabled are not converted by the ADC; they contain the
last value acquired before that channel was disabled.
The ADC conversion result registers are reset to 00h at
boot-up. These registers are not reset when a reboot
command is executed.
To temporarily disable voltage monitoring during voltage margining conditions, set r73h[2] to ‘1’ to enable
margining mode functionality. Faults (except for faults
triggered by EXTFAULT being pulled low externally) are
not recorded when the device is in margining mode, but
the ADC continues to run and conversion results continue to be available. Set r73h[2] back to ‘0’ for normal
functionality.
MAX16068
Table 2. ADC Conversion Results (Read Only)
REGISTER ADDRESS BIT RANGE DESCRIPTION
00h [7:0] MON1 result (MSB)
01h [7:6] MON1 result (LSB)
02h [7:0] MON2 result (MSB)
03h [7:6] MON2 result (LSB)
04h [7:0] MON3 result (MSB)
05h [7:6] MON3 result (LSB)
06h [7:0] MON4 result (MSB)
07h [7:6] MON4 result (LSB)
08h [7:0] MON5 result (MSB)
09h [7:6] MON5 result (LSB)
0Ah [7:0] MON6 result (MSB)
0Bh [7:6] MON6 result (LSB)
______________________________________________________________________________________ 11
6-Channel, Flash-Configurable System Manager
with Nonvolatile Fault Registers
Table 3. ADC Configuration Registers
REGISTER ADDRESS FLASH ADDRESS BIT RANGE DESCRIPTION
MON1 Full-Scale Range
00 = 5.6V
[1:0]
MAX16068
[3:2]
43h 243h
[5:4]
[7:6]
[1:0]
44h 244h
[3:2]
[7:4] Not used
01 = 2.8V
10 = 1.4V
11 = channel not converted
MON2 Full-Scale Range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = channel not converted
MON3 Full-Scale Range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = channel not converted
MON4 Full-Scale Range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = channel not converted
MON5 Full-Scale Range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = channel not converted
MON6 Full-Scale Range
00 = 5.6V
01 = 2.8V
10 = 1.4V
11 = channel not converted
t
Boot-Up Delay
Once EN is above its threshold and the software enable
bit is set, a boot-up delay occurs before monitoring
where t
4 MSBs and b is the decimal value of the 4 LSBs.
= (5 x 10-6) x 2a x (16 + b) + 480µs
BOOT
is in seconds, a is the decimal value of the
BOOT
begins. This delay is configured in register 77h as shown
in Table 4, and it is stored as an 8-bit value calculated
as follows:
Table 4. Boot-Up Delay
REGISTER
ADDRESS
77h 277h [7:0] Boot-up delay
12 _____________________________________________________________________________________
FLASH
ADDRESS
BIT
RANGE
DESCRIPTION
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