Rainbow Electronics MAX16068 User Manual

19-5040; Rev 0; 10/09

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

General Description

The MAX16068 flash-configurable system manager monitors and manages up to six system voltages simultaneously. The MAX16068 integrates an analogto-digital converter (ADC). Device configuration information, including overvoltage and undervoltage limits, time delay settings is stored in nonvolatile flash memory. During a fault condition, fault flags and channel voltages can be automatically stored in the nonvolatile flash memory for later readback.

The internal 1% accurate, 10-bit ADC measures each input and compares the result to one overvoltage and one undervoltage limit. A fault signal asserts when a monitored voltage falls outside the set limits.

The MAX16068 supports a power-supply voltage of up to 14V and can be powered directly from the 12V intermediate bus in many systems.

The MAX16068 includes six programmable generalpurpose inputs/outputs (GPIOs). GPIOs are flash configurable as a fault output, as a watchdog input or output, or as a manual reset.

The MAX16068 features nonvolatile fault memory for recording information during system shutdown events. The fault logger records a failure in the internal flash and sets a lock bit protecting the stored fault data from accidental erasure.

An SMBus™ or a JTAG serial interface configures the MAX16068. The MAX16068 is available in a 28-pin, 5mm x 5mm, TQFN package and is fully specified over the

-40NC to +85NC extended temperature range.

Features

S Operates from 2.8V to 14V

S 1% Accurate, 10-Bit ADC Monitors 6 Voltage

Inputs

S Analog EN Monitoring Input

S 6 Monitored Inputs with Overvoltage and

Undervoltage Limits

S Nonvolatile Fault Event Logger

S Six General-Purpose Inputs/Outputs Configurable

as:

Dedicated Fault Output Watchdog Timer Function Manual Reset SMBus Alert Fault Propagation Input/Output

S SMBus and JTAG Interface

S Supports Cascading with MAX16065/MAX16066

S Flash-Configurable Time Delays and Thresholds

S -40NC to +85NC Extended Operating Temperature

Range

Applications

Networking Equipment

Telecom Equipment (Base Stations, Access)

Storage/Raid Systems

Servers

Typical Operating Circuit appears at end of data sheet.

MAX16068

Ordering Information/Selector Guide

PART PIN-PACKAGE VOLTAGE-DETECTOR INPUTS

MAX16068ETI+ 28 TQFN-EP* 6 6

Note: This device is specified over the -40NC to +85NC extended temperature range.

+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.

SMBus is a trademark of Intel Corp.

_______________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

GENERAL-PURPOSE INPUTS/

OUTPUTS

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

ABSOLUTE MAXIMUM RATINGS

to GND ...............……………………………….-0.3V to +15V

MON_, SCL, SDA, A0 to GND ................................-0.3V to +6V

EN, TCK, TMS, TDI to GND ....................................-0.3V to +4V

TDO to GND ............................................-0.3V to (V

RESET, GPIO_

(configured as open-drain) to GND. ....................-0.3V to +6V

RESET, GPIO_ (configured as push-pull)

to GND .................................................-0.3V to (V

DBP, ABP to GND .......................................-0.3V to minimum of

MAX16068

(4V and (VCC + 0.3V))

*As per JEDEC 51 Standard, Multilayer Board (PCB).

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DBP

+ 0.3V)

ELECTRICAL CHARACTERISTICS

(VCC = 2.8V to 14V, TA = TJ = -40NC to +85NC, unless otherwise specified. Typical values are at V TA = +25NC.) (Note 2)

Continuous Current (all pins) .......................................... Q20mA

Continuous Power Dissipation (TA = +70NC)

28-Pin TQFN (derate 34.5mW/NC above +70NC) ..... 2759mW*

Thermal Resistance (Note 1)

BJA ................................................................................29NC/W

BJC ........................…………………………….………… 2NC/W

Operating Temperature Range .......................... -40NC to +85NC

Junction Temperature .....................................................+150NC

Storage Temperature Range ............................ -65NC to +150NC

Lead Temperature (soldering, 10s) ................................+300NC

ABP

= V

= VCC = 3.3V,

DBP

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Operating Voltage Range V

Undervoltage Lockout V

Undervoltage Lockout Hysteresis UVLO

Minimum Flash Operating Voltage V

Supply Current

DBP Regulator Voltage V ABP Regulator Voltage V Boot Time t Flash Writing Time 8-byte word 122 ms Internal Timing Accuracy (Note 4) -10 +10 %

ADC

Resolution 10 Bits

Gain Error ADC

Offset Error ADC

UVLO

FLASH

CC1

CC2

DBP

ABP

BOOT

RESET output asserted low 1.2

2.8 14

Minimum voltage on VCC to ensure the device is flash configurable

HYS

Minimum voltage on VCC to ensure flash erase and write operations

No load on any output 2.8 4

No load on any output, during flash writing cycle

VCC = V VCC = 5V, C VCC = 5V, C V

TA = +25NC

GAIN

TA = -40NC to +85NC

OFF

> V

ABP

UVLO

= V

DBP

= 1FF, no load

DBP

= 1FF, no load

ABP

= 3.6V (Note 3) 5

2.7 V

2.8 3 3.2 V

2.85 3 3.15 V

2.7 V

55 mV

7.7 14

100 200

0.35

0.75

1.5 LSB

mAI

2 ______________________________________________________________________________________

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

ELECTRICAL CHARACTERISTICS (continued)

(VCC = 2.8V to 14V, TA = TJ = -40NC to +85NC, unless otherwise specified. Typical values are at V TA = +25NC.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Integral Nonlinearity ADC Differential Nonlinearity ADC

ADC Total Monitoring Cycle Time t

ADC MON_ Ranges ADC

ADC LSB Step Size ADC

ADC Input Leakage Current 1

ENABLE INPUT (EN)

EN Input-Voltage Threshold

EN Input Current I EN Input-Voltage Range 0 3.6 V

OUTPUTS (RESET, GPIO_)

Output-Voltage Low V

Maximum Output Sink Current

CYCLE

TH_EN_R

TH_EN_F

INL

DNL

Monitoring all 6 inputs, no MON_ fault detected

MON_ range set to ‘00’ 5.552

RNG

MON_ range set to ‘10’ 1.388 MON_ range set to ‘00’ 5.42

LSB

MON_ range set to ‘10’ 1.35

EN voltage rising 1.24 EN voltage falling 1.195 1.215 1.235

-0.5 +0.5

= 2mA 0.4

SINK

= 10mA, GPIO_ only 0.7

SINK

VCC = 1.2V, I

Total current into RESET, GPIO_, VCC = 3.3V

= 100FA (RESET only)

SINK

= V

ABP

24 30

18 mA

= VCC = 3.3V,

DBP

1 LSB 1 LSB

0.3

VMON_ range set to ‘01’ 2.776

mVMON_ range set to ‘01’ 2.71

MAX16068

Output-Voltage High (Push-Pull) V

Output Leakage Current (Open-Drain)

INPUTS (A0, GPIO_)

Input Logic-Low V Input Logic-High V WDI Pulse Width t MR Pulse Width

SMBus INTERFACE

Logic-Input Low Voltage V Logic-Input High Voltage V Input Leakage Current VCC shorted to GND, V Output Sink Current V Input Capacitance C

_______________________________________________________________________________________ 3

OUT_LKG

WDI

SOURCE

Input voltage falling 0.8 V

Input voltage rising 2.0 V

SINK

=100FA

= 3mA 0.4 V

2.4 V

20 V

100 ns

= 0 or 6V -1 +1

MON_

0.8 V

5 pF

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

ELECTRICAL CHARACTERISTICS (continued)

(VCC = 2.8V to 14V, TA = TJ = -40NC to +85NC, unless otherwise specified. Typical values are at V TA = +25NC.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SMBus TIMING

Serial Clock Frequency f

Bus Free Time Between STOP and START Condition

MAX16068

START Condition Setup Time t START Condition Hold Time t STOP Condition Setup Time t Clock Low Period t Clock High Period t Data Setup Time t Output Fall Time t

Data Hold Time t

Pulse Width of Spike Suppressed t SMBus Timeout t

JTAG INTERFACE

TDI, TMS, TCK Logic-Low Input Voltage

TDI, TMS, TCK Logic-High Input Voltage

TDO Logic-Output Low Voltage V TDO Logic-Output High Voltage V TDI, TMS Pullup Resistors R I/O Capacitance C TCK Clock Period t TCK High/Low Time t TCK to TMS, TDI Setup Time t TCK to TMS, TDI Hold Time t TCK to TDO Delay t TCK to TDO High-Z Delay t

Note 2: Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at TA =

+25NC and TA = +85NC. Specifications at TA = -40NC are guaranteed by design.

Note 3: For VCC of 3.6V or lower, connect VCC, DBP, and ABP together. For higher supply applications, connect only VCC to the

supply rail.

Note 4: Applies to RESET (except for a reset timeout period of 25Fs), fault, autoretry, sequence delays, and watchdog timeout.

SCL

BUF

SU:STA

HD:STA

SU:STO

LOW

HIGH

SU:DAT

HD:DAT

TIMEOUT

OL_TDOISINK

OH_TDO

JPU

2, t3

10pF P C

From 50% SCL falling to SDA change

SMBCLK time low for reset 22 35 ms

Input voltage falling 0.8 V

Input voltage rising 2.0 V

SOURCE

Pullup to DBP 30 50 65

I/O

1.3

0.6

1.3

0.6

100 ns

P 400pF

BUS

Receive 0.15 Transmit 0.3 0.9

= 3mA 0.4 V

= 200FA

2.4 V

50 500 ns 15 ns 15 ns

= V

ABP

250 ns

5 pF

= VCC = 3.3V,

DBP

400 kHz

250 ns

1000 ns

500 ns 500 ns

Fs Fs Fs Fs Fs

4 ______________________________________________________________________________________

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

SDA

STOP

BUF

START

CONDITION

SU:DAT

LOW

SCL

HIGH

HD:STA

START

CONDITION

Figure 1. SMBus Timing Diagram

HD:DAT

SU:STA

REPEATED START

CONDITION

HD:STA

SU:STO

CONDITION

MAX16068

TCK

TDI, TMS

TDO

Figure 2. JTAG Timing Diagram

_______________________________________________________________________________________ 5

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

Typical Operating Characteristics

(Typical values are at VCC = 3.3V, TA = +25NC.)

4.0

3.5

MAX16068

3.0

2.5

(mA)

2.0

1.5

1.0

0.5

0 14

1.055

1.040

1.025

1.010

0.995

0.980

NORMALIZED EN THRESHOLD

0.965

0.950

-40

VCC SUPPLY CURRENT

vs. V

SUPPLY VOLTAGE

ABP AND DBP CONNECTED TO V

TA = -40°C

ABP AND DBP REGULATORS ACTIVE

VCC (V)

NORMALIZED EN THRESHOLD

vs. TEMPERATURE

TEMPERATURE (°C)

TA = +85°C

TA = +25°C

12102 4 6 8

806040200-20

MAX16068 toc01

MAX16068 toc03

NORMALIZED MON_THRESHOLD

vs. TEMPERATURE

1.055

1.040

1.025

1.010

0.995

0.980

NORMALIZED MON_ THRESHOLD

0.965

0.950

-40 TEMPERATURE (°C)

5.6V RANGE HALF-SCALE PUV THRESHOLD

TRANSIENT DURATION

vs. THRESHOLD OVERDRIVE (EN)

TRANSIENT DURATION (µs)

1 100

EN OVERDRIVE (mV)

MAX16068 toc02

806040200-20

MAX16068 toc04

NORMALIZED TIMING ACCURACY

vs. TEMPERATURE

1.055

1.040

1.025

1.010

0.995

0.980

NORMALIZED SLOT DELAY

0.965

0.950

-40 TEMPERATURE (°C)

806040200-20

MAX16068 toc05

TRANSIENT DURATION (us)

TRANSIENT DURATION

vs. MON_ DEGLITCH

DEGLITCH VALUE

1684

6 ______________________________________________________________________________________

MAX16068 toc06

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

Typical Operating Characteristics (continued)

(Typical values are at VCC = 3.3V, TA = +25NC.)

MAX16068

MR TO RESET PROPAGATION DELAY

vs. TEMPERATURE

1100

1000

900

800

700

600

DELAY (ns)

500

400

300

200

100

MAX

MIN

TEMPERATURE (°C)

OUTPUT-VOLTAGE HIGH vs.

SOURCE CURRENT (PUSH-PULL OUTPUT)

3.4

3.3

3.2

3.1

3.0

(V)

2.9

OUT

2.8

2.7

2.6

2.5

2.4 0 1200

RESET

SOURCE

GPIO_

(µA)

DIFFERENTIAL NONLINEARITY vs. CODE

1.0

0.8

0.6

0.4

0.2

DNL (LSB)

-0.2

-0.4

-0.6

-0.8

-1.0 0 1024

CODE (LSB)

OUTPUT VOLTAGE vs. SINK CURRENT

(OUT = LOW)

0.40

806040200-20-40

MAX16068 toc07

0.35

0.30

0.25

(V)

0.20

OUT

0.15

0.10

0.05

0 20

SINK

RESET, GPIO_

(mA)

15105

MAX16068 toc08

INTEGRAL NONLINEARITY vs. CODE

1.0

0.8

MAX16068 toc09

1000800600400200

0.6

0.4

0.2

INL (LSB)

-0.2

-0.4

-0.6

-0.8

-1.0 0 1024

CODE (LSB)

MAX16068 toc10

896768512 640256 384128

RESET OUTPUT CURRENT

vs. V

SUPPLY VOLTAGE

MAX16068 toc11

896768512 640256 384128

OUTPUT CURRENT (mA)

0 14

ABP AND DBP CONNECTED TO V

ABP AND DBP REGULATORS ACTIVE

RESET

VCC (V)

MAX16068 toc12

= 0.3V

12108642

_______________________________________________________________________________________ 7

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

Pin Configuration

MAX16068

TOP VIEW

MON3

MON4

MON5

MON6

RESET

GPIO1

GPIO2

MON2

MON1

2021 19 17 16 15

1 2 4 5 6 7

GPIO3

GPIO4

MAX16068

GPIO5

GND

ABP

GPIO6

GND

EP*

DBP

SCL

N.C.

TMS

TCK

TDI

TDO

SDA

THIN QFN

(5mm x 5mm)

*CONNECT EXPOSED PAD TO GND.

Pin Description

PIN NAME FUNCTION

GPIO3–

1–4, 27, 28

GPIO6, GPIO1,

General-Purpose Inputs/Outputs. Each GPIO_ can be configured to act as an input, a push-pull output, an open-drain output, or a special function.

GPIO2

5, 19 GND Ground. Connect all GNDs together.

6 A0 Four-State SMBus Address. Address is sampled upon POR. 7 SCL SMBus Serial-Clock Input 8 SDA SMBus Serial-Data Open-Drain Input/Output

9 TDO JTAG Test Data Output 10 TDI JTAG Test Data Input 11 TCK JTAG Test Clock 12 TMS JTAG Test Mode Select

13, 14 N.C. No Connection. Not internally connected.

15 EN Analog Enable Input. All outputs deassert when VEN is below the enable threshold.

8 ______________________________________________________________________________________

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

Pin Description (continued)

PIN NAME FUNCTION

16 DBP

17 V

18 ABP

20–25

MON1–

MON6

26 RESET Configurable Reset Output

— EP

Functional Diagram

MON1

Digital Bypass. All push-pull outputs are referenced to DBP. Bypass DBP with a 1FF capacitor to GND.

Power-Supply Input. Bypass VCC to GND with a 10FF ceramic capacitor. Analog Bypass. Bypass ABP to GND with a 1FF ceramic capacitor.

Monitor Voltage Inputs. Set the monitor voltage range through the configuration registers. Measured values are written to the ADC registers and can be read back through the SMBus or JTAG interface.

Exposed Pad. Internally connected to GND. Connect to ground, but do not use EP as the main ground connection.

ABP

REF REG

TH_EN

DBP

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

DECODE

LOGIC

WATCHDOG

TIMER

ALERT

EXTFAULT

FAULT

WDI

WDO

GPIO

CONTROL

MAX16068

MON2

MON3

MON4

MON5

MON6

VOLTAGE

AND

SCALING

MUX

10-BIT ADC

SMBus

INTERFACE

AO SCL SDA

(SAR)

MAX16068

ADC

REGISTERS

RAM

REGISTERS

FLASH

REGISTERS

DIGITAL

COMPARATORS

INTERFACE

TDI TCK TMSGND GND

TDO

JTAG

RESET

OUTPUT

LOGIC

RESET

_______________________________________________________________________________________ 9

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

Detailed Description

The MAX16068 monitors up to six system power supplies. The monitoring phase begins after boot-up if EN is high and the software enable bit is set to ‘1’. An internal multiplexer cycles through each MON_ input. At each multiplexer stop, the 10-bit ADC converts the monitored analog voltage to a digital result and stores the result in a register. Each time a conversion cycle (5Fs, max) completes, internal logic circuitry compares the conversion

MAX16068

results to the overvoltage and undervoltage thresholds stored in memory. When a result violates a programmed threshold, the conversion can be configured to generate a fault. GPIO_ can be programmed to assert on combinations of faults. Additionally, faults can be configured to trigger the nonvolatile fault logger, which writes all fault information automatically to the flash and write-protects the data to prevent accidental erasure.

The MAX16068 contains both SMBus and JTAG serial interfaces for accessing registers and flash. Use only one interface at any given time. For more information on how to access the internal memory through these interfaces, see the SMBus-Compatible Serial Interface and JTAG Serial Interface sections. The memory map is divided into three pages with access controlled by special SMBus and JTAG commands.

The factory-default values at POR (power-on reset) for all RAM registers are ‘0’s. POR occurs when VCC reaches the undervoltage-lockout threshold (UVLO) of 2.7V (max). At POR, the device begins a boot-up sequence. During the boot-up sequence, all monitored inputs are masked from initiating faults and flash contents are copied to the respective register locations. During bootup, the MAX16068 is not accessible through the serial

interface. The boot-up sequence takes up to 150Fs, after which the device is ready for normal operation. RESET is asserted low up to the boot-up phase after which it assumes its programmed active state. RESET remains active for its programmed timeout period once all monitored channels are within their respective thresholds. Up to the boot-up phase, the GPIO_s are high impedance.

Power

Apply 2.8V to 14V to VCC to power the MAX16068. Bypass VCC to ground with a 10FF capacitor. Two internal voltage regulators, ABP and DBP, supply power to the analog and digital circuitry within the device. For operation at 3.6V or lower, disable the regulators by connecting ABP and DBP to VCC.

ABP is a 3.0V (typ) voltage regulator that powers the internal analog circuitry. Bypass ABP to GND with a 1FF ceramic capacitor installed as close as possible to the device.

DBP is an internal 3.0V (typ) voltage regulator. DBP powers flash and digital circuitry. All push-pull outputs refer to DBP. DBP supplies the input voltage to the internal charge pump when the programmable outputs are configured as charge-pump outputs. Bypass the DBP output to GND with a 1FF ceramic capacitor installed as close as possible to the device.

Do not power external circuitry from ABP or DBP.

Enable Input (EN)

To enable monitoring, the voltage at EN must be above

1.24V (typ) and the software enable bit in r73h[0] must be set to ‘1.’ To disable monitoring, either pull EN below 1.215V (typ) or set the software enable bit to ‘0.’ See Table 1 for the software enable bit configurations. Connect EN to ABP if not used.

Table 1. Software Enable Configurations

ADDRESS

73h 273h

10 _____________________________________________________________________________________

FLASH

ADDRESS

BIT RANGE DESCRIPTION

Software Enable

[0]

[1] Reserved [2] 1 = Margin mode enabled [3] Reserved

[4]

1 = Sequencing enabled 0 = Power-down

Independent watchdog mode enable 1 = Watchdog timer is independent of EN input 0 = Watchdog timer boots after EN goes high and the boot-up delay completes

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

When in the monitoring state, and when EN falls below the undervoltage threshold, a register bit, ENRESET (r20h[2]), is set to a ‘1.’ This register bit latches and must be cleared through software. This bit indicates if RESET asserted low due to EN going under the threshold. The POR state of ENRESET is ‘0.’ The bit is only set on a falling edge of the EN comparator output or the software enable bit. If operating in latch-on fault mode, toggle EN or toggle the software enable bit to clear the latch condition and restart the device once the fault condition has been removed.

Set r73h[2] to ‘1’ to enable monitoring functionality. Faults are not recorded when the device is in margining mode. Set r73h[2] to ‘0’ for normal functionality.

Voltage Monitoring

The MAX16068 features an internal 10-bit ADC that monitors the MON_ voltage inputs. An internal multiplexer cycles through each of the enabled inputs, taking less than 24Fs for a complete monitoring cycle. Each acquisition takes approximately 4Fs. At each multiplexer stop, the 10-bit ADC converts the analog input to a digital result and stores the result in a register. ADC conversion results are stored in registers r00h–r0Bh (see Table 2). Use the SMBus or JTAG serial interface to read ADC conversion results.

The MAX16068 provides six inputs, MON1–MON6, for voltage monitoring. Each input-voltage range is programmable in registers r43h–r44h (see Table 3). When

MON_ configuration registers are set to ’11,’ MON_ voltages are not monitored and the multiplexer does not stop at these inputs, decreasing the total cycle time. These inputs cannot be configured to trigger fault conditions.

The two programmable thresholds for each monitored voltage include an overvoltage and an undervoltage threshold. See the Faults section for more information on setting overvoltage and undervoltage thresholds. All voltage thresholds are 8 bits wide. The 8 MSBs of the 10-bit ADC conversion result are compared to these overvoltage and undervoltage thresholds.

For any undervoltage or overvoltage condition to be monitored and any faults detected, the MON_ input must be assigned to monitoring mode. Inputs that are not enabled are not converted by the ADC; they contain the last value acquired before that channel was disabled. The ADC conversion result registers are reset to 00h at boot-up. These registers are not reset when a reboot command is executed.

To temporarily disable voltage monitoring during voltage margining conditions, set r73h[2] to ‘1’ to enable margining mode functionality. Faults (except for faults triggered by EXTFAULT being pulled low externally) are not recorded when the device is in margining mode, but the ADC continues to run and conversion results continue to be available. Set r73h[2] back to ‘0’ for normal functionality.

MAX16068

Table 2. ADC Conversion Results (Read Only)

00h [7:0] MON1 result (MSB) 01h [7:6] MON1 result (LSB) 02h [7:0] MON2 result (MSB) 03h [7:6] MON2 result (LSB) 04h [7:0] MON3 result (MSB) 05h [7:6] MON3 result (LSB) 06h [7:0] MON4 result (MSB) 07h [7:6] MON4 result (LSB) 08h [7:0] MON5 result (MSB) 09h [7:6] MON5 result (LSB) 0Ah [7:0] MON6 result (MSB) 0Bh [7:6] MON6 result (LSB)

______________________________________________________________________________________ 11

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

Table 3. ADC Configuration Registers

MON1 Full-Scale Range 00 = 5.6V

[1:0]

MAX16068

[3:2]

43h 243h

[5:4]

[7:6]

[1:0]

44h 244h

[3:2]

[7:4] Not used

01 = 2.8V 10 = 1.4V 11 = channel not converted

MON2 Full-Scale Range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = channel not converted

MON3 Full-Scale Range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = channel not converted

MON4 Full-Scale Range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = channel not converted

MON5 Full-Scale Range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = channel not converted

MON6 Full-Scale Range 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = channel not converted

Boot-Up Delay

Once EN is above its threshold and the software enable bit is set, a boot-up delay occurs before monitoring

where t 4 MSBs and b is the decimal value of the 4 LSBs.

= (5 x 10-6) x 2a x (16 + b) + 480µs

BOOT

is in seconds, a is the decimal value of the

BOOT

begins. This delay is configured in register 77h as shown in Table 4, and it is stored as an 8-bit value calculated as follows:

Table 4. Boot-Up Delay

ADDRESS

77h 277h [7:0] Boot-up delay

12 _____________________________________________________________________________________

FLASH

ADDRESS

BIT

RANGE

DESCRIPTION

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

General-Purpose Inputs/Outputs

GPIO1–GPIO6 are programmable general-purpose inputs/outputs. GPIO1–GPIO6 are configurable as a manual reset input, a watchdog timer input and output, logic inputs/outputs, and fault-dependent outputs. When programmed as outputs, GPIO_s are open-drain or push-pull. See Tables 5 and 6 for more detailed information on configuring GPIO1–GPIO6.

Table 5. GPIO_ Configuration Registers

[1:0] GPIO1 configuration

3Fh 23Fh

40h 240h

[3:2] GPIO2 configuration [5:4] GPIO3 configuration [7:6] GPIO4 configuration [1:0] GPIO5 configuration [3:2] GPIO6 configuration

[7:5] Not used

Table 6. GPIO_ Function Configuration Bits

GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6

00 Logic input Logic input Logic input Logic input Logic input Logic input

Logic output

(push-pull)

Logic output

(open drain)

ALERT (open drain)

Logic output

(push-pull) Logic output (open drain)

FAULT (open drain)

When GPIO1–GPIO6 are configured as general-purpose inputs/outputs, read values from the GPIO_ ports through r1Eh and write values to GPIO_s through r3Eh. Note that r3Eh has a corresponding flash register, which programs the default state of a general-purpose output. See Table 7 for more information on reading and writing to the GPIO_.

[4] ARAEN bit

Logic output

(push-pull) Logic output (open drain)

MR input

Logic output

(push-pull) Logic output (open drain)

WDI

Logic output

(push-pull) Logic output (open drain)

WDO

(open drain)

Logic output

(push-pull) Logic output (open drain)

EXTFAULT

(open drain)

MAX16068

Table 7. GPIO_ State Registers

1Eh —

3Eh 23Eh

FLASH

ADDRESS

______________________________________________________________________________________ 13

BIT RANGE DESCRIPTION

[0] GPIO1 input state [1] GPIO2 input state [2] GPIO3 input state [3] GPIO4 input state [4] GPIO5 input state [5] GPIO6 input state

[7:6] Not used

[0] GPIO1 output state [1] GPIO2 output state [2] GPIO3 output state [3] GPIO4 output state [4] GPIO5 output state [5] GPIO6 output state

[7:6] Not used

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

GPIO1 is configurable as the SMBus alert signal, ALERT. ALERT asserts when any fault condition occurs. When the

SMBus host sends the ARA (Alert Response Address), the MAX16068 responds with its slave address and deasserts ALERT. ALERT is an open-drain output.

Set the ARAEN bit in r40h[4] to ‘1’ to disable the ARA feature. Under these conditions, the device does not respond to an ARA on the SMBus line.

MAX16068

GPIO2 is configurable as a dedicated fault output, FAULT. FAULT asserts when an overvoltage or undervoltage condition occurs on the selected inputs. FAULT dependencies are set using registers r36h and r37h (see Table 8). When FAULT depends on more than one MON_, the fault output asserts when one or more MON_ exceeds a programmed threshold voltage. FAULT acts independently of the critical fault system, described in the Critical Faults section. Use r37h[7] to set the polarity of FAULT.

ALERT

FAULT

Manual Reset (MR)

GPIO3 is configurable to act as an active-low manual reset input, MR. Drive MR low to assert RESET. RESET remains asserted for the selected reset timeout period after MR transitions from low to high. When connecting MR to a push- button, use a pullup resistor. See the Reset Output section for more information on selecting a reset timeout period.

Watchdog Input (WDI) and Output (WDO)

GPIO4 and GPIO5 are configurable as the watchdog timer input (WDI) and output, WDO, respectively. See Table 16 for configuration details. WDO is an open-drain, active-low output. See the Watchdog Timer section for more information about the operation of the watchdog timer.

External Fault (EXTFAULT)

GPIO6 is configurable as the external fault input/output, EXTFAULT. EXTFAULT asserts if any monitored voltage exceeds an overvoltage or undervoltage threshold. EXTFAULT also asserts if a power-up or power-down sequencing fault occurs. This signal can be used to cascade multiple MAX16068s.

For the MAX16068, if register bit r6Dh[2] is set in addition to r72h[5], EXTFAULT going low triggers a nonvolatile fault log operation.

Table 8. FAULT Dependencies

ADDRESS

36h 236h

37h 237h

FLASH

ADDRESS

BIT RANGE DESCRIPTION

[0] FAULT depends on MON1 undervoltage threshold [1] FAULT depends on MON2 undervoltage threshold [2] FAULT depends on MON3 undervoltage threshold [3] FAULT depends on MON4 undervoltage threshold [4] FAULT depends on MON5 undervoltage threshold [5] FAULT depends on MON6 undervoltage threshold

[7:6] Not used

[0] FAULT depends on MON1 overvoltage threshold [1] FAULT depends on MON2 overvoltage threshold [2] FAULT depends on MON3 overvoltage threshold [3] FAULT depends on MON4 overvoltage threshold [4] FAULT depends on MON5 overvoltage threshold [5] FAULT depends on MON6 overvoltage threshold [6] Not used

[7]

0 = FAULT is an active-low digital output 1 = FAULT is an active-high digital output

14 _____________________________________________________________________________________

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

Faults

The MAX16068 monitors the input (MON_) channels and compares the results with an overvoltage threshold and an undervoltage threshold. Based on these conditions, the MAX16068 asserts various fault outputs and save specific information about the channel conditions and voltages into the nonvolatile flash. Once a critical fault event occurs, the failing channel condition, ADC conversions at the time of the fault, or both can be saved by configuring the event logger. The event logger records a single failure in the internal flash and sets a lock bit that protects the stored fault data from accidental erasure on a subsequent power-up.

Table 9. Fault Threshold Registers

The MAX16068 is capable of measuring overvoltage and undervoltage fault events. Fault conditions are detected at the end of each ADC conversion. An overvoltage event occurs when the voltage at a monitored input exceeds the overvoltage threshold for that input. An undervoltage event occurs when the voltage at a monitored input falls below the undervoltage threshold. Fault thresholds are set in registers r49h–r59h as shown in Table 9. Disabled inputs are not monitored for fault conditions and are skipped over by the input multiplexer. Only the upper 8 bits of a conversion result are compared with the programmed fault thresholds.

MAX16068

ADDRESS

48h 248h [7:0] Not used 49h 249h [7:0] MON1 overvoltage threshold 4Ah 24Ah [7:0] MON1 undervoltage threshold 4Bh 24Bh [7:0] Not used 4Ch 24Ch [7:0] MON2 overvoltage threshold 4Dh 24Dh [7:0] MON2 undervoltage threshold 4Eh 24Eh [7:0] Not used 4Fh 24Fh [7:0] MON3 overvoltage threshold 50h 250h [7:0] MON3 undervoltage threshold 51h 251h [7:0] Not used 52h 252h [7:0] MON4 overvoltage threshold 53h 253h [7:0] MON4 undervoltage threshold 54h 254h [7:0] Not used 55h 255h [7:0] MON5 overvoltage threshold 56h 256h [7:0] MON5 undervoltage threshold 57h 257h [7:0] Not used 58h 258h [7:0] MON6 overvoltage threshold 59h 259h [7:0] MON6 undervoltage threshold

FLASH

ADDRESS

BIT RANGE DESCRIPTION

______________________________________________________________________________________ 15

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

Deglitch

Fault conditions are detected at the end of each conversion. When the voltage on an input falls outside a monitored threshold for one acquisition, the input multiplexer remains on that channel and performs several successive conversions. To trigger a fault, the input must stay outside the threshold for a certain number of acquisitions as determined by the deglitch setting in r74h[6:5] (see Table 10).

MAX16068

Table 10. Deglitch Configuration

ADDRESS

74h 274h [6:5]

Table 11. Fault Flags

ADDRESS

1Bh

1Ch

FLASH

ADDRESS

BIT RANGE DESCRIPTION

[0] MON1 undervoltage threshold [1] MON2 undervoltage threshold [2] MON3 undervoltage threshold [3] MON4 undervoltage threshold [4] MON5 undervoltage threshold [5] MON6 undervoltage threshold

[7:6] Reserved

[0] MON1 overvoltage threshold [1] MON2 overvoltage threshold [2] MON3 overvoltage threshold [3] MON4 overvoltage threshold [4] MON5 overvoltage threshold [5] MON6 overvoltage threshold [6] [7] SMB alert

BIT RANGE DESCRIPTION

External fault (EXTFAULT)

Fault Flags

Fault flags indicate the fault status of a particular input. The fault flag of any monitored input in the device can be read at any time from registers r1Bh and r1Ch, as shown in Table 11. Clear a fault flag by writing a ‘1’ to the appropriate bit in the flag register. Unlike the fault signals sent to the fault outputs, these bits are masked by the critical fault enable bits (see Table 12). The fault flag is only set when the matching enable bit in the critical fault enable register is also set.

Voltage Comparator Deglitch Configuration 00 = 2 cycles 01 = 4 cycles 10 = 8 cycles 11 = 16 cycles

16 _____________________________________________________________________________________

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

If GPIO6 is configured as the EXTFAULT input/output and EXTFAULT is pulled low by an external circuit, bit r1Ch[6] is set.

The SMB Alert (ALERT) bit is set if the MAX16068 has asserted the SMBus Alert output. Clear by writing a ‘1’. See the SMBALERT (ALERT) section for more details.

Table 12. Critical Fault Configuration

ADDRESS

6Dh 26Dh

6Eh 26Eh

6Fh 26Fh

70h

71h 271h [7:0] Not used

72h 272h

FLASH

ADDRESS

270h

BIT

RANGE

Fault Information to Log 00 = Save failed line flags and ADC values in flash

[1:0]

[2] 1 = Fault log triggered when EXTFAULT is pulled low externally

[7:3] Not used

[0] 1 = Fault log triggered when MON1 is below its undervoltage threshold [1] 1 = Fault log triggered when MON2 is below its undervoltage threshold [2] 1 = Fault log triggered when MON3 is below its undervoltage threshold [3] 1 = Fault log triggered when MON4 is below its undervoltage threshold [4] 1 = Fault log triggered when MON5 is below its undervoltage threshold

[5] 1 = Fault log triggered when MON6 is below its undervoltage threshold [7:6] Not used [3:0] Not used

[4] 1 = Fault log triggered when MON1 is above its overvoltage threshold

[5] 1 = Fault log triggered when MON2 is above its overvoltage threshold

[6] 1 = Fault log triggered when MON3 is above its overvoltage threshold

[7] 1 = Fault log triggered when MON4 is above its overvoltage threshold

[0] 1 = Fault log triggered when MON5 is above its overvoltage threshold

[1] 1 = Fault log triggered when MON6 is above its overvoltage threshold [7:2] Not used

[4:0] Not used

[5]

[7:6] Not used

01 = Save only failed line flags in flash 10 = Save only ADC values in flash 11 = Do not save anything

1 = EXTFAULT pulled low externally causes the device to stop monitoring until EN is toggled or the autoretry delay expires (see Autoretry/Latch Mode section) 0 = EXTFAULT pulled low externally does not cause the device to stop monitoring

During normal operation, a fault condition can be stored in the flash memory by setting the appropriate critical fault enable bits. Set the appropriate critical fault enable bits in registers r6Eh–r72h (see Table 12) for a fault condition to trigger a critical fault.

DESCRIPTION

Critical Faults

MAX16068

______________________________________________________________________________________ 17

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

Logged fault information is stored in flash registers r200h–r208h (see Table 13). After fault information is logged, the flash is locked and must be unlocked to enable a new fault log to be stored. Write a ‘0’ to r8Ch[1] to unlock the configuration flash. Fault information can be configured to store ADC conversion results and/or fault flags in registers. Select the critical fault configuration in r6Dh[1:0]. Set r6Dh[1:0] to ‘11’ to turn off the fault logger. All stored ADC results are 8 bits wide (MSBs of

MAX16068

the conversion).

Table 13. Nonvolatile Fault Log Registers

FLASH

ADDRESS

200h [7:0] Reserved

201h

202h

203h [7:0] MON1 ADC output (8 MSBs) 204h [7:0] MON2 ADC output (8 MSBs) 205h [7:0] MON3 ADC output (8 MSBs) 206h [7:0] MON4 ADC output (8 MSBs) 207h [7:0] MON5 ADC output (8 MSBs) 208h [7:0] MON6 ADC output (8 MSBs)

BIT RANGE DESCRIPTION

[0] Fault log triggered on MON1 falling below its undervoltage threshold [1] Fault log triggered on MON2 falling below its undervoltage threshold [2] Fault log triggered on MON3 falling below its undervoltage threshold [3] Fault log triggered on MON4 falling below its undervoltage threshold [4] Fault log triggered on MON5 falling below its undervoltage threshold [5] Fault log triggered on MON6 falling below its undervoltage threshold

[7:6] Not used

[0] Fault log triggered on MON1 exceeding its overvoltage threshold [1] Fault log triggered on MON2 exceeding its overvoltage threshold [2] Fault log triggered on MON3 exceeding its overvoltage threshold [3] Fault log triggered on MON4 exceeding its overvoltage threshold [4] Fault log triggered on MON5 exceeding its overvoltage threshold [5] Fault log triggered on MON6 exceeding its overvoltage threshold [6] [7] Not used

Fault log triggered on EXTFAULT

Autoretry/Latch Mode

The MAX16068 can be configured for one of two fault management methods: autoretry or latch-on-fault. Set r74h[4:3] to ‘00’ to select the latch-on-fault mode. The device does not reinitiate monitoring until EN is toggled or the software enable bit is toggled. See the Enable Input (EN) section for more information on setting the software enable bit.

18 _____________________________________________________________________________________

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

Set r74h[4:3] to a value other than ‘00’ to select autoretry mode (see Table 14). In this configuration, the device stops monitoring after a critical fault event then monitors again following the boot-up delay plus 20ms (see the Boot-Up Delay section). Use r74h[2:0] to select an autoretry delay from 20ms to 1.6s. See Table 14 for more information on setting the autoretry delay.

When fault information is stored in flash (see the Critical Faults section) and autoretry mode is selected, set an autoretry delay greater than the time required for the storing operation. When fault information is stored in flash and latch-on-fault mode is chosen, toggle EN or reset the software enable bit only after the completion of the storing operation. When saving information about the failed lines only, ensure a delay of at least 102ms before the restart procedure. Otherwise, ensure a minimum 153ms timeout, to ensure that ADC conversions are completed and values are stored correctly in flash.

The reset output, RESET, indicates the status of the monitored inputs. It asserts during the boot phase and deasserts following the reset timeout period once the monitored input voltage is within the undervoltage/overvoltage.

During normal monitoring, RESET can be configured to assert when any combination of MON_ inputs violates configurable combinations of undervoltage or overvoltage thresholds. Select the combination of MON_ inputs using r3Ch[5:0] and r3Dh[5:0]. Note that MON_ inputs configured as critical faults always cause RESET to assert regardless of these configuration bits.

RESET can be configured as push-pull or open drain using r3Bh[3], and active high or active low using r3Bh[2]. Select the reset timeout by loading a value from Table 15 into r3Bh[7:4].

To generate a one-shot pulse on RESET, write a ‘1’ into r3Bh[0]. The pulse width is the configured reset timeout. Register bit r3Bh[0] clears automatically (see Table 15). The current state of RESET can be checked by reading r20h[0].

Reset Output

MAX16068

Table 14. Autoretry Configuration

ADDRESS

74h 274h

FLASH

ADDRESS

BIT

RANGE

[2:0]

[4:3]

Retry Delay 000 = 20ms 001 = 40ms 010 = 80ms 011 = 150ms 100 = 280ms 101 = 540ms 110 = 1s 111 = 2s

Autoretry/Latch Mode 00 = Latch 01 = Retry 1 time 10 = Retry 3 times 11 = Always retry

DESCRIPTION

______________________________________________________________________________________ 19

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

Table 15. Reset Output Configuration

ADDRESS

MAX16068

3Bh 23Bh

3Ch 23Ch

3Dh 23Dh

FLASH

ADDRESS

BIT RANGE DESCRIPTION

RESET Soft Trigger

[0]

[1] Not used

[2]

[3]

[7:4]

[0] 1 = RESET depends on MON1 undervoltage [1] 1 = RESET depends on MON2 undervoltage [2] 1 = RESET depends on MON3 undervoltage [3] 1 = RESET depends on MON4 undervoltage [4] 1 = RESET depends on MON5 undervoltage [5] 1 = RESET depends on MON6 undervoltage

[7:6] Not used

[0] 1 = RESET depends on MON1 overvoltage [1] 1 = RESET depends on MON2 overvoltage [2] 1 = RESET depends on MON3 overvoltage [3] 1 = RESET depends on MON4 overvoltage [4] 1 = RESET depends on MON5 overvoltage [5] 1 = RESET depends on MON6 overvoltage

[7:6] Not used

0 = Normal RESET behavior 1 = Force RESET to assert

0 = Active low 1 = Active high

0 = Open drain 1 = Push-pull

Reset Timeout Period 0000 = 25Fs 0001 = 1.5ms 0010 = 2.5ms 0011 = 4ms 0100 = 6ms 0101 = 10ms 0110 = 15ms 0111 = 25ms 1000 = 40ms 1001 = 60ms 1010 = 100ms 1011 = 150ms 1100 = 250ms 1101 = 400ms 1110 = 600ms 1111 = 1s

20 _____________________________________________________________________________________

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

Watchdog Timer

The watchdog timer operates together with or independently of the MAX16068. When operating in dependent mode, the watchdog is not activated until RESET is deasserted. When operating in independent mode, the watchdog timer activates immediately after VCC exceeds the UVLO threshold and the boot phase is complete. Set r73h[4] to ‘0’ to configure the watchdog in dependent mode. Set r73h[4] to ‘1’ to configure the watchdog in independent mode. See Table 16 for more information on configuring the watchdog timer in dependent or independent mode. The watchdog timer can be reset by toggling the WDI inputs (GPIO4) or by writing a ‘1’ to r75h[5].

Dependent Watchdog Timer Operation

Use the watchdog timer to monitor FP activity in two modes. Flexible timeout architecture provides an adjustable watchdog startup delay of up to 300s, allowing complicated systems to complete lengthy boot-up routines. An adjustable watchdog timeout allows the supervisor to provide quick alerts when the processor activity fails. After each reset event (VCC drops below UVLO

then returns above UVLO, software reboot, manual reset (MR), EN input going low then high, or watchdog reset), the watchdog startup delay provides an extended time for the system to power up and fully initialize all FP and system components before assuming responsibility for routine watchdog updates. Set r76h[6:4] to a value other than ‘000’ to enable the watchdog startup delay. Set r76h[6:4] to ‘000’ to disable the watchdog startup delay.

The normal watchdog timeout period, t

, begins after

WDI

the first transition on WDI before the conclusion of the long startup watchdog period, t

WDI_STARTUP

(Figures 3

and 4). During the normal operating mode, WDO asserts if the FP does not toggle WDI with a valid transition (high- to-low or low-to-high) within the standard timeout period, t

. WDO remains asserted until WDI is toggled or

WDI

RESET is asserted (Figure 4).

While EN is low, the watchdog timer is in reset. The watchdog timer does not begin counting until the monitoring starts and RESET is deasserted. The watchdog timer is reset and WDO deasserts any time RESET is asserted (Figure 5). The watchdog timer is held in reset while RESET is asserted.

MAX16068

LAST MON_

WDI

RESET

Figure 3. Normal Watchdog Startup Sequence

WDI

WDO

Figure 4. Watchdog Timer Operation

< t

WDI

< t

WDI

< t

WDI

WDI_STARTUP

< t

WDI

> t

WDI

< t

WDI

< t

WDI

< t

______________________________________________________________________________________ 21

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

WDI

RESET

< t

WDI

< t

WDI_STARTUP

< t

WDI

MAX16068

WDO

1µs

Figure 5. Watchdog Startup Sequence with Watchdog Reset Enable Bit Set to ‘1’

Table 16. Watchdog Configuration

ADDRESS

73h 273h [4]

76h 276h

FLASH

ADDRESS

BIT

RANGE

[7]

[6:4]

[3:0]

1 = Independent mode 0 = Dependent mode

1 = Watchdog reset output enabled 0 = Watchdog reset output disabled

Watchdog Startup Delay 000 = No initial timeout 001 = 30s 010 = 40s 011 = 80s 100 = 120s 101 = 160s 110 = 220s 111 = 300s

Watchdog Timeout 0000 = Watchdog disabled 0001 = 1ms 0010 = 2ms 0011 = 4ms 0100 = 8ms 0101 = 14ms 0110 = 27ms 0111 = 50ms 1000 = 100ms 1001 = 200ms 1010 = 400ms 1011 = 750ms 1100 = 1.4s 1101 = 2.7s 1110 = 5s 1111 = 10s

DESCRIPTION

22 _____________________________________________________________________________________

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

The watchdog can be configured to control the RESET output as well as the WDO output. RESET asserts for the reset timeout, tRP, when the watchdog timer expires and the Watchdog Reset Output Enable bit (r76h[7]) is set to ‘1’. When RESET is asserted, the watchdog timer is cleared and WDO is deasserted, therefore, WDO pulses low for a short time (approximately 1Fs) when the watchdog timer expires. RESET is not affected by the watchdog timer when the Watchdog Reset Output Enable bit (r76h[7]) is set to ‘0’. If a RESET is asserted by the watchdog timeout, the WDRESET bit is set to ‘1’. A connected processor can check this bit to see the reset was due to a watchdog timeout.

See Table 16 for more information on configuring watchdog functionality.

Independent Watchdog Timer Operation

When r73h[3] is ‘1,’ the watchdog timer operates in the independent mode. In the independent mode, the watchdog timer operates as if it were a separate device. The watchdog timer is activated immediately upon VCC exceeding UVLO and once the boot-up sequence is finished. When RESET is asserted by EN being low, the watchdog timer and WDO are not affected.

There is a startup delay if r76h[6:4] is set to a value different than ‘000’. If r76h[6:4] is set to ‘000’, there is not a startup delay. See Table 16 for delay times.

In independent mode, if the Watchdog Reset Output Enable bit r76h[7] is set to ‘1,’ when the watchdog timer expires, WDO asserts then RESET asserts. WDO then deasserts. WDO is low for approximately 1Fs. If the Watchdog Reset Output Enable bit (r76h[7]) is set to ‘0,’ when the watchdog timer expires, WDO asserts but RESET is not affected.

User-Defined Register

Register r8Ah provides storage space for a user-defined configuration or firmware version number. Note that this register controls the contents of the JTAG USERCODE register bits 7-0. The user-defined register is stored at r28Ah in the flash memory.

Memory Lock Bits

Register r8Ch contains the lock bits for the configuration registers, configuration flash, user flash, and fault register lock. See Table 17 for details.

SMBus-Compatible Interface

The MAX16068 features an SMBus-compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX16068 and the master device at clock rates up to 400kHz. Figure 1 shows the 2-wire interface timing diagram. The MAX16068 is a transmit/receive, slave-only device, relying upon a master device to generate a clock signal. The master device (typically a microcontroller) initiates a data transfer on the bus and generates SCL to permit that transfer.

MAX16068

Table 17. Memory Lock Bits

ADDRESS

8Ch 28Ch

FLASH

ADDRESS

______________________________________________________________________________________ 23

BIT RANGE DESCRIPTION

[0]

[1]

[2]

[3]

[7.4] Not used

Configuration Register Lock 1 = Locked 0 = Unlocked

Flash Fault Register Lock 1 = Locked 0 = Unlocked

Flash Configuration Lock 1 = Locked 0 = Unlocked

User Flash Lock 1 = Locked 0 = Unlocked

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

A master device communicates to the MAX16068 by transmitting the proper address followed by command and/or data words. The slave address input, A0, is capable of detecting four different states, allowing multiple identical devices to share the same serial bus. The slave address is described further in the Slave Address section. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits

MAX16068

long and is always followed by an acknowledge pulse. SCL is a logic input, while SDA is an open-drain input/ output. SCL and SDA both require external pullup resistors to generate the logic-high voltage. Use 4.7kI for most applications.

Bit Transfer

Each clock pulse transfers one data bit. The data on SDA must remain stable while SCL is high (Figure 6); otherwise, the MAX16068 registers a START or STOP condition (Figure 7) from the master. SDA and SCL idle high when the bus is not busy.

START and STOP Conditions

Both SCL and SDA idle high when the bus is not busy. A master device signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high. The master device issues a STOP condition by transitioning SDA from low to high while SCL is high. A STOP condition frees the bus for another transmission. The bus remains active if a REPEATED START condition is generated, such as in the block read protocol (see Figure 1, SMBus Timing Diagram).

Early STOP Conditions

The MAX16068 recognizes a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition. This condition is not a legal SMBus format; at least one clock pulse must separate any START and STOP condition.

REPEATED START Conditions

A REPEATED START can be sent instead of a STOP condition to maintain control of the bus during a read operation. The START and REPEATED START conditions are functionally identical.

SDA

SCL

DATA LINE STABLE,

DATA VALID

Figure 6. Bit Transfer Figure 7. START and STOP Conditions

CHANGE OF

DATA ALLOWED

SDA

SCL

START

CONDITION

STOP

CONDITION

24 _____________________________________________________________________________________

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

Acknowledge

The acknowledge bit (ACK) is the 9th bit attached to any 8-bit data word. The receiving device always generates an ACK. The MAX16068 generates an ACK when receiving an address or data by pulling SDA low during the 9th clock period (Figure 8). When transmitting data, such as when the master device reads data back from the MAX16068, the device waits for the master device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if the receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master can reattempt communication at a later time. The MAX16068 generates a NACK after the command byte received during a software reboot, while writing to the flash, or when receiving an illegal memory address.

Use the slave address input, A0, to allow multiple identical devices to share the same serial bus. Connect A0 to GND, DBP (or an external supply voltage greater than 2V), SCL, or SDA to set the device address on the bus. See Table 18 for a listing of all possible 7-bit addresses.

The slave address can also be set to a custom value by loading the address into register r8Bh[6:0]. See Table

19. If r8Bh[6:0] is loaded with 00h, the address is set by input A0. Do not set the address to 09h or 7Fh to avoid address conflicts. The slave address setting takes effect immediately after writing to the register.

CLOCK PULSE FOR ACKNOWLEDGE

Slave Address

MAX16068

SCL

SDA BY

TRANSMITTER

SDA BY

RECEIVER

Figure 8. Acknowledge

Table 18. Setting the SMBus Slave Address

SLAVE ADDRESSES

A0 SLAVE ADDRESS

0 1010 100R

1 1010 101R

SCL 1010 110R

SDA 1010 111R

R = Read/write select bit.

8 9

NACK

ACK

______________________________________________________________________________________ 25

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

Packet Error Checking (PEC)

The MAX16068 features a packet-error checking (PEC) mode that is useful to improve the reliability of the communication bus by detecting bit errors. By enabling PEC, an extra CRC-8 error check byte is added in the data string during each read and/or write sequence. Enable PEC by writing a ‘1’ to r8Bh[7].

The CRC-8 byte is calculated using the polynomial:

MAX16068

The PEC calculation includes all bytes in the transmission, including address, command and data. The PEC calculation does not include ACK, NACK, START, STOP, or REPEATED START.

The MAX16068 uses eight command codes for block read, block write, and other commands. See Table 20 for a list of command codes.

To initiate a software reboot, send A7h using the send byte format. A software-initiated reboot is functionally the same as a hardware-initiated power-on reset. During boot-up, flash configuration data in the range of 230h–28Ch is copied to r30h–r8Ch registers in the default page.

C = X8 + X2 + X + 1

Command Codes

Send command code A8h to trigger a fault store to flash. Configure the Critical Fault Log Control register (6Dh) to store ADC conversion results and/or fault flags.

While in the flash page, send command code A9h to access the flash page (addresses from 200h–2FFh). Once command code A9h has been sent, all addresses are recognized as flash addresses only. Send command code AAh to return to the default page (addresses from 000h–0FFh). Send command code ABh to access the user flash-page (addresses from 300h–3FFh), and send command code ACh to return to the flash page.

Restrictions When Writing to Flash

Flash must be written to 8 bytes at a time. The initial address must be aligned to 8-byte boundaries—the 3 LSBs of the initial address must be ‘000’. Write the 8 bytes using a single block write command or using eight successive Write Byte commands. A write operation requires 122ms for each 8-byte block. After programming a block, check r20h[1] (see Table 25) to make sure the write operation is complete before attempting to write the next block.

Table 19. SMBus Settings Register

ADDRESS

8Bh 28Bh

FLASH

ADDRESS

BIT RANGE DESCRIPTION

Table 20. Command Codes

COMMAND CODE ACTION

A5h Block write A6h Block read A7h Reboot flash in register file A8h Trigger emergency save to flash A9h Flash page access ON AAh Flash page access OFF ABh User flash access ON (must be in flash page already)

ACh User flash access OFF (return to flash page)

[6:0]

[7] 1 = Enable PEC (Packet Error Check).

SMBus Slave Address Register. Set to 00h to use A0 pin address setting.

26 _____________________________________________________________________________________

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

Send Byte

The send byte protocol allows the master device to send one byte of data to the slave device (see Figure

9). The send byte presets a register pointer address for a subsequent read or write. The slave sends a NACK instead of an ACK if the master tries to send a memory address or command code that is not allowed. If the master sends A5h or A6h, the data is ACK, because this could be the start of the write block or read block. If the master sends a STOP condition before the slave asserts an ACK, the internal address pointer does not change. If the master sends A7h, this signifies a software reboot. The send byte procedure is as follows:

1) The master sends a START condition.

2) The master sends the 7-bit slave address and a write bit (low).

3) The addressed slave asserts an ACK on SDA.

4) The master sends an 8-bit memory address or command code.

5) The addressed slave asserts an ACK (or NACK) on SDA.

6) The master sends a STOP condition.

Receive Byte

The receive byte protocol allows the master device to read the register content of the MAX16068 (see Figure

9). The flash or register address must be preset with a

send byte or write word protocol first. Once the read is complete, the internal pointer increases by one. Repeating the receive byte protocol reads the contents of the next address. The receive byte procedure follows:

1) The master sends a START condition.

2) The master sends the 7-bit slave address and a read

bit (high).

3) The addressed slave asserts an ACK on SDA.

4) The slave sends 8 data bits.

5) The master asserts a NACK on SDA.

6) The master generates a STOP condition.

Write Byte

The write byte protocol (see Figure 9) allows the master device to write a single byte in the default page, extended page, or flash page, depending on which page is currently selected. The write byte procedure is as follows:

1) The master sends a START condition.

2) The master sends the 7-bit slave address and a write bit (low).

3) The addressed slave asserts an ACK on SDA.

4) The master sends an 8-bit memory address.

5) The addressed slave asserts an ACK on SDA.

6) The master sends an 8-bit data byte.

7) The addressed slave asserts an ACK on SDA.

8) The master sends a STOP condition.

To write a single byte, only the 8-bit memory address and a single 8-bit data byte are sent. The data byte is written to the addressed location if the memory address is valid. The slave asserts a NACK at step 5 if the memory address is not valid.

When PEC is enabled, the Write Byte protocol becomes:

1) The master sends a START condition.

2) The master sends the 7-bit slave ID plus a write bit (low).

3) The addressed slave asserts an ACK on the data line.

4) The master sends an 8-bit command code.

5) The active slave asserts an ACK on the data line.

6) The master sends an 8-bit data byte.

7) The slave asserts an ACK on the data line.

8) The master sends an 8-bit PEC byte.

9) The slave asserts an ACK on the data line (if PEC is good, otherwise NACK).

10) The master generates a STOP condition.

Read Byte

The read byte protocol (see Figure 9) allows the master device to read a single byte located in the default page, extended page, or flash page depending on which page is currently selected. The read byte procedure is as follows:

1) The master sends a START condition.

2) The master sends the 7-bit slave address and a write

bit (low).

3) The addressed slave asserts an ACK on SDA.

4) The master sends an 8-bit memory address.

5) The addressed slave asserts an ACK on SDA.

6) The master sends a REPEATED START condition.

7) The master sends the 7-bit slave address and a read

bit (high).

8) The addressed slave asserts an ACK on SDA.

MAX16068

______________________________________________________________________________________ 27

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

9) The slave sends an 8-bit data byte.

10) The master asserts a NACK on SDA.

11) The master sends a STOP condition.

If the memory address is not valid, it is NACKed by the slave at step 5 and the address pointer is not modified.

When PEC is enabled, the Read Byte protocol becomes:

1) The master sends a START condition.

2) The master sends the 7-bit slave ID plus a write bit

MAX16068

(low).

3) The addressed slave asserts an ACK on the data line.

4) The master sends 8 data bits.

5) The active slave asserts an ACK on the data line.

6) The master sends a REPEATED START condition.

7) The master sends the 7-bit slave ID plus a read bit (high).

8) The addressed slave asserts an ACK on the data line.

9) The slave sends 8 data bits.

10) The master asserts an ACK on the data line.

11) The slave sends an 8-bit PEC byte.

12) The master asserts a NACK on the data line.

13) The master generates a STOP condition.

Block Write

The block write protocol (see Figure 9) allows the master device to write a block of data (1–16 bytes) to memory. Preload the destination address by a previous send byte command; otherwise the block write command begins to write at the current address pointer. After the last byte is written, the address pointer remains preset to the next valid address. If the number of bytes to be written causes the address pointer to exceed 8Fh for configuration registers or configuration flash or FFh for user flash, the address pointer stays at 8Fh or FFh, respectively, overwriting this memory address with the remaining bytes of data. The slave generates a NACK at step 5 if the command code is invalid or if the device is busy, and the address pointer is not altered.

The block write procedure is as follows:

1) The master sends a START condition.

2) The master sends the 7-bit slave address and a write bit (low).

3) The addressed slave asserts an ACK on SDA.

4) The master sends the 8-bit command code for block write (94h).

5) The addressed slave asserts an ACK on SDA.

6) The master sends the 8-bit byte count (1 byte to 16 bytes), n.

7) The addressed slave asserts an ACK on SDA.

8) The master sends 8 bits of data.

9) The addressed slave asserts an ACK on SDA.

10) Repeat steps 8 and 9 n - 1 times.

11) The master sends a STOP condition.

When PEC is enabled, the Block Write protocol becomes:

1) The master sends a START condition.

2) The master sends the 7-bit slave ID plus a write bit (low).

3) The addressed slave asserts an ACK on the data line.

4) The master sends 8 bits of the block write command code.

5) The slave asserts an ACK on the data line.

6) The master sends 8 bits byte count (min 1, max 16) n.

7) The slave asserts an ACK on the data line.

8) The master sends 8 bits of data.

9) The slave asserts an ACK on the data line.

10) Repeat 8 and 9 n - 1 times.

11) The master sends an 8-bit PEC byte.

12) The slave asserts an ACK on the data line (if PEC is good, otherwise NACK).

13) The master generates a STOP condition.

Block Read

The block read protocol (see Figure 9) allows the master device to read a block of up to 16 bytes from memory. Read fewer than 16 bytes of data by issuing an early STOP condition from the master, or by generating a NACK with the master. The destination address should be preloaded by a previous send byte command; otherwise, the block read command begins to read at the current address pointer. If the number of bytes to be read causes the address pointer to exceed 8Fh for the configuration register or configuration flash or FFh in user flash, the address pointer stays at 8Fh or FFh, respectively.

28 _____________________________________________________________________________________

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

SEND BYTE FORMAT

ADDRESS

SLAVE ADDRESS: Address of the slave on the serial interface bus.

WRITE BYTE FORMAT

SLAVE ADDRESS: Address of the slave on the serial interface bus.

READ BYTE FORMAT

SLAVE ADDRESS: Address of the slave on the serial interface bus.

BLOCK WRITE FORMAT

SLAVE ADDRESS: Address of the slave on the serial interface bus.

BLOCK READ FORMAT

SLAVE ADDRESS: Address of the slave on the serial interface bus.

WRITE BYTE FORMAT WITH PEC

S ADDRESS COMMAND PEC P

R/W ACK COMMAND ACK P

7 BITS 0 00 8 BITS

DATA BYTE: Presets the internal address pointer or represents a command.

ADDRESS

R/W ACK COMMAND ACK

7 BITS 0 0 0

SLAVE

R/W

ADDRESS

7 BITS 0 0 0 0 18 BITS

R/W

ADDRESS

7 BITS 0

R/W R/W

ADDRESS

7 BITS

R/W

7 BITS

8 BITS

COMMAND BYTE: Sets the internal address pointer.

ACK COMMAND ACK

COMMAND BYTE: Sets the internal address pointer.

ACK COMMAND ACK

COMMAND BYTE: FAh

ACK COMMAND ACK

COMMAND BYTE: FBh

ACK ACK ACK ACK

8 BITS

00 8 BITS 0

DATA ACK P

8 BITS

DATA BYTE: Data is written to the locations set by the internal address pointer.

SLAVE

ADDRESS

7 BITS 1

BYTE

COUNT = N

8 BITS

ADDRESS

SR ACK

7 BITS0 0

SLAVE ADDRESS: Address of the slave on the serial interface bus.

DATA

8 BITS

RECEIVE BYTE FORMAT

ADDRESS

SLAVE ADDRESS: Address of the slave on the serial interface bus.

R/W

ACK DATA BYTE

DATA BYTE: Data is written to the locations set by the internal address pointer.

ACK P

DATA BYTE 1 ACK

8 BITS

0 0

DATA BYTE: Data is written to the locations set by the internal address pointer.

0 0 0

R/W ACK DATA NACK P

7 BITS 1 0

DATA BYTE: Data is read from the location pointed to by the internal address pointer.

SMBALERT#

S ADDRESS R/W ACK DATA NACK P

0001100 D.C. 8 BITS

ALERT RESPONSE ADDRESS: Only the device that interrupted the master responds to this address.

NACK P

8 BITS

DATA BYTE … ACK

0 08 BITS

8 BITS

BYTE

ACK P

COUNT = N

8 BITS

DATA BYTE: Data is read from the locations set by the internal address pointer.

DATA BYTE N ACK

8 BITS

18 BITS

0 1

SLAVE ADDRESS: Slave places its own address on the serial bus.

DATA BYTE N ACK

8 BITS

DATA BYTE … NACK

8 BITS

ACK DATA BYTE N

8 BITS

SLAVE TO MASTER

MASTER TO SLAVE

18 BITS

MAX16068

READ BYTE FORMAT WITH PEC

ADDRESS COMMAND DATA PEC P

7 BITS

BLOCK WRITE WITH PEC

ADDRESS

7 BITS

BLOCK READ WITH PEC

ADDRESS

7 BITS

S = START CONDITION P = STOP CONDITION Sr = REPEATED START CONDITION D.C. = DON’T CARE

ACK ACK ACK ACK NACK

R/W R/W

ACK ACK ACK ACK ACK ACK

R/W

ACK ACK ACK ACK ACK ACK ACK

R/W R/W

Figure 9. SMBus Protocols

______________________________________________________________________________________ 29

SRSRADDRESS

8 BITS

COMMAND

8 BITS

COMMAND

8 BITS

ACK = ACKNOWLEDGE, SDA PULLED LOW DURING RISING EDGE OF SCL. NACK = NOT ACKNOWLEDGE, SDA LEFT HIGH DURING RISING EDGE OF SCL.

ALL DATA IS CLOCKED IN/OUT OF THE DEVICE ON RISING EDGES OF SCL.

7 BITS

BYTE COUNT N

8 BITS

ADDRESS

7 BITS

1 1

DATA BYTE 1

8 BITS

BYTE COUNT N

8 BITS

DATA BYTE

8 BITS

DATA N

8 BITS

0 0 0

DATA BYTE 1

8 BITS

DATA BYTE

8 BITS

= SDA TRANSITIONS FROM HIGH TO LOW DURING PERIOD OF SCL.

= SDA TRANSITIONS FROM LOW TO HIGH DURING PERIOD OF SCL.

ACK

PEC

8 BITS

DATA N

0 0

8 BITS

PEC

NACK1P

8 BITS

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

The block read procedure is the following:

1) The master sends a START condition.

2) The master sends the 7-bit slave address and a write bit (low).

3) The addressed slave asserts an ACK on SDA.

4) The master sends 8 bits of the block read command (95h).

5) The slave asserts an ACK on SDA, unless busy.

MAX16068

6) The master generates a REPEATED START condition.

REGISTERS

AND EEPROM

MEMORY WRITE REGISTER

[LENGTH = 8 BITS]

MEMORY READ REGISTER

[LENGTH = 8 BITS]

MEMORY ADDRESS REGISTER

[LENGTH = 8 BITS]

USER CODE REGISTER

[LENGTH = 32 BITS]

IDENTIFICATION REGISTER

[LENGTH = 32 BITS]

BYPASS REGISTER

[LENGTH = 1 BIT]

7) The master sends the 7-bit slave address and a read bit (high).

8) The slave asserts an ACK on SDA.

9) The slave sends the 8-bit byte count (16).

10) The master asserts an ACK on SDA.

11) The slave sends 8 bits of data.

12) The master asserts an ACK on SDA.

13) Repeat steps 11 and 12 up to fifteen times.

14) The master asserts a NACK on SDA.

15) The master sends a STOP condition.

01100

01011

01010

01001

01000

00111

00110

MUX 1

00101

COMMAND

00100

00011

00000

11111

DECODER

01100

01011

01010

01001

01000

00111

SETFLSHADD

RSTFLSHADD

RSTUSRFLSH

SETUSRFLSH

SAVE

REBOOT

INSTRUCTION REGISTER

[LENGTH = 5 BITS]

TDI

TMS

TCK

TEST ACCESS PORT

(TAP) CONTROLLER

MUX 2

Figure 10. JTAG Block Diagram

30 _____________________________________________________________________________________

TDO

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

When PEC is enabled, the Block Read protocol becomes:

1) The master sends a START condition.

2) The master sends the 7-bit slave ID plus a write bit (low).

3) The addressed slave asserts an ACK on the data line.

4 The master sends 8 bits of the block read command

code.

5) The slave asserts an ACK on the data line unless busy.

6) The master sends a REPEATED START condition.

7) The master sends the 7-bit slave ID plus a read bit (high).

8) The slave asserts an ACK on the data line.

9) The slave sends 8-bit byte count (16).

10) The master asserts an ACK on the data line.

11) The slave sends 8 bits of data.

12) The master asserts an ACK on the data line.

13) Repeat 11 and 12 up to 15 times.

14) The slave sends an 8-bit PEC byte.

15) The master asserts a NACK on the data line.

16) The master generates a STOP condition.

SMBALERT (ALERT)

The MAX16068 supports the SMBus alert protocol. To enable the SMBus alert output, set r40h[4] to ‘1’, then configure GPIO1 to act as the SMBus alert (ALERT) according to Table 12. This output is open drain and uses the wired-OR configuration with other devices on the SMBus. During a fault, the MAX16068 asserts ALERT low, signaling the master that an interrupt has occurred. The master responds by sending the ARA (Alert Response Address) protocol on the SMBus. This protocol is a read byte with 09h as the slave address. The slave acknowledges the ARA (09h) address and sends its own SMBus address to the master. The slave then deasserts ALERT. The master can then query the slave and determine the cause of the fault. By checking r1C[7], the master can confirm that the MAX16068 triggered the SMBus alert. The master must send the ARA before clearing r1Ch[7]. Clear r1Ch[7] by writing a ‘1’. If GPIO1 is configured as the SMBus alert output but the SMBus alert feature is disabled (r40h[4] is set to ‘0’), GPIO1 acts as an additional fault output.

The MAX16068 features a JTAG port that complies with a subset of the IEEE 1149.1 specification. Either the SMBus or the JTAG interface can be used to access internal memory; however, only one interface is allowed to run at a time. The MAX16068 contains extra JTAG instructions and registers not included in the JTAG specification that provide access to internal memory. The extra instructions include LOAD ADDRESS, WRITE, READ, REBOOT, and SAVE.

The TAP controller is a finite state machine that responds to the logic level at TMS on the rising edge of TCK. See Figure 11 for a diagram of the finite state machine. The possible states are described as follows:

Test-Logic-Reset: At power-up, the TAP controller is in the test-logic-reset state. The instruction register contains the IDCODE instruction. All system logic of the device operates normally. This state can be reached from any state by driving TMS high for five clock cycles.

Run-Test/Idle: The run-test/idle state is used between scan operations or during specific tests. The instruction register and test data registers remain idle.

Select-DR-Scan: All test data registers retain their previous state. With TMS low, a rising edge of TCK moves the controller into the capture-DR state and initiates a scan sequence. TMS high during a rising edge on TCK moves the controller to the select-IR-scan state.

Capture-DR: Data can be parallel-loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected test data register does not allow parallel loads, the test data register remains at its current value. On the rising edge of TCK, the controller goes to the shift-DR state if TMS is low or it goes to the exit1-DR state if TMS is high.

Shift-DR: The test data register selected by the current instruction connects between TDI and TDO and shifts data one stage toward its serial output on each rising edge of TCK while TMS is low. On the rising edge of TCK, the controller goes to the exit1-DR state if TMS is high.

Exit1-DR: While in this state, a rising edge on TCK puts the controller in the update-DR state. A rising edge on TCK with TMS low puts the controller in the pause-DR state.

JTAG Serial Interface

Test Access Port (TAP)

Controller State Machine

MAX16068

______________________________________________________________________________________ 31

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

TEST-LOGIC-RESET

RUN-TEST/IDLE

MAX16068

SELECT-DR-SCAN SELECT-IR-SCAN

CAPTURE-DR

SHIFT-DR SHIFT-IR

EXIT1-DR EXIT1-IR

PAUSE-DR PAUSE-IR

EXIT2-DR EXIT2-IR

UPDATE-DR

1 1

CAPTURE-IR

UPDATE-IR

Figure 11. Tap Controller State Diagram

Pause-DR: Shifting of the test data registers halts while in this state. All test data registers retain their previous state. The controller remains in this state while TMS is low. A rising edge on TCK with TMS high puts the controller in the exit2-DR state.

Exit2-DR: A rising edge on TCK with TMS high while in this state puts the controller in the update-DR state. A rising edge on TCK with TMS low enters the shift-DR state.

Update-DR: A falling edge on TCK while in the updateDR state latches the data from the shift register path of the test data registers into a set of output latches. This prevents changes at the parallel output because of changes in the shift register. On the rising edge of TCK, the controller goes to the run-test/idle state if TMS is low or goes to the select-DR-scan state if TMS is high.

Select-IR-Scan: All test data registers retain the previous states. The instruction register remains unchanged during this state. With TMS low, a rising edge on TCK

32 _____________________________________________________________________________________

moves the controller into the capture-IR state. TMS high during a rising edge on TCK puts the controller back into the test-logic-reset state.

Capture-IR: Use the capture-IR state to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of TCK. If TMS is high on the rising edge of TCK, the controller enters the exit1-IR state. If TMS is low on the rising edge of TCK, the controller enters the shift-IR state.

Shift-IR: In this state, the shift register in the instruction register connects between TDI and TDO and shifts data one stage for every rising edge of TCK toward the TDO serial output while TMS is low. The parallel outputs of the instruction register as well as all test data registers remain at the previous states. A rising edge on TCK with TMS high moves the controller to the exit1-IR state. A rising edge on TCK with TMS low keeps the controller in the shift-IR state while moving data one stage through the instruction shift register.

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

Exit1-IR: A rising edge on TCK with TMS low puts the controller in the pause-IR state. If TMS is high on the rising edge of TCK, the controller enters the update-IR state.

Pause-IR: Shifting of the instruction shift register halts temporarily. With TMS high, a rising edge on TCK puts the controller in the exit2-IR state. The controller remains in the pause-IR state if TMS is low during a rising edge on TCK.

Exit2-IR: A rising edge on TCK with TMS high puts the controller in the update-IR state. The controller loops back to shift-IR if TMS is low during a rising edge of TCK in this state.

Update-IR: The instruction code that has been shifted into the instruction shift register latches to the parallel outputs of the instruction register on the falling edge of TCK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on TCK with TMS low puts the controller in the runtest/idle state. With TMS high, the controller enters the select-DR-scan state.

Instruction Register

The instruction register contains a shift register as well as a latched 5-bit wide parallel output. When the TAP controller enters the shift-IR state, the instruction shift register connects between TDI and TDO. While in the

shift-IR state, a rising edge on TCK with TMS low shifts the data one stage toward the serial output at TDO. A rising edge on TCK in the exit1-IR state or the exit2-IR state with TMS high moves the controller to the updateIR state. The falling edge of that same TCK latches the data in the instruction shift register to the instruction register parallel output. Table 21 shows the instructions supported by the MAX16068 and the respective operational binary codes.

BYPASS: When the BYPASS instruction is latched into the instruction register, TDI connects to TDO through the 1-bit bypass test data register. This allows data to pass from TDI to TDO without affecting the device’s operation.

IDCODE: When the IDCODE instruction is latched into the parallel instruction register, the identification data register is selected. The device identification code is loaded into the identification data register on the rising edge of TCK following entry into the capture-DR state. Shift-DR can be used to shift the identification code out serially through TDO. During test-logic-reset, the IDCODE instruction is forced into the instruction register. The identification code always has a ‘1’ in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. See Table 22.

MAX16068

Table 21. JTAG Instruction Set

INSTRUCTION CODE NOTES

BYPASS 0x1F Mandatory instruction code IDCODE 0x00 Load manufacturer ID code/part number USERCODE 0x03 Load user code LOAD ADDRESS 0x04 Load address register content READ DATA 0x05 Read data pointed by current address WRITE DATA 0x06 Write data pointed by current address REBOOT 0x07 Reboot FLASH data content into register file SAVE 0x08 Trigger emergency save to flash SETFLSHADD 0x09 Flash page access ON RSTFLSHADD 0x0A Flash page access OFF SETUSRFLSH 0x0B User flash access ON (must be in flash page already) RSTUSRFLSH 0x0C User flash access OFF (return to flash page)

Table 22. 32-Bit Identification Code

MSB LSB

VERSION (4 BITS) PART NUMBER (16 BITS) MANUFACTURER (11 BITS) FIXED VALUE (1 BIT)

0001 1000000000000010 00011001011 1

______________________________________________________________________________________ 33

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

USERCODE: When the USERCODE instruction latches into the parallel instruction register, the user-code data register is selected. The device user-code loads into the user-code data register on the rising edge of TCK following entry into the capture-DR state. Shift-DR can be used to shift the user-code out serially through TDO. See Table 24. This instruction can be used to help identify multiple MAX16068 devices connected in a JTAG chain.

LOAD ADDRESS: This is an extension to the standard

MAX16068

IEEE 1149.1 instruction set to support access to the memory in the MAX16068. When the LOAD ADDRESS instruction latches into the instruction register, TDI connects to TDO through the 8-bit memory address test data register during the shift-DR state.

READ DATA: This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the MAX16068. When the READ instruction latches into the instruction register, TDI connects to TDO through the 8-bit memory read test data register during the shift-DR state.

WRITE DATA: This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the MAX16068. When the WRITE instruction latches into the instruction register, TDI connects to TDO through the 8-bit memory write test data register during the shift-DR state.

REBOOT: This is an extension to the standard IEEE

1149.1 instruction set to initiate a software-controlled

reset to the MAX16068. When the REBOOT instruction latches into the instruction register, the MAX16068 resets and immediately begins the boot-up sequence.

SAVE: This is an extension to the standard IEEE 1149.1 instruction set that triggers a fault log. The current ADC conversion results along with fault information are saved to flash depending on the configuration of the Critical Fault Log Control register (r6Dh).

SETFLSHADD: This is an extension to the standard IEEE 1149.1 instruction set that allows access to the flash page. Flash registers include ADC conversion results, DACOUT enables, and GPIO input/output data. Use this page to access registers 200h–2FFh.

RSTFLSHADD: This is an extension to the standard IEEE 1149.1 instruction set. Use RSTFLSHADD to return to the default page and disable access to the flash page.

SETUSRFLSH: This is an extension to the standard IEEE 1149.1 instruction set that allows access to the user flash page. When on the configuration flash page, send the SETUSRFLSH command, all addresses are recognized as flash addresses only. Use this page to access registers 300h–3FFh.

RSTUSRFLSH: This is an extension to the standard IEEE 1149.1 instruction set. Use RSTUSRFLSH to return to the configuration flash page and disable access to the user flash.

Restrictions When Writing to Flash

Flash must be written to 8 bytes at a time. The initial address must be aligned to 8-byte boundaries—the 3 LSBs of the initial address must be ‘000’. Write the 8 bytes using eight successive Write Data commands. A write operation requires 122ms for each 8-byte block. After programming a block, check r20h[1] (see Table

25) to make sure the write operation is complete before attempting to write the next block.

Table 23. 32-Bit User-Code Data

MSB LSB

DON’T CARE SMBUS SLAVE ID USER ID (r8A[7:0])

00000000000000000 See Table 18

Table 24. Maximum Write Time

r6Dh[1:0] VALUE DESCRIPTION MAXIMUM WRITE TIME (ms)

00 Save flags and ADC readings 153 01 Save flags 102 10 Save ADC readings 153 11 Do not save anything —

34 _____________________________________________________________________________________

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

Table 25. RESET State, Flash State, and Reset Reason

Reset output state

r20h

[0]

[1] 1 = Flash memory is busy [2] 1 = Last reset asserted due to EN going low [3] 1 = Last reset asserted due to watchdog timeout

[7:4] Not used

0 = RESET is low 1 = RESET is high

MAX16068

Applications Information

Device Behavior at Power-Up

When VCC is ramped from 0V, the RESET output is high impedance until VCC reaches 1.4V, at which point RESET goes low. All other outputs are high impedance until VCC reaches 2.7V, then the flash contents are copied into register memory. This takes 150Fs (max) after which the outputs assume their programmed states.

Programming the MAX16068 in Circuit

The MAX16068 can be programmed in the application circuit by taking into account the following points during circuit design:

U The MAX16068 needs to be powered from an inter-

mediate voltage bus or an auxiliary voltage supply so programming can occur even when the board’s power supplies are off. This could also be achieved by using ORing diodes so that power can be provided through the programming connector.

U The SMBus or JTAG bus lines should not connect

through a bus multiplexer powered from a voltage rail controlled by the MAX16068. If the device needs to be controlled by an on-board FP, consider connecting the FP to one bus (such as SMBus) and use the other bus for in-circuit programming.

circuit. Table 25 shows that the amount of time required depends on the settings in the fault control register (r6Dh[1:0]).

Maintain power for shutdown during fault conditions in applications where the always-on power supply cannot be relied upon by placing a diode and a large capacitor between the voltage source, VIN, and VCC (Figure 12). The capacitor value depends on VIN and the time delay required, t

FAULT_SAVE

. Use the following formula to cal-

culate the capacitor size:

C = (t

FAULT_SAVE

where the capacitance is in Farads and t seconds, I

CC(MAX)

across the diode, and V a VIN of 14V, a diode drop of 0.7V, and a t

x I

CC(MAX)

is 14mA, V

UVLO

)/(VIN - V

is the voltage drop

DIODE

- V

DIODE

FAULT_SAVE

UVLO

)

is in

is 2.7V. For example, with

FAULT_SAVE

of 153ns, the minimum required capacitance is 202FF.

MAX16068

Maintaining Power During

a Fault Condition

Power to the MAX16068 must be maintained for a specific period of time to ensure a successful flash fault log operation during a fault that removes power to the

______________________________________________________________________________________ 35

GND

Figure 12. Power Circuit for Shutdown During Fault Conditions

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

Configuring the Device

An evaluation kit and a graphical user interface (GUI) are available to create a custom configuration for the device (Figure 13).

Refer to the MAX16068 Evaluation Kit for configuration.

Cascading Multiple MAX16068s

Multiple MAX16068s can be cascaded to monitor more power supplies. There are many ways to cascade the

MAX16068

devices depending on the desired behavior. In general, there are several techniques as follows:

U Configure a GPIO on each device to be EXTFAULT

(open drain). Externally wire them together with a single pullup resistor. Set register bits r72h[5] and r6Dh[2] to ‘1’ so that all faults propagate between devices. If a critical fault occurs on one device, EXTFAULT asserts,

triggering the nonvolatile fault logger in all cascaded devices and recording a snapshot of all system voltages.

U Connect open-drain RESET outputs together to obtain

a master system reset signal.

U Connect all EN inputs together for a master enable

signal.

Layout and Bypassing

Bypass DBP and ABP each with a 1FF ceramic capacitor to GND. Bypass VCC with a 10FF capacitor to ground. Avoid routing digital return currents through a sensitive analog area, such as an analog supply input return path or ABP’s bypass capacitor ground connection. Use dedicated analog and digital ground planes. Connect the capacitors as close as possible to the device.

Figure 13. Graphical User Interface Screenshot

36 _____________________________________________________________________________________

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

MAX16068

FLASH

ADDRESS

ADC VALUES, FAULT REGISTERS, GPIO_s AS INPUT PORTS—NOT IN FLASH

— 000 R MON1 ADC output, MSBs — 001 R MON1 ADC output, LSBs — 002 R MON2 ADC output, MSBs — 003 R MON2 ADC output, LSBs — 004 R MON3 ADC output, MSBs — 005 R MON3 ADC output, LSBs — 006 R MON4 ADC output, MSBs — 007 R MON4 ADC output, LSBs — 008 R MON5 ADC output, MSBs — 009 R MON5 ADC output, LSBs — 00A R MON6 ADC output, MSBs — 00B R MON6 ADC output, LSBs — 00C–01A — Reserved — 01B R/W Fault register—failed line flags — 01C R/W Fault register—failed line flags — 01D — Reserved — 01E R GPIO_ data in (read only) — 01F — Reserved — 020 R/W Flash status/reset output monitor — 021 — Reserved

GPIO_ AND OUTPUT DEPENDENCIES/CONFIGURATIONS

230 030 — Reserved 231 031 — Reserved 232 032 — Reserved 233 033 — Reserved 234 034 — Reserved 235 035 — Reserved 236 036 R/W 237 037 R/W

238–23A 038–03A — Reserved

23B 03B R/W RESET output configuration 23C 03C R/W RESET output dependencies 23D 03D R/W RESET output dependencies

23E 03E R/W GPIO data out

23F 03F R/W GPIO configuration

240 040 R/W GPIO configuration, ARANEN (ARA Enable)

241–242 041–042 — Reserved

ADDRESS

READ/ WRITE

DESCRIPTION

FAULT dependencies FAULT dependencies

______________________________________________________________________________________ 37

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

FLASH

ADDRESS

ADC—CONVERSIONS

243 043 R/W ADCs voltage ranges for MON_ monitoring

244 044 R/W ADCs voltage ranges for MON_ monitoring

245–247 045–047 — Reserved

INPUT THRESHOLDS

MAX16068

248 048 — Reserved

249 049 R/W MON1 OV threshold

24A 04A R/W MON1 UV threshold

24B 04B — Reserved

24C 04C R/W MON2 OV threshold

24D 04D R/W MON2 UV threshold

24E 04E — Reserved

24F 04F R/W MON3 OV threshold

250 050 R/W MON3 UV threshold

251 051 — Reserved

252 052 R/W MON4 OV threshold

253 053 R/W MON4 UV threshold

254 054 — Reserved

255 055 R/W MON5 OV threshold

256 056 R/W MON5 UV threshold

257 057 — Reserved

258 058 R/W MON6 OV threshold

259 059 R/W MON6 UV threshold

25A–26C 05A–06C — Reserved

FAULT SETUP

26D 06D R/W

26E 06E R/W Faults causing store in flash

26F 06F R/W Faults causing store in flash

270 070 R/W Faults causing store in flash

271 071 — Reserved

272 072 R/W

ADDRESS

READ/ WRITE

DESCRIPTION

Save after EXTFAULT fault control

EXTFAULT enable

38 _____________________________________________________________________________________

6-Channel, Flash-Configurable System Manager

with Nonvolatile Fault Registers

MAX16068

FLASH

ADDRESS

TIMEOUTS

273 073 R/W

274 074 R/W ADC fault deglitch/autoretry configuration

275 075 R/W WDI toggle/fault timeout, reverse sequencing bit

276 076 R/W WDRESET, WD timers

277 077 R/W Boot-up delay

278 078 — Reserved

279 079 — Reserved

27A 07A — Reserved

27B 07B — Reserved 27C 07C — Reserved 27D 07D — Reserved

MISCELLANEOUS

27E 07E — Reserved

27F 07F — Reserved

280 080 — Reserved

281–283 081–083 — Reserved

284 084 — Reserved

285 085 — Reserved

286 086 — Reserved

287–289 087–089 — Reserved

28A 08A R/W Customer use (version)

28B 08B R/W PEC enable/SMBus address 28C 08C R/W Lock bits 28D 08D R Revision code

ADDRESS

READ/ WRITE

DESCRIPTION

Watchdog independent mode, MARGIN enabled, soft RESET functionality

______________________________________________________________________________________ 39

6-Channel, Flash-Configurable System Manager with Nonvolatile Fault Registers

Typical Operating Circuit

+48V IN

OUT

DC-DC

MAX16068

LATCH

CIRCUIT

OUTIN

DC-DC

MON1 MON2

Chip Information

PROCESS: BiCMOS

DC-DC

OUTIN

MAX16068

DBPABP

DC-DC

AOGND

OUTIN

MON3–

MON6

FAULT

RESET

SCL

SDA

3.3V

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

28 TQFN-EP T2855+6

21-0140

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

40 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Rainbow Electronics MAX16068 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual