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MAX16066
User Manual
61 pgs2.79 Mb0

Rainbow Electronics MAX16066 User Manual

19-4717; Rev 0; 7/09
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
General Description
The MAX16065/MAX16066 flash-configurable system managers monitor and sequence multiple system volt­ages. The MAX16065/MAX16066 can also accurately monitor (±2.5%) one current channel using a dedicated high-side current-sense amplifier. The MAX16065 man­ages up to twelve system voltages simultaneously, and the MAX16066 manages up to eight supply voltages. These devices integrate a selectable differential or sin­gle-ended analog-to-digital converter (ADC) and con­figurable outputs for sequencing power supplies. Device configuration information, including overvoltage and undervoltage limits, timing settings, and the sequenc­ing order is stored in nonvolatile flash memory. During a fault condition, fault flags and channel voltages can be automatically stored in the nonvolatile flash memory for later read-back.
The internal 1% accurate 10-bit ADC measures each input and compares the result to one overvoltage, one undervoltage, and one early warning limit that can be configured as either undervoltage or overvoltage. A fault signal asserts when a monitored voltage falls outside the set limits. Up to three independent fault output signals are configurable to assert under various fault conditions.
Because the MAX16065/MAX16066 support a power­supply voltage of up to 14V, they can be powered directly from the 12V intermediate bus in many systems.
The integrated sequencer provides precise control over the power-up and power-down order of up to twelve (MAX16065) or up to eight (MAX16066) power supplies. Eight outputs (EN_OUT1–EN_OUT8) are configurable with charge-pump outputs to directly drive external n-channel MOSFETs.
SMBus is a trademark of Intel Corp.
Features
S Operate from 2.8V to 14V
S ±2.5% Current-Monitoring Accuracy
S 1% Accurate 10-Bit ADC Monitors 12/8 Voltage
Inputs
S Single-Ended or Differential ADC for System
Voltage/Current Monitoring
S Integrated High-Side Current-Sense Amplifier
S 12/8 Monitored Inputs with Overvoltage/
Undervoltage/Early Warning Limit
S Nonvolatile Fault Event Logger
S Power-Up and Power-Down Sequencing
Capability
S Independent Secondary Sequence Block
S 12/8 Outputs for Sequencing/Power-Good
Indicators
S Two Programmable Fault Outputs and One Reset
Output
S Eight General-Purpose Inputs/Outputs
Configurable as:
Dedicated Fault Outputs Watchdog Timer Function Manual Reset
Margin Enable
S SMBus (with Timeout) or JTAG Interface
S Flash Configurable Time Delays and Thresholds
S -40NC to +85NC Operating Temperature Range
Applications
Networking Equipment
Telecom Equipment (Base Stations, Access)
Storage/Raid Systems
Servers
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX16065ETM+ MAX16066ETL+
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
Pin Configuration and Typical Operating Circuits appear at end of data sheet.
-40NC to +85NC
-40NC to +85NC
48 TQFN-EP* 40 TQFN-EP*
MAX16065/MAX16066
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers
ABSOLUTE MAXIMUM RATINGS
VCC, CSP, CSM to GND ........................................-0.3V to +15V
CSP to CSM .......................................................... -0.7V to +0.7V
MON_, GPIO_, SCL, SDA, A0, RESET, EN_OUT9–EN_OUT12 to
GND (programmed as open-drain outputs) ........-0.3V to +6V
EN, TCK, TMS, TDI to GND ....................................-0.3V to +4V
DBP, ABP to GND ...-0.3V to the lower of +3V and (VCC + 0.3V) EN_OUT1–EN_OUT8 to GND (programmed as open-drain
outputs) ............................................................-0.3V to +15V
TDO, EN_OUT_, GPIO_, RESET (programmed as push-pull
outputs)............................................... -0.3V to (V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DBP
+ 0.3V)
ELECTRICAL CHARACTERISTICS
(VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at ABP = DBP = VCC = 3.3V, TA = +25NC.) (Note 1)
MAX16065/MAX16066
Operating Voltage Range V
Undervoltage Lockout (Rising) V
Undervoltage Lockout Hysteresis V
Minimum Flash Operating Voltage
Supply Current I
ABP Regulator Voltage V DBP Regulator Voltage V Boot Time t Flash Writing Time 8-byte word 122 ms Internal Timing Accuracy (Note 3) -8 +8 %
EN Input Voltage
EN Input Current I Input Voltage Range 0 5.5 V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CC
UVLO
UVLO_HYS
V
flash
CC
ABP
DBP
BOOT
V
TH_EN_R
V
TH_EN_F
EN
Reset output asserted low 1.2 (Note 2) 2.8 14
Minimum voltage on VCC to ensure the device is flash configurable
Minimum voltage on VCC to ensure flash erase and write operations
No load on output pins 4.5 7 During flash writing cycle 10 14 C
= 1μF, no load, VCC = 5V 2.85 3 3.15 V
ABP
C
= 1μF, no load, VCC = 5V 2.8 3 3.1 V
ABP
VCC > V
EN voltage rising 1.41 EN voltage falling 1.365 1.39 1.415
UVLO
Continuous Power Dissipation (TA = +70NC)
48-Pin TQFN (derate 27.8mW/NC above +70NC) .......2222mW
Operating Temperature Range .......................... -40NC to +85NC
V
2.7 V
100 mV
2.7 V
mA
200 350 μs
V
-0.5 +0.5 μA
2 ______________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at ABP = DBP = VCC = 3.3V, TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ADC DC ACCURACY
Resolution 10 Bits
Gain Error ADC
Offset Error ADC Integral Nonlinearity ADC Differential Nonlinearity ADC ADC Total Monitoring Cycle Time t
ADC IN_ Ranges
CURRENT SENSE
CSP Input-Voltage Range V
Input Bias Current
CSP Total Unadjusted Error CSP
Overcurrent Differential Threshold
V
Fault Threshold
SENSE
Hysteresis
Secondary Overcurrent Threshold Timeout
V
Ranges
SENSE
ADC Current Measurement Accuracy
Gain Accuracy
Common-Mode Rejection Ratio CMRR Power-Supply Rejection Ratio PSRR
CYCLE
I
I
CSM
OVC
OVC
OVC
CSP
CSP
GAIN
TA = +25°C 0.35 TA = -40°C to +85°C 0.70
OFF
INL
DNL
No MON_ fault detected 40 50 μs 1 LSB = 5.43mV 5.56
1 LSB = 1.36mV 1.39
3 14 V
14 25
V
= V
CSP
(Note 4) 2 %FSR
ERR
V
TH
HYS
DEL
SNSVCSP
SNS
CSP
V
CSM
r73h[6:5] = ‘00’ 0 r73h[6:5] = ‘01’ 3 4 5 r73h[6:5] = ‘10’ 12 16 20 r73h[6:5] = ‘11’ 50 64 60 Gain = 6 232 Gain = 12 116 Gain = 24 58 Gain = 48 29 V
SENSE
V
SENSE
V
SENSE
V
SENSE
V
SENSE
gain = 6
CSM
Gain = 48 21.5 25 30.5 Gain = 24 46 51 56
­Gain = 12 94 101 108 Gain = 6 190 202 210
= 150mV (gain = 6 only) -2.5 = 50mV, gain = 12 -4 = 25mV, gain = 24 = 10mV, gain = 48
= 20mV to 100mV, V
> 4V 80 dB
CSP
= 5V,
-1.5 +1.5 %
3 5
0.5 % OVC
Q0.2 Q0.2 Q0.5
Q1
80 dB
1 LSB 1 LSB 1 LSB
+2.5
+4
%
V1 LSB = 2.72mV 2.78
μA
mV
TH
ms
mV
%
MAX16065/MAX16066
_______________________________________________________________________________________ 3
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at ABP = DBP = VCC = 3.3V, TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OUTPUTS (EN_OUT_, RESET, GPIO_)
I
= 2mA 0.4
SINK
I
Output-Voltage Low V
Maximum Output Sink Current
Output-Voltage High (Push-Pull) I
Output Leakage (Open Drain)
OUT_ Overdrive (Charge Pump) (EN_OUT1–EN_OUT8 Only)
OUT_ Pullup Current (Charge Pump)
MAX16065/MAX16066
SMBus INTERFACE
Logic-Input Low Voltage V Logic-Input High Voltage V Input Leakage Current IN = GND or V Output Sink Current V Input Capacitance C SMBus Timeout t
INPUTS (A0, GPIO_)
Input Logic-Low V Input Logic-High V WDI Pulse Width t
MR Pulse Width MR to RESET Delay MR Glitch Rejection
SMBus TIMING
Serial Clock Frequency f
Bus Free Time Between STOP and START Condition
START Condition Setup Time t START Condition Hold Time t STOP Condition Setup Time t Clock Low Period t Clock High Period t Data Setup Time t
OL
I
CH_UP
IL
IH
OL
IN
TIMEOUT
IL
IH
WDI
t
MR
SCL
t
BUF
SU:STA
HD:STA
SU:STO
LOW
HIGH
SU:DAT
= 10mA, GPIO_ only 0.7
SINK
VCC = 1.2V, I Total current into EN_OUT_, RESET,
GPIO_, VCC = 3.3V
SOURCE
EN_OUT1–EN_OUT8 = 13.2V 5
I
GATE_
During power up, V
Input voltage falling 0.8 V Input voltage rising 2.0 V
I
SINK
SCL time low for reset 25 35 ms
= 100μA 2.4 V
= 1μA 10 11 13 V
= 3mA 0.4 V
= 100μA (RESET only)
SINK
= 1V 2.5 4 μA
GATE
CC
-1 +1 μA
5 pF
2.0 V
100 ns
1 μs
0.5 μs
100 ns
1.3 μs
0.6 μs
0.6 μs
0.6 μs
1.3 μs
0.6 μs
100 ns
0.3
30 mA
1
0.8 V
400 kHz
V
μA
4 ______________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
ELECTRICAL CHARACTERISTICS
(VCC = 2.8V to 14V, TA = -40NC to +85NC, unless otherwise specified. Typical values are at ABP = DBP = VCC = 3.3V, TA = +25NC.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Fall Time t Data Hold Time t Pulse Width of Spike Suppressed t
JTAG INTERFACE
TDI, TMS, TCK Logic-Low Input Voltage
TDI, TMS, TCK Logic-High Input Voltage
TDO Logic-Output Low Voltage V TDO Logic-Output High Voltage V TDI, TMS Pullup Resistors R I/O Capacitance C TCK Clock Period t TCK High/Low Time t2, t TCK to TMS, TDI Setup Time t TCK to TMS, TDI Hold Time t TCK to TDO Delay t TCK to TDO High-Z Delay t
OF
HD:DAT
V
V
SP
IL
IH
OL
OH
PU
I/O
1
4
5
6
7
C
= 10pF to 400pF 250 ns
BUS
From 50% SCL falling to SDA change 0.3 0.9 μs
30 ns
Input voltage falling 0.8 V
Input voltage rising 2 V
I
= 3mA 0.4 V
SINK
I
SOURCE
Pullup to DBP 40 50 60 kω
3
= 200μA 2.4 V
5 pF
50 500 ns 15 ns 10 ns
1000 ns
500 ns 500 ns
MAX16065/MAX16066
Note 1: Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at TA =
+25NC and TA = +85NC. Specifications at TA = -40NC are guaranteed by design.
Note 2: For V
supply rail.
Note 3: Applies to RESET, fault, autoretry, sequence delays, and watchdog timeout. Note 4: Total unadjusted error is a combination of gain, offset, and quantization error.
of 3.6V or lower, connect VCC, DBP, and ABP together. For higher supply applications, connect only VCC to the
CC
_______________________________________________________________________________________ 5
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers
SDA
t
BUF
SCL
t
HD:STA
t
SU:DAT
t
t
t
LOW
t
HIGH
t
R
HD:DAT
t
F
SU:STA
t
HD:STA
t
SU:STO
START
CONDITION
MAX16065/MAX16066
Figure 1. SMBus Timing Diagram
t
2
TCK
TDI, TMS
t
6
t
7
t
4
REPEATED START
CONDITION
t
1
t
5
STOP
CONDITION
t
3
START
CONDITION
TDO
Figure 2. JTAG Timing Diagram
6 ______________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
VCC SUPPLY CURRENT
vs. V
CC
SUPPLY VOLTAGE
MAX16065 toc01
VCC (V)
I
CC
(mA)
12108642
1
2
3
4
5
6
0
0 14
TA = +85NC
TA = +25NC
TA = -40NC
FOR LOW-VOLTAGE APPLICATIONS V
CC
< 3.6V CONNECT ABP AND
DBP TO V
CC
ABP AND DBP REGULATORS ACTIVE
ABP AND DBP CONNECTED TO V
CC
Managers with Nonvolatile Fault Registers
Typical Operating Characteristics
(Typical values are at VCC = 3.3V, T
= +25°C, unless otherwise noted.)
A
MAX16065/MAX16066
TRANSIENT DURATION
vs. THRESHOLD OVERDRIVE (EN)
160
140
120
100
80
60
TRANSIENT DURATION (µs)
40
20
0
1 100
10
EN OVERDRIVE (mV)
NORMALIZED MON_ THRESHOLD
1.2
1.0
0.8
0.6
0.4
NORMALIZED MON_ THRESHOLD
0.2
0
-40 80
NORMALIZED TIMING ACCURACY
0.986
0.984
MAX16065 toc04
0.982
0.980
0.978
0.976
NORMALIZED SLOT DELAY
0.974
0.972
-40
vs. TEMPERATURE
5.6V RANGE, HALF SCALE, PUV THRESHOLD
TEMPERATURE (NC)
vs. TEMPERATURE
TEMPERATURE (NC)
NORMALIZED EN THRESHOLD
vs. TEMPERATURE
1.006
1.004
MAX16065 toc02
1.002
1.000
0.998
0.996
NORMALIZED EN THRESHOLD
0.994
6040200-20
0.992
-40 TEMPERATURE (NC)
MAX16065 toc03
806040200-20
MON_ DEGLITCH
vs. TRANSIENT DURATION
120
806040200-20
MAX16065 toc05
TRANSIENT DURATION (µs)
100
80
60
40
20
0
2
4 8 16
DEGLITCH VALUE
MAX16065 toc06
MR TO RESET PROPAGATION DELAY
2.0
1.8
1.6
1.4
1.2
1.0
DELAY (µs)
0.8
0.6
0.4
0.2
0
-40
vs. TEMPERATURE
MAX
MIN
TEMPERATURE (NC)
806020 400-20
MAX16065 toc07
OUTPUT VOLTAGE vs. SINK CURRENT
(OUT = LOW)
0.45
0.40
0.35
0.30
0.25
(V)
OUT
V
0.20
0.15
0.10
0.05
0
0 20
EN_OUT_
GPIO_
I
(mA)
OUT
MAX16065 toc08
RESET
15105
OUTPUT-VOLTAGE HIGH vs. SOURCE
CURRENT (CHARGE-PUMP OUTPUT)
12
10
8
(V)
6
OUT
V
4
2
0
0 4
I
(µA)
OUT
_______________________________________________________________________________________ 7
MAX16065 toc09
321
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers
Typical Operating Characteristics (continued)
(Typical values are at VCC = 3.3V, T
= +25°C, unless otherwise noted.)
A
OUTPUT-VOLTAGE HIGH vs. SOURCE
CURRENT (PUSH-PULL OUTPUT)
3.4
3.3
3.2
3.1
3.0
(V)
2.9
OUT
V
2.8 EN_OUT_
2.7
2.6
2.5
2.4
RESET
0 1500
GPIO_
1000500
I
(µA)
OUT
MAX16065 toc10
INTEGRAL NONLINEARITY vs. CODE
1.0
0.8
0.6
0.4
0.2
0
INL (LSB)
-0.2
-0.4
-0.6
-0.8
-1.0 0 1024
MAX16065/MAX16066
NORMALIZED CURRENT-SENSE
ACCURACY vs. TEMPERATURE
1.05
1.03
200mV
1.01
0.99
100mV
0.97
NORMALIZED CURRENT-SENSE OUTPUT
0.95
TEMPERATURE (NC)
25mV
6040200-20-40 80
MAX16065 toc13
ERROR (mV)
-0.2
-0.4
-0.6
-0.8
-1.0
CURRENT-SENSE ACCURACY
1.0
0.8
0.6
0.4
0.2
0
0 30
CODE (LSB)
vs. CSP-CSM VOLTAGE
CSP-CSM VOLTAGE (mV)
DIFFERENTIAL NONLINEARITY vs. CODE
1.0
0.8
MAX16065 toc11
0.6
0.4
0.2
0
DNL (LSB)
-0.2
-0.4
-0.6
-0.8
896768512 640256 384128
-1.0 0 1024
CODE (LSB)
MAX16065 toc12
896768512 640256 384128
CURRENT-SENSE TRANSIENT DURATION
vs. CSP-CSM OVERDRIVE
1.8
1.6
MAX16065 toc14
1.4
1.2
1.0
0.8
0.6
TRANSIENT DURATION (Fs)
0.4
0.2
252015105
0
0 100
CSP-CSM OVERDRIVE (mV)
80604020
MAX16065 toc15
RESET OUTPUT CURRENT
FET TURN-ON WITH CHARGE PUMP
EN_OUT
I
LOAD
V
LOAD
20ms/div
MAX16065 toc16
SEQUENCING MODE
20ms/div
MAX16065 toc17
18
16
14
12
10
8
6
OUTPUT CURRENT (mA)
4
2
0
vs. SUPPLY VOLTAGE
ABP AND DBP CONNECTED TO V
ABP AND DBP
REGULATORS ACTIVE
0 14
SUPPLY VOLTAGE (V)
8 ______________________________________________________________________________________
V
CC
RESET
MAX16065 toc18
= 0.3V
12106 842
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Pin Description
MAX16065/MAX16066
PIN
MAX16065 MAX16066
1–6, 43–46 1–5, 36–40
47, 48 —
7 6 CSP
8 7 CSM
9 8 RESET Configurable Reset Output 10 9 TMS JTAG Test Mode Select 11 10 TDI JTAG Test Data Input 12 11 TCK JTAG Test Clock 13 12 TDO JTAG Test Data Output 14 13 SDA SMBus Serial-Data Open-Drain Input/Output 15 14 A0 Four-State SMBus Address. Address sampled upon POR. 16 15 SCL SMBus Serial-Clock Input
17, 42 16, 35 GND Ground
20–25 17–22
18, 19 —
26–29 —
NAME FUNCTION
MON1– MON10
MON11,
MON12
GPIO1–
GPIO6
GPIO7,
GPIO8
EN_OUT12–
EN_OUT9
Monitor Voltage Inputs. Set monitor voltage range through configuration registers. Measured value written to ADC register can be read back through the SMBus or JTAG interface.
Monitor Voltage Inputs. Set monitor voltage range through configuration registers. Measured value written to ADC register can be read back through the SMBus or JTAG interface.
Current-Sense Amplifier Positive Input. Connect CSP to the source side of the external sense resistor.
Current-Sense Amplifier Negative Input. Connect CSM to the load side of the external sense resistor.
General-Purpose Input/Outputs. GPIO_s can be configured to act as a TTL input, a push-pull, open-drain, or high-impedance output or a pulldown circuit during a fault event.
General-Purpose Input/Outputs. GPIO_s can be configured to act as a TTL input, a push-pull, open-drain, or high-impedance output or a pulldown circuit during a fault event or reverse sequencing.
Outputs. Set EN_OUT_ with active-high/active-low logic and with push-pull or open-drain configuration. EN_OUT_ can be asserted by a combination of IN_ voltages configurable through the flash.
30–37 23–30
38 31 EN
39 32 DBP
40 33 V
41 34 ABP
— — EP
_______________________________________________________________________________________ 9
EN_OUT1–
EN_OUT8
CC
Outputs. Set EN_OUT_ with active-high/active-low logic and with push-pull or open-drain configuration. EN_OUT_ can be asserted by a combination of IN_ voltages configurable through the flash. EN_OUT1–EN_OUT8 can be configured with a charge-pump output (+10V above GND) that can drive an external n-channel MOSFET.
Analog Enable Input. All outputs deassert when VEN is below the enable threshold.
Digital Bypass. All push-pull outputs are referenced to DBP. Bypass DBP with a 1FF capacitor to GND.
Device Power Supply. Connect VCC to a voltage from 2.8V to 14V. Bypass VCC with a 10FF capacitor to GND.
Analog Bypass. Bypass ABP with a 1FF ceramic capacitor to GND.
Exposed Pad. Internally connected to GND. Connect to ground, but do not use as the main ground connection.
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers
Functional Diagram
V
CC
MAX16065
EN
MAX16065/MAX16066
CSP
CSM
MON1– MON12
1.4V
VOLTAGE SCALING
AND MUX
A
V
V
CSTH
REF
10-BIT ADC
(SAR)
ADC
REGISTERS
ABP DBP
DIGITAL
COMPARATORS
DECODE
LOGIC
WATCHDOG
TIMER
PRIMARY
SEQUENCE
BLOCK
SECONDARY
SEQUENCE
BLOCK
OVERC
RESET
ANYFAULT
FAULT1
FAULT2
MR
MARGIN
WDI
WDO
GPIO1–GPIO8
RESET
G P I O
C O N T R O L
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
EN_OUT1– EN_OUT12
RAM
REGISTERS
SMBus INTERFACE
AO
SCL SDA
FLASH
MEMORY
GND
TDO TDI TCK TMS
JTAG
INTERFACE
10 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Detailed Description
The MAX16065 manages up to twelve system power supplies and the MAX16066 can manage up to eight system power supplies. After boot-up, if EN is high and the software enable bit is set to ‘1,’ a power-up sequence begins based on the configuration stored in flash and the EN_OUT_s are controlled accordingly. When the power-up sequence is successfully completed, the monitoring phase begins. An internal multiplexer cycles through each MON_ input. At each multiplexer stop, the 10-bit ADC converts the monitored analog voltage to a digital result and stores the result in a register. Each time a conversion cycle (50Fs, max) completes, internal logic circuitry compares the conversion results to the over­voltage and undervoltage thresholds stored in memory. When a result violates a programmed threshold, the conversion can be configured to generate a fault. GPIO_ can be programmed to assert on combinations of faults. Additionally, faults can be configured to shut off the sys­tem and trigger the nonvolatile fault logger, which writes all fault information automatically to the flash and write­protects the data to prevent accidental erasure.
The MAX16065/MAX16066 contain both SMBus and JTAG serial interfaces for accessing registers and flash. Use only one interface at any given time. For more infor­mation on how to access the internal memory through these interfaces, see the SMBus-Compatible Interface and JTAG Serial Interface sections. The memory map is divided into three pages with access controlled by special SMBus and JTAG commands.
The factory-default values at POR (power-on reset) for all RAM registers are ‘0’s. POR occurs when VCC reaches the undervoltage-lockout threshold (UVLO) of 2.8V (max). At POR, the device begins a boot-up sequence. During the boot-up sequence, all monitored inputs are masked from initiating faults and flash contents are copied to the respective register locations. During boot-up, the MAX16065/MAX16066 are not accessible through the serial interface. The boot-up sequence takes up to 150Fs, after which the device is ready for normal opera­tion. RESET is asserted low up to the boot-up phase and remains asserted for its programmed timeout period once sequencing is completed and all monitored channels are within their respective thresholds. Up to the boot-up phase, the GPIO_s and EN_OUT_s are high impedance.
Apply 2.8V to 14V to VCC to power the MAX16065/ MAX16066. Bypass VCC to ground with a 10FF capaci­tor. Two internal voltage regulators, ABP and DBP, supply power to the analog and digital circuitry within the device. For operation at 3.6V or lower, disable the regulators by connecting ABP and DBP to VCC.
ABP is a 3.0V (typ) voltage regulator that powers the inter­nal analog circuitry. Bypass ABP to GND with a 1FF ceram­ic capacitor installed as close to the device as possible.
DBP is an internal 3.0V (typ) voltage regulator. DBP powers flash and digital circuitry. All push-pull outputs refer to DBP. DBP supplies the input voltage to the inter­nal charge pump when the programmable outputs are configured as charge-pump outputs. Bypass the DBP output to GND with a 1FF ceramic capacitor installed as close as possible to the device.
Do not power external circuitry from ABP or DBP.
To sequence a system of power supplies safely, the output voltage of a power supply must be good before the next power supply may turn on. Connect EN_OUT_ outputs to the enable input of an external power supply and connect MON_ inputs to the output of the power supply for voltage monitoring. More than one MON_ can be used if the power supply has multiple outputs.
Sequence Order
The MAX16065/MAX16066 provide a system of ordered slots to sequence multiple power supplies. To determine the sequence order, assign each EN_OUT_ to a slot ranging from Slot 1 to Slot 12. EN_OUT_(s) assigned to Slot 1 are turned on first, followed by outputs assigned to Slot 2, and so on through Slot 12. Multiple EN_OUT_s assigned to the same slot turn on at the same time.
Each slot includes a built-in configurable sequence delay (registers r77h to r7Dh) ranging from 20Fs to 1.6s. During a reverse sequence, slots are turned off in reverse order starting from Slot 12. The MAX16065/MAX16066 can be configured to power-down in simultaneous mode or in reverse sequence mode as set in r75h[0]. See Tables 5 and 6 for the EN_OUT_ slot assignment bits, and Tables 3 and 4 for the sequence delays.
During power-up or power-down sequencing, the cur­rent sequencer state can be found in r21h[4:0].
Power
Sequencing
MAX16065/MAX16066
______________________________________________________________________________________ 11
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers
Table 1. Current Sequencer Slot
REGISTER
ADDRESS
21h
MAX16065/MAX16066
BIT RANGE DESCRIPTION
Current Sequencer State: 00000 = Slot 0 00001 = Slot 1 00010 = Slot 2 00011 = Slot 3 00100 = Slot 4 00101 = Slot 5 00110 = Slot 6 00111 = Slot 7
[4:0]
[7:5] Reserved
01000 = Slot 8 01001 = Slot 9 01010 = Slot 10 01011 = Slot 11 01100 = Slot 12 01101 = Secondary sequence monitoring mode 01110 = Primary sequence fault 01111 = Primary sequence monitoring mode 10000 = Secondary sequence fault 10001 to 11111 = Reserved
Multiple Sequencing Groups
The MAX16065/MAX16066 sequencing slots can be split into two groups: the primary sequence and the sec­ondary sequence. The last slot of the primary sequence is selected using register bits r7Dh[7:4]. The second­ary sequence begins at the slot after the one speci­fied in register bits 7Dh[7:4]. The primary sequence is controlled by the EN input and the software enable bit in r73h[0]. Outputs assigned to slots in the primary sequence turn on, and monitoring begins for inputs assigned to these slots. RESET deasserts after the pri­mary sequence and timeout period completes.
To initiate secondary sequencing and monitoring, set the software enable 73h[1] bit to 1. Additionally, if GPIO_ is configured as EN2 then both the software enable 2 and EN2 must be high. Outputs assigned to slots in the secondary sequence turn on, and monitoring begins for inputs assigned to these slots. If a GPIO_ is configured as the RESET2 output, it deasserts after the secondary sequence and timeout period completes.
If a critical fault occurs in the primary sequence group, both sequence groups automatically shut down. If a critical fault occurs in the secondary sequence group, then just the outputs assigned to slots in the second­ary sequence turn off. The failing slot in secondary sequence is stored in r1Dh.
Multiple sequencing groups can be used to conserve power by powering down secondary systems when not in use.
Enable and Enable2
To initiate sequencing/tracking and enable monitoring, the voltage at EN must be above 1.4V and the software enable bit in r73h[0] must be set to ‘1.’ To power down and disable monitoring, either pull EN below 1.35V or set the Software Enable bit to ‘0.’ See Table 2 for the software enable bit configurations. Connect EN to ABP if not used.
If a fault condition occurs during the power-up cycle, the EN_OUT_ outputs are powered down immediately, regardless of the state of EN. In the monitoring state, if EN falls below the threshold, the sequencing state machine begins the power-down sequence. If EN rises above the threshold during the power-down sequence, the sequence state machine continues the power-down sequence until all the channels are powered off and then the device immediately begins the power-up sequence. When in the monitoring state, a register bit, ENRESET, is set to a ‘1’ when EN falls below the undervoltage threshold. This register bit latches and must be cleared through software. This bit indicates if RESET asserted low due to EN going under the threshold. The POR state of ENRESET is ‘0’. The bit is only set on a falling edge
12 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
of the EN comparator output or the software enable bit. If operating in latch-on fault mode, toggle EN or toggle the Software Enable bit to clear the latch condition and restart the device once the fault condition has been removed.
To initiate secondary sequencing and monitoring set the software enable r73h[1] bit to 1. Additionally, if GPIO_ is configured as EN2 then both the software enable 2 bit and EN2 must be high. To power-down and disable monitor­ing, either drive EN2 low or set the Software Enable2 bit to ‘0.’ See Table 2 for the software enable bit configurations.
When a fault condition occurs during the power-up cycle, the EN_OUT_ outputs are powered down immediately, independent of the state of EN2. Drive EN2 low to begin the secondary power-down sequence. When EN2 is driv-
Table 2. Software Enable Configurations
REGISTER
ADDRESS
73h 273h
FLASH
ADDRESS
BIT RANGE DESCRIPTION
[0] Software enable 1 (primary sequence) [1] Software enable 2 (secondary sequence) [2] 1 = Margin mode enabled
Early warning threshold select
[3]
[4]
0 = Early warning is undervoltage 1 = Early warning is overvoltage
Independent watchdog mode enable 1 = Watchdog timer is independent of sequencer 0 = Watchdog timer boots after sequence completes
en high during the power-down sequence, the sequence state machine continues the power-down sequence until the secondary channels are powered off and then the device immediately begins the power-up sequence.
Monitoring Inputs While Sequencing
An enabled MON_ input can be assigned to a slot ranging from Slot 1 to Slot 12. EN_OUT_s are always asserted at the beginning of a slot. The supply volt­ages connected to the MON_ inputs must exceed the undervoltage threshold before the programmed timeout period expires otherwise a fault condition will occur. The undervoltage threshold checking cannot be disabled during power-up and power-down. See Tables 5 and 6 for the MON_ slot assignment bits. The programmed
MAX16065/MAX16066
Table 3. Slot Delay Register
REGISTER
ADDRESS
77h 277h
78h 278h
79h 279h
7Ah 27Ah
7Bh 27Bh
7Ch 27Ch
7Dh 27Dh
FLASH
ADDRESS
______________________________________________________________________________________ 13
BIT RANGE DESCRIPTION
[3:0] Sequence Slot 0 Delay [7:4] Sequence Slot 1 Delay [3:0] Sequence Slot 2 Delay [7:4] Sequence Slot 3 Delay [3:0] Sequence Slot 4 Delay [7:4] Sequence Slot 5 Delay [3:0] Sequence Slot 6 Delay [7:4] Sequence Slot 7 Delay [3:0] Sequence Slot 8 Delay [7:4] Sequence Slot 9 Delay [3:0] Sequence Slot 10 Delay [7:4] Sequence Slot 11 Delay [3:0] Sequence Slot 12 Delay [7:4] Grouped Sequence Split Location, Final Slot of Primary Sequence
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers
Table 4. Power-Up/Power-Down Slot Delays
CODE VALUE
0000 0001 0010 1ms 0011 2ms 0100 3ms 0101 4ms 0110 6ms 0111 8ms 1000 10ms 1001 12ms 1010 25ms 1011 100ms 1100 200ms 1101 400ms 1110 800ms
MAX16065/MAX16066
1111 1.6s
25Fs
500Fs
sequence delay is then counted before moving to the next slot.
Slot 0 does not monitor any MON_ input and does not control any EN_OUT_. Slot 0 waits for the Software Enable bit r73h[0] to be a logic-high and for the voltage on EN to rise above 1.4V before initiating the power-up sequence and counting its own sequence delay.
Any MON_ input that suffers a fault that occurs during power-up sequencing causes all the EN_OUT_s to turn off and the sequencer to shut down regardless of the state of the critical fault enables (see the Faults section for more information). If a MON_ input is less critical to system operation, it can be configured as “monitoring only” (see Table 6) for either the primary or secondary sequence. Monitoring for MON_ inputs assigned as “monitoring only” begins after sequencing is complete for that group, and can trigger a critical fault only if specifically configured to do so using the critical fault enables.
Power-Up
On power-up, when EN is high and the Software Enable bit is 1, the MAX16065/MAX16066 begin sequencing with Slot 0. After the sequencing delay for Slot 0 expires, the sequencer advances to Slot 1, and all EN_OUT_s assigned to the slot assert. All MON_ inputs assigned to Slot 1 are monitored and when the voltage rises above the UV fault threshold, the sequence delay counter is started.
When the t assigned to the slot are above the fault UV threshold, a fault asserts. EN_OUT_ outputs are disabled and the MAX16065/MAX16066 return to the power-off state. When the sequence delay expires, the MAX16065/ MAX16066 proceed to the next slot.
After the voltages on all MON_ inputs assigned to the last slot exceed the UV fault threshold and the slot delay expires, the MAX16065/MAX16066 start the reset time­out counter. After the reset timeout, RESET deasserts. r75h[4:1] sets the t
Power-down starts when EN is pulled low or the Software Enable bit is set to ‘0.’ Power down EN_OUT_s simul­taneously or in reverse-sequence mode by setting the Reverse Sequence bit (r75h[0]) appropriately.
When the MAX16065/MAX16066 are fully powered up (including secondary sequence group, if enabled) and EN or the Software Enable bit is set to ‘0’, the EN_OUT_s assigned to Slot 12 deassert, the MAX16065/MAX16066 wait for the Slot 12 sequence delay and then proceed to the previous slot (Slot 11), and so on until the EN_OUT_s assigned to Slot 1 turn off. When simultaneous power­down is selected (r75h[0] set to ‘0’), all EN_OUT_s turn off at the same time.
counter expires before all MON_ inputs
FAULT
delay. See Table 7 for details.
FAULT
Power-Down
Reverse-Sequence Mode
14 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
MAX16065/MAX16066
BOTH ARE ASSIGNED TO SLOT 1
BOTH ARE ASSIGNED TO SLOT 2
EN_OUT1
MON4
EN_OUT2
MON3
MON5
RESET
SLOT 0
SLOT1-SLOT2
DELAY
UV/OV
MONITORING BEGINS
WHEN MON4 REACHES UV THRESHOLD
SLOT 1
t
FAULT
SLOT1-SLOT2
MON4 MUST
REACH UV
THRESHOLD BY THIS
TIME
DELAY
UV
OV
SLOT 2
FINAL SLOT
(PRIMARY
SEQUENCE)
RESET
TIMEOUT
EN
Figure 3. Delay and Reset Timing
Table 5. MON_ and EN_OUT_ Assignment Registers
REGISTER
ADDRESS
7Eh 27Eh
7Fh 27Fh
80h 280h
81h 281h
82h 282h
83h 283h
FLASH
ADDRESS
BIT RANGE DESCRIPTION
[3:0] MON1 [7:4] MON2 [3:0] MON3 [7:4] MON4 [3:0] MON5 [7:4] MON6 [3:0] MON7 [7:4] MON8 [3:0] MON9 [7:4] MON10 [3:0] MON11 [7:4] MON12
______________________________________________________________________________________ 15
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers
Table 5. MON_ and EN_OUT_ Assignment Registers (continued)
REGISTER
ADDRESS
84h 284h
85h 285h
86h 286h
87h 287h
88h 288h
89h 289h
FLASH
ADDRESS
BIT RANGE DESCRIPTION
[3:0] EN_OUT1 [7:4] EN_OUT2 [3:0] EN_OUT3 [7:4] EN_OUT4 [3:0] EN_OUT5 [7:4] EN_OUT6 [3:0] EN_OUT7 [7:4] EN_OUT8 [3:0] EN_OUT9 [7:4] EN_OUT10 [3:0] EN_OUT11 [7:4] EN_OUT12
MAX16065/MAX16066
Table 6. MON_ and EN_OUT_ Slot Assignment Codes
SLOT ASSIGNMENT
CODE MON_ DESCRIPTION
0000 Not assigned 0001 Slot 1 0010 Slot 2 0011 Slot 3 0100 Slot 4 0101 Slot 5 0110 Slot 6 0111 Slot 7 1000 Slot 8 1001 Slot 9 1010 Slot 10 1011 Slot 11 1100 Slot 12 1101 Monitoring only, primary sequence 1110 Monitoring only, secondary sequence 1111 Not assigned
General-purpose input (EN_OUT9–EN_OUT12 only)
General-purpose output (EN_OUT9–EN_OUT12 only)
OUT_ DESCRIPTION
Not assigned
Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8
Slot 9 Slot 10 Slot 11 Slot 12
Not assigned
16 _____________________________________________________________________________________
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 7. t
Delay Settings
FAULT
CODE DELAY
0000 0001 0010 0011 0100 0101 1ms 0110 1.5ms 0111 2.5ms 1000 4ms 1001 6ms 1010 10ms 1011 15ms 1100 25ms 1101 40ms 1110 60ms 1111 100ms
120Fs 150Fs 250Fs 380Fs 600Fs
MAX16065/MAX16066
To power down the secondary sequence group, drive EN2 low or set r75h[1] to ‘0’. The secondary reverse power-down sequence will start at Slot 12 and end at the primary sequence monitoring mode state at which point only the slots assigned to the primary sequence are active.
Voltage/Current Monitoring
The MAX16065/MAX16066 feature an internal 10-bit ADC that monitors the MON_ voltage inputs. An internal multiplexer cycles through each of the enabled inputs, taking less than 40Fs for a complete monitoring cycle. Each acquisition takes approximately 3.2Fs. At each multiplexer stop, the 10-bit ADC converts the analog input to a digital result and stores the result in a regis­ter. ADC conversion results are stored in registers r00h to r1Ah (see Table 10). Use the SMBus or JTAG serial interface to read ADC conversion results.
The MAX16065 provides twelve inputs, MON1–MON12, for voltage monitoring. The MAX16066 provides eight inputs, MON1–MON8, for voltage monitoring. Each input
voltage range is programmable in registers r43h to r45h (see Table 9). When MON_ configuration registers are set to ’11,’ MON_ voltages are not monitored, and the multiplexer does not stop at these inputs, decreasing the total cycle time. These inputs cannot be configured to trigger fault conditions.
The three programmable thresholds for each monitored voltage include an overvoltage, an undervoltage, and a secondary warning threshold that can be set in r73h[3] to be either an undervoltage or overvoltage threshold. See the Faults section for more information on setting overvoltage and undervoltage thresholds. All voltage thresholds are 8 bits wide. The 8 MSBs of the 10-bit ADC conversion result are compared to these overvoltage and undervoltage thresholds.
For any undervoltage or overvoltage condition to be monitored and any faults detected, the MON_ input must be assigned to a sequence order or set to monitoring mode as described in the Sequencing section.
Inputs that are not enabled are not converted by the ADC; they contain the last value acquired before that channel was disabled.
The ADC conversion result registers are reset to 00h at boot-up. These registers are not reset when a reboot command is executed.
Configure the MAX16065/MAX16066 for differential mode in r46h (Table 9). The possible differential pairs
______________________________________________________________________________________ 17
12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers
are MON1/MON2, MON3/MON4, MON5/MON6, MON7/ MON8, MON9/MON10, MON11/MON12 with the first input always being at a higher voltage than the second. Use differential voltage sensing to eliminate voltage off­sets or measure supply current. See Figure 4. In differ­ential mode, the odd-numbered MON_ input measures the absolute voltage with respect to GND while the result of the even input is the difference between the odd and even inputs. See Figure 4 for the typical differential mea­surement circuit.
Internal Current-Sense Amplifier
The current-sense inputs, CSP/CSM, and a current­sense amplifier facilitate power monitoring (see Figure
5). The voltage on CSP relative to GND is also monitored by the ADC when the current-sense amplifier is enabled with r47h[0]. The conversion results are located in regis­ters r19h and r1Ah (see Table 10). There are two select­able voltage ranges for CSP set by r47h[1], see Table
8. Although the voltage can be monitored over SMBus
MAX16065/MAX16066
or JTAG, this voltage has no threshold comparators and cannot trigger any faults. Regarding the current-sense amplifier, there are four selectable ranges and the ADC output for a current-sense conversion is:
X
where X r18h, V
= (V
ADC
is the 8-bit decimal ADC result in register
ADC
is V
SENSE
CSP
x AV)/1.4V x (28 - 1)
SENSE
- V
and AV is the current-
CSM,
sense voltage gain set by r47h[3:2].
In addition, there are two programmable current-sense trip thresholds: primary overcurrent and secondary over­current. For fast fault detection, the primary overcurrent threshold is implemented with an analog comparator connected to the internal OVERC signal. The OVERC signal can be output on one of the GPIO_s. See the General-Purpose Inputs/Outputs section for configur­ing the GPIO_ to output the OVERC signal. The primary threshold is set by:
ITH = V
where ITH is the current threshold to be set, V threshold set by r47h[3:2], and R
CSTH/RSENSE
SENSE
is the
CSTH
is the value of
the sense resistor. See Table 8 for a description of r47h. OVERC depends only on the primary overcurrent thresh­old. The secondary overcurrent threshold is implement­ed through ADC conversions and digital comparison set by r6Ch. The secondary overcurrent threshold includes programmable time delay options located in r73h[6:5]. Primary and secondary current-sense faults are enabled/ disabled through r47h[0].
General-Purpose Inputs/Outputs
GPIO1–GPIO8 are programmable general-purpose inputs/outputs. GPIO1–GPIO8 are configurable as a manual reset input, a watchdog timer input and output, logic inputs/outputs, fault-dependent outputs. When pro­grammed as outputs, GPIO_s are open drain or push­pull. See Tables 12 and 13 for more detailed information on configuring GPIO1–GPIO8.
R
ODD
MAX16065 MAX16066
MON
S
ODD
LOAD
MON
EVEN
MON
POWER
SUPPLY
MON
POWER
SUPPLY
Figure 4. Differential Measurement Connections Figure 5. Current-Sense Amplifier
18 _____________________________________________________________________________________
EVEN
I
LOAD
R
SENSE
V
MON
LOAD
CS+
CS-
OVERC
*ADJUSTABLE BY r47h[1:0]
-
+
MAX16065
-
+
+
-
TO ADC MUX
*A
V
*V
CSTH
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 8. Overcurrent Primary Threshold and Current-Sense Control
REGISTER ADDRESS
47h 247h
73h 273h [6:5]
FLASH
ADDRESS
BIT
RANGE
[0]
[1]
[3:2]
DESCRIPTION
1 = Current sense is enabled 0 = Current sense is disabled
1 = CSP full-scale range is 14V 0 = CSP full-scale range is 7V
Overcurrent Primary Threshold and Current-Sense Gain Setting: 00 = 200mV threshold, AV = 6V/V 01 = 100mV threshold, AV = 12V/V 10 = 50mV threshold, AV = 24V/V 11 = 25mV threshold, AV = 48V/V
Overcurrent Secondary Threshold Deglitch: 00 = No delay 01 = 4ms 10 = 15ms 11 = 60ms
MAX16065/MAX16066
Table 9. ADC Configuration Registers
REGISTER ADDRESS
43h 243h
FLASH
ADDRESS
BIT RANGE DESCRIPTION
[1:0]
[3:2]
[5:4]
[7:6]
ADC1 Full-Scale Range: 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted
ADC2 Full-Scale Range: 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted
ADC3 Full-Scale Range: 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted
ADC4 Full-Scale Range: 00 = 5.6V 01 = 2.8V 10 = 1.4V 11 = Channel not converted
______________________________________________________________________________________ 19
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