Rainbow Electronics MAX1587A User Manual

General Description

The MAX1586/MAX1587 power-management ICs are
optimized for devices using Intel X-Scale™ micro­processors, including third-generation smart cell
phones, PDAs, internet appliances, and other portable
devices requiring substantial computing and multime­dia capability at low power.

The ICs integrate seven high-performance, low-operating­current power supplies along with supervisory and man­agement functions. Regulator outputs include three step­down DC-DC outputs, three linear regulators, and a
seventh always-on output. DC-DC converter outputs
power I/O, DRAM, and the CPU core. The I/O supply can
be preset to 3.3V or 3.0V, or can be adjusted to other val­ues. The DRAM supply on the MAX1586A and MAX1587A
is preset for 1.8V or 2.5V, while the MAX1586B DRAM
supply is preset for 3.3V or 2.5V. The DRAM supply on all
parts can also be adjusted with external resistors. The
CPU core supply is serial programmed for dynamic volt­age management. Linear-regulated outputs are provided
for SRAM, PLL, and USIM supplies.

To minimize sleep-state quiescent current, critical
power supplies have bypass “sleep” LDOs that can be
activated to minimize battery drain when output current
is very low. Other functions include separate on/off con­trol for all DC-DC converters, low-battery and dead-bat­tery detection, a reset and power-OK output, a backup­battery input, and a two-wire serial interface.

All DC-DC outputs use fast, 1MHz PWM switching and
small external components. They operate with fixed-fre­quency PWM control and automatically switch from
PWM to skip-mode operation at light loads to reduce
operating current and extend battery life. The core out­put is capable of operating in forced-PWM mode at all
loads to minimize ripple and noise. A 2.6V to 5.5V input
voltage range allows 1-cell lithium-ion (Li+), 3-cell
NiMH, or a regulated 5V input. The MAX1587 is avail­able in a tiny 6mm x 6mm, 40-pin thin QFN package.
The MAX1586 features an additional linear regulator
(V6) for VCC_USIM and low-battery and dead- battery
comparators. The MAX1586 is available in a 7mm x
7mm, 48-pin thin QFN package.

Applications

PDA, Palmtop, and Wireless Handhelds
Third-Generation Smart Cell Phones
Internet Appliances and Web-Books

Features

♦ Six Regulators in One Package:

Step-Down DC-DC for I/O at 1.3A
Step-Down DC-DC for Memory at 0.9A
Step-Down Serial-Programmed DC-DC for CORE
Three LDO Outputs for SRAM, PLL, and USIM
Always-On Output for VCC_BATT

♦ Low Operating Current

60µA in Sleep Mode (Sleep LDOs On)
130µA with DC-DCs On (Core Off)
200µA All Regulators On, No Load
5µA Shutdown Current

♦ Optimized for X-Scale Processors
♦ Backup-Battery Input
♦ Separate ON Controls for Any Desired Power

Sequencing

♦ 1MHz PWM Switching Allows Small External

Components

♦ Tiny 6mm x 6mm, 40-Pin and 7mm x 7mm, 48-Pin

Thin QFN Packages

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-I

Q

PMICs with

Dynamic Core for PDAs and Smart Phones

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

MAX1586
MAX1587

V1

V2

V3

V4

V5

V6

V7

VCC_IO 3.3V

VCC_MEM 2.5V

VCC_CORE

0.8V TO 1.3V

VCC_USIM
0V, 1.8V, 3.0V

MAIN BATTERY

VCC_PLL 1.3V

VCC_SRAM 1.1V

BACKUP
BATTERY

IN

BKBT

MR
RSO

VCC_BATT

POK

nRESET

nVCC_FAULT

SYS_EN

PWR_EN

ON1-2

ON3-6

nBATT_FAULT

DBO

Simplified Functional Diagram

19-3089; Rev 1; 12/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Pin Configurations appear at end of data sheet.

PART

PIN-PACKAGE

MAX1586AETM

48 Thin QFN 7mm x 7mm

MAX1586BETM

48 Thin QFN 7mm x 7mm

MAX1587AETL

40 Thin QFN 6mm x 6mm

X-Scale is a trademark of Intel Corp.

TEMP RANGE

-40°C to +85°C

-40°C to +85°C

-40°C to +85°C

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VIN= 3.6V, V

BKBT

= 3.0V, V

LBI

= 1.1V, V

DBI

= 1.35V, circuit of Figure 5, TA = 0°C to +85°C, unless otherwise noted. Typical values

are at T

A

= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

IN, IN45, IN6, MR, LBO, DBO, RSO, POK, SCL, SDA,

BKBT, V7, SLP, SRAD, PWM3 to GND...............-0.3V to +6V

REF, CC_, ON_, FB_, DBI, LBI, V1, V2, RAMP, BYP,

MR to GND ...........................................-0.3V to (V

IN

+ 0.3V)

PV1, PV2, PV3, SLPIN to IN...................................-0.3V to +0.3V

V4, V5 to GND ..........................................-0.3V to (V

IN45

+ 0.3V)

V6 to GND ..................................................-0.3V to (V

IN6

+ 0.3V)

PV1 to PG1 ............................................................-0.3V to +6.0V

PV2 to PG2 ............................................................-0.3V to +6.0V

PV3 to PG3 ............................................................-0.3V to +6.0V

LX1 Continuous Current....................................-1.30A to +1.30A

LX2 Continuous Current........................................-0.9A to +0.9A

LX3 Continuous Current........................................-0.5A to +0.5A

PG1, PG2, PG3 to GND.........................................-0.3V to +0.3V

V1, V2, V4, V5, V6 Output Short-Circuit Duration.......Continuous

Continuous Power Dissipation (T

A

= +70°C)
6mm x 6mm 40-Pin Thin QFN

(derate 26.3mW/°C above +70°C)...........................2105mW

7mm x 7mm 48-Pin Thin QFN

(derate 26.3mW/°C above +70°C)...........................2105mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

PARAMETER CONDITIONS

UNITS

PV1, PV2, PV3, SLPIN, IN Supply
Voltage Range

PV1, PV2, PV3, IN, and SLPIN must connect together
externally

V

IN45, IN6 Supply Voltage Range

V

V

IN

rising

IN Undervoltage-Lockout (UVLO)
Threshold

V

IN

falling

V

32

Only V7 on, VIN below

5

REG1 and REG2 on in
switch mode, REG3 off

60

REG1 and REG2 on in
sleep mode, REG3 off

60

Quiescent Current

No load (I

PV1

+

I

PV2

+ I

PV3

+ I

IN

+

I

SLPIN

+ I

IN45

+

I

IN6

)

All REGs on

µA

ON1 = 0 4

BKBT Input Current

ON1 = IN

µA

REF Output Voltage 0 to 10µA load

V

SYNCHRONOUS-BUCK PWM REG1

FB1 = GND, 3.6V ≤ V

PV1

≤ 5.5V, load = 0 to 1200mA

REG1 Voltage Accuracy

FB1 = IN, 3.6V ≤ V

PV1

≤ 5.5V, load = 0 to 1200mA

V

FB1 Voltage Accuracy

FB1 used with external resistors, 3.6V ≤ V

PV1

≤ 5.5V,

load = 0 to 1200mA

V

FB1 Input Current FB1 used with external resistors

nA

Error-Amplifier Transconductance Referred to FB 87 µS

Load = 800mA

Dropout Voltage (Note 1)

Load = 1300mA

mV

MIN TYP MAX

2.6 5.5

2.4 5.5

2.25 2.40 2.55

2.200 2.35 2.525

MAX1586

DBI threshold V

IN

= 3.0V

MAX1587
MAX1586 130
MAX1587 130
MAX1586
MAX1587
MAX1586 225
MAX1587 200

0.8

1.2375 1.25 1.2625

3.25 3.3 3.35

2.955 3.0 3.045

1.225 1.25 1.275

180 280
293 450

100

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-I

Q

PMICs with

Dynamic Core for PDAs and Smart Phones

_______________________________________________________________________________________ 3

PARAMETER CONDITIONS

UNITS

I

LX1

= -180mA

P-Channel On-Resistance

I

LX1

= -180mA, V

PV1

= 2.6V

Ω

I

LX1

= 180mA

N-Channel On-Resistance

I

LX1

= 180mA, V

PV1

= 2.6V

Ω

Current-Sense Transresistance

V/A

P-Channel Current-Limit Threshold

A

PWM Skip-Mode Transition Load
Current

Decreasing load current (Note 2) 30 mA

OUT1 Maximum Output Current 2.6V ≤ V

PV1

≤ 5.5V (Note 3)

A

LX1 Leakage Current V

PV1

= 5.5V, LX1 = GND or PV1, V

ON1

= 0V

µA

SYNCHRONOUS-BUCK PWM REG2

FB2 = GND, 3.6V ≤ V

PV2

≤ 5.5V, load = 0 to 900mA

MAX1586A, MAX1587A, FB2 = IN, 3.6V ≤ V

PV2

≤ 5.5V,

load = 0 to 900mA

REG2 Voltage Accuracy

MAX1586B, FB2 = IN, 3.6V ≤ V

PV2

≤ 5.5V,

load = 0 to 900mA

V

FB2 Voltage Accuracy

FB2 used with external resistors, 3.6V ≤ V

PV2

≤ 5.5V,

load = 0 to 900mA

V

FB2 Input Current FB2 used with external resistors, V

FB2

= 1.25V

nA
Error-Amplifier Transconductance Referred to FB 87 µS
Dropout Voltage Load = 900mA (Note 1)

mV

I

LX2

= -180mA

P-Channel On-Resistance

I

LX2

= -180mA, VPV2 = 2.6V

Ω

I

LX2

= 180mA

N-Channel On-Resistance

I

LX2

= 180mA, VPV2 = 2.6V

Ω

Current-Sense Transresistance

V/A

P-Channel Current-Limit Threshold

A

PWM Skip-Mode Transition Load
Current

Decreasing load current (Note 2) 30 mA

OUT2 Maximum Output Current 2.6V ≤ V

PV2_

≤ 5.5V (Note 3)

A

LX2 Leakage Current V

PV2_

= 5.5V, LX2 = GND or PV2, V

ON2

= 0V

µA

SYNCHRONOUS-BUCK PWM REG3

REG3 from 1.3V to 1.475V, 2.6V ≤ V

PV3

_ ≤ 5.5V,

load = 0 to 400mA

REG3 Output Voltage Accuracy

REG3 from 0.70V to 1.275V, 2.6V ≤ V

PV3

_≤ 5.5V,

load = 0 to 500mA

-2

%

Error-Amplifier Transconductance 68 µS

ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.6V, V

BKBT

= 3.0V, V

LBI

= 1.1V, V

DBI

= 1.35V, circuit of Figure 5, TA = 0°C to +85°C, unless otherwise noted. Typical values

are at T

A

= +25°C.)

MIN TYP MAX

0.18 0.3

0.21 0.35

0.13 0.225

0.15 0.25

0.5

-1.55 -1.80 -2.10

1.20

-20 +0.1 +20

2.463 2.5 2.537

1.773 1.8 1.827

3.25 3.3 3.35

1.231 1.25 1.269

243 380

0.225 0.375

0.26 0.425

0.15 0.25

0.17 0.275

0.75

-1.1 -1.275 -1.50

0.9

-10 +0.1 +10

-1.5 +1.5

100

+2

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones

4 _______________________________________________________________________________________

PARAMETER CONDITIONS

UNITS

I

LX3

= -180mA

P-Channel On-Resistance

I

LX2

= -180mA, V

PV3

= 2.6V

Ω

I

LX3

= 180mA

N-Channel On-Resistance

I

LX3

= 180mA, V

PV3

= 2.6V

Ω

Current-Sense Transresistance

V/A

P-Channel Current-Limit Threshold

A

PWM Skip-Mode Transition Load
Current

Decreasing load current (Note 2) 30 mA

OUT3 Maximum Output Current 2.6V ≤ V

PV3_

≤ 5.5V (Note 3)

A

LX3 Leakage Current V

PV3_

= 5.5V, LX3 = GND or PV2, V

ON3

= 0V

µA

LDOS V4, V5, V6, V1 SLEEP, V2 SLEEP, AND V7 OUTPUT

V4, V5, V6, V1 SLEEP, V2 SLEEP
Output Current

mA

V7 Output Current

mA

REG4 Output Voltage Load = 0.1 to 35mA

V

REG4 Noise With 1µF C

OUT

and 0.01µF C

BYP

15

µVRMS

REG5 Output Voltage Load = 0.1mA to 35mA

V

IN45, IN6 Input Voltage Range

V

0

1.8V setting, load = 0.1mA to 35mA

2.5V setting, load = 0.1mA to 35mA

REG6 Output Voltage (POR Default
to 0V, Set by Serial Input)

3.0V setting, load = 0.1mA to 35mA

V

V1 on and in regulation

V7 Output Voltage

V1 off

V

V1 and V2 SLEEP Output Voltage
Accuracy

Set to same output voltage as REG1 and REG2

%

V1 and V2 SLEEP Dropout Voltage LOAD = 20mA 75

mV

V6 Dropout Voltage M AX 1586 3V m od e, l oad = 30m A, 2.5V m od e, l oad = 30m A

mV

V7 Switch Voltage Drop LOAD = 20mA, V

BKBT

= V

V1

= 3.0V

mV

V4, V5, V6 Output Current Limit

90 mA

BKBT Leakage 1 µA

OSCILLATOR

PWM Switching Frequency

1

MHz

SUPERVISORY/MANAGEMENT FUNCTIONS

Rising

97

POK Trip Threshold (Note 4)

Falling

%

ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.6V, V

BKBT

= 3.0V, V

LBI

= 1.1V, V

DBI

= 1.35V, circuit of Figure 5, TA = 0°C to +85°C, unless otherwise noted. Typical values

are at T

A

= +25°C.)

MIN TYP MAX

0.225 0.375

0.26 0.425

0.15 0.25

0.17 0.275

1.25

-0.60 -0.7 -0.85

MAX1586

0V setti ng ( ei ther ON 6 l ow or ser i al p r og r am m ed )

0.5

-10 +0.1 +10

35

30

1.261 1.3 1.339

1.067 1.1 1.133

2.4 5.5

1.746 1.8 1.854

2.425 2.5 2.575

2.91 3.0 3.09

-3.0 +3.0

V

V1

V

BKBT

110 200
100 200

40

0.93

92 94.75

88.5 90.5 92.5

150

1.07

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-I

Q

PMICs with

Dynamic Core for PDAs and Smart Phones

_______________________________________________________________________________________ 5

PARAMETER CONDITIONS

MIN

TYP

MAX

UNITS

LBI = IN (for preset)

LBI Threshold (Falling)

MAX1586 hysteresis is
5% (typ)

With resistors at LBI

V

DBI = IN (for preset)

DBI Threshold (Falling)

MAX1586 hysteresis is
5% (typ)

With resistors at LBI

V

RSO Threshold (Falling) Voltage on REG7, hysteresis is 5% (typ)

V

RSO Deassert Delay

70 ms

LBI Input Bias Current MAX1586

nA
DBI Input Bias Current MAX1586 15 50 nA
Thermal-Shutdown Temperature TJ rising

°C

Thermal-Shutdown Hysteresis 15 °C

LOGIC INPUTS AND OUTPUTS

LBO, DBO, POK, RSO, SDA Output
Low Level

2.6V ≤ V7

≤ 5.5V, sinking 1mA

V

LBO, DBO, POK, RSO Output Low
Level

V7

= 1V, sinking 100µA

V

LBO, DBO, POK, RSO Output-High
Leakage Current

Pin

= 5.5V

µA

ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input High Level

2.6V ≤ V

IN

≤ 5.5V

V

ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Low Level

2.6V ≤ V

IN

≤ 5.5V

V

ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Leakage Current

Pin = GND, 5.5V 1 1 µA

SERIAL INTERFACE

Clock Frequency

kHz

Bus-Free Time Between START and
STOP

µs

H ol d Ti m e Rep eated S TART C ond i ti on

µs

CLK Low Period

µs

CLK High Period

µs

S etup Ti m e Rep eated S TART C ond i ti on

µs
DATA Hold Time 0µs
DATA Setup Time

ns
Maximum Pulse Width of Spikes that

Must be Suppressed by the Input

Filter of Both DATA and CLK Signals

50 ns

Setup Time for STOP Condition

µs

ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.6V, V

BKBT

= 3.0V, V

LBI

= 1.1V, V

DBI

= 1.35V, circuit of Figure 5, TA = 0°C to +85°C, unless otherwise noted. Typical values

are at T

A

= +25°C.)

3.51 3.6 3.69

0.98 1.00 1.02

3.024 3.15 3.276

1.208 1.232 1.256

2.25 2.41 2.56
61 65.5

-50 -5

+160

1.6

1.3

0.6

1.3

0.6

0.6

100

0.6

0.4

0.4

0.2

0.4

400

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones

6 _______________________________________________________________________________________

PARAMETER CONDITIONS

MIN

MAX

UNITS

PV1, PV2, PV3, SLPIN, IN Supply
Voltage Range

PV1, PV2, PV3, IN, and SLPIN must connect together
externally

V

IN45, IN6 Supply Voltage Range

V

V

IN

rising

IN Undervoltage-Lockout (UVLO)
Threshold

V

IN

falling

V

SYNCHRONOUS-BUCK PWM REG1

FB1 = GND, 3.6V ≤ V

PV1

≤ 5.5V, load = 0 to 1300mA

REG1 Voltage Accuracy

FB1 = IN, 3.6V ≤ V

PV1

≤ 5.5V, load = 0 to 1300mA

V

FB1 Voltage Accuracy

FB1 used with external resistors, 3.6V ≤ V

PV1

≤ 5.5V,

load = 0 to 1300mA

V

FB1 Input Current FB1 used with external resistors

nA

Load = 800mA (Note 1)

Dropout Voltage

Load = 1300mA (Note 1)

mV

I

LX1

= -180mA

P-Channel On-Resistance

I

LX1

= -180mA, V

PV1

= 2.6V

Ω

I

LX1

= 180mA

N-Channel On-Resistance

I

LX1

= 180mA, V

PV1

= 2.6V

Ω

P-Channel Current-Limit Threshold

A

OUT1 Maximum Output Current 2.6V ≤ V

PV1

≤ 5.5V (Note 3)

A

LX1 Leakage Current V

PV1

= 5.5V, LX1 = GND or PV1, V

ON1

= 0V

µA

SYNCHRONOUS-BUCK PWM REG2

FB2 = GND, 3.6V ≤ V

PV2

≤ 5.5V, load = 0 to 900mA

MAX1586A, MAX1587A, FB2 = IN, 3.6V ≤ V

PV2

≤ 5.5V,

load = 0 to 900mA

REG2 Voltage Accuracy

MAX1586B, FB2 = IN, 3.6V ≤ V

PV2

≤ 5.5V,

load = 0 to 900mA

V

FB2 Voltage Accuracy

FB2 used with external resistors, 3.6V ≤ V

PV2

≤ 5.5V,

load = 0 to 900mA

V

FB2 Input Current FB2 used with external resistors, V

FB2

= 1.25V

nA

Dropout Voltage Load = 900mA (Note 1)

mV

I

LX2

= -180mA

P-Channel On-Resistance

I

LX2

= -180mA, V

PV2

= 2.6V

Ω

I

LX2

= -180mA

N-Channel On-Resistance

I

LX2

= -180mA, V

PV2

= 2.6V

Ω

P-Channel Current-Limit Threshold

A

OUT2 Maximum Output Current 2.6V ≤ V

PV2_

≤ 5.5V (Note 3)

A

LX2 Leakage Current V

PV2

= 5.5V, LX2 = GND or PV2, V

ON2

= 0V

µA

ELECTRICAL CHARACTERISTICS

(VIN= 3.6V, V

BKBT

= 3.0V, V

LBI

= 1.1V, V

DBI

= 1.35V, circuit of Figure 5, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)

2.6 5.5

2.4 5.5

2.25 2.55

2.200 2.525

3.25 3.35

2.955 3.045

1.231 1.269

100
280
450

0.3

0.35

0.225

0.25

-1.55 -2.10

1.30

-10 +10

2.463 2.537

1.773 1.827

3.25 3.35

1.231 1.269

-1.1 -1.50

0.9

-10 +10

100
380

0.375

0.425

0.25

0.275

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-I

Q

PMICs with

Dynamic Core for PDAs and Smart Phones

_______________________________________________________________________________________ 7

PARAMETER CONDITIONS

MIN

MAX

UNITS

SYNCHRONOUS-BUCK PWM REG3

REG3 from 1.3V to 1.475V, 2.6V ≤ V

PV3_

≤ 5.5V,

load = 0 to 500mA

REG3 Output Voltage Accuracy

REG3 from 0.70V to 1.275V, 2.6V ≤ V

PV3_

≤ 5.5V, load = 0

to 500mA

-2

%

I

LX3

= -180mA

P-Channel On-Resistance

I

LX2

= -180mA, V

PV3

= 2.6V

Ω

I

LX3

= 180mA

N-Channel On-Resistance

I

LX3

= 180mA, V

PV3

= 2.6V

Ω

P-Channel Current-Limit Threshold

A

OUT3 Maximum Output Current 2.6V ≤ V

PV3_

≤ 5.5V (Note 3)

A

LX3 Leakage Current V

PV3

= 5.5V, LX3 = GND or PV2, V

ON3

= 0V

µA

LDOs V4, V5, V6, V1 SLEEP, V2 SLEEP, AND V7 OUTPUT

V4, V5, V6, V1 SLEEP, V2 SLEEP
Output Current

mA

V7 Output Current

mA

REG4 Output Voltage Load = 0.1mA to 35mA

V

REG5 Output Voltage Load = 0.1mA to 35mA

V

IN45, IN6 Input Voltage Range

V

1.8V setting, load = 0.1mA to 35mA

2.5V setting, load = 0.1mA to 35mA

REG6 Output Voltage (POR Default
to 0V, Set by Serial Input)

MAX1586

3.0V setting, load = 0.1mA to 35mA

V

V1 and V2 SLEEP Output Voltage
Accuracy

Set to same output voltage as REG1 and REG2

%

V1 and V2 SLEEP Dropout Voltage Load = 20mA

mV

V6 Dropout Voltage

mV

V7 Switch Voltage Drop Load = 20mA, V

BKBT

= V

V1

= 3.0V

mV

V4, V5, V6 Output Current Limit

mA

BKBT Leakage 1 µA

OSCILLATOR

PWM Switching Frequency

MHz

SUPERVISORY/MANAGEMENT FUNCTIONS

Rising

97

POK Trip Threshold (Note 4)

Falling

%

LBI = IN (for preset)

LBI Threshold (Falling)

MAX1586,
hysteresis is 5% (typ)

With resistors at LBI

V

DBI = IN (for preset)

DBI Threshold (Falling)

MAX1586,
hysteresis is 5% (typ)

With resistors at LBI

V

RSO Threshold (Falling) Voltage on REG7, hysteresis is 5% (typ)

V

ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.6V, V

BKBT

= 3.0V, V

LBI

= 1.1V, V

DBI

= 1.35V, circuit of Figure 5, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)

M AX 1586 3V m od e, l oad = 30m A; 2.5V m od e, l oad = 30m A 200

-1.5 +1.5

-0.60 +0.85

0.4

-10 +10

35

30

1.254 1.346

1.061 1.139

2.4 5.5

1.737 1.863

2.412 2.588

2.895 3.105

-3.5 +3.5

40

0.93 1.07

92

88.5 92.5

3.51 3.69

0.98 1.02

2.993 3.307

1.208 1.256

2.25 2.60

+2

0.375

0.425

0.25

0.275

150

200

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones

8 _______________________________________________________________________________________

PARAMETER CONDITIONS

MIN

MAX

UNITS

RSO Deassert Delay

69 ms

LBI Input Bias Current MAX1586

nA

DBI Input Bias Current MAX1586 75 nA

LOGIC INPUTS AND OUTPUTS

LBO, DBO, POK, RSO, SDA Output
Low Level

2.6V ≤ V7

≤ 5.5V, sinking 1mA

V

LBO, DBO, POK, RSO, SDA Output
Low Level

V7

= 1V, sinking 100µA

V

LBO, DBO, POK, RSO Output-High
Leakage Current

Pin

= 5.5V

µA

ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input High Level

2.6V ≤ V

IN

≤ 5.5V

V

ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Low Level

2.6V ≤ V

IN

≤ 5.5V

V

ON_, SCL, SDA, SLP, PWM3, MR,
SRAD Input Leakage Current

Pin = GND, 5.5V 1 1 µA

SERIAL INTERFACE

Clock Frequency

kHz

Bus-Free Time Between START and
STOP

µs

Hold Time Repeated START
Condition

µs

CLK Low Period

µs

CLK High Period

µs

Setup Time Repeated START
Condition

µs

DATA Hold Time 0µs
DATA Setup Time

ns

Setup Time for STOP Condition

µs

ELECTRICAL CHARACTERISTICS (continued)

(VIN= 3.6V, V

BKBT

= 3.0V, V

LBI

= 1.1V, V

DBI

= 1.35V, circuit of Figure 5, TA = -40°C to +85°C, unless otherwise noted.) (Note 5)

62

-50

1.6

0.4

0.4

0.2

0.4

1.3

0.6

1.3

0.6

0.6

100

0.6

400

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-I

Q

PMICs with

Dynamic Core for PDAs and Smart Phones

_______________________________________________________________________________________ 9

Note 1: Dropout voltage is guaranteed by the P-channel switch resistance and assumes a maximum inductor resistance of 45mΩ.
Note 2: The PWM-skip-mode transition has approximately 10mA of hysteresis.
Note 3: The maximum output current is guaranteed by the following equation:

where:

and R

N

= N-channel synchronous rectifier R

DS(ON)

RP = P-channel power switch R

DS(ON)

RL = external inductor ESR
I

OUT(MAX)

= maximum required load current
f = operating frequency minimum
L = external inductor value
I

LIM

can be substituted for I

OUT(MAX)

(desired) when solving for D. This assumes that the inductor ripple current is

small relative to the absolute value.

Note 4: POK only indicates the status of supplies that are enabled (except V7). When a supply is turned off, POK does not trigger

low. When a supply is turned on, POK immediately goes low until that supply reaches regulation. POK is forced low when all
supplies (except V7) are disabled.

Note 5: Specifications to -40°C are guaranteed by design, not production tested.

D

VI RR

VI RR

OUT OUT MAX N L

IN OUT MAX N P

=

++

+ −

()

()

()

()

I

I

VD

xfxL

RR

D

xfxL

OUT

LIM

OUT

NL

max

()

()

()

=

−

−

++

−

1

2

1

1

2

ELECTRICAL CHARACTERISTICS (continued)

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones

10 ______________________________________________________________________________________

Typical Operating Characteristics

(Circuit of Figure 5, V

IN

= 3.6V, TA = +25°C, unless otherwise noted.)

100

0.1 1 10 100 1000 10,000

90

80

70

60

50

40

REG1 3.3V OUTPUT EFFICIENCY

vs. LOAD CURRENT

MAX1586A/86B/87A toc01

LOAD CURRENT (mA)

EFFICIENCY (%)

VIN = 3.6V

VIN = 4.0V

VIN = 5.0V

100

40

0.1 10 10011000

REG2 2.5V OUTPUT EFFICIENCY

vs. LOAD CURRENT

MAX1586A/86B/87A toc02

LOAD CURRENT (mA)

EFFICIENCY (%)

50

60

70

80

90

VIN = 3.6V

VIN = 4.0V

VIN = 5.0V

100

40

0.1 10 10011000

REG3 1.3V OUTPUT EFFICIENCY

vs. LOAD CURRENT

MAX1586A/86B/87A toc03

LOAD CURRENT (mA)

EFFICIENCY (%)

50

60

70

80

90

VIN = 3.6V

VIN = 4.0V VIN = 5.0V

100

40

0.1 10 10011000

REG3 1.3V OUTPUT WITH FORCED-PWM

EFFICIENCY vs. LOAD CURRENT

MAX1586A/86B/87A toc04

LOAD CURRENT (mA)

EFFICIENCY (%)

50

60

70

80

90

VIN = 3.6V

VIN = 5.0V

VIN = 4.0V

REG1 SLEEP LDO 3.3V OUTPUT

EFFICIENCY vs. LOAD CURRENT

MAX1586A/86B/87A toc05

LOAD CURRENT (mA)

EFFICIENCY (%)

100

40

50

60

70

80

90

0.1 1 10

VIN = 3.6V

VIN = 4.0V

VIN = 5.0V

REG2 SLEEP LDO 2.5V OUTPUT

EFFICIENCY vs. LOAD CURRENT

MAX1586A/86B/87A toc06

LOAD CURRENT (mA)

EFFICIENCY (%)

90

30

40

50

60

70

80

0.1 1 10

VIN = 3.6V VIN = 4.0V

VIN = 5.0V

0

20

140

100

180

220

021345

QUIESCENT CURRENT
vs. SUPPLY VOLTAGE

MAX1586A/86B/87A toc07

INPUT VOLTAGE (V)

INPUT CURRENT (µA)

BKBT BIASED AT 3.6V

V1, V2, AND V3 ON

V1 AND V2 ON

V1 ON

V1 AND V2 SLEEP

V1 SLEEP

ALL BUT V7 OFF

200

160

40

60

80

120

0

100

50

200

150

250

300

0400200 600 800 1000 1200

DROPOUT VOLTAGE
vs. LOAD CURRENT

MAX1586A/86B/87A toc08

LOAD CURRENT (mA)

DROPOUT VOLTAGE (mV)

REG1 3.3V OUTPUT

-100

0

-50

100

50

150

200

0 400200 600 800 1000 1200

CHANGE IN OUTPUT VOLTAGE

vs. LOAD CURRENT

MAX1586A/86B/87A toc09

LOAD CURRENT (mA)

CHANGE IN OUTPUT VOLTAGE (mV)

VIN = 3.6V

REG1 3.3V OUTPUT

REG3 1.3V OUTPUT

REG2 2.5V OUTPUT

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-I

Q

PMICs with

Dynamic Core for PDAs and Smart Phones

______________________________________________________________________________________ 11

960

1000

880

920

1040

2.5 3.53.0 4.0 4.5 5.0 5.5

SWITCHING FREQUENCY

vs. SUPPLY VOLTAGE

MAX1586A/86B/87A toc10

INPUT VOLTAGE (V)

SWITCHING FREQUENCY (kHz)

TA = -40°C

TA = +85°C

TA = +25°C

1.225

1.265

1.260

1.255

1.250

1.245

1.240

1.235

1.230

-40 -15 10 35 60 85

REFERENCE VOLTAGE

vs. TEMPERATURE

MAX1586A/86B/87A toc11

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

REG1 SWITCHING WAVEFORMS

WITH 800mA LOAD

MAX1586A/86B/87A toc12

400ns/div

0

0

500mA/div

10mv/div
AC-COUPLED

2V/div

V

LX1

I

L1

V1

REG1 SWITCHING WAVEFORMS

WITH 10mA LOAD

MAX1586A/86B/87A toc13

20µs/div

0

0

500mA/div

50mv/div
AC-COUPLED

2V/div

V

LX1

V1

I

L1

REG3 SWITCHING WAVEFORMS

WITH 250mA LOAD

MAX1586A/86B/87A toc14

400ns/div

0

0

500mA/div

10mv/div
AC-COUPLED

2V/div

V3

I

L3

V

LX3

REG3 PULSE-SKIP SWITCHING

WAVEFORMS WITH 10mA LOAD

MAX1586A/86B/87A toc15

10µs/div

0

0

500mA/div

10mv/div
AC-COUPLED

2V/div

V

LX3

V3

I

L3

Typical Operating Characteristics (continued)

(Circuit of Figure 5, V

IN

= 3.6V, TA = +25°C, unless otherwise noted.)

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones

12 ______________________________________________________________________________________

Typical Operating Characteristics (continued)

(Circuit of Figure 5, V

IN

= 3.6V, TA = +25°C, unless otherwise noted.)

PWR_EN STARTUP WAVEFORMS

MAX1586A/86B/87A toc19

1ms/div

2V/div

2V/div

2V/div

2V/div

2V/div

V5

V4

V3

V

EN3

AND

V

EN45

V

POK

REG1 LOAD-TRANSIENT RESPONSE

MAX1586A/86B/87A toc20

200µs/div

0A

V1
100mV/div
AC-COUPLED

I

LOAD1

200mA/div

REG2 LOAD-TRANSIENT RESPONSE

MAX1586A/86B/87A toc21

200µs/div

0A

V2
100mV/div
AC-COUPLED

I

LOAD2

200mA/div

REG3 FORCED-PWM SWITCHING

WAVEFORMS WITH 10mA LOAD

MAX1586A/86B/87A toc16

400ns/div

0mA

0V

500mA/div

10mv/div
AC-COUPLED

2V/div

V

LX3

V3

I

L3

V7 AND RSO

STARTUP WAVEFORMS

MAX1586A/86B/87A toc17

10ms/div

0V

2V/div

0V

2V/div

0V

2V/div

RSO

V

IN

V7

SYS_EN STARTUP WAVEFORMS

MAX1586A/86B/87A toc18

2ms/div

2V/div

2V/div

2V/div

2V/div

V2

V1

V

EN1

AND
V

EN2

V

POK

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-I

Q

PMICs with

Dynamic Core for PDAs and Smart Phones

______________________________________________________________________________________ 13

Typical Operating Characteristics (continued)

(Circuit of Figure 5, V

IN

= 3.6V, TA = +25°C, unless otherwise noted.)

REG3 LOAD-TRANSIENT RESPONSE

MAX1586A/86B/87A toc22

200µs/div

0A

V3
100mV/div
AC-COUPLED

I

LOAD3

200mA/div

REG3 OUTPUT VOLTAGE CHANGING FROM

1.3V TO 1.0V WITH DIFFERENT VALUES OF C

RAMP

MAX1586A/86B/87A toc23

200µs/div

C

RAMP

= 2200pF

C

RAMP

= 1500pF

C

RAMP

= 1000pF

C

RAMP

= 330pF

REG6 USIM TRANSITIONS

MAX1586A/86B/87A toc24

10µs/div

0

500mV/div

V6

2.5V TO 3.0V

V6

1.8V TO 2.5V

V6

0 TO 1.8V

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones

14 ______________________________________________________________________________________

Pin Description

PIN

FUNCTION

1

Dual-Mode™, Low-Battery Input. Connect to IN to set the low-battery threshold to 3.6V (no resistors
needed). Connect LBI to a resistor-divider for an adjustable LBI threshold. When IN is below the set
threshold, LBO output switches low. LBO is deactivated and forced low when IN is below the dead-battery
(DBI) threshold and when all REGs are disabled.

2

REG1 Compensation Node. Connect a series resistor and capacitor from CC1 to GND to compensate the
regulation loop. See the Compensation and Stability section.

31

REG1 Feedback Input. Connect to IN to set V1 to 3.0V or connect FB1 to GND to set V1 to 3.3V. Connect
FB1 to external feedback resistors for other output voltages.

42

Input Connection for Backup Battery. This input can also accept the output of an external boost converter.

53V7

Also known as VCC_BATT. V7 is always active if main or backup power is present. It is the first regulator
that powers up. V7 has two states:

1) V7 tracks V1 if ON1 is high and V1 is in regulation.

2) V7 tracks V

BKBT

when ON1 is low or V1 is out of regulation.

64V1

REG1 Voltage-Sense Input. Connect directly to the REG1 output voltage. The output voltage is set by FB1
to either 3.0V, 3.3V, or adjustable with resistors.

75

Inp ut to V 1 and V 2 S l eep Reg ul ator s. The i np ut to the stand b y r eg ul ator s at V 1 and V 2. C onnect S LP IN to IN .

86V2

REG2 Voltage-Sense Input. Connect directly to the REG2 output voltage. The output voltage is set by FB2
to either 1.8V/2.5V (MAX1586A, MAX1587A), 3.3V/2.5V (MAX1586B), or adjustable with resistors.

97

REG2 Feedback Input. Connect to GND to set V2 to 2.5V on all devices. Connect FB2 to IN to set V2 to

1.8V on the MAX1586A and MAX1587A. Connect FB2 to IN to set V2 to 3.3V on the MAX1586B. Connect
FB2 to external feedback resistors for other voltages.

8

REG2 Compensation Node. Connect a series resistor and capacitor from CC2 to GND to compensate the
regulation loop. See the Compensation and Stability section.

9

Power-OK Output. Open-drain output that is low when any of the V1–V6 outputs are below their regulation
threshold. When all activated outputs are in regulation, POK is high impedance. POK maintains a valid low
output with V7 as low as 1V. POK does not flag an out-of-regulation condition while REG3 is transitioning
between voltages set by serial programming. POK also does not flag for any REG channel that has been
turned off; however, if all REG channels are off (V1–V6), then POK is forced low. If IN < UVLO, then POK is
low. POK is expected to connect to nVCC_FAULT.

Serial Clock Input

Serial Data Input. Data is read on the rising edge of SCL. Serial data programs the REG3 (core) and REG6
(VCC_USIM) voltage. REG3 and REG6 can be programmed even when off, but at least one of the ON_ pins
must be logic-high to activate the serial interface. On power-up, REG3 defaults to 1.3V and REG6 defaults
to 0V.

Force V3 to PWM at All Loads. Connect PWM3 to GND for normal operation (skip mode at light loads). Drive
or connect high for forced-PWM operation at all loads for V3 only.

Low-Battery Output. Open-drain output that goes low when IN is below the threshold set by LBI.

Dual Mode is a trademark of Maxim Integrated Products, Inc.

MAX
1586

10

11

NAME

MAX

1587

— LBI

40 CC1

FB1

BKBT

SLPIN

FB2

CC2

POK

12 10 SCL

13 11 SDA

14 12 PWM3

15 — LBO

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-I

Q

PMICs with

Dynamic Core for PDAs and Smart Phones

______________________________________________________________________________________ 15

Pin Description (continued)

PIN

MAX

1586

FUNCTION

16

REG2 Power Input. Bypass to PG2 with a 4.7µF or greater low-ESR capacitor. PV1, PV2, PV3, and IN must
connect together externally.

17

REG2 Switching Node. Connects to REG2 inductor.

18

REG2 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close to the IC as possible.

19

IN Main Battery Input. This input provides power to the IC.

20

V3 Ramp-Rate Control. A capacitor connected from RAMP to GND sets the rate-of-change when V3 is
changed. The output impedance of RAMP is 100kΩ. FB3 regulates to 1.28 x V

RAMP

.

21

Analog Ground

22

Reference Output. Output of the 1.25V reference. Bypass to GND with a 0.1µF or greater capacitor.

23

Low-Noise LDO Bypass. Low-noise bypass pin for V4 LDO. Connect a 0.01µF capacitor from BYP to GND.

24

Dead or Missing Battery Output. DBO is an open-drain output that goes low when IN is below the threshold
set by DBI. DBO does not deactivate any MAX1586/MAX1587 regulator outputs. DBO is expected to
connect to nBATT_FAULT on Intel CPUs.

25

On/Off Input for REG2. Drive high to turn on. When enabled, the REG2 output soft-starts. ON2 has
hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON1, ON2, and ON6 are connected to SYS_EN.

26

On/Off Input for REG4. Drive high to turn on. When enabled, the REG4 output activates. ON4 has hysteresis
so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that
ON4 is connected to PWR_EN.

27

V4 Also Known as VCC_PLL. 1.3V, 35mA linear-regulator output for PLL. Regulator input is IN45.

28

Power Input to V4 and V5 LDOs. Typically connected to V2, but can also connect to IN or another voltage
from 2.5V to V

IN

.

29

V5 Also Known as VCC_SRAM. 1.1V, 35mA linear-regulator output for CPU SRAM. Regulator input is IN45.

30

On/Off Input for REG5. Drive high to turn on. When enabled, the MAX1586/MAX1587 soft-starts the REG5
output. ON5 has hysteresis so an RC can be used to implement manual sequencing with respect to other
inputs. It is expected that ON5 is connected to PWR_EN.

31

REG3 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND
together at a single point as close to the IC as possible.

32

REG3 Switching Node. Connects to the REG3 inductor.

33

REG3 Power Input. Bypass to PG3 with a 4.7µF or greater low-ESR ceramic capacitor. PV1, PV2, PV3, and
IN must connect together externally.

34

On/Off Input for REG3 (Core). Drive high to turn on. When enabled, the REG3 output ramps up. ON3 has
hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON3 is driven from CPU SYS_EN.

NAME

MAX

1587

13 PV2

14 LX2

15 PG2

16

17 RAMP

18 GND
19 REF
20 BYP

— DBO

21 ON2

— ON4

23

24 IN45

25

— ON5

26 PG3

27 LX3

28 PV3

34 ON3

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones

16 ______________________________________________________________________________________

Pin Description (continued)

PIN

FUNCTION

Serial Address Bit. SRAD allows the serial address of the MAX1586/MAX1587 to be changed in case it
conflicts with another serial device. If SRAD = GND, A1 = 0. If SRAD = IN, A1 = 1.

Open-Drain Reset Output. Deasserts when V7 exceeds 2.55V (typ rising). Has 65ms delay before release.
RSO is expected to connect to nRESET on the CPU.

Manual Reset Input. A low input causes the RSO output to go low but impacts no other MAX1586/MAX1587
functions.

REG 3 Compensation Node. Connect a series resistor and capacitor from CC3 to GND to compensate the
regulation loop. See the Compensation and Stability section.

REG3 Feedback-Sense Input. Connect directly to the REG3 output voltage. Output voltage is set by the
serial interface.

On/Off Input for REG6. Drive high to turn on. When enabled, the REG6 output activates. ON6 has hysteresis
so an RC can be used to implement manual sequencing with respect to other inputs. It is expected that
ON1, ON2, and ON6 are connected to SYS_EN.

V6

Also known as VCC_USIM. Linear-regulator output. This voltage is programmable through the I

2

C™

interface to 0V, 1.8V, 2.5V, or 3.0V. The default voltage is 0V. REG6 is activated when ON6 is high.
Power Input to the V6 LDO. Typically connected to V1, but can also connect to IN.
REG1 Power Ground. Connect directly to a power-ground plane. Connect PG1, PG2, PG3, and GND

together at a single point as close to the IC as possible.
REG1 Switching Node. Connects to the REG1 inductor.
REG1 Power Input. Bypass to PG2 with a 4.7µF or greater low-ESR ceramic capacitor. PV1, PV2, PV3, and

IN must connect together externally.

On/Off Input for REG1. Drive high to turn on REG1. When enabled, the REG1 output soft-starts. ON1 has
hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. It is
expected that ON1, ON2, and ON6 connect to SYS_EN.

Sleep Input. SLP selects which regulators ON1 and ON2 turn on. SLP = high is normal operation (ON1 and
ON2 are the enables for the V1 and V2 DC-DC converters). SLP = low is sleep operation (ON1 and ON2 are
the enables for the V1 and V2 LDOs).

Dual-Mode, Dead-Battery Input. Connect DBI to IN to set the dead-battery falling threshold to 3.15V (no
resistors needed). Connect DBI to a resistor-divider for an adjustable DBI threshold.

On/Off Input for REG4 and REG5. Drive high to turn on. When enabled, the REG4 and REG5 outputs
activate. ON45 has hysteresis so an RC can be used to implement manual sequencing with respect to
other inputs. It is expected that ON45 is connected to PWR_EN.

EP

Exposed Metal Pad. Connect the exposed pad to ground. Connecting the exposed pad to ground does not
remove the requirement for proper ground connections to the appropriate ground pins.

I2C is a trademark of Philips Corp. Purchase of I2C components
from Maxim Integrated Products, Inc. or one of its sublicensed
Associated Companies, conveys a license under the Philips
I

2

C Patent Rights to use these components in an I2C system,

provided that the system conforms to the I

2

C Standard

Specification as defined by Philips.

MAX
1586

35 29 SRAD

36 30 RSO

37 31 MR

38 32 CC3

39 33 FB3

40 — ON6

41 —

42 — IN6

43 36 PG1

44 37 LX1

45 38 PV1

NAME

MAX

1587

46 35 ON1

47 39 SLP

48 — DBI

—22ON45

EP EP

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-I

Q

PMICs with

Dynamic Core for PDAs and Smart Phones

______________________________________________________________________________________ 17

MAIN

BATT

PV1

BATT

STEP-DOWN

PWM
REG1

SLEEP

LDO

LX1

PG1

V1

FB1

V2

FB2

PV2

ON

SLPININ

ON

STEP-DOWN

PWM
REG2

SLEEP

LDO

LX2

PG2

FB3

ON3

IN45

V4

BYP

ON4
ON5

V6

ON6

IN6

V5

PV3

TO BATT

TO V2

TO V2

TO BATT

PWM

LDO
REG

4

LDO
REG

5

STEP-DOWN

PWM
REG3

LX3

PG3

LDO
REG

6

V2, VCC_MEM

2.5V WITH FB2 = GND,

1.8V WITH FB2 = IN (MAX1586A, MAX1587A)

3.3V WITH FB2 = IN (MAX1586B)
OR ADJ WITH RESISTORS

V1, VCC_IO

3.3V WITH FB1 = GND,

3.0V WITH FB1 = IN,
OR ADJ WITH RESISTORS

VCC_USIM
0V, 1.8V, 3.0V (DEF = 0V)

V4, VCC_PLL

1.3V, 35mA

V5, VCC_SRAM

1.1V, 35mA

V3, VCC_CORE

0.75V TO 1.3V
(DEF = 1.3V)

FROM CPU
PWR_EN

FROM CPU
SYS_EN

ON1

RUN

SLEEP

ON2

DBI (3.15V OR ADJ)

LBO

REF

1.25V

REF

UVLO

AND
BATT
MON

LBI (3.6V OR ADJ)

BKBT

DBO

SLP

TO V1

REG1 OK

POK

SCL SDA

GND

I

2

C

SERIAL

CC1

V7, VCC_BATT

(1ST SUPPLY, ALWAYS ON)

FROM CPU

SYS_EN

V7

V1–V6

POWER-

OK

CC2
CC3

TO CPU
nRESET

TO CPU

nVCC_FAULT

RSO

MR

RESET INPUT

Li+
BACKUP
BATTERY

OPEN-DRAIN LOW-BATT OUT

OPEN-DRAIN DEAD-BATT OUT

TO nBATT_FAULT

V3

DAC

RAMP

SRAD

PWM3

FORCE REG3

TO PWM

V7

RESET

2.425V

65ms

ADJ ON

MAX1586

100kΩ

Figure 1. MAX1586 Functional Diagram. The MAX1587 omits some features. See the Pin Description section.

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones

18 ______________________________________________________________________________________

Detailed Description

The MAX1586/MAX1587 power-management ICs are
optimized for devices using Intel X-Scale microproces­sors, including third-generation smart cell phones,
PDAs, internet appliances, and other portable devices
requiring substantial computing and multimedia
capability at low power. The MAX1586A/MAX1586B/
MAX1587A comply with Intel Processor Power
specifications.

The ICs integrate seven high-performance, low-operat­ing-current power supplies along with supervisory and
management functions. Regulator outputs include three
step-down DC-DC outputs (V1, V2, and V3), three lin­ear regulators (V4, V5, and V6), and one always-on out­put, V7 (Intel VCC_BATT). The V1 step-down DC-DC
converter provides 3.0V, 3.3V, or adjustable output volt­age for I/O and peripherals. The V2 step-down DC-DC
converter on the MAX1586A and MAX1587A is preset
for 1.8V or 2.5V, while the MAX1586B V2 supply is pre­set for 3.3V or 2.5V. V2 can also be adjusted with exter­nal resistors on all parts. The V3 step-down DC-DC
converter provides a serial-programmed output for
powering microprocessor cores. The three linear regu­lators (V4, V5, and V6) provide power for PLL, SRAM,
and USIM.

To minimize sleep-state quiescent current, V1 and V2
have bypass “sleep” LDOs that can be activated to
minimize battery drain when output current is very low.
Other functions include separate on/off control for all
DC-DC converters, low-battery and dead-battery
detection, a power-OK output, a backup-battery input,
and a two-wire serial interface.

All DC-DC outputs use fast, 1MHz PWM switching and
small external components. They operate with fixed-fre­quency PWM control and automatically switch from
PWM to skip-mode operation at light loads to reduce
operating current and extend battery life. The V3 core
output is capable of forced-PWM operation at all loads.
The 2.6V to 5.5V input voltage range allows 1-cell Li+,
3-cell NiMH, or a regulated 5V input.

The following power-supply descriptions include the
Intel terms for the various voltages in parenthesis. For
example, the MAX1586/MAX1587 V1 output is referred
to as VCC_IO in Intel documentation. See Figure 1.

V1 and V2 (VCC_IO, VCC_MEM)

Step-Down DC-DC Converters

V1 is a 1MHz current-mode step-down converter. The V1
output voltage can be preset to 3.3V or adjusted using a
resistor voltage-divider. V1 supplies loads up to 1300mA.

V2 is also a 1MHz current-mode step-down converter.
The V2 step-down DC-DC converter on the MAX1586A
and MAX1587A is preset for 1.8V or 2.5V, while the
MAX1586B V2 supply is preset for 3.3V or 2.5V. V2 can
also be adjusted with external resistors on all parts. V2
supplies loads up to 900mA.

Under moderate to heavy loading, the converters operate
in a low-noise PWM mode with constant frequency and
modulated pulse width. Switching harmonics generated
by fixed-frequency operation are consistent and easily fil­tered. Efficiency is enhanced under light loading (<30mA
typ), by assuming an Idle Mode during which the con­verter switches only as needed to service the load.

Synchronous Rectification

Internal N-channel synchronous rectifiers eliminate the
need for external Schottky diodes and improve efficien­cy. The synchronous rectifier turns on during the sec­ond half of each cycle (off-time). During this time, the
voltage across the inductor is reversed, and the induc­tor current falls. In normal operation (not forced PWM),
the synchronous rectifier turns off at the end of the
cycle (at which time another on-time begins) or when
the inductor current approaches zero.

100% Duty-Cycle Operation

If the inductor current does not rise sufficiently to sup­ply the load during the on-time, the switch remains on,
allowing operation up to 100% duty cycle. This allows
the output voltage to maintain regulation while the input
voltage approaches the regulation voltage. Dropout
voltage is approximately 180mV for an 800mA load on
V1 and 220mV for an 800mA load on V2. During
dropout, the high-side P-channel MOSFET turns on,
and the controller enters a low-current-consumption
mode. The device remains in this mode until the regula­tor channel is no longer in dropout.

Sleep LDOs

In addition to the high-efficiency step-down converters,
V1 and V2 can also be supplied with low-quiescent cur­rent, low-dropout (LDO) linear regulators that can be
used in sleep mode or at any time when the load current
is very low. The sleep LDOs can source up to 35mA. To

Idle Mode is a trademark of Maxim Integrated Products, Inc.

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-I

Q

PMICs with

Dynamic Core for PDAs and Smart Phones

______________________________________________________________________________________ 19

enable the sleep LDOs, drive SLP low. When SLP is high,
the switching step-down converters are active. The output
voltage of the sleep LDOs is set to be the same as the
switching step-down converters as described in the
Setting the Output Voltages section. SLPIN is the input to
the V1 and V2 sleep LDOs and must connect to IN.

V3 (VCC_CORE) Step-Down

DC-DC Converter

V3 is a 1MHz current-mode step-down converter that
supplies loads up to 500mA. The V3 output voltage is set
by the I2C serial interface to between 0.7V and 1.475V in
25mV increments. The default voltage on power-up is

1.3V. See the Serial Interface section for details.

Forced PWM on REG3

Under moderate to heavy loading, the V3 always operates
in a low-noise PWM mode with constant frequency and
modulated pulse width. Switching harmonics generated by
fixed-frequency operation are consistent and easily filtered.

With light loads (<30mA) and PWM3 low, V3 operates
in an enhanced-efficiency Idle Mode during which the
converter switches only as needed to service the load.
With PWM3 high, V3 operates in low-noise forced-PWM
mode under all load conditions.

Linear Regulators (V4, V5, and V6)

V4 (VCC_PLL)

V4 is a linear regulator that provides a fixed 1.3V output
and supplies loads up to 35mA. The power input for the
V4 and V5 linear regulators is IN45, which is typically

connected to V2. To enable V4 on the MAX1587, drive
ON4 high, or drive ON4 low for shutdown. On the
MAX1586, the enable pins for V4 and V5 are combined.
Drive ON45 high to enable V4 and V5, or drive ON45 low
for shutdown. V4 is intended to connect to VCC_PLL.

V5 (VCC_SRAM)

V5 is a linear regulator that provides a fixed 1.1V output
and supplies loads up to 35mA. The power input for the
V4 and V5 linear regulators is IN45, which is typically
connected to V2. To enable V5 on the MAX1587, drive
ON5 high, or drive ON5 low for shutdown. On the
MAX1586, the enable pins for V4 and V5 are combined.
Drive ON45 high to enable V4 and V5, or drive ON45 low
for shutdown. V5 is intended to connect to VCC_SRAM.

V6 (VCC_USIM—MAX1586 Only)

V6 is a linear regulator on the MAX1586 that supplies
loads up to 35mA. The V6 output voltage is pro­grammed with the I2C serial interface to 0V, 1.8V, 2.5V,
or 3.0V. The power-up default for V6 is 0V. See the
Serial Interface section for details on changing the volt­age. The power input for the V6 linear regulator is IN6,
which is typically connected to V1. To enable V6, drive
ON6 high, or drive ON6 low for shutdown. V6 is intend­ed to connect to VCC_USIM.

V7 Always-On Output (VCC_BATT)

The V7 output is always active if V1 is enabled and in
regulation or if backup power is present. When ON1 is
high and V1 is in regulation, V7 is sourced from V1 by
an internal MOSFET switch. When ON1 is low or V1 is

Table 1. Quiescent Operating Current in Various States

OPERATING

DESCRIPTION

TYPICAL MAX1586/MAX1587

NO-LOAD OPERATING CURRENT

RUN All supplies on and running

IDLE All supplies on and running, peripherals on

SENSE All supplies on, minimal loading, peripherals monitored

STANDBY All supplies on, minimal loading, peripherals not monitored

200µA MAX1587,
225µA MAX1586

SLEEP P W R_E N contr ol l ed vol tag es ( V 3, V 4, V 5) ar e off. V 1 and V 2 on.

60µA if V1 and V2 SLEEP LDOs on;
130µA if V1, V2 step-down DC-DCs enabled

DEEP SLEEP All supplies off except V7. V7 biased from backup battery.

5µA MAX1587 if IN > DBI threshold;
32µA MAX1586 if IN > DBI threshold;
4µA if IN < DBI threshold

POWER MODE

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones

20 ______________________________________________________________________________________

out of regulation, V7 is sourced from BKBT by a second
on-chip MOSFET. V7 can supply loads up to 30mA. V7
is intended to connect to VCC_BATT on Intel CPUs.

Due to variations in system implementation, BKBT and
V7 can be utilized in different ways. See the Backup-
Battery Configurations section for information on how to
use BKBT and V7.

Quiescent Operating Current

in Various States

The MAX1586/MAX1587 are designed for optimum effi­ciency and minimum operating current for all typical
operating modes, including sleep and deep sleep.
These states are outlined in Table 1.

Voltage Monitors, Reset, and

Undervoltage-Lockout Functions

Undervoltage Lockout

When the input voltage is below 2.35V (typ), an under­voltage-lockout (UVLO) circuit disables the IC. The
inputs remain high impedance while in UVLO, reducing
battery load under this condition. All serial registers are
maintained with the input voltage down to at least 2.35V.

Reset Output

(RSO)

and MRInput

The reset output (RSO) is low when the MR input is low
or when V7 is below 2.425V. V7 is powered from V1
(when enabled) or the backup-battery input (BKBT).
RSO normally goes low:

1) When power is first applied in configurations with
no separate backup battery (external diode from
IN to BKBT).

2) When power is removed in configurations with no
separate backup battery (external diode from IN
to BKBT).

3) If the backup battery falls below 2.425V when V1
is off or out of regulation.

4) When the manual reset button is pressed (MR
goes low).

RSO has a timer that delays release until 65ms after V7
exceeds 2.3V when V

IN

> 2.4V. If V

IN

< 2.4V when V7
exceeds 2.3V, RSO deasserts immediately with no 65ms
delay. There is no delay in this case because the timer
circuitry is deactivated to minimize operating current dur­ing IN undervoltage lockout. RSO is not triggered by any
output besides V7. If BKBT is not powered, RSO does
not function and is high impedance.

MR is a manual reset input for hardware reset. When MR
goes low, RSO asserts for a minimum of 65ms. MR does
not reset any internal MAX1586/MAX1587 functions.

Dead-Battery and Low-Battery Comparators—

DBI, LBI (MAX1586 only)

The DBI and LBI inputs monitor input power (usually a
battery) and trigger the DBO and LBO outputs. The
dead-battery comparator triggers DBO when the battery
(VIN) discharges to the dead-battery threshold. The
factory-set 3.15V threshold is selected by connecting
DBI to IN, or the threshold can be programmed with a
resistor-divider at DBI. The low-battery comparator has
a factory-set 3.6V threshold that is selected by connect­ing LBI to IN, or its threshold can be programmed with a
resistor-divider at LBI.

One three-resistor-divider can set both DBI and LBI
(R1, R2, and R3 in Figure 2) according to the following
equations:

1) Choose R3 to be less than 250kΩ

2) R1 = R3 VLB(1 - (1.232 / VDB))

3) R2 = R3 (1.232 x (V

LB

/ VDB) - 1)

where VLBis the low-battery threshold and VDBis the
dead-battery threshold.

Alternately, LBI and DBI can be set with separate two­resistor-dividers. Choose the lower resistor of the divider
chain to be 250kΩ or less (R5 and R7 in Figure 3). The
equations for upper divider-resistors as a function of
each threshold are then:

R4 = R5 (V

DB

/ 1.232) - 1)

R6 = R7 (VLB- 1)

When resistors are used to set VLB, the threshold at LBI
is 1.00V. When resistors are used to set VDB, the
threshold at DBI is 1.232V. A resistor-set threshold can

MAX1586

MAIN BATTERY

R1

438kΩ

R2

62kΩ

R3

200kΩ

IN

DBI (1.232V THRESHOLD)

LBI (1.00V THRESHOLD)

Figure 2. Setting the Low-Battery and Dead-Battery Thresholds
with One Resistor Chain. The values shown set a DBI threshold
of 3.3V and an LBI threshold of 3.5V (no resistors are needed
for the factory preset thresholds).

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-I

Q

PMICs with

Dynamic Core for PDAs and Smart Phones

______________________________________________________________________________________ 21

also be used for only one of DBI or LBI. The other
threshold can then be factory set by connecting the
appropriate input to IN.

If BKBT is not powered, DBO does not function and is
high impedance. DBO is expected to connect to
nBATT_FAULT on Intel CPUs. If BKBT is not powered,
LBO does not function and is high impedance.

Power-OK Output (POK)

POK is an open-drain output that goes low when any
activated regulator (V1–V6) is below its regulation
threshold. POK does not monitor V7. When all active
output voltages are within 10% of regulation, POK is
high impedance. POK does not flag an out-of-regula­tion condition while V3 is transitioning between voltages
set by serial programming or when any regulator chan­nel has been turned off. POK momentarily goes low
when any regulator is turned on, but returns high when
that regulator reaches regulation. When all regulators
(V1–V6) are off, POK is forced low. If the input voltage
is below the UVLO threshold, POK is held low and
maintains a valid low output with IN as low as 1V. If
BKBT is not powered, POK does not function and is
high impedance.

Connection to Processor

and Power Sequencing

Typical processor connections have only power-control
pins, typically labeled PWR_EN and SYS_EN. The
MAX1586/MAX1587 provide numerous on/off control
pins for maximum flexibility. In a typical application,
many of these pins are connected together. ON1, ON2,
and ON6 typically connect to SYS_EN. ON3, ON4, and
ON5 typically connect to PWR_EN. V7 remains on as long
as the main or backup power is connected. Sequencing
is not performed internally on the MAX1586/MAX1587;
however, all ON_ inputs have hysteresis and can connect
to RC networks to set sequencing. For typical connec­tions to Intel CPUs, no external sequencing is required.

Backup-Battery Input

The backup-battery input (BKBT) provides backup
power for V7 when V1 is disabled. Normally, a primary
or rechargeable backup battery is connected to this
pin. If a backup battery is not used, then BKBT should
connect to IN through a diode or external regulator. See
the Backup-Battery Configurations section for informa-
tion on how to use BKBT and V7.

Serial Interface

An I2C-compatible, two-wire serial interface controls
REG3 on the MAX1587, and REG3 and REG6 on the
MAX1586. The serial interface operates when IN exceeds
the 2.40V UVLO threshold and at least one of ON1–ON6
is asserted. The serial interface is shut down to minimize
off-current drain when no regulators are enabled.

The serial interface consists of a serial data line (SDA)
and a serial clock line (SCL). Standard I

2

C-compatible
write-byte commands are used. Figure 4 shows a tim­ing diagram for the I

2

C protocol. The MAX1586/
MAX1587 are slave-only devices, relying upon a master
to generate a clock signal. The master (typically a
microprocessor) initiates data transfer on the bus and
generates SCL to permit data transfer. A master device
communicates to the MAX1586/MAX1587 by transmit­ting the proper address followed by the 8-bit data code
(Table 2). Each transmit sequence is framed by a
START (A) condition and a STOP (L) condition. Each
word transmitted over the bus is 8 bits long and is
always followed by an acknowledge clock pulse.

Table 2 shows the serial data codes used to program
V3 and V6. The default power-up voltage for V3 is 1.3V
and for V6 is 0V.

MAX1586

MAIN BATTERY

R6

500kΩ

R7

200kΩ

IN

DBI (1.232V THRESHOLD)

LBI (1.00V THRESHOLD)

R5

200kΩ

R4

334kΩ

Figure 3. Setting the Low-Battery and Dead-Battery Thresholds
with Separate Resistor-Dividers. The values shown set a DBI
threshold of 3.3V and an LBI threshold of 3.5V (no resistors are
needed for factory-preset thresholds).

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones

22 ______________________________________________________________________________________

Bit Transfer

One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see the START
and STOP Conditions section). Both SDA and SCL idle
high when the bus is not busy.

START and STOP Conditions

When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu­ing a START condition. A START condition is a high-to­low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA while SCL is high
(Figure 4). A START condition from the master signals
the beginning of a transmission to the MAX1586/
MAX1587. The master terminates transmission by issu­ing a not acknowledge followed by a STOP condition
(see the Acknowledge Bit section). The STOP condition
frees the bus.

When a STOP condition or incorrect address is detect­ed, the MAX1586/MAX1587 internally disconnect SCL
from the serial interface until the next START condition,
minimizing digital noise and feedthrough.

Acknowledge Bit (ACK)

The acknowledge bit (ACK) is the ninth bit attached to
every 8-bit data word. The receiving device always
generates ACK. The MAX1586/MAX1587 generate an
ACK when receiving an address or data by pulling SDA
low during the ninth clock period. Monitoring ACK
allows for detection of unsuccessful data transfers. An

unsuccessful data transfer occurs if a receiving device
is busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.

Serial Address

A bus master initiates communication with a slave
device by issuing a START condition followed by the
7-bit slave address (Table 3). When idle, the
MAX1586/MAX1587 wait for a START condition fol­lowed by its slave address. The serial interface com­pares each address value bit by bit, allowing the
interface to power down immediately if an incorrect
address is detected.

The LSB of the address word is the read/write (R/W) bit.
R/W indicates whether the master is writing or reading
(RD/W 0 = write, RD/W 1 = read). The MAX1586/
MAX1587 only support the SEND BYTE format; there­fore, RD/W is required to be 0.

After receiving the proper address, the MAX1586/
MAX1587 issue an ACK by pulling SDA low for one
clock cycle. The MAX1586/MAX1587 have two user­programmed addresses (Table 3). Address bits A6
through A1 are fixed, while A1 is controlled by SRAD.
Connecting SRAD to GND sets A1 = 0. Connecting
ADD to IN sets A1 = 1.

V3 Output Ramp-Rate Control

When V3 is dynamically changed with the serial inter­face, the output voltage changes at a rate controlled by
a capacitor (C

RAMP

) connected from RAMP to ground.

SCL

AB CDEFG HIJK

SDA

t

SU:STA

t

HD:STA

t

LOWtHIGH

t

SU:DAT

t

HD:DAT

t

SU:STO

t

BUF

A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMB DATA LINE LOW

L M

F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT)
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMB DATA LINE LOW

J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION

Figure 4. I2C-Compatible Serial-Interface Timing Diagram

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-I

Q

PMICs with

Dynamic Core for PDAs and Smart Phones

______________________________________________________________________________________ 23

Table 2. V3 and V6 Serial Programming Codes

D7 D6

D5

D4 D3 D2 D1 D0

OUTPUT

(V)

DESCRIPTION

0 000000.700
0 000010.725
0 000100.750
0 000110.775
0 001000.800
0 001010.825
0 001100.850
0 001110.875
0 010000.900
0 010010.925
0 010100.950
0 010110.975
0 011001.000
0 011011.025
0 011101.050
0 011111.075
0 100001.100
0 100011.125
0 100101.150
0 100111.175
0 101001.200
0 101011.225
0 101101.250
0 101111.275

0 110001.300

0 110011.325
0 110101.350
0 110111.375
0 111001.400
0 111011.425
0 111101.450
0 111111.475

V3, CORE

VOLTAGES

1 XXX00 0

1 XXX011.8
1 XXX102.5

XX

1 XXX113.0

V6, USIM

VOLTAGES

[MAX1586

ONLY]

0 = PROG V3
1 = PROG V6

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones

24 ______________________________________________________________________________________

The voltage change is a conventional RC exponential
described by:

Vo(t) = Vo(0) + dV(1 – exp(-t / (100kΩ C

RAMP

)))

A useful approximation is that it takes approximately 2.2
RC time constants for V3 to move from 10% to 90% of
the voltage difference. For C

RAMP

= 1500pF, this time
is 330µs. For 1V to 1.3V change, this equates to
1mV/µs. See the Typical Operating Characteristics for
examples of different ramp-rate settings.

The maximum capacitor value that can be used at
RAMP is 2200pF. If larger values are used, the V3 ramp
rate is still controlled according to the above equation,
but when V3 is first activated, POK indicates an “in reg­ulation” condition before V3 reaches its final voltage.

The RAMP pin is effectively the reference for REG3.
FB3 regulates to 1.28 times the voltage on RAMP.

Design Procedure

Setting the Output Voltages

The outputs V1 and V2 have preset output voltages, but
can also be adjusted using a resistor voltage-divider. V1
has 3.3V and 3.0V presets. To set V1 to 3.0V, connect
FB1 to IN. To set to 3.3V, connect FB1 to GND. V2 can
be preset to 1.8V or 2.5V on the MAX1586A and
MAX1587A. To set V2 to 1.8V on the MAX1586A and
MAX1587A, connect FB2 to IN. To set to 2.5V, connect
FB2 to GND. V2 can preset to 3.3V or 2.5V on the
MAX1587B. To set V2 to 3.3V on the MAX1587B, connect
FB2 to IN. To set to 2.5V, connect FB2 to GND.

To set V1 or V2 to other than the preset output voltages,
connect a resistor voltage-divider from the output volt­age to the corresponding FB input. The FB_ input bias
current is less than 100nA, so choose the low-side (FB_­to-GND) resistor (RL) to be 100kΩ or less. Then calcu­late the high-side (output-to-FB_) resistor (RH) using:

RH= RL[(V

OUT

/ 1.25) – 1]

The V3 (VCC_CORE) output voltage is set from 0.7V to

1.475V in 25mV steps by the I2C serial interface. See
the Serial Interface section for details.

Linear regulator V4 provides a fixed 1.3V output volt­age. Linear regulator V5 provides a fixed 1.1V output
voltage. V4 and V5 voltages are not adjustable.

The output voltage of linear regulator V6 (VCC_USIM) is
set to 0V, 1.8V, 2.5V, or 3.0V by the I

2

C serial interface.

See the Serial Interface section for details.
Linear regulator V7 (VCC_BATT) tracks the voltage at

V1 as long as ON1 is high and V1 is in regulation. When
ON1 is low or V1 is not in regulation, V7 switches to the
backup battery (V

BKBT

).

Inductor Selection

The external components required for the step-down
are an inductor, input and output filter capacitors, and a
compensation RC network.

The MAX1586/MAX1587 step-down converters provide
best efficiency with continuous inductor current. A rea­sonable inductor value (L

IDEAL

) is derived from:

L

IDEAL

= [2(VIN) x D(1 - D)] / (I

OUT(MAX)

x f

OSC

)

This sets the peak-to-peak inductor current at 1/2 the
DC inductor current. D is the duty cycle:

D = V

OUT

/ V

IN

Given L

IDEAL

, the peak-to-peak inductor ripple current

is 0.5 x I

OUT

. The peak inductor current is 1.25 x

I

OUT(MAX)

. Make sure the saturation current of the
inductor exceeds the peak inductor current and the
rated maximum DC inductor current exceeds the maxi­mum output current (I

OUT(MAX)

). Inductance values

larger than L

IDEAL

can be used to optimize efficiency or
to obtain the maximum possible output current. Larger
inductance values accomplish this by supplying a
given load current with a lower inductor peak current.
Typically, output current and efficiency are improved
for inductor values up to about two times L

IDEAL

. If the
inductance is raised too much, however, the inductor
size may become too large, or the increased inductor
resistance may reduce efficiency more than the gain
derived from lower peak current.

Smaller inductance values allow smaller inductor sizes,
but also result in larger peak inductor current for a
given load. Larger output capacitance may then be
needed to suppress the increase in output ripple
caused by larger peak current.

Capacitor Selection

The input capacitor in a DC-DC converter reduces cur­rent peaks drawn from the battery or other input power
source and reduces switching noise in the controller.
The impedance of the input capacitor at the switching
frequency should be less than that of the input source
so high-frequency switching currents do not pass
through the input source.

The output capacitor keeps output ripple small and
ensures control-loop stability. The output capacitor

Table 3. Serial Address

SRADA7A6A5A4A3A2

A1

A0

RD/W

0

0

1

0

0010100
0010101

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-I

Q

PMICs with

Dynamic Core for PDAs and Smart Phones

______________________________________________________________________________________ 25

must also have low impedance at the switching fre­quency. Ceramic, polymer, and tantalum capacitors
are suitable, with ceramic exhibiting the lowest ESR
and lowest high-frequency impedance.

Output ripple with a ceramic output capacitor is
approximately:

V

RIPPLE

= I

L(PEAK)

[1 / (2π x f

OSC

x C

OUT

)]

If the capacitor has significant ESR, the output ripple
component due to capacitor ESR is:

V

RIPPLE(ESR)

= I

L(PEAK)

x ESR

Output capacitor specifics are also discussed in the
Compensation and Stability section.

Compensation and Stability

The relevant characteristics for REG1, REG2, and
REG3 compensation are:

1) Transconductance (from FB_ to CC_), gm

EA

2) Current-sense amplifier transresistance, R

CS

3) Feedback regulation voltage, VFB(1.25V)

4) Step-down output voltage, V

OUT

, in V

5) Output load equivalent resistance, R

LOAD

= V

OUT

/

I

LOAD

The key steps for step-down compensation are:

1) Set the compensation RC zero to cancel the R

LOAD

C

OUT

pole.

2) Set the loop crossover at or below approximately
1/10th the switching frequency.

For example, with V

IN(MAX)

= 5V, V

OUT

= 2.5V for

REG2, and I

OUT

= 800mA, then R

LOAD

= 3.125Ω. For

REG2, RCS= 0.75V/A and gmEA= 87µS.
Choose the crossover frequency, fC≤ f

OSC

/ 10.
Choose 100kHz. Then calculate the value of the com­pensation capacitor, CC:

CC= (V

FB

/ V

OUT

) x (R

LOAD

/ RCS) x (gm / (2π x fC))

= (1.25 / 2.5) x (3.125 / 0.75) x (87 x 10

-6

/ (6.28

x 100,000)) = 289pF
Choose 330pF, the next highest standard value.
Now select the compensation resistor, R

C

, so transient­droop requirements are met. As an example, if 3% tran­sient droop is allowed for the desired load step, the
input to the error amplifier moves 0.03 x 1.25V, or

37.5mV. The error-amplifier output drives 37.5mV x
gmEA, or I

EAO

= 37.5mV x 87µS = 3.26µA across RCto
provide transient gain. Find the value of RCthat allows
the required load-step swing from:

RC= RCSx I

IND(PK)

/ I

EAO

where I

IND(PK)

is the peak inductor current. In a step-

down DC-DC converter, if L

IDEAL

is used, output cur-

rent relates to inductor current by:

I

IND(PK)

= 1.25 x I

OUT

So for an 800mA output load step with VIN= 3.6V and
V

OUT

= 2.5V:

RC= RCSx I

IND(PK)

/ I

EAO

= (0.75V/A) x

(1.25 x 0.8A) / 3.26µA = 230kΩ

We choose 240kΩ. Note that the inductor does not limit
the response in this case since it can ramp at (V

IN

-

V

OUT

) / L, or (3.6 - 2.5) / 3.3µH = 242mA/µs.

The output filter capacitor is then selected so that the
C

OUTRLOAD

pole cancels the RCCCzero:

C

OUT

x R

LOAD

= RCx C

C

For the example:

R

LOAD

= V

OUT

x I

LOAD

= 2.5V / 0.8A =

3.125Ω

C

OUT

= RC x CC / R

LOAD

= 240kΩ x 330pF /

3.125Ω = 25µF
We choose 22µF.
Recalculate R

C

using the selected C

OUT

.

RC= C

OUT

x R

LOAD

/ CC = 208kΩ

PARAMETER

REG3

Error-Amplifier

Transconductance, gm

EA

68µS

Current-Sense Amp

Transresistance, R

CS

1.25V/A

Table 4. Compensation Parameters

COMPONENT OR

PARAMETER

REG1 REG2 REG3

V

OUT

3.3V 2.5V 1.3V

Output Current

500mA

Inductor 3.3µH 6.8µH 10µH

Load-Step Droop 3% 3% 3%

Loop Crossover Freq (fC)

100kHz

C

C

330pF 270pF 330pF

R

C

240kΩ

C

OUT

22µF 22µF 22µF

Table 5. Typical Compensation Values

REG1 REG2

87µS 87µS

0.5V/A 0.75V/A

1300mA 900mA

100kHz 100kHz

240kΩ 240kΩ

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones

26 ______________________________________________________________________________________

MAIN

BATT

PV1

BATT

TO

BATT

STEP-DOWN

PWM
REG1

SLEEP

LDO

LX1

C12

4.7µF

C11

10µF

C19

0.1µF

C25
1µF

C24
1µF

C28
330pF

C27
270pF

C26
330pF

R20

1MΩ

R21
240kΩ

R18

1MΩ

R22
240kΩ

R23
240kΩ

R19

1MΩ

C15
22µF

C16
22µF

C17
22µF

C13

4.7µF

C14

4.7µF

C20

0.01µF

C23
1µF

C22
1µF

C21
1µF

L1

3.3µH

L2

6.8µH

L3

10µH

PG1

V1

FB1

V2

FB2

PV2

ON

SLPININ

ON

STEP-DOWN

PWM
REG2

SLEEP

LDO

LX2

PG2

FB3
ON3
IN45

V4

BYP

ON4
ON5

IN6

ON6

V5

V6

PV3

TO BATT

TO V2

TO V2

TO BATT

PWM

LDO
REG

4

LDO
REG

5

STEP-DOWN

PWM
REG3

LX3

PG3

LDO
REG

6

V1
VCC_IO

3.3V
1300mA

V2
VCC_MEM

2.5V
900mA

V6
VCC_USIM
0V, 1.8V, 3.0V (DEF = 0V)
35mA

V4, VCC_PLL

1.3V, 35mA

V5
VCC_SRAM

1.1V, 35mA

V3
VCC_CORE

0.75V TO 1.3V
500mA

FROM CPU
PWR_EN

FROM CPU
SYS_EN

ON1

RUN

SLEEP

ON2

DBI (3.2V OR ADJ)

LBO

REF

1.25V

REF

UVLO

AND
BATT
MON

LBI (3.6V OR ADJ)

BKBT

DBO

SLP

TO V1

TO V1

TO V1

REG1 OK

POK

ADJ ON

SCL SDA

GND

I

2

C

SERIAL

CC1

V7, VCC_BATT

(ALWAYS ON)

FROM CPU

SYS_EN

V7

V1–V6

POWER-

OK

CC2
CC3

TO CPU
nRESET

TO CPU

nVCC-FAULT

RSO

MR

RESET INPUT

Li+

BACKUP

BATTERY

LOW-BATT

WARNING

TO CPU

nBATT_FAULT

V3

DAC

RAMP

C18

1500pF

SRAD

PWM3

V7

RESET

2.3V

65ms

MAX1586

100kΩ

Figure 5. MAX1586 Typical Applications Circuit. The MAX1587 omits some features. See the Pin Description section.

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-I

Q

PMICs with

Dynamic Core for PDAs and Smart Phones

______________________________________________________________________________________ 27

Note that the pole cancellation does not have to be
exact. RCx CCneed only be within 0.75 to 1.25 times
R

LOAD

x C

OUT

. This provides flexibility in component

selection.
If the output filter capacitor has significant ESR, a zero

occurs at:

Z

ESR

= 1 / (2π x C

OUT

x R

ESR

)

If Z

ESR

> fC, it can be ignored, as is typically the case

with ceramic or polymer output capacitors. If Z

ESR

is
less than fC, it should be cancelled with a pole set by
capacitor CPconnected from CC_ to GND:

CP= C

OUTRESR

/ R

C

If CPis calculated to be < 10pF, it can be omitted.

Optimizing Transient Response

In applications that require load-transient response to
be optimized in favor of minimum component values,
increase the output filter capacitor to increase the R in
the compensation RC. From the equations in the previ­ous section, doubling the output cap allows a doubling
of the compensation R, which then doubles the tran­sient gain.

Applications Information

Backup-Battery and V7 Configurations

The MAX1586/MAX1587 include a backup-battery con­nection, BKBT, and an output, V7. These can be utilized
in different ways for various system configurations.

Primary Backup Battery

A connection with a primary (nonrechargeable) lithium
coin cell is shown in Figure 5. The lithium cell connects to
BKBT directly. V7 powers the CPU VCC_BATT from either
V1 (if enabled) or the backup battery. It is assumed

whenever the main battery is good, V1 is on (either with
its DC-DC converter or sleep LDO) to supply V7.

No Backup Battery (or Alternate Backup)

If no backup battery is used, or if an alternate backup
and VCC_BATT scheme is used that does not use the
MAX1586/MAX1587, then BKBT should be biased from
IN with a small silicon diode (1N4148 or similar, as in
Figure 6). BKBT must still be powered when no backup
battery is used because DBO, RSO, and POK require
this supply to function. If BKBT is not powered, these
outputs do not function and are high impedance.

Rechargeable Li+ Backup Battery

If more backup power is needed and a primary cell has
inadequate capacity, a rechargeable lithium cell can be
accommodated as shown in Figure 7. A series resistor
and diode charge the cell when the 3.3V V1 supply is

MAX1586
MAX1587

MAIN

POWER

D1

1N4148

IN

BKBT

V7

4.7µF

1µF

Figure 6. BKBT connection when no backup battery is used, or
if an alternate backup scheme, not involving the
MAX1586/MAX1587, is used.

MAX1586
MAX1587

MAIN

POWER

1-CELL

Li+ RECHARGEABLE

BACKUP BATTERY

IN

BKBT

1kΩ

V7

V1

4.7µF

1µF

4.7µF

Figure 7. A 1-cell rechargeable Li+ battery provides more back­up power when a primary cell is insufficient. The cell is charged
to 3.3V when V1 is active. Alternately, the battery can be
charged from IN if the voltages are appropriate for the cell type.

MAX1586
MAX1587

MAX1724

EZK30

MAIN
POWER

1N4148

MURATA

LQH32C 10µH

1-CELL

NiMH

RECHARGEABLE

BACKUP BATTERY

10kΩ

IN

BKBT

GND

BATT

LX

SHDN

OUT

V7

4.7µF

4.7µF

1µF

10µF

3.0V

Figure 8. A 1-cell NiMH battery can provide backup by boost­ing with a low-power DC-DC converter. A series resistor-diode
trickle charges the battery when the main power is on.

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones

28 ______________________________________________________________________________________

active. In addition to biasing V7, the rechargeable bat­tery may be required to also power other supplies.

Rechargeable NiMH Backup Battery

In some systems, a NiMH battery may be desired for
backup. Usually this requires multiple cells because
the typical NiMH cell voltage is only 1.2V. By adding a
small DC-DC converter (MAX1724), the low-battery
voltage is boosted to 3V to bias BKBT (Figure 8). The
DC-DC converter’s low operating current (1.5µA typ)
allows it to remain on constantly so the 3V BKBT bias is
always present. A resistor and diode trickle charge the
NiMH cell when the main power is present.

PC Board Layout and Routing

Good PC board layout is important to achieve optimal
performance. Conductors carrying discontinuous cur­rents and any high-current path should be made as
short and wide as possible. A separate low-noise
ground plane containing the reference and signal
grounds should connect to the power-ground plane at
only one point to minimize the effects of power-ground
currents. Typically, the ground planes are best joined
right at the IC.

Keep the voltage feedback network very close to the
IC, preferably within 0.2in (5mm) of the FB_ pin. Nodes
with high dV/dt (switching nodes) should be kept as
small as possible and should be routed away from
high-impedance nodes such as FB_. Refer to the
MAX1586 or MAX1587 evaluation kit data sheets for a
full PC board example.

Increasing V3 (VCC_CORE) Voltage Range

The programmable V3 output voltage range can be
increased by adding two resistors as shown in Figure 9.

Chip Information

TRANSISTOR COUNT: 13,958
PROCESS: BiCMOS

TOP VIEW

RSO
SRAD

LX3
PG3

V4
ON45
ON2

V5
IN45

PV3

V7
V1

SLPIN

V2

FB2
CC2
POK

SCL

BKBT

FB1

1
2
3
4
5
6
7
8
9

10

111213141516171819

20

403938373635343332

31

30
29
28
27
26
25
24
23
22
21

PG2

IN

RAMP

REF

BYP

LX2

PV2

PWM3

SDA

SLP

PV1

LX1

PG1

ON1

ON3

FB3

CC3

MR

CC1

THIN QFN

6mm × 6mm

MAX1587AETL

GND

RSO
SRAD

LX3
PG3

V4
ON4
ON2

ON5

ON3

V5
IN45

PV3
V7
V1

SLPIN

V2

FB2

CC2

CC1

POK
SCL

BKBT

FB1

LB1

PG2

IN

RAMP

REF

BYP

LX2

PV2

LBO

PWM3

SDA

SLP

PV1

LX1

PG1

IN6V6ON6

ON1

FB3

CC3

MR

DBI

THIN QFN

7mm × 7mm

MAX1586AETM
MAX1586BETM

GND

DBO

1
2
3
4
5
6
7
8

9
10
11
12

36
35
34
33
32
31
30
29
28
27
26
25

4847464544434241403938

37

1314151617181920212223

24

Pin Configurations

PV3

STEP-DOWN

PWM
REG3

R24 VALUES:

R24 = 3.32kΩ, V3: 0.73V TO 1.55V, 26mV/STEP
R24 = 5.11kΩ, V3: 0.75V TO 1.60V, 27mV/STEP
R24 = 7.5kΩ, V3: 0.78V TO 1.65V, 28mV/STEP

LX3

PG3

FB3

V3
VCC_CORE

TO BATT

R25
100kΩ

R24

MAX1586
MAX1587

Figure 9. Adding R24 and R25 to Increase Core Voltage
Programming Range

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-I

Q

PMICs with

Dynamic Core for PDAs and Smart Phones

______________________________________________________________________________________ 29

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)

QFN THIN 6x6x0.8.EPS

e e

LL

A1 A2

A

E/2

E

D/2

D

E2/2

E2

(NE-1) X e

(ND-1) X e

e

D2/2

D2

b

k

k

L

C

L

C

L

C

L

C

L

D

1

2

21-0141

PACKAGE OUTLINE
36,40L THIN QFN, 6x6x0.8 mm

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones

30 ______________________________________________________________________________________

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

9. DRAWING CONFORMS TO JEDEC MO220.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

3. N IS THE TOTAL NUMBER OF TERMINALS.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

NOTES:

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

D

2

2

21-0141

PACKAGE OUTLINE
36, 40L THIN QFN, 6x6x0.8 mm

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-I

Q

PMICs with

Dynamic Core for PDAs and Smart Phones

______________________________________________________________________________________ 31

32, 44, 48L QFN.EPS

PROPRIETARY INFORMATION

APPROVAL

TITLE:

DOCUMENT CONTROL NO.

21-0144

PACKAGE OUTLINE

32, 44, 48L THIN QFN, 7x7x0.8 mm

1

C

REV.

2

e

L

e

L

A1AA2

E/2

E

D/2

D

DETAIL A

D2/2

D2

b

L

k

E2/2

E2

(NE-1) X e

(ND-1) X e

e

C

L

C

L

C

L

C

L

k

DALLAS

SEMICONDUCTOR

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)

MAX1586A/MAX1586B/MAX1587A

High-Efficiency, Low-IQPMICs with
Dynamic Core for PDAs and Smart Phones

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

PROPRIETARY INFORMATION

DOCUMENT CONTROL NO.APPROVAL

TITLE:

C

REV.

2

2

21-0144

PACKAGE OUTLINE

32, 44, 48L THIN QFN, 7x7x0.8 mm

DALLAS

SEMICONDUCTOR

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)