19-0892; Rev 3; 12/96
CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
_______________General Description
The MAX154/MAX158 are high-speed multi-channel
analog-to-digital converters (ADCs). The MAX154 has
four analog input channels while the MAX158 has eight
channels. Conversion time for both devices is 2.5µs.
The MAX154/MAX158 also feature a 2.5V on-chip reference, forming a complete high-speed data acquisition
system.
Both converters include a built-in track/hold, eliminating
the need for an external track/hold. The analog input
range is 0V to +5V, although the ADC operates from a
single +5V supply.
____________________________Features
♦ One-Chip Data Acquisition System
♦ Four or Eight Analog Input Channels
♦ 2.5µs per Channel Conversion Time
♦ Internal 2.5V Reference
♦ Built-In Track/Hold Function
1
♦
LSB Error Specification
/
2
♦ Single +5V Supply Operation
♦ No External Clock
♦ New Space-Saving SSOP Package
Microprocessor interfaces are simplified by the ADC’s
ability to appear as a memory location or I/O port without
the need for external logic. The data outputs use latched,
three-state buffer circuitry to allow direct connection to a
microprocessor data bus or system input port.
________________________Applications
Digital Signal Processing
High-Speed Data Acquisition
Telecommunications
High-Speed Servo Control
Audio Instrumentation
______________Ordering Information
PART
MAX154ACNG
MAX154BCNG
MAX154BC/D 0°C to +70°C
MAX154ACWG
MAX154BCWG
MAX154ACAG 0°C to +70°C
TEMP. RANGE PIN-PACKAGE
0°C to +70°C
0°C to +70°C
24 Narrow
Plastic DIP
24 Narrow
Plastic DIP
Dice
0°C to +70°C 24 Wide SO
0°C to +70°C
24 Wide SO
24 SSOP
MAX154BCAG 0°C to +70°C 24 SSOP ±1
Ordering Information continued at end of data sheet.
ERROR
(LSB)
1
±
±1
1
±
1
±
±1
1
±
/
/
/
/
__________________________________________________________Pin Configurations
MAX154/MAX158
2
2
2
2
TOP VIEW
AIN4
AIN3
AIN2
AIN1
REF OUT
DB0
DB1
DB2
DB3
INT
GND
1
2
3
4
MAX154
5
6
7
8
9
RD
10
11
12
V
DD
24
N.C.
23
A0
22
A1
21
DB7
20
DB6
19
DB5
18
DB4
17
CS
16
RDY
15
+
V
14
REF
V
-
13
REF
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
REF OUT
DB0
DB1
DB2
DB3
INT
GND
1
2
3
4
MAX158
5
6
7
8
9
10
11
RD
12
13
14
AIN7
28
AIN8
27
V
26
DD
A0
25
A1
24
A2
23
DB7
22
DB6
21
DB5
20
DB4
19
CS
18
RDY
17
+
V
16
REF
V
-
15
REF
DIP/SO/SSOP
DIP/SO/SSOP
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDto GND.........................................0V, +10V
Voltage at Any Other Pins........................GND -0.3V, V
Output Current (REF OUT)..................................................30mA
Power Dissipation (any package) to +75°C ....................450mW
Derate above +25°C by..............................................6mW/°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DD
+0.3V
ELECTRICAL CHARACTERISTICS
(VDD= +5V, V
PARAMETER SYMBOL MIN TYP MAX UNITS
ACCURACY
Resolution 8 Bits
MAX154/MAX158
Total Unadjusted Error (Note 1)
No-Missing-Codes Resolution 8 Bits
Channel-to-Channel Mismatch ±1/4 LSB
REFERENCE INPUT
Reference Resistance 14kΩ
V
+ Input Voltage Range V
REF
V
- Input Voltage Range GND V
REF
REFERENCE OUTPUT (Note 2)
Output Voltage REF OUT 2.47 2.50 2.53 V
Load Regulation -6 -10 mV
Power-Supply Sensitivity ±1 ±3 mV
Output Noise e
Capacitive Load 0.01 µF
ANALOG INPUT
Analog Input Voltage Range A
Analog Input Capacitance C
Analog Input Current I
Slew Rate, Tracking SR 0.7 0.157 V/µs
LOGIC INPUTS (–R—D–, –C—S–, A0, A1, A2)
Input High Voltage V
Input Low Voltage V
Input High Current I
Input Low Current I
Input Capacitance (Note 4) C
REF+
= +5V, V
= GND, Mode 0, TA= T
REF-
N
INR
AIN
AIN
INH
INL
INH
INL
IN
to T
MIN
MAX15_A
TA= +25°C
IL= 0mA to 10mA, TA= +25°C
VDD±5%, TA= +25°C
MAX15_ _C
MAX15_ _E
MAX15_ _M
Any channel, AIN = 0V to 5V
Operating Temperature Ranges
MAX15_ _C_ _.....................................................0°C to +70°C
MAX15_ _E_ _..................................................-40°C to +85°C
MAX15_ _M_ _...............................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
, unless otherwise noted).
MAX
CONDITIONS
±1/2
±1MAX15_B
-VDDV
REF
REF
40 70
40 70Temperature Drift (Note 3)
60 100
200 µV/rms
V
-V
REF
45 pF
2.4 V
58pF
REF
±3 µA
0.8 V
-1 µA
LSB
+ V
ppm/°C
+ V
1 µA
2 _______________________________________________________________________________________
CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +5V, V
LOGIC OUTPUTS
Output High Voltage
Output Low Voltage
Output Capacitance (Note 4)
POWER-SUPPLY
Supply Voltage
Supply Current
Note 1: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 2: Specified with no external load unless otherwise noted.
Note 3: Temperature drift is defined as change in output voltage from +25°C to T
Note 4: Guaranteed by design.
REF+
= +5V, V
= GND, MODE 0, TA= T
REF-
OH
V
OL
OUT
DD
DD
to T
MIN
, unless otherwise noted).
MAX
CONDITIONS
DB0-DB7, INT; I
DB0-DB7, INT; RDY
DB0-DB7, RDY; V
OUT
OUT
= -360µA
I
OUT
I
OUT
= 0V to V
= 1.6mA
= 2.6mA
5V ±5% for specified performance
CS = RD = 2.4V
VDD= ±5%
TIMING CHARACTERISTICS (Note 5)
(VDD= +5V, V
REF+
= +5V, V
= GND, MODE 0, TA= T
REF-
MIN
to T
, unless otherwise noted).
MAX
DD
MIN
or T
divided by (25 - T
MAX
MIN
0.4
0.4
) or (T
MAX
MAX154/MAX158
UNITSMIN TYP MAXSYMBOLPARAMETER
V4.0V
V
µA±3Three-State Output Current
pF58C
V4.75 5.25V
mA15I
mW25 75Power Dissipation
LSB±1/16 ±1/4PSSPower-Supply Sensitivity
- 25).
PARAMETER
CS to RD Setup Time
CS to RD Hold Time
Multiplexer Address
Setup Time
Multiplexer Address
Hold Time
CS to RDY Delay
Conversion Time (Mode 0)
Data Access Time After RD
Data Access Time
After INT, Mode 0
RD to INT Delay (Mode 1)
Data Hold Time
Delay Time
Between Conversions
RD Pulse Width (Mode 1)
SYMBOL
t
CSS
t
CSH
t
AS
t
AH
t
RDY
t
CRD
t
ACC1
t
ACC2
t
INTH
t
DH
t
P
t
RD
CONDITIONS
CL= 50pF, RL= 5kΩ
(Note 6)
(Note 6)
CL= 50pF
(Note 7)
Note 5: All input control signals are specified with t
TA= +25°C
MIN TYP MAX
0
0
0
30
30 40
1.6 2.0
85
20 50
40 75
60
500
60 600
= tF= 20ns (10% to 90% of +5V) and timed from a 1.6V voltage level.
R
MAX15_C/E
MIN MAX MIN MAX
0
0
0
35
60
2.4
110
60
100
70
500
80 500 80 400
MAX15_M
0
0
0
40
600
Note 6: Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 7: Defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
60
2.8
120
70
100
70
UNITS
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
_______________________________________________________________________________________ 3
CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
REFERENCE TEMPERATURE DRIFT
2.520
MX7824/28-1
2.510
2.500
REF OUT VOLTAGE (V)
2.490
MAX154/MAX158
2.480
-50 150
050
AMBIENT TEMPERATURE (°C)
100
ACCURACY vs. V
[V
= V
2.0
1.5
1.0
LINEARITY ERROR (LSB)
0.5
0
REF
05
OUTPUT CURRENT
vs. TEMPERATURE
20
VDD = 5V
16
12
8
OUTPUT CURRENT (mA)
4
0
-100 150
-50 0 50
AMBIENT TEMPERATURE (°C)
I
SOURCE VOUT
I
SINK VOUT
REF
(+) - V
(-)]
REF
V
= 5V
DD
MX7824/28-4
3412
(V)
V
REF
REF
= 2.4V
= 0.4V
100
POWER-SUPPLY CURRENT vs. TEMPERATURE
8
7
6
5
4
– SUPPLY CURRENT (mA)
DD
I
3
2
vs. DELAY BETWEEN CONVERSIONS (t
ACCURACY
2.0
MX7824/28-2
1.5
1.0
LINEARITY ERROR (LSB)
0.5
0
300 900
tp (ns)
(NOT INCLUDING REFERENCE LADDER)
V
= 5.25V
DD
V
= 5V
DD
V
= 4.75V
DD
-100 150
AMBIENT TEMPERATURE (°C)
50 100-50 0
MX7824/28-5
)
p
V
= 5V
DD
V
REF
700 800400 500 600
= 5V
MX7824/28-3
+5V
3k
DBN
3k
DBN
100pF
DGND
a. High-Z to V
OH
b. High-Z to V
Figure 1. Load Circuits for Data-Access Time Test
10pF
DGND
DBN
3k
DGND
OL
a. High-Z to V
OH
Figure 2. Load Circuits for Data-Hold Time Test
DBN
100pF
4 _______________________________________________________________________________________
+5V
3k
10pF
b. High-Z to V
DGND
OL
CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
_____________________________________________________________Pin Descriptions
PIN
MAX154
24
V
V
RD10
INT11
REF
REF
RDY15
CS16
DD
FUNCTIONNAME
Analog Input Channel 4AIN41
Analog Input Channel 3AIN32
Analog Input Channel 2AIN23
Analog Input Channel 1AIN14
Reference Output (2.5V) for MAX154REF OUT5
Three-State Data Output, bit 0 (LSB)DBO6
Three-State Data Output, bit 1DB17
Three-State Data Output, bit 2DB28
Three-State Data Output, bit 3DB39
Read Input. RD controls conversions and
data access. See
Interrupt Output. INT going low indicates the completion of a conversion.
See
Digital Interface
GroundGND12
Lower Limit of Reference Span. Sets
the zero-code voltage.
-13
Range: GND to V
Upper Limit of Reference Span. Sets
the full-scale input voltage.
+14
Range: V
Ready Output. Open-drain output with
no active pull-up device. Goes low
when CS goes low and high impedance at the end of a conversion.
Chip-Select Input. CS must be low for
the device to be selected.
Three-State Data Output, bit 4DB417
Three-State Data Output, bit 5DB518
Three-State Data Output, bit 6DB619
Three-State Data Output, bit 7 (MSB)DB720
Channel Address 1 InputA121
Channel Address 0 InputA022
No ConnectNC23
Power-Supply Voltage, +5VV
REF
- to VDD.
Digital Interface
section.
+.
REF
section.
PIN
MAX158
26
FUNCTIONNAME
Analog Input Channel 6AIN61
Analog Input Channel 5AIN52
Analog Input Channel 4AIN43
Analog Input Channel 3AIN34
Analog Input Channel 2AIN25
Analog Input Channel 1AIN16
Reference Output (2.5V) for MAX158 REF OUT7
Three-State Data Output, bit 0 (LSB)DB08
Three-State Data Output, bit 1DB19
Three-State Data Output, bit 2DB210
Three-State Data Output, bit 3DB311
Read Input. RD controls conversions
RD12
INT13
V
REF
V
REF
RDY17
CS18
DD
and data access.
See
Digital Interface
Interrupt Output. INTgoing low indicates the completion of a conversion.
See
Digital Interface
GroundGND14
Lower Limit of Reference Span. Sets
the zero-code voltage.
-15
Range: GND to V
Upper Limit of Reference Span. Sets
the full-scale input voltage.
+16
Range: V
Ready Output. Open-drain output with
no active pull-up device. Goes low
when CSgoes low and high impedance at the end of a conversion.
Chip-Select input. –CS must be low for
the device to be selected.
Three-State Data Output, bit 4DB419
Three-State Data Output, bit 5DB520
Three-State Data Output, bit 6DB621
Three-State Data Output, bit 7 (MSB)DB722
Channel Address 2 InputA223
Channel Address 1 InputA124
Channel Address 0 InputA025
Power-Supply Voltage, +5VV
Analog Input Channel 8AIN827
Analog Input Channel 7AIN728
REF
- to VDD.
section.
section.
REF
+.
MAX154/MAX158
_______________________________________________________________________________________ 5
CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
_______________Detailed Description
Converter Operations
The MAX154/MAX158 use what is commonly called a
"half-flash" conversion technique (Figure 3). Two 4-bit
flash ADC converter sections are used to achieve an 8bit result. Using 15 comparators, the upper 4-bit MS
(most significant) flash ADC compares the unknown
input voltage to the reference ladder and provides the
upper four data bits.
An internal DAC uses the MS bits to generate an analog
signal from the first flash conversion. A residue voltage
representing the difference between the unknown input
and the DAC voltage is then compared to the reference
ladder by 15 LS (least significant) flash comparators to
obtain the lower four output bits.
MAX154/MAX158
Operating Sequence
The operating sequence is shown in Figure 4. A conversion is initiated by a falling edge of RD and CS. The
comparator inputs track the analog input voltage for
approximately 1µs. After this first cycle, the MS flash
result is latched into the output buffers and the LS conversion begins. INT goes low approximately 600ns later,
indicating the end of the conversion, and that the lower
four bits are latched into the output buffers. The data
can then be accessed using the CSand RD inputs.
___________________Digital Interface
The MAX154/MAX158 use only Chip Select (CS) and
Read (RD) as control inputs. A READ operation, taking
CS and RD low, latches the multiplexer address inputs
and starts a conversion (Table 1).
Table 1. Truth Table for Input Channel
Selection
MAX154/MX7824
A1 A0
00
01
10
11
There are two interface modes, which are determined
by the length of the RD input. Mode 0, implemented by
keeping RD low until the conversion ends, is designed
for microprocessors that can be forced into a WAIT
state. In this mode, a conversion is started with a READ
operation (taking CS and RD low), and data is read
when the conversion ends. Mode 1, on the other hand,
does not require microprocessor WAIT states. A READ
operation simultaneously initiates a conversion and
reads the previous conversion result.
MAX158/MX7828
A2 A1 A0
000
001
010
011
100
101
110
111
SELECTED
CHANNEL
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
V
+
REF
V
-
REF
AIN1
AIN4
AIN8
REF OUT
*MAX154 – 4-Channel Mux
MAX158 – 8-Channel Mux
Figure 3. Functional Diagram
6 _______________________________________________________________________________________
MUX*
2.5V
REF
ADDRESS
LATCH
DECODE
A0
A1 A2
V
+
REF
16
4-BIT
FLASH
ADC
(4MSB)
4-BIT
DAC
4-BIT
FLASH
ADC
(4LSB)
TIMING AND CONTROL
CIRCUITRY
RDY CS RD
THREE-
STATE
DRIVERS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
INT
CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
RD
500ns
SETUP TIME REQUIRED
BY THE INTERNAL
COMPARATORS PRIOR TO
STARTING CONVERSION
V
IS TRACKED
IN
BY INTERNAL
COMPARATORS
1000ns
IS SAMPLED
V
IN
AND THE FOUR MSBs
ARE LATCHED
600ns
INT GOING LOW INDICATES
THAT CONVERSION IS
COMPLETE AND THAT
DATA CAN BE READ
Figure 4. Operating Sequence
Interface Mode 0
Figure 5 shows the timing diagram for Mode 0 operation. This is used with microprocessors that have WAIT
state capability, whereby a READ instruction is extended to accommodate slow-memory devices. Taking CS
and RD low latches the analog multiplexer address and
starts a conversion. Data outputs DB0–DB7 remain in
the high-impedance condition until the conversion is
complete.
There are two status outputs: Interrupt (INT) and Ready
(RDY). RDY, an open-drain output (no internal pull-up
device), is connected to the processor’s READY/WAIT
input. RDY goes low on the falling edge of CS and goes
high impedance at the end of the conversion, when the
conversion result appears on the data outputs. If the
RDY output is not required, its external pull-up resistor
can be omitted. INT goes low when the conversion is
complete and returns high on the rising edge of CS or
RD.
Interface Mode 1
Mode 1 is designed for applications where the microprocessor is not forced into a WAIT state. Taking CS
and RD low latches the multiplexer address and starts
a conversion (Figure 6). Data from the previous
conversion is immediately read from the outputs
(DB0–DB7).
INT goes high at the rising edge of CS or RD and goes
low at the end of the conversion. A second READ operation is required to read the result of this conversion.
The second READ latches a new multiplexer address
and starts another conversion. A delay of 2.5µs must
be allowed between READ operations. RDY goes low
on the falling edge of CS and goes high impedance at
the rising edge of CS. If RDY is not needed, its external
pull-up resistor can be omitted.
MAX154/MAX158
CS
t
RD
ANALOG
CHANNEL
ADDRESS
RDY
INT
DATA
CSS
t
AS
ADDR
VALID
Figure 5. Mode 0 Timing Diagram
_______________________________________________________________________________________ 7
t
AH
t
RDY
HIGH IMPEDANCE
t
CSH
t
P
t
INTH
t
CRD
t
ACC2
DATA
VALID
t
DH
t
CSS
t
AS
ADDR
VALID
CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
CS
t
RD
ANALOG
CHANNEL
ADDRESS
RDY
CSS
t
AS
ADDR
VALID
t
AH
t
RDY
MAX154/MAX158
INT
DATA
t
ACCI
t
RD
t
CRD
t
INTH
t
OLD
DATA
Figure 6. Mode 1 Timing Diagram
_____________Analog Considerations
Reference and Input
The V
zero and the full-scale of the ADC. In other words, the
voltage at V
duces an output code of all zeros, and the voltage at
V
REF
code of all ones (Figure 7).
Figure 8 shows some possible reference configura-
tions. A 0.01µF bypass capacitor to GND should be
used to reduce the high-frequency output impedance
of the internal reference. Larger capacitors should not
be used, as this degrades the stability of the reference
buffer. The 2.5V reference output is with respect to the
GND pin.
A 47µF electrolytic and 0.1µF ceramic capacitor should
be used to bypass the VDDpin to GND. These capacitors must have minimum lead length, since excess lead
length may contribute to conversion errors and instability. If the reference inputs are driven by long lines,
they should be bypassed to GND with 0.1µF capacitors at the reference input pins.
REF
+ and V
REF
- inputs of the converter define the
REF
- is equal to the input voltage that pro-
+ is equal to input voltage that produces an output
Bypassing
t
t
CSS
CSH
t
P
t
AS
ADDR
VALID
DH
OUTPUT
CODE
11111111
11111110
11111101
00000011
00000010
00000001
00000000
1
V
-
REF
23
t
AH
t
RDY
t
ACCI
AIN INPUT VOLTAGE
t
RD
NEW
DATA
1LSB = F8 = V
256 256
(IN TERMS OF LSBs)
t
t
INTH
t
DH
FULL-SCALE
TRANSITION
REF
CSH
+ - V
FS–1LSB
REF
-
+
V
REF
FS
Figure 7. Transfer Function
8 _______________________________________________________________________________________
CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
(+)
AIN
x
(-)
AIN
x
+5V
0.1µF47µF
0.01µF
Figure 8a. Internal Reference
(+)
AIN
x
AINx(-)
+5V
0.1µF
47µF
Figure 8b. Power Supply as Reference
V
IN
GND
V
DD
REFOUT
V
+
REF
-
V
REF
V
IN
GND
V
DD
V
REF
V
REF
MAX154
MAX158
MAX154
MAX158
+
-
Input Current
MAX154/MAX158
The converters’ analog inputs behave somewhat differently from conventional ADCs. The sampled data comparators take varying amounts of current from the input,
depending on the cycle they are in. The equivalent circuit of the converter is shown in Figure 9a. When the
conversion starts, AIN(n) is connected to the MS and
LS comparators. Thus, AIN(n) is connected to thirty-one
1pF capacitors.
To acquire the input signal in approximately 1µs, the input
capacitors must charge to the input voltage through the
on-resistance of the multiplexer (about 600Ω) and the
comparator’s analog switches (2kΩ to 5kΩ per compara-
tor). In addition, about 12pF of stray capacitance must be
charged. The input can be modeled as an equivalent RC
network shown in Figure 9b. As RS(source impedance)
increases, the capacitors take longer to charge.
Since the length of the input acquisition time is internally set, large source resistances (greater than 100Ω) will
cause settling errors. The output impedance of an opamp is its open-loop output impedance divided by the
loop gain at the frequency of interest. It is important
that the amplifier driving the converter input have sufficient loop gain at approximately 1MHz to maintain low
output impedance.
The transients in the analog input caused by the sam-
Input Filtering
pled data comparators do not degrade the converter’s
performance, since the ADC does not “look” at the
input when these transients occur. The comparator’s
outputs track the input during the first 1µs of the conversion, and are then latched. Therefore, at least 1µs
will be provided to charge the ADC’s input capacitance. It is not necessary to filter these transients with
an external capacitor on the AIN terminals.
* Current path must
still exist from
to Ground
V
+5V
0.1µF
IN(-)
47µF
AIN
AIN
(+)
x
2.5V
(-)
x
*
Figure 8c. Inputs Not Referenced to GND
_______________________________________________________________________________________ 9
V
IN
GND
V
DD
V
REF
V
REF
+
-
MAX154
MAX158
Sinusoidal Inputs
The MAX154/MAX158 can measure input signals with
slew rates as high as 157mV/µs to the rated specifications.
This means that the analog input frequency can be as
high as 10kHz without the aid of an external track/hold.
The maximum sampling rate is limited by the conversion
time (typical t
conversions (tp= 500ns). It is calculated as:
f
MAX
=
f
permits a maximum sampling rate of 50kHz per
MAX
channel when using the MAX158 and 100kHz per
channel when using the MAX154. These rates are well
above the Nyquist requirement of 20kHz sampling rate
for a 10kHz input bandwidth.
= 2µs) plus the time required between
CRD
t
CRD
1
+ t
p
=
1 =400kHz
(2.0 + 0.5) µs
CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
Bipolar Input Operation
The circuit in Figure 10a can be used for bipolar input
operation. The input voltage is scaled by an amplifier
so that only positive voltages appear at the ADC’s
inputs. The analog input range is ±4V and the output
code is complementary offset binary. The ideal
input/output characteristic is shown in Figure 10b.
C
S
2pF
R
S
AIN1
V
IN
R
12pF
MAX154/MAX158
Figure 9a. Equivalent Input Circuit
R
S
AIN1
C
V
IN
Figure 9b. RC Network Model
11.5Ω
V
IN
10.0k
0.01µF
2pF
16.2k
S1
MUX
B MUX
600Ω
3.57k
R
ON
TO LS
LADDER
15 LSB COMPARATORS
R
ON
TO MS
LADDER
16 MSB COMPARATORS
350Ω
C
S2
2pF
R
ON
AIN1
1pF
1pF
MAX154
MAX158
1pFCS
•
•
•
1pF
•
•
•
32pF
CS
RDY
RD
11111111
11111110
11111101
10000010
10000001
10000000
01111111
01111110
00000010
00000001
00000000
-FS
2
+ 1LSB
Figure 10b. Transfer Function for ±4V Input Operation
A15
A0
MREQ
ZBO
WAIT
RD
AIN INPUT VOLTAGE (LSBs)
ADDRESS BUS
ADDRESS
EN
DECODE
5V
5k
0V
FS = 8V
1LSB = FS / 256
A1 A2*A0
MAX154
CS
MAX158
RDY
RD
+FS
2
0.01µF
+5V
0.1µF47µF
ONLY CHANNEL 1 SHOWN
+
V
REF
REFOUT
V
DD
V
-
REF
GND
INT
DB0-DB7
D0-D7
*A2 ON MAX158.
Figure 11. Simple Mode 0 Interface
DATA BUS
Figure 10a. Bipolar ±4V Input Operation
10 ______________________________________________________________________________________
DB0-DB7
CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
+5V
26
V
DD
BANDPASS
FILTER 1
BANDPASS
FILTER 2
6
AIN1 CS
5
AIN2
RD
MAX158
SPEECH
INPUT
AMP
BANDPASS
FILTER 7
BANDPASS
FILTER 8
+5V
28
AIN7
27
AIN8
16
V
REF+
V
REF-
15 14
DB0-DB7
A2
A1
A0
GND
Figure 12. Speech Analysis Using Real-Time Filtering
18
12
23
24
25
DATA
_Ordering Information (continued)
PART
TEMP. RANGE PIN-PACKAGE
MAX154AENG -40°C to +85°C 24 Plastic DIP ±
MAX154BENG -40°C to +85°C 24 Plastic DIP ±1
MAX154AEWG
MAX154BEWG
MAX154AEAG -40°C to +85°C
MAX154BEAG
MAX154AMRG
MAX154BMRG -55°C to +125°C
MAX158ACPI
MAX158BCPI
-40°C to +85°C
-40°C to +85°C
24 Wide SO
24 Wide SO
24 SSOP
-40°C to +85°C 24 SSOP
-55°C to +125°C
24 CERDIP
24 CERDIP
0°C to +70°C 28 Plastic DIP
0°C to +70°C
28 Plastic DIP
MAX158BC/D 0°C to +70°C Dice ±
MAX158ACWI 0°C to +70°C 28 Wide SO ±
MAX158BCWI 0°C to +70°C 28 Wide SO ±1
MAX158ACAI 0°C to +70°C 28 SSOP ±
MAX158BCAI 0°C to +70°C 28 SSOP ±1
MAX158AEPI -40°C to +70°C 28 Plastic DIP ±
MAX158BEPI -40°C to +85°C 28 Plastic DIP ±1
MAX158AEWI -40°C to +85°C 28 Wide SO ±
MAX158BEWI -40°C to +85°C 28 Wide SO ±1
MAX158AEAI -40°C to +85°C 28 SSOP ±
MAX158BEAI -40°C to +85°C 28 SSOP ±1
MAX158AMJI -55°C to +125°C 28 CERDIP ±
MAX158BMJI -55°C to +125°C 28 CERDIP ±1
ERROR
(LSB)
1
/
2
1
/
±
2
±1
1
±
/
2
±1
1
±
/
2
±1
1
±
/
2
±1
1
/
2
1
/
2
1
/
2
1
/
2
1
/
2
1
/
2
1
/
2
MAX154/MAX158
+5V
24 16 10
CS
MAX154
A0
A1
RD
INT
DB0-DB7
A1
A0
V
DD
4
AIN1
3
AIN2
2
AIN3
1
AIN4
14
V
REF+
13
V
REF-
12
GND
Figure 13. 4-Channel Fast Sample and Infinite Hold
______________________________________________________________________________________ 11
SAMPLE
PULSE
15
16
17
WR
DB0-DB7
A1
A0
11
21
22
+5V
V
MAX506
V
18
DD
V
V
OUT
V
OUT
V
OUT
V
OUT
DGND
AGND
SS
3
REF
+5V
4
2
A
1
B
20
C
19
D
6
5
CMOS High-Speed 8-Bit ADCs with
Multiplexer and Reference
___________________Chip Topography
AIN4
AIN6
AIN5
(AIN2)
(AIN3)
AIN7
AIN8
(AIN4)
VDDA0
AIN3
(N.C.)
(N.C.)
(AIN1)
AIN2 (N.C.)
AIN1 (N.C.)
TP (REF OUT)
DB0
DB1
MAX154/MAX158
DB2
DB3
A0
( ) ARE FOR MAX154/MX7824
INT
GND
V
REF
V
-
REF
0.124"
(3.150mm)
+ ADY
A1
A2 (N.C.)
(3.228mm)
DB7
DB6
DB5
DB4
CS
0.127"
________________________________________________________Package Information
DIM
A1
C
α
D
HE
H
C
L
INCHES
MIN
MAX
A
0.068
0.002
B
0.010
0.004
E
0.205
e
0.301
L
0.025
α
0.078
0.008
0.015
0.008
SEE VARIATIONS
0.209
0.311
0.037
0˚
8˚
MILLIMETERS
MIN
1.73
0.05
0.25
0.09
5.20
0.65 BSC0.0256 BSC
7.65
0.63
0˚
MAX
1.99
0.21
0.38
0.20
5.38
7.90
0.95
8˚
14
16
20
24
28
INCHES
MIN
0.239
0.239
0.278
0.317
0.397
DIM
PINS
e
SSOP
A
SHRINK
SMALL-OUTLINE
B
A1
PACKAGE
D
D
D
D
D
MAX
0.249
0.249
0.289
0.328
0.407
MILLIMETERS
MAX
MIN
6.33
6.07
6.33
6.07
7.33
7.07
8.33
8.07
10.33
10.07
21-0056A
D
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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