Rainbow Electronics MAX1545 User Manual

General Description

The MAX1519/MAX1545 are dual-phase, Quick-PWM™, step-down controllers for desktop and mobile Pentium®4 (P4) CPU core supplies. Dual-phase operation reduces input ripple current requirements and output voltage ripple while easing component selection and layout difficulties. The Quick-PWM control scheme provides instantaneous response to fast load-current steps. The MAX1519/MAX1545 include active voltage positioning with adjustable gain and offset, reducing power dissipation and bulk output capacitance requirements.

The MAX1519/MAX1545 are intended for two different notebook CPU core applications: stepping down the battery directly or stepping down the 5V system supply to create the core voltage. The single-stage conversion method allows these devices to directly step down highvoltage batteries for the highest possible efficiency. Alternatively, two-stage conversion (stepping down the 5V system supply instead of the battery) at a higher switching frequency provides the minimum possible physical size.

The MAX1519/MAX1545 comply with Intel’s P4 specifications. The switching regulator features soft-start, power-up sequencing, and soft-shutdown. The MAX1519/MAX1545 also feature independent four-level logic inputs for setting the suspend voltage (S0–S1).

The MAX1519/MAX1545 include output undervoltage protection (UVP), thermal protection, and voltage regulator power-OK (VROK) output. When any of these protection features detect a fault, the controller shuts down. Additionally, the MAX1519/MAX1545 include overvoltage protection.

The MAX1519/MAX1545 are available in low-profile, 40pin, 6mm x 6mm thin QFN packages. For other CPU platforms, refer to the pin-to-pin compatible MAX1544 and MAX1532/MAX1546/MAX1547 data sheets.

Applications

Desktop and Mobile P4 Computers

Multiphase CPU Core Supply

Voltage-Positioned Step-Down Converters

Servers/Desktop Computers

Low-Voltage, Digitally Programmable Power Supplies

Features

♦ Dual-Phase, Quick-PWM Controllers

♦ ±0.75% V

OUT

Accuracy Over Line, Load, and

Temperature (1.3V)

♦ Active Voltage Positioning with Adjustable Gain

and Offset

♦ 5-Bit On-Board DAC

Mobile: 0.60V to 1.75V Output Range Desktop: 1.10V to 1.85V Output Range

♦ Selectable 100kHz/200kHz/300kHz/550kHz

Switching Frequency

♦ 4V to 28V Battery Input Voltage Range

♦ Adjustable Slew-Rate Control

♦ Drive Large Synchronous Rectifier MOSFETs

♦ Output Overvoltage Protection (MAX1545 Only)

♦ Undervoltage and Thermal-Fault Protection

♦ Power Sequencing and Timing

♦ Selectable Suspend Voltage (0.675V to 1.45V)

♦ Soft-Shutdown

♦ Selectable Single- or Dual-Phase Pulse Skipping

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

________________________________________________________________ Maxim Integrated Products 1

Pin Configuration

Ordering Information

19-2734; Rev 1; 9/03

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Quick-PWM is a trademark of Maxim Integrated Products, Inc.

Pentium is a registered trademark of Intel Corp.

PART TEMP RANGE PIN-PACKAGE

MAX1519ETL -40°C to +100°C 40 Thin QFN 6mm

MAX1545ETL -40°C to +100°C 40 Thin QFN 6mm ✕ 6mm

✕ 6mm

TOP VIEW

TIME

TON SUS

S0 S1

SHDN

OFS

REF

ILIM

CSN

CMN

CMPV+BSTS

CSP

403938373635343332

MAX1519 MAX1545

111213141516171819

CCI

CCV

GND

GNDS

THIN QFN

LXS

DHS

DLS

PGND

DLM

DHM

LXM BSTM

VROK

OAIN-

OAIN+

SKIP

CODE

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

V+ to GND ..............................................................-0.3V to +30V

to GND..............................................................-0.3V to +6V

to PGND............................................................-0.3V to +6V

SKIP, SUS, D0–D4 to GND.......................................-0.3V to +6V

ILIM, FB, OFS, CCV, CCI, REF, OAIN+,

OAIN- to GND.........................................-0.3V to (V

+ 0.3V)

CMP, CSP, CMN, CSN, GNDS to GND ......-0.3V to (V

+ 0.3V)

TON, TIME, VROK, S0–S1, CODE to GND.-0.3V to (V

+ 0.3V)

SHDN to GND (Note 1)...........................................-0.3V to +18V

DLM, DLS to PGND....................................-0.3V to (V

+ 0.3V)

BSTM, BSTS to GND ..............................................-0.3V to +36V

DHM to LXM ...........................................-0.3V to (V

BSTM

+ 0.3V)

LXM to BSTM............................................................-6V to +0.3V

DHS to LXS..............................................-0.3V to (V

BSTS

+ 0.3V)

LXS to BSTS .............................................................-6V to +0.3V

GND to PGND .......................................................-0.3V to +0.3V

REF Short-Circuit Duration .........................................Continuous

Continuous Power Dissipation (T

= +70°C)

40-Pin 6mm

✕ 6mm Thin QFN

(derate 23.2mW/°C above +70°C)...............................1.860W

Operating Temperature Range .........................-40°C to +100°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 1, V+ = 15V, VCC= VDD= V

SHDN

= V

TON

= V

SKIP

= VS0= VS1= V

CODE

= 5V, VFB= V

CMP

= V

CMN

= V

CSP

= V

CSN

= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.)

Note 1: SHDN may be forced to 12V for the purpose of debugging prototype boards using the no-fault test mode, which disables

fault protection and overlapping operation.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PWM CONTROLLER

Input Voltage Range

DC Output Voltage Accuracy (Note 2)

Line Regulation Error VCC = 4.5V to 5.5V, V+ = 4.5V to 28V 5 mV

IFB, I

Input Bias Current

OFS

GNDS

OFS Input Range 02V

OFS Gain A

OFS

GNDS Input Range -20 +200 mV

GNDS Gain A

TIME Frequency Accuracy f

GNDS

TIME

Battery voltage, V+ 4 28

, V

V+ = 4.5V to 28V, includes load regulation error

DAC codes ≥ 1V -10 +10

DAC codes from

0.60V to 1V

4.5 5.5

-15 +15

FB, GNDS -2 +2

OFS -0.1 +0.1

∆V

/∆V

OUT

OFS

OUT

OFS

OUT

= V

/∆V

= V

/∆V

OFS;

GNDS

OFS, VOFS

- V

OFS

REF, VOFS

∆V

∆V ∆V

∆V

1000kHz nominal, R

500kHz nominal, R

250kHz nominal, R

Shutdown, R

= 30kΩ 125

TIME

= 0 to 1V

= 1V to 2V

= 15kΩ 900 1000 1100

TIME

= 30kΩ 460 500 540

TIME

= 60kΩ 225 250 275

TIME

-0.129 -0.125 -0.117

0.97 0.99 1.01 V/V

µA

V/V

kHz

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = 15V, VCC= VDD= V

SHDN

= V

TON

= V

SKIP

= VS0= VS1= V

CODE

= 5V, VFB= V

CMP

= V

CMN

= V

CSP

= V

CSN

= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.)

)

On-Time (Note 3) t

Minimum Off-Time (Note 3) t

BIAS AND REFERENCE

Quiescent Supply Current (VCC)I

Quiescent Supply Current (VDD)I

Quiescent Battery Supply Current (V+)

Shutdown Supply Current (VCC) Measured at VCC, SHDN = GND 4 10 µA

Shutdown Supply Current (VDD) Measured at VDD, SHDN = GND <1 5 µA

Shutdown Battery Supply Current (V+)

Reference Voltage V Reference Load Regulation ∆V

FAULT PROTECTION

Output Overvoltage Protection Threshold (MAX1545 Only)

Output Overvoltage Propagation Delay (MAX1545 Only)

Output Undervoltage Protection Threshold

Output Undervoltage Propagation Delay

VROK Threshold

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

OFF(MIN

V+

REF

OVP

UVP

V+ = 12V, V

TON = GND 300 375

TON = VCC, open, or REF 400 480

Measured at VCC, FB forced above the regulation point, OAIN- = FB, V

OAIN+

Measured at VDD, FB forced above the regulation point

Measured at V+ 25 40 µA

Measured at V+, SHDN = GND, V

REF

SKIP = VCC, measured at FB with respect to unloaded output voltage

SKIP = REF or GND 2.00 V

FB forced 2% above trip threshold 10 µs

Measured at FB with respect to unloaded output voltage

FB forced 2% below trip threshold 10 µs

Measured at FB with respect to unloaded output voltage

= V

CCI

= 1.3V

= VDD = 0 or 5V

= 4.5V to 5.5V, I

= -10µA to +100µA -10 +10 mV

= 1.2V

TON = GND (550kHz)

TON = REF (300kHz)

TON = open (200kHz)

TON = V (100kHz)

= 0 1.990 2.000 2.010 V

REF

Lower threshold

(undervoltage)

Upper threshold

(overvoltage)

SKIP = V

155 180 205

320 355 390

475 525 575

920 1000 1140

13 16 19 %

67 70 73 %

-12 -10 -8

+8 +10 +12

1.70 3.20 mA

<1 5 µA

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = 15V, VCC= VDD= V

SHDN

= V

TON

= V

SKIP

= VS0= VS1= V

CODE

= 5V, VFB= V

CMP

= V

CMN

= V

CSP

= V

CSN

= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.)

)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Undervoltage Fault and VROK Transition Blanking Time

BLANK

(Note 4)

VROK Startup Delay

Measured from the time when FB reaches the voltage set by the DAC code; clock speed set by R

TIME

Measured from the time when FB first reaches the voltage set by the DAC code after startup

357ms

24 Clks

VROK Delay t

VROK

VROK Output Low Voltage I

FB forced 2% outside the VROK trip threshold

= 3mA 0.4 V

SINK

10 µs

VROK Leakage Current High state, VROK forced to 5.5V 1 µA

VCC Undervoltage Lockout Threshold

Thermal-Shutdown Threshold T

UVLO(VCC

SHDN

Rising edge, hysteresis = 90mV, PWM disabled below this level

4.0 4.25 4.4 V

Hysteresis = 10°C 160 °C

CURRENT LIMIT AND BALANCE

Current-Limit Threshold Voltage (Positive, Default)

Current-Limit Threshold Voltage (Positive, Adjustable)

Current-Limit Threshold Voltage (Negative)

LIMIT(NEG

Current-Limit Threshold Voltage (Zero Crossing)

CMP, CMN, CSP, CSN Input Ranges

CMP, CMN, CSP, CSN Input Current

Secondary Driver-Disable Threshold

ILIM Input Current I

Current-Limit Default Switchover Threshold

ZERO

LIMIT

CSP

ILIM

CMP - CMN, CSP - CSN; ILIM = V

CMP - CMN, CSP - CSN

= 0.2V 8 10 12

ILIM

= 1.5V 73 75 77

ILIM

CMP - CMN, CSP - CSN; ILIM = VCC, SKIP = V

28 30 32 mV

-41 -36 -31 mV

CMP - CMN, CSP - CSN; SKIP = GND 1.5 mV

02V

= V

= 0 to 5V -2 +2 µA

CSN

3VCC - 1

0.4

= 0 to 5V 0.1 200 nA

3VCC - 1

0.4

CSP

ILIM

- V

Current-Balance Offset V

Current-Balance Transconductance

OS(IBAL

m(IBAL

CMP

-20mV < (V

1.0V < V

CCI

CMN

CMP

< 2.0V

) - (V

- V

CSP

CMN

- V

CSN

) < 20mV,

); I

CCI

= 0,

-2 +2 mV

400 µS

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

_______________________________________________________________________________________ 5

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = 15V, VCC= VDD= V

SHDN

= V

TON

= V

SKIP

= VS0= VS1= V

CODE

= 5V, VFB= V

CMP

= V

CMN

= V

CSP

= V

CSN

= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.)

)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

GATE DRIVERS

DH_ Gate-Driver On-Resistance R

DL_ Gate-Driver On-Resistance R

DH_ Gate-Driver Source/Sink Current

DL_ Gate-Driver Sink Current I

DL_ Gate-Driver Source Current I

Dead Time t

ON(DH)

ON(DL)

DL(SINK

DL(SOURCE

DEAD

VOLTAGE-POSITIONING AMPLIFIER

Input Offset Voltage V

Input Bias Current I

Op Amp Disable Threshold V

Common-Mode Input Voltage Range

BIAS

OAIN-

Common-Mode Rejection Ratio CMRR V

Power-Supply Rejection Ratio PSRR VCC = 4.5V to 5.5V 75 100 dB

Large-Signal Voltage Gain A

Output Voltage Swing

Input Capacitance 11 pF

Gain-Bandwidth Product 3 MHz

Slew Rate 0.3 V/µs

Capacitive-Load Stability No sustained oscillations 400 pF

LOGIC AND I/O

SHDN Input High Voltage V SHDN Input Low Voltage V SHDN No-Fault Threshold V

SHDN

Three-Level Input Logic Levels SUS, SKIP

Logic Input Current SHDN, SUS, SKIP -1 +1 µA

D0–D4 Logic Input High Voltage 1.6 V

D0–D4 Logic Input Low Voltage 0.8 V

BST_ - LX_ forced to 5V 1.0 4.5 Ω

High state (pullup) 1.0 4.5

Low start (pulldown) 0.4 2

DH_ forced to 2.5V, BST_ - LX_ forced to 5V

1.6 A

DL_ forced to 5V 4 A

DL_ forced to 2.5V 1.6 A

DL_ rising 35

DH_ rising 26

-1 +1 mV

OAIN+, OAIN- 0.1 200 nA

3VCC - 1

0.4

Guaranteed by CMRR test 0 2.5 V

OAIN+

= V

= 0 to 2.5V 70 115 dB

OAIN-

RL = 1kΩ to VCC/2 80 112 dB

- V

OAIN+

= 1kΩ to VCC/2

OAIN-

| ≥ 10mV,

VCC - V

FBL

FBH

77 300

47 200

0.8 V

0.4 V

12 15 V

High 2.7

REF 1.2 2.3

Low 0.8

Ω

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

6 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = 15V, VCC= VDD= V

SHDN

= V

TON

= V

SKIP

= VS0= VS1= V

CODE

= 5V, VFB= V

CMP

= V

CMN

= V

CSP

= V

CSN

= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA= 0°C to +85°C, unless otherwise specified. Typical values are at TA= +25°C.)

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 1, V+ = 15V, VCC= VDD= V

SHDN

= V

TON

= V

SKIP

= VS0= VS1= V

CODE

= 5V, VFB= V

CMP

= V

CMN

= V

CSP

= V

CSN

= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA= -40°C to +100°C, unless otherwise specified.) (Note 5)

)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

D0–D4 Input Current D0–D4 -2 +2 µA

CODE Input High Voltage 2.4 V

CODE Input Low Voltage 0.8 V

CODE Input Current -1 +1 µA

Four-Level Input Logic Levels TON, S0–S1

Four-Level Input Current TON, S0–S1 forced to GND or V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PWM CONTROLLER

Input Voltage Range

DC Output Voltage Accuracy (Note 2)

OFS Input Range 02V

OFS Gain A

GNDS Gain A

On-Time (Note 3) t

Minimum Off-Time (Note 3) t

OFS

GNDS

TIME

OFF(MIN

High

0.4

Open 3.15 3.85

REF 1.65 2.35

Low 0.4

-3 +3 µA

Battery voltage, V+ 4 28

, V

V+ = 4.5V to 28V, includes load regulation error

∆V

/∆V

OUT

OFS

OUT

OFS

OUT

OFS;

= V

OFS, VOFS

/∆V

OFS;

= V

OFS

/∆V

GNDS

- V

REF, VOFS

∆V

∆V ∆V

∆V

1000kHz nominal, R

500kHz nominal, R

250kHz nominal, R

V+ = 12V, V

= V

CCI

= 1.2V

DAC codes ≥ 1V -13 +13

DAC codes from

0.60V to 1V

= 0 to 1V

= 1V to 2V

= 15kΩ 880 1120

TIME

= 30kΩ 450 550TIME Frequency Accuracy f

TIME

= 60kΩ 220 280

TIME

TON = GND (550kHz)

TON = REF (300kHz)

TON = open (200kHz)

TON = V

(100kHz)

4.5 5.5

-20 +20

-0.131 -0.115

0.94 1.01 V/V

150 210

315 395

470 580

910 1150

TON = GND 380

TON = VCC, open, or REF 490

V/V

kHz

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

_______________________________________________________________________________________ 7

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = 15V, VCC= VDD= V

SHDN

= V

TON

= V

SKIP

= VS0= VS1= V

CODE

= 5V, VFB= V

CMP

= V

CMN

= V

CSP

= V

CSN

= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA= -40°C to +100°C, unless otherwise specified.) (Note 5)

)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

BIAS AND REFERENCE

Quiescent Supply Current (VCC)I

Quiescent Supply Current (VDD)I

Quiescent Battery Supply Current (V+)

V+

Shutdown Supply Current (VCC) Measured at VCC, SHDN = GND 20 µA

Shutdown Supply Current (VDD) Measured at VDD, SHDN = GND 20 µA

Shutdown Battery Supply Current (V+)

Reference Voltage V

REF

FAULT PROTECTION

Output Overvoltage Protection Threshold (MAX1545 Only)

Output Undervoltage Protection Threshold

OVP

UVP

VROK Threshold

Measured at VCC, FB forced above the regulation point, OAIN- = FB,

= 1.3V

OAIN+

Measured at VDD, FB forced above the regulation point

3.2 mA

20 µA

Measured at V+ 50 µA

Measured at V+, SHDN = GND, V

= VDD = 0 or 5V

VCC = 4.5V to 5.5V, I

= 0 1.985 2.015 V

REF

SKIP = VCC, measured at FB with respect to unloaded output voltage

Measured at FB with respect to unloaded output voltage

Lower threshold

Measured at FB with respect to unloaded output voltage

(undervoltage)

Upper threshold (overvoltage) SKIP = V

13 19 %

67 73 %

-13 -7

+7 +13

20 µA

VROK Startup Delay

VCC Undervoltage Lockout Threshold

CURRENT LIMIT AND BALANCE

Current-Limit Threshold Voltage (Positive, Default)

Current-Limit Threshold Voltage (Positive, Adjustable)

Current-Limit Threshold Voltage (Negative)

Current-Balance Offset V

UVLO(VCC

LIMIT

LIMIT(NEG

OS(IBAL

Measured from the time when FB first reaches the voltage set by the DAC code after startup

Rising edge, hysteresis = 90mV, PWM disabled below this level

CMP - CMN, CSP - CSN; ILIM = V

ILIM

CMP - CMN, CSP - CSN

= 0.2V 7 13

= 1.5V 72 78

CMP - CMN, CSP - CSN; ILIM = VCC, SKIP = V

-20mV < (V

1.0V < V

CMP

- V

CMN

CCI

) - (V

CMP

< 2.0V

- V

CSP

CMN

- V

CSN

) < 20mV,

); I

CCI

= 0,

3ms

3.90 4.45 V

27 33 mV

-30 -42 mV

-3 +3 mV

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

8 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V+ = 15V, VCC= VDD= V

SHDN

= V

TON

= V

SKIP

= VS0= VS1= V

CODE

= 5V, VFB= V

CMP

= V

CMN

= V

CSP

= V

CSN

= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; TA= -40°C to +100°C, unless otherwise specified.) (Note 5)

)

Note 2: DC output accuracy specifications refer to the trip level of the error amplifier. When pulse skipping, the output slightly rises

(< 0.5%) when transitioning from continuous conduction to no load.

Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DHM and DHS pins, with LX_ forced to

GND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual incircuit times may be different due to MOSFET switching speeds.

Note 4: The output fault-blanking time is measured from the time when FB reaches the regulation voltage set by the DAC code.

During normal operation (SUS = GND), regulation voltage is set by the VID DAC inputs (D0–D4). During suspend mode (SUS = REF or high), the regulation voltage is set by the suspend DAC inputs (S0–S1).

Note 5: Specifications to T

= -40°C and +100°C are guaranteed by design and are not production tested.

GATE DRIVERS

DH_ Gate-Driver On-Resistance R

DL_ Gate-Driver On-Resistance R

VOLTAGE-POSITIONING AMPLIFIER

Input Offset Voltage V

Common-Mode Input Voltage Range

Output Voltage Swing

LOGIC AND I/O

SHDN Input High Voltage V SHDN Input Low Voltage V

D0–D4 Logic Input High Voltage 1.6 V

D0–D4 Logic Input Low Voltage 0.8 V

CODE Input High Voltage 2.4 V

CODE Input Low Voltage 0.8 V

Four-Level Input Logic Levels TON, S0–S1

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

ON(DH

ON(DL)

BST_ - LX_ forced to 5V 4.5 Ω

High state (pullup) 4.5

Low start (pulldown) 2

Guaranteed by CMRR test 0 2.5 V

OAIN+

= 1kΩ to VCC/2

- V

OAIN-

| ≥ 10mV,

VCC - V

High 2.7 REF 1.2 2.3Three-Level Input Logic Levels SUS, SKIP

Low 0.8

High

Open 3.15 3.85

REF 1.65 2.35

Low 0.4

FBL

FBH

-2.0 +2.0 mV

0.8 V

0.4

300

200

0.4 V

Ω

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

_______________________________________________________________________________________ 9

)

Typical Operating Characteristics

(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN = SKIP = VCC, D0–D4 set for 1.5V (SUS = GND), S0–S1 set for 1V (SUS = V

), OFS = GND, TA= +25°C, unless otherwise specified.)

100

0.1 10 100

LOAD CURRENT (A)

EFFICIENCY (%)

EFFICIENCY vs. LOAD CURRENT

OUT

= 1.00V)

MAX1519 toc04

VIN = 20V

VIN = 12V

VIN = 8V

SKIP = REF SKIP = V

OUTPUT VOLTAGE vs. LOAD CURRENT

OUT

= 0.80V)

MAX1519 toc05

LOAD CURRENT (A)

OUTPUT VOLTAGE (V)

SUS = V

10 20

0.74

0.76

0.78

0.80

0.82

0.72 040

100

0.1 10 100

LOAD CURRENT (A)

EFFICIENCY (%)

DUAL-PHASE EFFICIENCY vs. LOAD CURRENT

OUT

= 0.80V)

MAX1519 toc06

VIN = 20V

VIN = 8V

VIN = 12V

SKIP = REF

100

0.1 10 100

LOAD CURRENT (A)

EFFICIENCY (%)

SINGLE-PHASE EFFICIENCY

vs. LOAD CURRENT

OUT

= 0.80V)

MAX1519 toc07

VIN = 20V

VIN = 8V

= 12V

SKIP = GND

SWITCHING FREQUENCY

vs. LOAD CURRENT

MAX1532toc08

LOAD CURRENT (A)

SWITCHING FREQUENCY (kHz)

3010 20

100

200

300

400

040

OUT

= 1V (NO LOAD)

SKIP MODE (SKIP = REF)

FORCED-PWM (SKIP = VCC)

NO-LOAD SUPPLY CURRENT

vs. INPUT VOLTAGE (FORCED-PWM MODE)

MAX1519 toc09

INPUT VOLTAGE (V)

SUPPLY CURRENT (mA)

20 255 1510

120

150

030

SKIP = V

ICC + I

OUTPUT VOLTAGE vs. LOAD CURRENT

1.52

1.50

1.48

1.46

1.44

OUTPUT VOLTAGE (V)

1.42

1.40

1.38 060

= 1.50V)

OUT

LOAD CURRENT (A)

MAX1519 toc01

EFFICIENCY (%)

40 503010 20

EFFICIENCY vs. LOAD CURRENT

= 1.50V)

100

0.1 1 10 100

OUT

VIN = 8V

VIN = 12V

VIN = 20V

SKIP = REF SKIP = V

LOAD CURRENT (A)

OUTPUT VOLTAGE vs. LOAD CURRENT

= 1.00V)

1.02

1.00

MAX1519 toc02

0.98

0.96

0.94

OUTPUT VOLTAGE (V)

0.92

0.90 060

OUT

5010 3020 40

LOAD CURRENT (A

MAX1519 toc03

Typical Operating Characteristics (continued)

(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN = SKIP = VCC, D0–D4 set for 1.5V (SUS = GND), S0–S1 set for 1V (SUS = V

), OFS = GND, TA= +25°C, unless otherwise specified.)

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

10 ______________________________________________________________________________________

NO-LOAD SUPPLY CURRENT

vs. INPUT VOLTAGE (PULSE SKIPPING)

3.0 SKIP = REF

2.5

2.0

1.5

1.0

SUPPLY CURRENT (mA)

0.5

030

CURRENT-BALANCE OFFSET

SAMPLE SIZE = 100

SAMPLE PERCENTAGE (%)

-2.50 2.50

OUTPUT OFFSET VOLTAGE

vs. OFS VOLTAGE

150

100

MAX1519 toc10

ICC + I

IIN

20 255 1510

INPUT VOLTAGE (V)

-50

OUTPUT OFFSET VOLTAGE (mV)

-100

-150

02.0 OFS VOLTAGE (V)

CURRENT-LIMIT THRESHOLD

VOLTAGE DISTRIBUTION

1.25-1.25

OFFSET VOLTAGE (mV)

MAX1519 toc13

SAMPLE PERCENTAGE (%)

9.0 11.0

ILIM

SAMPLE SIZE = 100

DISTRIBUTION

= 0.20V

10.0

CURRENT LIMIT (mV)

UNDEFINED REGION

1.50.5 1.0

10.59.5

SAMPLE SIZE = 100

MAX1519 toc11

SAMPLE PERCENTAGE (%)

1.990 2.010

MAX1519 toc14

GAIN (dB)

-10

-20

-30

-40

0.1 10 100 10001 10,000

REFERENCE VOLTAGE

DISTRIBUTION

2.000

REFERENCE VOLTAGE (V)

2.0051.995

VOLTAGE-POSITIONING AMPLIFIER

GAIN AND PHASE vs. FREQUENCY

GAIN

PHASE

FREQUENCY (kHz)

MAX1519 toc15

MAX1519 toc12

180

144

108

-36

-72

-108

-144

-180

PHASE (DEGREES)

VPS AMPLIFIER OFFSET VOLTAGE

vs. COMMON-MODE VOLTAGE

180

160

140

120

100

OFFSET VOLTAGE (µV)

1 205

COMMON-MODE VOLTAGE (V)

VPS AMPLIFIER

DISABLED

MAX1519 toc16

INDUCTOR CURRENT DIFFERENCE

vs. LOAD CURRENT

1.0

0.8

(A)

0.6

L(CM)

- I

0.4

L(CS)

0.2

SKIP = REF

SKIP = V

= 1mΩ

SENSE

050

30 40

LOAD CURRENT (A)

MAX1519 toc17

Typical Operating Characteristics (continued)

(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN = SKIP = VCC, D0–D4 set for 1.5V (SUS = GND), S0–S1 set for 1V (SUS = V

), OFS = GND, TA= +25°C, unless otherwise specified.)

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

______________________________________________________________________________________ 11

A. SHDN, 5V/div B. 1.5V OUTPUT, 1V/div C. VROK, 5V/div R

= 64.9k

TIME

1.5V

10A

A. SHDN, 5V/div B. 1.5V OUTPUT, 1V/div

, 10A/div

C. I

, 10A/div

D. I

= 75mΩ, R

LOAD

POWER-UP SEQUENCE

1ms/div

Ω

SOFT-SHUTDOWN

200µs/div

= 64.9k

TIME

MAX1519 toc18

MAX1519 toc20

Ω

SOFT-START

1.5V

10A

100µs/div

A. SHDN, 5V/div B. 1.5V OUTPUT, 1V/div C. I

, 10A/div

D. I R

LOAD

= 75mΩ, R

TIME

= 64.9k

Ω

1.50V LOAD TRANSIENT (10A TO 50A LOAD)

50A

10A

1.5V

20A

20µs/div

A. LOAD CURRENT, (I B. OUTPUT VOLTAGE (1.5V NO LOAD), 100mV/div

, 10A/div

C. I

, 10A/div

D. I

= 10A TO 50A), 50A/div

LOAD

MAX1519 toc19

MAX1519 toc21

Typical Operating Characteristics (continued)

(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN = SKIP = VCC, D0–D4 set for 1.5V (SUS = GND), S0–S1 set for 1V (SUS = V

), OFS = GND, TA= +25°C, unless otherwise specified.)

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

12 ______________________________________________________________________________________

30A

10A

1.00V LOAD TRANSIENT (10A TO 30A LOAD)

MAX1519 toc22

0.2V

OFFSET TRANSITION

MAX1519 toc23

1.0V

10A

20µs/div

A. LOAD CURRENT, (I B. OUTPUT VOLTAGE (1.00V NO LOAD), 50mV/div

, 10A/div

C. I

, 10A/div

D. I

= 10A TO 30A), 25A/div

LOAD

SUSPEND TRANSITION

(DUAL-PHASE PWM OPERATION)

3.3V 0V

1.5V

1.0V

2.5A

40µs/div

A. SUS, 5V/div B. V

= 1.5V TO 1.0V, 0.5V/div

OUT

, 10A/div

C. I

, 10A/div

D. I

5A LOAD, SKIP = V

, R

TIME

= 64.9k

MAX1519 toc24

Ω

1.5V

A. V

OFS

B. V

OUT

C. I

D. I

10A LOAD

20µs/div

= 0 TO 200mV, 0.2V/div

= 1.500V TO 1.475V, 20mV/div , 10A/div , 10A/div

SUSPEND TRANSITION

(SINGLE-PHASE SKIP OPERATION)

3.3V 0V

1.5V

1.0V

10A

A. SUS, 5V/div B. V

= 1.5V TO 1.0V, 0.5V/div

OUT

, 10A/div

C. I

, 10A/div

D. I

5A LOAD, C

OUT

100µs/div

= (4) 680µF, SKIP = SUS, R

MAX1519 toc25

TIME

= 64.9k

Ω

Typical Operating Characteristics (continued)

(Circuit of Figure 1, VIN= 12V, VCC= VDD= 5V, SHDN = SKIP = VCC, D0–D4 set for 1.5V (SUS = GND), S0–S1 set for 1V (SUS = V

), OFS = GND, TA= +25°C, unless otherwise specified.)

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

______________________________________________________________________________________ 13

1.5V

SINGLE-PHASE SKIP TO DUAL-PHASE

PWM TRANSITION

, 10A/div

TO GND, 5V/div

A. SKIP = V B. 1.5V OUTPUT, 50mV/div C. I D. I 2A LOAD

20µs/div

MAX1519 toc26

DUAL-PHASE SKIP TO DUAL-PHASE

PWM TRANSITION

5V 2V

1.5V

20µs/div

A. SKIP = V B. 1.5V OUTPUT, 50mV/div C. I D. I 2A LOAD

, 10A/div

TO REF, 5V/div

MAX1519 toc27

100mV DAC CODE TRANSITION

3.3V

1.5V

1.4V

A. D1, 5V/div B. V

= 1.50V TO 1.40V, 100mV/div

OUT

, 10A/div

C. I

, 10A/div

D. I

10A LOAD

20µs/div

MAX1519 toc28

400mV DAC CODE TRANSITION

3.3V

1.5V

1.1V

A. D3, 5V/div B. V

= 1.50V TO 1.10V, 0.5V/div

OUT

, 10A/div

C. I

, 10A/div

D. I

10A LOAD

40µs/div

MAX1519 toc29

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

14 ______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1TIME

2TON

3 SUS

4, 5 S0, S1

6 SHDN

Slew-Rate Adjustment Pin. Connect a resistor from TIME to GND to set the internal slew-rate clock. A 150kΩ to 15kΩ resistor sets the clock from 100kHz to 1MHz, f

On-Time Selection Control Input. This four-level input sets the K-factor value used to determine the DH_ on-time (see the On-Time One-Shot TON section): GND = 550kHz, REF = 300kHz, OPEN = 200kHz, V

Suspend Input. SUS is a three-level logic input. When the controller detects on-transition on SUS, the controller slews the output voltage to the new voltage level determined by SUS, S0–S1, and D0–D4. The controller blanks VROK during the transition and another 24 R DAC code is reached. Connect SUS as follows to select which multiplexer sets the nominal output voltage:

3.3V or V REF = suspend mode; S0–S1 high-range suspend code (Table 5), GND = normal operation; D0–D4 VID DAC code (Table 4).

Suspend-Mode Voltage Select Inputs. S0–S1 are four-level digital inputs that select the suspend mode VID code (Table 5) for the suspend mode multiplexer inputs. If SUS is high, the suspend mode VID code is delivered to the DAC (see the Internal Multiplexers section), overriding any other voltage setting (Figure 3).

S hutd ow n C ontr ol Inp ut. Thi s i np ut cannot w i thstand the b atter y vol tag e. C onnect to V op er ati on. C onnect to g r ound to p ut the IC i nto i ts 1µA ( typ ) shutd ow n state. D ur i ng the tr ansi ti on fr om nor m al op er ati on to shutd ow n, the outp ut vol tag e r am p s d ow n at 4 ti m es the outp ut- vol tag e sl ew r ate p r og r am m ed b y the TIM E p i n. In shutd ow n m od e, D LM and D LS ar e for ced to V g r ound . For ci ng SH DN to 12V ~ 15V d i sab l es b oth over vol tag e p r otecti on and und er vol tag e p r otecti on ci r cui ts, d i sab l es over l ap op er ati on, and cl ear s the faul t l atch. D o not connect SH DN to > 15V .

= 100kHz.

(high) = suspend mode; S0–S1 low-range suspend code (Table 5),

= 500kHz × 30kΩ/R

SLEW

clock cycles after the new

TIME

for nor m al

C C

to cl am p the outp ut to

D D

Voltage-Divider Input for Offset Control. For 0 < V

7 OFS

8 REF

9 ILIM

10 V

11 GND Analog Ground. Connect the MAX1519/MAX1545’s exposed pad to analog ground.

12 CCV

subtracted from the output. For 1.2V < V is added to the output. Voltages in the range of 0.8V < V disables the offset amplifier during suspend mode (SUS = REF or high).

2V Reference Output. Bypass to GND with a 0.22µF or greater ceramic capacitor. The reference can source 100µA for external loads. Loading REF degrades output voltage accuracy according to the REF load regulation error.

Current-Limit Adjustment. The current-limit threshold defaults to 30mV if ILIM is tied to V adjustable mode, the current-limit threshold voltage is precisely 1/20 the voltage seen at ILIM over a

0.2V to 1.5V range. The logic threshold for switchover to the 30mV default value is approximately V

- 1V.

Analog Supply Voltage Input for PWM Core. Connect VCC to the system supply voltage (4.5V to 5.5V) with a series 10Ω resistor. Bypass to GND with a 1µF or greater ceramic capacitor, as close to the IC as possible.

Voltage Integrator Capacitor Connection. Connect a 47pF to 1000pF (47pF, typ) capacitor from CCV to analog ground (GND) to set the integration time constant.

< 2V, 0.125 times the difference between REF and OFS

OFS

< 0.8V, 0.125 times the voltage at OFS is

OFS

< 1.2V are undefined. The controller

OFS

. In

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

______________________________________________________________________________________ 15

Pin Description (continued)

PIN NAME FUNCTION

Ground Remote-Sense Input. Connect GNDS directly to the CPU ground-sense pin. GNDS internally

13 GNDS

14 CCI

15 FB

16 OAIN-

17 OAIN+

18 SKIP

19 CODE

connects to an amplifier that adjusts the output voltage, compensating for voltage drops from the regulator ground to the load ground.

Current-Balance Compensation. Connect a 470pF capacitor between CCI and FB (see the Current- Balance Compensation (CCI) section).

Feedback Input. FB is internally connected to both the feedback input and the output of the voltagepositioning op amp. See the Setting Voltage Positioning section to set the voltage-positioning gain.

Op Amp Inverting Input and Op Amp Disable Input. When using the internal op amp for additional voltage-positioning gain, connect to the negative terminal of the current-sense resistor through a resistor as described in the Setting Voltage Positioning section. Connect OAIN- to V op amp. The logic threshold to disable the op amp is approximately V

Op Amp Noninverting Input. When using the internal op amp for additional voltage-positioning gain, connect to the positive terminal of the current-sense resistor through a resistor as described in the Setting Voltage Positioning section.

Pulse-Skipping Select Input. When pulse skipping, the controller blanks the VROK upper threshold:

3.3V or V REF = Dual-phase pulse-skipping operation, GND = Single-phase pulse-skipping operation.

VID DAC Code Selection Output. Connect CODE to GND to select the desktop P4 code set, or connect CODE to V

(high) = Dual-phase forced-PWM operation,

to select the mobile P4 code set (Table 4).

- 1V.

to disable the

Low-Voltage VID DAC Code Inputs. The D0–D4 inputs do not have internal pullups. These 1.0V logic inputs are designed to interface directly with the CPU. In normal mode (Table 4, SUS = GND), the

20–24 D4–D0

25 VROK

26 BSTM

27 LXM Main Inductor Connection. LXM is the internal lower supply rail for the DHM high-side gate driver.

28 DHM Main High-Side Gate-Driver Output. Swings LXM to BSTM.

29 DLM

30 V

output voltage is set by the VID code indicated by the logic-level voltages on D0–D4. In suspend mode (Table 5, SUS = REF or high), the decoded state of the four-level S0–S1 inputs sets the output voltage.

Open-Drain Power-Good Output. After output voltage transitions, except during power-up and powerdown, if OUT is in regulation, then VROK is high impedance. The controller blanks VROK whenever the slew-rate control is active (output voltage transitions). VROK is forced low in shutdown. A pullup resistor on VROK causes additional finite shutdown current. During power-up, VROK includes a 3ms (min) delay after the output reaches the regulation voltage.

Main Boost Flying Capacitor Connection. An optional resistor in series with BSTM allows the DHM pullup current to be adjusted.

Main Low-Side Gate-Driver Output. DLM swings from PGND to V MAX1519/MAX1545 power down.

Supply Voltage Input for the DLM and DLS Gate Drivers. Connect to the system supply voltage (4.5V to 5.5V). Bypass V possible.

to PGND with a 2.2µF or greater ceramic capacitor as close to the IC as

. DLM is forced high after the

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

16 ______________________________________________________________________________________

Detailed Description

Dual 180° Out-of-Phase Operation

The two phases in the MAX1519/MAX1545 operate 180° out-of-phase (SKIP = REF or high) to minimize input and output filtering requirements, reduce electromagnetic interference (EMI), and improve efficiency. This effectively lowers component count—reducing cost, board space, and component power requirements—making the MAX1519/MAX1545 ideal for highpower, cost-sensitive applications.

Typically, switching regulators provide transfer power using only one phase instead of dividing the power among several phases. In these applications, the input capacitors must support high instantaneous current requirements. The high-RMS ripple current can lower efficiency due to I2R power loss associated with the input capacitor’s effective series resistance (ESR). Therefore, the system typically requires several low-ESR input capacitors in parallel to minimize input voltage ripple, reduce ESR-related power losses, and to meet the necessary RMS ripple current rating.

With the MAX1519/MAX1545, the controller shares the current between two phases that operate 180° out-of- phase, so the high-side MOSFETs never turn on simultaneously during normal operation. The instantaneous input current of either phase is effectively cut in half, resulting in reduced input voltage ripple, ESR power

loss, and RMS ripple current (see the Input Capacitor Selection section). As a result, the same performance can be achieved with fewer or less expensive input capacitors.

Transient Overlap Operation

When a transient occurs, the response time of the controller depends on how quickly it can slew the inductor current. Multiphase controllers that remain 180° out-of- phase when a transient occurs actually respond slower than an equivalent single-phase controller. In order to provide fast transient response, the MAX1519/ MAX1545 support a phase-overlap mode, which allows the dual regulators to operate in-phase when heavy load transients are detected, reducing the response time. After either high-side MOSFET turns off and if the output voltage does not exceed the regulation voltage when the minimum off-time expires, the controller simultaneously turns on both high-side MOSFETs during the next on-time cycle. This maximizes the total inductorcurrent slew rate. The phases remain overlapped until the output voltage exceeds the regulation voltage and after the minimum off-time expires.

After the phase-overlap mode ends, the controller automatically begins with the opposite phase. For example, if the secondary phase provided the last on-time pulse before overlap operation began, the controller starts switching with the main phase when overlap operation ends.

Pin Description (continued)

PIN NAME FUNCTION

31 PGND Power Ground. Ground connection for low-side gate drivers DLM and DLS.

32 DLS

33 DHS Secondary High-Side Gate-Driver Output. Swings LXS to BSTS.

34 LXS

35 BSTS

36 V+

37 CMP Main Inductor Positive Current-Sense Input

38 CMN Main Inductor Negative Current-Sense Input

39 CSN Secondary Inductor Positive Current-Sense Input

40 CSP Secondary Inductor Negative Current-Sense Input

Secondary Low-Side Gate-Driver Output. DLS swings from PGND to V MAX1519/MAX1545 power down.

Secondary Inductor Connection. LXS is the internal lower supply rail for the DHS high-side gate driver.

Secondary Boost Flying Capacitor Connection. An optional resistor in series with BSTS allows the DHS pullup current to be adjusted.

Battery Voltage-Sense Connection. Used only for PWM one-shot timing. DH_ on-time is inversely proportional to input voltage over a range of 4V to 28V.

. DLS is forced high after the

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

______________________________________________________________________________________ 17

Power-Up Sequence

The MAX1519/MAX1545 are enabled when SHDN is driven high (Figure 2). The reference powers up first. Once the reference exceeds its undervoltage lockout threshold, the PWM controller evaluates the DAC target and starts switching.

For the MAX1519/MAX1545, the slew-rate controller ramps up the output voltage in 25mV increments to the proper operating voltage (see Tables 3 and 4) set by either D0–D4 (SUS = GND) or S0–S1 (SUS = REF or high). The ramp rate is set with the R

TIME

resistor (see

the Output Voltage Transition Timing section). The con-

troller pulls VROK low until at least 3ms after the MAX1519/MAX1545 reach the target DAC code.

Shutdown

When SHDN goes low, the MAX1519/MAX1545 enter low-power shutdown mode. VROK is pulled low immediately, and the output voltage ramps down to 0V in 25mV increments at 4 times the clock rate set by R

TIME

SHDN

SLEW

DAC

LSB

≤

 



 



Table 1. Component Selection for Standard Multiphase Applications*

*Contact Intel for the Mobile P4 specifications and contact Maxim for a reference schematic.

DESIGNATION

Input Voltage Range 7V to 24V 7V to 24V

VID Output Voltage (D4–D0)

Suspend Voltage (SUS, S0–S1)

Maximum Load Current 60A 60A

Number of Phases (η

Inductor (per phase)

Switching Frequency 300kHz (TON = REF) 300kHz (TON = REF)

High-Side MOSFET (N

, per phase)

Low-Side MOSFET (N

, per phase)

Total Input Capacitance (CIN)

TOTAL

)

MAX1519/MAX1545

2-PHASE DESKTOP P4

Circuit of Figure 1 Circuit of Figure 12

1.5V

(CODE = GND, D4–D0 = 01110)

Not Used

(SUS = GND)

Two phases

(1) MAX1519/MAX1545

0.6µH

Panasonic ETQP1H0R6BFA

Siliconix (1) Si7886DP

International Rectifier (2) IRF6604

Siliconix (2) Si7442DP or

International Rectifier (2) IRF6603

(6) 10µF, 25V

Taiyo Yuden TMK432BJ106KM or

TDK C4532X5R1E106M

(1) MAX1519/MAX1545 + (2) MAX1980

0.7µH Panasonic ETQP2H0R7BFA or

International Rectifier (1) IRF7811W or

MAX1519/MAX1545

4- PHASE DESKTOP P4

(CODE = GND, D4–D0 = 01110)

(SUS = GND)

0.8µH Sumida CDEP105L-0R8

Fairchild (1) FDS6694

Fairchild (2) FDS6688 or

Siliconix (1) Si7442DP

(6) 10µF, 25V

Taiyo Yuden TMK432BJ106KM or

TDK C4532X5R1E106M

1.5V

Not Used

Four phases

Total Output Capacitance

)

OUT

Current-Sense Resistor

SENSE

, per phase)

(4) 680µF, 2.5V

Sanyo 2R5TPD680M

1.0mΩ

Panasonic ERJM1WTJ1M0U

(4) 680µF, 2.5V

Sanyo 2R5TPD680M

1.5mΩ

Panasonic ERJM1WTJ1M5U

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

18 ______________________________________________________________________________________

Figure 1. Standard Two-Phase Desktop P4 Application Circuit

5V BIAS SUPPLY

BST1

0.22µF

1.5kΩ ±1%

CCI

470pF

BST2

0.22µF

BST DIODES

2.2µF

INPUT*

1kΩ

±1%

1kΩ

±1%

7V TO 24V

SENSE1

1.0mΩ

R10

10Ω

R11

100kΩ

POWER-

GOOD

DAC INPUTS

SUSPEND INPUTS

(FOUR-LEVEL LOGIC)

STP_CPU#

PWM

SKIP

OFF

0.22µF

49.9kΩ

REF

100pF

REF

±1%

1µF

64.9kΩ

REF (300kHz)

100kΩ

±1%

TIME

C 47pF

R28 182kΩ ±1%

R27 20kΩ ±1%

VROK

D0 D1 D2 D3 D4

CODEGND (DESKTOP P4) S0 S1

SHDN

TIME

CCV

TON

REF

ILIM

OFS

SKIP

SUS

MAX1519 MAX1545

BSTM

DHM

LXM

DLM

PGND

GND

CMN CMP

OAIN+ OAIN-

CCI

CSP CSN

BSTS

DHS

LXS

DLS

GNDS

V+

R3 1kΩ ±1%

R5 1kΩ ±1%

SENSE2

1.5kΩ ±1%

OUT

OUTPUT

OUT

POWER GROUND

ANALOG GROUND

*LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE.

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

______________________________________________________________________________________ 19

where f

SLEW

= 500kHz ✕ 30kΩ/R

TIME

, V

DAC

is the DAC setting when the controller begins the shutdown sequence, and V

LSB

= 25mV is the DAC’s smallest voltage increment. Slowly discharging the output capacitors by slewing the output over a long period of time (4/f

SLEW

) keeps the average negative inductor current low (damped response), thereby eliminating the negative output voltage excursion that occurs when the controller discharges the output quickly by permanently turning on the low-side MOSFET (underdamped response).

This eliminates the need for the Schottky diode normally connected between the output and ground to clamp the negative output voltage excursion. When the DAC reaches the 0V setting, DL_ goes high, DH_ goes low, the reference turns off, and the supply current drops to about 1µA. When a fault condition—output undervoltage lockout, output overvoltage lockout (MAX1545), or thermal shutdown—activates the shutdown sequence, the controller sets the fault latch to prevent the controller from restarting. To clear the fault latch and reactivate the controller, toggle SHDN or cycle VCCpower below 1V.

Table 2. Component Suppliers

Figure 2. Power-Up and Shutdown Sequence Timing Diagram

SHDN

VID (D0–D4)

SOFT-START

1LSB PER R

CORE

VROK

MANUFACTURER PHONE WEBSITE

BI Technologies

Central Semiconductor

Coilcraft

Coiltronics

Fairchild Semiconductor

International Rectifier

Kemet

Panasonic

Sanyo

Siliconix (Vishay)

Sumida

Taiyo Yuden

CYCLE

TIME

VROK(START)

3ms, TYP

714-447-2345 (USA) www.bitechnologies.com

631-435-1110 (USA) www.centralsemi.com

800-322-2645 (USA) www.coilcraft.com

561-752-5000 (USA) www.coiltronics.com

888-522-5372 (USA) www.fairchildsemi.com

310-322-3331 (USA) www.irf.com

408-986-0424 (USA) www.kemet.com

847-468-5624 (USA) www.panasonic.com

65-6281-3226 (Singapore) www.secc.co.jp

203-268-6261 (USA) www.vishay.com

408-982-9660 (USA) www.sumida.com

03-3667-3408 (Japan)

408-573-4150 (USA)

www.t-yuden.com

DO NOT CARE

SOFT-SHUTDOWN 1LSB PER 4 R

TIME

CYCLES

TDK

TOKO

847-803-6100 (USA)

81-3-5201-7241 (Japan)

858-675-8013 (USA) www.tokoam.com

www.component.tdk.com

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

20 ______________________________________________________________________________________

When SHDN goes high, the reference powers up. Once the reference voltage exceeds its UVLO threshold, the controller evaluates the DAC target and starts switching. The slew-rate controller ramps up from 0V in 25mV increments to the currently selected output-voltage setting (see the Power-Up Sequence section). There is no traditional soft-start (variable current-limit) circuitry, so full output current is available immediately.

Internal Multiplexers

The MAX1519/MAX1545 have a unique internal DAC input multiplexer (muxes) that selects one of three different DAC code settings for different processor states (Figure 3). On startup, the MAX1519/MAX1545 select the DAC code from the D0–D4 (SUS = GND) or S0–S1 (SUS = REF or high) input decoders.

DAC Inputs (CODE, D0–D4)

During normal forced-PWM operation (SUS = GND), the DAC programs the output voltage using code and the D0–D4 inputs. Connect CODE to VCCor GND for the mobile or desktop P4 setting, respectively. Do not leave D0–D4 unconnected. D0–D4 can be changed while the MAX1519/MAX1545 are active, initiating a transition to

a new output voltage level. Change D0–D4 together, avoiding greater than 1µs skew between bits. Otherwise, incorrect DAC readings can cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall transition time. The available DAC codes and resulting output voltages are compatible with desktop and mobile P4 (Table 4) specifications.

Four-Level Logic Inputs

TON and S0–S1 are four-level logic inputs. These inputs help expand the functionality of the controller without adding an excessive number of pins. The fourlevel inputs are intended to be static inputs. When left open, an internal resistive voltage-divider sets the input voltage to approximately 3.5V. Therefore, connect the four-level logic inputs directly to VCC, REF, or GND when selecting one of the other logic levels. See Electrical Characteristics for exact logic level voltages.

Suspend Mode

When the processor enters low-power suspend mode, it sets the regulator to a lower output voltage to reduce power consumption. The MAX1519/MAX1545 include

Table 3. Operating Mode Truth Table

SHDN SUS SKIP OFS

GND x x x GND

GND V

GND x

REF

high

x x x GND

REF

GND

GND or REF

0 to 0.8V

1.2V to 2V

OUTPUT

VOLTAGE

D0–D4

(no offset)

D0–D4

(no offset)

D0–D4

(plus offset)

SUS, S0–S1

(no offset)

OPERATING MODE

Low-Power Shutdown Mode. DL_ is forced high, DH_ is forced low, and the PWM controller is disabled. The supply current drops to 1µA (typ).

N or m al Op er ati on. The no- l oad outp ut vol tag e i s d eter m i ned b y the sel ected V ID D AC cod e ( C OD E and D 0–D 4, Tab l e 4) .

Pulse-Skipping Operation. When SKIP is pulled low, the MAX1519/MAX1545 immediately enter pulse-skipping operation, allowing automatic PWM/PFM switchover under light loads. The VROK upper threshold is blanked.

Deep-Sleep Mode. The no-load output voltage is determined by the selected VID DAC cod e ( C OD E and D 0–D 4, Table 4), plus the offset voltage set by OFS.

Suspend Mode. The no-load output voltage is determined by the selected suspend code (SUS, S0–S1, Table 5), overriding all other active modes of operation.

Fault Mode. The fault latch has been set by either UVP, OVP (MAX1545 only), or thermal shutdown. The controller remains in FAULT mode until V toggled.

power is cycled or SHDN

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

______________________________________________________________________________________ 21

independent suspend-mode output voltage codes set by the four-level S0–S1 inputs and the three-level SUS input. When the CPU suspends operation (SUS = REF or high), the controller disables the offset amplifier and overrides the 5-bit VID DAC code set by D0–D4 (normal operation). The master controller slews the output to the selected suspend-mode voltage. During the transition, the MAX1519/MAX1545 blank VROK and the UVP fault protection until 24 R

TIME

clock cycles after the slew-rate con-

troller reaches the suspend-mode voltage.

SUS is a three-level logic input: GND, REF, or high. This expands the functionality of the controller without adding an additional pin. This input is intended to be driven by a dedicated open-drain output with the pullup resistor connected either to REF (or a resistive-divider from VCC) or to a logic-level bias supply (3.3V or greater). When pulled up to REF, the MAX1519/ MAX1545 select the upper suspend voltage range. When pulled high (2.7V or greater), the controller selects the lower suspend voltage range. See Electrical Characteristics for exact logic level voltages.

Output Voltage Transition Timing

The MAX1519/MAX1545 are designed to perform mode transitions in a controlled manner, automatically minimiz-

ing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output voltage level with the lowest possible peak currents for a given output capacitance.

At the beginning of an output voltage transition, the MAX1519/MAX1545 blank the VROK output, preventing them from changing states. VROK remains blanked during the transition and is enabled 24 clock cycles after the slew-rate controller has set the final DAC code value. The slew-rate clock frequency (set by resistor R

TIME

) must be set fast enough to ensure that the transition is completed within the maximum allotted time.

The slew-rate controller transitions the output voltage in 25mV steps during soft-start, soft-shutdown, and suspend-mode transitions. The total time for a transition depends on R

TIME

, the voltage difference, and the accuracy of the MAX1519/MAX1545s’ slew-rate clock, and is not dependent on the total output capacitance. The greater the output capacitance, the higher the surge current required for the transition. The MAX1519/MAX1545 automatically control the current to the minimum level required to complete the transition in the calculated time, as long as the surge current is less

Figure 3. Internal Multiplexers Functional Diagram

SEL

D0–D4

DECODER

S0–S1

DECODER

SUS 3-LEVEL DECODER

OUT

SUSPEND

MUX

SEL

OUT

DAC

D0 D1 D2 D3 D4

CODE

S0 S1

SUS

2.5V

1.0V

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

22 ______________________________________________________________________________________

than the current limit set by ILIM. The transition time is given by:

where f

SLEW

= 500kHz ✕ 30kΩ / R

TIME

, V

OLD

is the

original DAC setting, V

NEW

is the new DAC setting, and

LSB

is the DAC’s smallest voltage increment. The additional two clock cycles on the falling edge time are due to internal synchronization delays. See TIME Frequency Accuracy in the Electrical Characteristics for f

SLEW

limits.

The practical range of R

TIME

is 15kΩ to 150kΩ corre-

sponding to 1.0µs to 10µs per 25mV step. Although the DAC takes discrete steps, the output filter makes the transitions relatively smooth. The average inductor current required to make an output voltage transition is:

Fault Protection

Output Overvoltage Protection

(MAX1545 Only)

The overvoltage protection (OVP) circuit is designed to protect the CPU against a shorted high-side MOSFET by drawing high current and blowing the battery fuse. The MAX1519/MAX1545 continuously monitor the output for

an overvoltage fault. During normal forced-PWM operation (SKIP = high), the controller detects an OVP fault if the output voltage exceeds the set DAC voltage by more than 13% (min). During pulse-skipping operation (SKIP = REF or GND), the controller detects an OVP fault if the output voltage exceeds the fixed 2V (typ) threshold. When the OVP circuit detects an overvoltage fault, it immediately sets the fault latch, pulls VROK low, and activates the shutdown sequence.

This action discharges the output filter capacitor and forces the output to ground. If the condition that caused the overvoltage (such as a shorted high-side MOSFET) persists, the battery fuse blows. The controller remains shut down until the fault latch is cleared by toggling SHDN or cycling the VCCpower supply below 1V.

Overvoltage protection can be disabled through the “nofault” test mode (see the No-Fault Test Mode section).

Output Undervoltage Shutdown

The output UVP function is similar to foldback current limiting, but employs a timer rather than a variable current limit. If the MAX1519/MAX1545 output voltage is under 70% of the nominal value, the controller activates the shutdown sequence and sets the fault latch.

Once the controller ramps down to the 0V DAC code setting, it forces the DL_ low-side gate-driver high, and pulls the DH_ high-side gate-driver low. Toggle SHDN or cycle the VCCpower supply below 1V to clear the fault latch and reactivate the controller. UVP is ignored during output voltage transitions and remains blanked

IC V f

L OUT LSB SLEW

≅××

for V ri g

for V falling

SLEW

OLD NEW

LSB

OUT

SLEW

OLD NEW

LSB

OUT

≈

 



 



≈

 



 







 





 

−

sin

Figure 4. Suspend Transition

SUS

DAC

OUTPUT SET BY SUS AND S0–S1

SLEW

TIME

CLOCK

VROK

VROK BLANKING

BLANK

= 24 CLKS

1 LSB PER R

CYCLE

TIME

OUTPUT SET BY D0–D4

SLEW

VROK BLANKING

BLANK

= 24 CLKSt

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

______________________________________________________________________________________ 23

for an additional 24 clock cycles after the controller reaches the final DAC code value.

UVP can be disabled through the “no-fault” test mode (see the No-Fault Test Mode section).

Thermal-Fault Protection

The MAX1519/MAX1545 feature a thermal fault-protection circuit. When the junction temperature rises above +160°C, a thermal sensor activates the fault latch and activates the soft-shutdown sequence. Once the con-

Table 4. Output Voltage VID DAC Codes (SUS = GND)

D4 D3 D2 D1 D0

0 0 0 0 0 1.750

0 0 0 0 1 1.700

0 0 0 1 0 1.650

0 0 0 1 1 1.600

0 0 1 0 0 1.550

0 0 1 0 1 1.500

0 0 1 1 0 1.450

0 0 1 1 1 1.400

0 1 0 0 0 1.350

0 1 0 0 1 1.300

0 1 0 1 0 1.250

0 1 0 1 1 1.200

0 1 1 0 0 1.150

0 1 1 0 1 1.100

0 1 1 1 0 1.050

0 1 1 1 1 1.000

1 0 0 0 0 0.975

1 0 0 0 1 0.950

1 0 0 1 0 0.925

1 0 0 1 1 0.900

1 0 1 0 0 0.875

1 0 1 0 1 0.850

1 0 1 1 0 0.825

1 0 1 1 1 0.800

1 1 0 0 0 0.775

1 1 0 0 1 0.750

1 1 0 1 0 0.725

1 1 0 1 1 0.700

1 1 1 0 0 0.675

1 1 1 0 1 0.650

1 1 1 1 0 0.625

1 1 1 1 1 0.600

CODE = V

OUTPUT

VOLTAGE

(V)

D4 D3 D2 D1 D0

0 0 0 0 0 1.850

0 0 0 0 1 1.825

0 0 0 1 0 1.800

0 0 0 1 1 1.775

0 0 1 0 0 1.750

0 0 1 0 1 1.725

0 0 1 1 0 1.700

0 0 1 1 1 1.675

0 1 0 0 0 1.650

0 1 0 0 1 1.625

0 1 0 1 0 1.600

0 1 0 1 1 1.575

0 1 1 0 0 1.550

0 1 1 0 1 1.525

0 1 1 1 0 1.500

0 1 1 1 1 1.475

1 0 0 0 0 1.450

1 0 0 0 1 1.425

1 0 0 1 0 1.400

1 0 0 1 1 1.375

1 0 1 0 0 1.350

1 0 1 0 1 1.325

1 0 1 1 0 1.300

1 0 1 1 1 1.275

1 1 0 0 0 1.250

1 1 0 0 1 1.225

1 1 0 1 0 1.200

1 1 0 1 1 1.175

1 1 1 0 0 1.150

1 1 1 0 1 1.125

1 1 1 1 0 1.100

1 1 1 1 1 Shutdown

CODE = GND

OUTPUT

VOLTAGE

(V)

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

24 ______________________________________________________________________________________

Table 5. Suspend Mode DAC Codes

*Connect the three-level SUS input to a 2.7V or greater supply (3.3V or VCC) for an input logic level high.

troller ramps down to the 0V DAC code setting, it forces the DL_ low-side gate-driver high, and pulls the DH_ high-side gate-driver low. Toggle SHDN or cycle the VCCpower supply below 1V to clear the fault latch and reactivate the controller after the junction temperature cools by 15°C.

Thermal shutdown can be disabled through the “no-fault” test mode (see the No-Fault Test Mode section).

No-Fault Test Mode

The latched-fault protection features and overlap mode can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a “nofault” test mode is provided to disable the fault protection (overvoltage protection, undervoltage protection, and thermal shutdown) and overlap mode. Additionally, the test mode clears the fault latch if it has been set. The nofault test mode is entered by forcing 12V to 15V on SHDN.

Multiphase Quick-PWM

5V Bias Supply (VCCand VDD)

The Quick-PWM controller requires an external 5V bias supply in addition to the battery. Typically, this 5V bias

supply is the notebook’s 95%-efficient 5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the 5V bias supply can be generated with an external linear regulator.

The 5V bias supply must provide V

(PWM controller) and VDD(gate-drive power), so the maximum current drawn is:

BIAS

= ICC+ fSW(Q

G(LOW)

+ Q

G(HIGH)

)

where ICCis provided in the Electrical Characteristics, fSWis the switching frequency, and Q

G(LOW)

and Q

G(HIGH)

are the MOSFET data sheet’s total gate-charge specification limits at VGS= 5V. V+ and VDDcan be tied together if the input power source is a fixed 4.5V to 5.5V supply. If the 5V bias supply is powered up prior to the battery supply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup.

Free-Running, Constant On-Time PWM

Controller with Input Feed Forward

The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time, current-mode regulator

SUS* S1 S0

High GND GND 0.675

High GND REF 0.700

High GND OPEN 0.725

High GND V

High REF GND 0.775

High REF REF 0.800

High REF OPEN 0.825

High REF V

High OPEN GND 0.875

High OPEN REF 0.900

High OPEN OPEN 0.925

High OPEN V

High V

LOWER SUSPEND CODES

OUTPUT

VOLTAGE

(V)

0.750

0.850

0.950

1.050

GND 0.975

REF 1.000

OPEN 1.025

UPPER SUSPEND CODES

SUS* S1 S0

REF GND GND 1.075

REF GND REF 1.100

REF GND OPEN 1.125

REF GND V

REF REF GND 1.175

REF REF REF 1.200

REF REF OPEN 1.225

REF REF V

REF OPEN GND 1.275

REF OPEN REF 1.300

REF OPEN OPEN 1.325

REF OPEN V

REF V

OUTPUT

VOLTAGE

(V)

GND 1.375

REF 1.400

OPEN 1.425

1.150

1.250

1.350

1.450

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

______________________________________________________________________________________ 25

with input voltage feed forward (Figure 5). This architecture relies on the output filter capacitor’s ESR to act as the current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to the input voltage, and directly proportional to the output voltage or the difference between the main and secondary inductor currents (see the On-Time One-Shot (TON) section). Another one-shot sets a minimum off-time. The on-time one-shot triggers when the error comparator goes low, the inductor current of the selected phase is below the valley currentlimit threshold, and the minimum off-time one-shot times out. The controller maintains 180° out-of-phase operation by alternately triggering the main and secondary phases after the error comparator drops below the output voltage set point.

On-Time One-Shot (TON)

The core of each phase contains a fast, low-jitter, adjustable one-shot that sets the high-side MOSFETs on-time. The one-shot for the main phase varies the ontime in response to the input and feedback voltages. The main high-side switch on-time is inversely proportional to the input voltage as measured by the V+ input, and proportional to the feedback voltage (VFB):

where K is set by the TON pin-strap connection (Table 6) and 0.075V is an approximation to accommodate the expected drop across the low-side MOSFET switch.

The one-shot for the secondary phase varies the on-time in response to the input voltage and the difference between the main and secondary inductor currents. Two identical transconductance amplifiers integrate the difference between the master and slave current-sense signals. The summed output is internally connected to CCI, allowing adjustment of the integration time constant with a compensation network connected between CCI and FB.

The resulting compensation current and voltage are determined by the following equations:

where Z

CCI

is the impedance at the CCI output. The secondary on-time one-shot uses this integrated signal (V

CCI

) to set the secondary high-side MOSFETs on-time. When the main and secondary current-sense signals (VCM= V

CMP

- V

CMN

and VCS= V

CSP

- V

CSM

) become unbalanced, the transconductance amplifiers adjust the secondary on-time, which increases or decreases the secondary inductor current until the current-sense signals are properly balanced:

This algorithm results in a nearly constant switching frequency and balanced inductor currents, despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. The on-time one-shots have good accuracy at the operating points specified in the Electrical Characteristics. On-times at operating points far removed from the conditions specified in the Electrical Characteristics can vary over a wider range. For example, the 300kHz setting typically runs about 3% slower with inputs much greater than 12V due to the very short on-times required.

Main On Time

Secondary Current Balance Correction

ON ND

CCI

CCI CCI

()

( )

0 075

 



 



 



 



 



 



−

IGVVGVV

VVIZ

CCI M CMP CMN M CSP CSN

CCI FB CCI CCI

()()

- - -

ON MAIN

KV V

()

0 075

Table 6. Approximate K-Factor Errors

TON

CONNECTION

Float 200 5 ±10

REF 300 3.3 ±10

GND 550 1.8 ±12.5

FREQUENCY

SETTING

(kHz)

100 10 ±10

K-FACTOR

(µs)

MAX

K-FACTOR

ERROR

(%)

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

26 ______________________________________________________________________________________

Figure 5. Dual-Phase Quick-PWM Functional Diagram

CSN

SECONDARY PHASE

CSP

ILIM

DRIVERS

BSTS

DHS

LXS

DLS

19R

CMP

CMN

REF

SHDN

GND

CCV

1.0V

REF

(2.0V)

REF

T = 1T

CMP

CMN

CSN

CSP

CCI

TON

BSTM

DHM

LXM

DLM

PGND

V+

TRIG

ON-TIME

ONE-SHOT

MINIMUM

OFF-TIME

TRIG

ONE-SHOT

ON-TIME

ONE-SHOT

SKIP

TRIGQ

FAULT

MAIN PHASE

DRIVERS

CMP

CMN

1.5mV

T = 0

MAX1519 MAX1545

INTERNAL MULTIPLEXERS, MODE

CONTROL, AND SLEW-RATE CONTROL

SUS CODE

SKIP

OFS

OAIN+

OAIN-

GNDS

R-2R

DAC

S[0:1] D[0:4]

TIME

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

______________________________________________________________________________________ 27

On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics are influenced by switching delays in the external highside MOSFET. Resistive losses, including the inductor, both MOSFETs, output capacitor ESR, and PC board copper losses in the output and ground tend to raise the switching frequency at higher output currents. Also, the dead-time effect increases the effective on-time, reducing the switching frequency. It occurs only during forcedPWM operation and dynamic output voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor’s EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the DH-rising dead time.

For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency (per phase) is:

where V

DROP1

is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; V

DROP2

is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and PC board resistances; and tONis the on-time as determined above.

Current Balance

Without active current-balance circuitry, the current matching between phases depends on the MOSFET’s on-resistance (R

DS(ON)

), thermal ballasting, on-/off-time matching, and inductance matching. For example, variation in the low-side MOSFET on-resistance (ignoring thermal effects) results in a current mismatch that is proportional to the on-resistance difference:

However, mismatches between on-times, off-times, and inductor values increase the worst-case current imbalance, making it impossible to passively guarantee accurate current balancing.

The multiphase Quick-PWM controller integrates the difference between the current-sense voltages and adjusts the on-time of the secondary phase to maintain current balance. The current balance now relies on the accuracy of the current-sense resistors instead of the inaccurate, thermally sensitive on-resistance of the lowside MOSFETs.

With active current balancing, the current mismatch is determined by the current-sense resistor values and the offset voltage of the transconductance amplifiers:

where V

OS(IBAL)

is the current-balance offset specifica-

tion in the Electrical Characteristics.

The worst-case current mismatch occurs immediately after a load transient due to inductor value mismatches resulting in different di/dt for the two phases. The time it takes the current-balance loop to correct the transient imbalance depends on the mismatch between the inductor values and switching frequency.

Feedback Adjustment Amplifiers

Voltage-Positioning Amplifier

The multiphase Quick-PWM controllers include an independent operational amplifier for adding gain to the voltage-positioning sense path. The voltage-positioning gain allows the use of low-value current-sense resistors in order to minimize power dissipation. This 3MHz gainbandwidth amplifier was designed with low offset voltage (70µV, typ) to meet the IMVP output accuracy requirements.

The inverting (OAIN-) and noninverting (OAIN+) inputs are used to differentially sense the voltage across the voltage-positioning sense resistor. The op amp’s output is internally connected to the regulator’s feedback input (FB). The op amp should be configured as a noninverting, differential amplifier, as shown in Figure 10. The voltage-positioning slope is set by properly selecting the feedback resistor connected from FB to OAIN- (see the Setting Voltage Positioning section). For applications using a slave controller, additional differential input resistors (summing configuration) can be connected to the slave’s voltage-positioning sense resistor. Summing together both the master and slave current-sense signals ensures that the voltage-positioning slope remains constant when the slave controller is disabled.

The controller also uses the amplifier for remote output sensing (FBS) by summing the remote-sense voltage into the positive terminal of the voltage-positioning amplifier (Figure 10).

In applications that do not require voltage-positioning gain, the amplifier can be disabled by connecting the OAIN- pin directly to V

. The disabled amplifier’s output becomes high impedance, guaranteeing that the unused amplifier does not corrupt the FB input signal. The logic threshold to disable the op amp is approximately VCC- 1V.

III

OS IBAL LM LS

OS IBAL

SENSE

()

== -

III

MAIN ND MAIN

MAIN

- - 21=

 

 

 

 

tVV V

OUT DROP

ON IN DROP DROP

()

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

28 ______________________________________________________________________________________

Integrator Amplifier

A feedback amplifier forces the DC average of the feedback voltage to equal the VID DAC setting. This transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure 5), allowing accurate DC output voltage regulation regardless of the output ripple voltage. The feedback amplifier has the ability to shift the output voltage. The differential input voltage range is at least ±80mV total, including DC offset and AC ripple. The integration time constant can be set easily with an external compensation capacitor at the CCV pin. Use a capacitor value of 47pF to 1000pF (47pF, typ).

Differential Remote Sense

The multiphase Quick-PWM controllers include differential remote-sense inputs to eliminate the effects of voltage drops down the PC board traces and through the processor’s power pins. The remote output sense (FBS) is accomplished by summing the remote-sense voltage into the positive terminal of the voltage-positioning amplifier (Figure 10). The controller includes a dedicated input and internal amplifier for the remote ground sense. The GNDS amplifier adds an offset directly to the feedback voltage, adjusting the output voltage to counteract the voltage drop in the ground path. Together, the feedback sense resistor (R

FBS

) and GNDS input sum the remote-sense voltages with the feedback signals that set the voltage-positioned output, enabling true differential remote sense of the processor voltage. Connect the feedback sense resistor (R

FBS

) and ground-sense input (GNDS) directly to the processor’s core supply remote-sense outputs as shown in the Standard Applications Circuit.

Offset Amplifier

The multiphase Quick-PWM controllers include a third amplifier used to add small offsets to the voltage-positioned load line. The offset amplifier is summed directly with the feedback voltage, making the offset gain independent of the DAC code. This amplifier has the ability to offset the output by ±100mV.

The offset is adjusted using resistive voltage-dividers at the OFS input. For inputs from 0 to 0.8V, the offset amplifier adds a negative offset to the output that is equal to 1/8 the voltage appearing at the selected OFS input (V

OUT

= V

DAC

- 0.125 × V

OFS

). For inputs from

1.2V to 2V, the offset amplifier adds a positive offset to the output that is equal to 1/8 the difference between the reference voltage and the voltage appearing at the selected OFS input (V

OUT

= V

DAC

+ 0.125 ×

REF

- V

OFS

)). With this scheme, the controller supports both positive and negative offsets with a single input. The piecewise linear transfer function is shown in the Typical Operating Characteristics. The regions of the transfer function below zero, above 2V, and between 0.8V and 1.2V are undefined. OFS inputs are disallowed in these regions, and the respective effects on the output are not specified.

The controller disables the offset amplifier during suspend mode (SUS = REF or high).

Forced-PWM Operation (Normal Mode)

During normal mode, when the CPU is actively running (SKIP = high, Table 7), the Quick-PWM controller operates with the low-noise forced-PWM control scheme. Forced-PWM operation disables the zero-crossing comparator, forcing the low-side gate-drive waveform to constantly be the complement of the high-side gatedrive waveform. This keeps the switching frequency fairly constant and allows the inductor current to

Table 7.

SSKKIIPP

Settings*

*Settings for a dual 180° out-of-phase controller.

SKIP

High

REF

GND

)

MODE OPERATION

Two-phase

forced-PWM

Two-phase

pulse skipping

One-phase

pulse skipping

The controller operates with a constant switching frequency, providing low-noise forced-PWM operation. The controller disables the zero-crossing comparators, forcing the low-side gatedrive waveform to constantly be the complement of the high-side gate-drive waveform.

The controller automatically switches over to PFM operation under light loads. The controller keeps both phases active and uses the automatic pulse-skipping control scheme—alternating between the primary and secondary phases with each cycle.

The controller automatically switches over to PFM operation under light loads. Only the main phase is active. The secondary phase is disabled—DHS and DLS are pulled low so LXS is high impedance.

CONNECTION

(3.3V or V

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

______________________________________________________________________________________ 29

reverse under light loads, providing fast, accurate negative output voltage transitions by quickly discharging the output capacitors.

Forced-PWM operation comes at a cost: the no-load 5V bias supply current remains between 10mA to 60mA per phase, depending on the external MOSFETs and switching frequency. To maintain high efficiency under light load conditions, the processor may switch the controller to a low-power pulse-skipping control scheme after entering suspend mode.

Low-Power Pulse Skipping

During pulse-skipping override mode (SKIP = REF or GND, Table 7), the multiphase Quick-PWM controllers use an automatic pulse-skipping control scheme. When SKIP is pulled low, the controller uses the automatic pulse-skipping control scheme, overriding forced-PWM operation, and blanks the upper VROK threshold.

SKIP is a three-level logic input—GND, REF, or high. This input is intended to be driven by a dedicated open-drain output with the pullup resistor connected either to REF (or a resistive divider from V

) or to a

logic-level high bias supply (3.3V or greater).

When driven to GND, the multiphase Quick-PWM controller disables the secondary phase (DLS = PGND and DHS = LXS) and the primary phase uses the automatic pulse-skipping control scheme. When pulled up to REF, the controller keeps both phases active and uses the automatic pulse-skipping control scheme—alternating between the primary and secondary phases with each cycle.

Automatic Pulse-Skipping Switchover

In skip mode (SKIP = REF or GND), an inherent automatic switchover to PFM takes place at light loads (Figure 7). A comparator that truncates the low-side

switch on-time at the inductor current’s zero crossing affects this switchover. The zero-crossing comparator senses the inductor current across the current-sense resistors. Once V

C_P

- VC_Ndrops below the zerocrossing comparator threshold (see the Electrical Characteristics), the comparator forces DL low (Figure 5). This mechanism causes the threshold between pulseskipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation. The PFM/PWM crossover occurs when the load current of each phase is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (Figure 7). For a battery input range of 7V to 20V, this threshold is relatively constant, with only a minor dependence on

Figure 8. “Valley” Current-Limit Threshold Point

Figure 7. Pulse-Skipping/Discontinuous Crossover Point

Figure 6. Offset Voltage

200

100

-100

OUTPUT OFFSET VOLTAGE (mV)

-200

01.00.5

0.8 1.2

OFS VOLTAGE (V)

UNDEFINED REGION

1.5 2.0

∆

- V

BATT

OUT

LIMIT(VALLEY)

= I

LOAD(MAX)

TIME

PEAK

= I

LOAD

PEAK

LOAD

LIMIT

2 - LIR

()

∆

INDUCTOR CURRENT

ON-TIME0 TIME

INDUCTOR CURRENT

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

30 ______________________________________________________________________________________

the input voltage due to the typically low duty cycles. The total load current at the PFM/PWM crossover threshold (I

LOAD(SKIP)

) is approximately:

where η

TOTAL

is the number of active phases, and K is

the on-time scale factor (Table 6).

The switching waveforms may appear noisy and asynchronous when light loading activates the pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Varying the inductor value makes trade-offs between PFM noise and light-load efficiency. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input voltage levels.

Current-Limit Circuit

The current-limit circuit employs a unique “valley” current-sensing algorithm that uses current-sense resistors between the current-sense inputs (C_P to C_N) as the current-sensing elements. If the current-sense signal of the selected phase is above the current-limit threshold, the PWM controller does not initiate a new cycle (Figure 8) until the inductor current of the selected phase drops below the valley current-limit threshold. When either phase trips the current limit, both phases are effectively current limited since the interleaved controller does not initiate a cycle with either phase.

Since only the valley current is actively limited, the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the current-sense resistance, inductor value, and battery voltage. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance.

There is also a negative current limit that prevents excessive reverse inductor currents when V

OUT

is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit, and therefore tracks the positive current limit when ILIM is adjusted. When a phase drops below the negative current limit, the controller immediately activates an ontime pulse—DL turns off, and DH turns on—allowing the inductor current to remain above the negative current threshold.

The current-limit threshold is adjusted with an external resistive voltage-divider at ILIM. The current-limit threshold voltage adjustment range is from 10mV to 75mV. In the adjustable mode, the current-limit threshold voltage is precisely 1/20 the voltage seen at ILIM. The threshold defaults to 30mV when ILIM is connected to V

. The logic threshold for switchover to the 30mV

default value is approximately VCC- 1V.

Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signals seen by the current-sense inputs (C_P, C_N).

MOSFET Gate Drivers (DH, DL)

The DH and DL drivers are optimized for driving moderately sized, high-side and larger, low-side power MOSFETs. This is consistent with the low-duty factor seen in the notebook CPU environment, where a large VIN- V

OUT

differential exists. An adaptive dead-time circuit monitors the DL output and prevents the highside FET from turning on until DL is fully off. There must be a low-resistance, low-inductance path from the DL driver to the MOSFET gate in order for the adaptive dead-time circuit to work properly. Otherwise, the sense circuitry in the Quick-PWM controller interprets the MOSFET gate as “off” while there is actually charge still left on the gate. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the device). The dead time at the other edge (DH turning off) is determined by a fixed 35ns internal delay.

The internal pulldown transistor that drives DL low is robust, with a 0.4Ω (typ) on-resistance. This helps prevent DL from being pulled up due to capacitive cou-

LOAD SKIP

TOTAL

()

 



 



 



 



V-V

OUT IN OUT

Figure 9. Optional Gate-Driver Circuitry

)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING

BST

NODE RISE TIME. (CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.

BST

PGND

BYP

BST

INPUT

)

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

______________________________________________________________________________________ 31

pling from the drain to the gate of the low-side MOSFETs when LX switches from ground to VIN. Applications with high input voltages and long, inductive DL traces may require additional gate-to-source capacitance to ensure fast-rising LX edges do not pull up the low-side MOSFET’s gate voltage, causing shootthrough currents. The capacitive coupling between LX and DL created by the MOSFET’s gate-to-drain capacitance (C

RSS

), gate-to-source capacitance (C

ISS

RSS

), and additional board parasitics should not

exceed the minimum threshold voltage:

Lot-to-lot variation of the threshold voltage can cause problems in marginal designs. Typically, adding a 4700pF between DL and power ground (CNLin Figure

9), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays.

Alternatively, shoot-through currents may be caused by a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually turned off. Adding a resistor less than 5Ω in series with BST slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading the turn-off time (R

BST

in Figure 9). Slowing down the high-side MOSFET also reduces the LX node rise time, thereby reducing EMI and high-frequency coupling responsible for switching noise.

Power-On Reset

Power-on reset (POR) occurs when VCCrises above approximately 2V, resetting the fault latch, activating boot mode, and preparing the PWM for operation. V

undervoltage lockout (UVLO) circuitry inhibits switching, and forces the DL gate driver high (to enforce output overvoltage protection). When VCCrises above

4.25V, the DAC inputs are sampled and the output voltage begins to slew to the target voltage.

For automatic startup, the battery voltage should be present before VCC. If the Quick-PWM controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. Toggle the SHDN pin to reset the fault latch.

Input Undervoltage Lockout

During startup, the VCCUVLO circuitry forces the DL gate driver high and the DH gate driver low, inhibiting switching until an adequate supply voltage is reached. Once VCCrises above 4.25V, valid transitions detected

at the trigger input initiate a corresponding on-time pulse (see the On-Time One-Shot section). If the V

voltage drops below 4.25V, it is assumed that there is not enough supply voltage to make valid decisions. To protect the output from overvoltage faults, the controller activates the shutdown sequence.

Multiphase Quick-PWM

Design Procedure

Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design:

• Input voltage range: The maximum value (V

IN(MAX)

) must accommodate the worst-case high

AC adapter voltage. The minimum value (V

IN(MIN)

) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency.

• Maximum load current: There are two values to consider. The peak load current (I

LOAD(MAX)

) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (I

LOAD

) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit I

LOAD

= I

LOAD(MAX)

× 80%.

For multiphase systems, each phase supports a fraction of the load, depending on the current balancing. When properly balanced, the load current is evenly distributed among each phase:

where η

TOTAL

is the total number of active phases.

• Switching frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses that are proportional to frequency and V

. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical.

• Inductor operating point: This choice provides trade-offs between size vs. efficiency and transient





RSS

GS TH IN

()









ISS

LOAD PHASE

LOAD

()

TOTAL

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

32 ______________________________________________________________________________________

response vs. output noise. Low-inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current.

Inductor Selection

The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows:

where η

TOTAL

is the total number of phases.

Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (I

PEAK

Transient Response

The inductor ripple current impacts transient-response performance, especially at low VIN- V

OUT

differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum offtime. For a dual-phase controller, the worst-case output sag voltage can be determined by:

where t

OFF(MIN)

is the minimum off-time (see the

Electrical Characteristics) and K is from Table 6.

The amount of overshoot due to stored inductor energy

can be calculated as:

where η

TOTAL

is the total number of active phases.

Setting the Current Limit

The minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at I

LOAD(MAX)

minus half

the ripple current; therefore:

where η

TOTAL

is the total number of active phases, and

LIMIT(LOW)

equals the minimum current-limit threshold

voltage divided by the current-sense resistor (R

SENSE

). For the 30mV default setting, the minimum current-limit threshold is 28mV.

Connect ILIM to VCCfor the default current-limit threshold (see the Electrical Characteristics). In adjustable mode, the current-limit threshold is precisely 1/20 the voltage seen at ILIM. For an adjustable threshold, connect a resistive divider from REF to GND with ILIM connected to the center tap. When adjusting the current limit, use 1% tolerance resistors with approximately 10µA of divider current to prevent a significant increase of errors in the current-limit tolerance.

Output Capacitor Selection

The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements.

In CPU V

CORE

converters and other applications where the output is subject to large load transients, the output capacitor’s size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance:

In non-CPU applications, the output capacitor’s size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor’s ESR. When operating multiphase systems out-of-



−

IN OUT

SW LOAD MAX

()





OUT









TOTAL

 



f I LIRVV

PEAK



I LIR

LOAD MAX





TOTAL



()

 



 



 

()

∆

LOAD MAX

() ()

SAG

OUT OUT

  

∆

LOAD MAX

()

OUT







 





()

VVK

−

 



IN OUT





OUT









OUT

 





 

 



OFF MIN

−

OFF MIN

()

 



  



()

  

SOAR

∆

()

LOAD MAX

≈

2η

TOTAL

()

OUT OUT

LIMIT LOW

()



I LIR

LOAD MAX





TOTAL



()

 



 

−

 



≤

STEP

∆

LOAD MAX

()

ESR

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

______________________________________________________________________________________ 33

phase, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage by reducing the total inductor ripple current. For 3- or 4phase operation, the maximum ESR to meet ripple requirements is:

where η

TOTAL

is the total number of active phases, t

is the calculated on-time per phase, and t

TRIG

is the trigger delay between the master’s DH rising edge and the slave’s DH rising edge. The trigger delay must be less than 1/(fSW×η

TOTAL

) for stable operation. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of polymer types).

When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent V

SAG

and V

SOAR

from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the V

SAG

and V

SOAR

equations

in the Transient Response section).

Output Capacitor Stability Considerations

For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation:

where:

and:

where C

OUT

is the total output capacitance, R

ESR

is the

total equivalent-series resistance, R

SENSE

is the cur-

rent-sense resistance, A

VPS

is the voltage-positioning

gain, and R

PCB

is the parasitic board resistance

between the output capacitors and sense resistors.

For a standard 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum, Sanyo POSCAP, and Panasonic SP capacitors in widespread use at the time of publication have typical ESR zero frequencies below 50kHz. For example, the ESR needed to support a 30mV

P-P

ripple in a 40A design

is 30mV/(40A × 0.3) = 2.5mΩ. Four 330µF/2.5V Panasonic SP (type XR) capacitors in parallel provide 2.5mΩ (max) ESR. Their typical combined ESR results in a zero at 40kHz.

Ceramic capacitors have a high ESR zero frequency, but applications with significant voltage positioning can take advantage of their size and low ESR. Do not put high-value ceramic capacitors directly across the output without verifying that the circuit contains enough voltage positioning and series PC board resistance to ensure stability. When only using ceramic output capacitors, output overshoot (V

SOAR

) typically determines the minimum output capacitance requirement. Their relatively low capacitance value can cause output overshoot when stepping from full-load to no-load conditions, unless a small inductor value is used (high switching frequency) to minimize the energy transferred from inductor to capacitor during load-step recovery. The efficiency penalty for operating at 550kHz is about 5% when compared to the 300kHz circuit, primarily due to the high-side MOSFET switching losses.

Unstable operation manifests itself in two related but distinctly different ways: double-pulsing and feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. Double-pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits.

The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot.

≤

ESR

−−()2 ηη

VVt Vt

IN TOTAL OUT ON TOTAL OUT TRIG

RIPPLE

ESR

2π

≤

EFF OUT

ESR

RR AR R

=+ +

EFF ESR VPS SENSE PCB

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

34 ______________________________________________________________________________________

Input Capacitor Selection

The input capacitor must meet the ripple current requirement (I

RMS

) imposed by the switching currents. The multiphase Quick-PWM controllers operate out-ofphase, while the Quick-PWM slave controllers provide selectable out-of-phase or in-phase on-time triggering. Out-of-phase operation reduces the RMS input current by dividing the input current between several staggered stages. For duty cycles less than 100%/η

OUTPH

per phase, the I

RMS

requirements may be determined

by the following equation:

where η

OUTPH

is the total number of out-of-phase switching regulators. The worst-case RMS current requirement occurs when operating with VIN= 2η

OUTPH

OUT

. At this

point, the above equation simplifies to I

RMS

= 0.5 ×

LOAD

/η

OUTPH

For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON™) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. If the Quick-PWM controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than 10°C temperature rise at the RMS input current for optimal circuit longevity.

Power MOSFET Selection

Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention.

The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both V

IN(MIN)

and V

IN(MAX)

. Calculate both of these sums.

Ideally, the losses at V

IN(MIN)

should be roughly equal to

losses at V

IN(MAX)

, with lower losses in between. If the

losses at V

IN(MIN)

are significantly higher than the losses

at V

IN(MAX)

, consider increasing the size of NH(reducing

DS(ON)

but with higher C

GATE

). Conversely, if the losses

at V

IN(MAX)

are significantly higher than the losses at

IN(MIN)

, consider reducing the size of NH(increasing

DS(ON)

to lower C

GATE

). If VINdoes not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses.

Choose a low-side MOSFET that has the lowest possible on-resistance (R

DS(ON)

), comes in a moderate-

sized package (i.e., one or two SO-8s, DPAK, or D2PAK), and is reasonably priced. Ensure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems can occur (see the MOSFET Gate Driver section).

MOSFET Power Dissipation

Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage:

where η

TOTAL

is the total number of phases.

Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the R

DS(ON)

required to stay within package power dissipation often limits how small the MOSFETs can be. Again, the optimum occurs when the switching losses equal the conduction (R

DS(ON)

) losses. Highside switching losses do not usually become an issue until the input is greater than approximately 15V.

Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH:

where C

RSS

is the reverse transfer capacitance of NHand

GATE

is the peak gate-drive source/sink current (1A, typ).

Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the C × V

× fSWswitching-loss equation. If the high-side

MOSFET chosen for adequate R

DS(ON)

at low battery voltages becomes extraordinarily hot when biased from V

IN(MAX)

, consider choosing another MOSFET with

lower parasitic capacitance.







OS-CON is a trademark of Sanyo.

RMS



 

LOAD

OUTPH



ηη()





VV V

OUTPH

OUT IN OUT

−

OUTPH

PD N RESISTIVE

()

 



OUT



 







LOAD

TOTAL



DS ON

()

 

CfII



RSS SW

PD N SWITCHING V

()()

H IN MAX

()

 

GATE





LOAD









TOTAL

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

______________________________________________________________________________________ 35

For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage:

The worst-case for MOSFET power dissipation occurs under heavy overloads that are greater than I

LOAD(MAX)

but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, you can “overdesign” the circuit to tolerate:

where I

VALLEY(MAX)

is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good size heatsink to handle the overload power dissipation.

Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 of the load current-per-phase. This diode is optional and can be removed if efficiency is not critical.

Boost Capacitors

The boost capacitors (C

BST

) selected must be large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1µF ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1µF. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFET’s gates:

where N is the number of high-side MOSFETs used for one regulator, and Q

GATE

is the gate charge specified in the MOSFET’s data sheet. For example, assume (2) IRF7811W N-channel MOSFETs are used on the high side. According to the manufacturer’s data sheet, a single IRF7811W has a maximum gate charge of 24nC (VGS= 5V). Using the above equation, the required boost capacitance would be:

Selecting the closest standard value, this example requires a 0.22µF ceramic capacitor.

Figure 10. Voltage-Positioning Gain

ERROR

COMPARATOR

MAX1519 MAX1545

CMN

CMP

OAIN+

OAIN-

CSP

CSN

SENSE

FBS

PC BOARD TRACE RESISTANCE

CPU SENSE POINT

PC BOARD TRACE RESISTANCE

MAIN

PHASE

SECOND

PHASE

D N RESISTIVE

()





=−



 



OUT

IN MAX

()



















LOAD

TOTAL



DS ON

()

 

LOAD

TOTA

TOTAL



VALLEY MAX





VALLEY MAX

()

∆

INDUCTOR

I LIR



LOAD MAX

()

 

 



 



NxQ

BST

200

GATE

xnC

224

BST

200

024. µ

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

36 ______________________________________________________________________________________

Current-Balance Compensation (CCI)

The current-balance compensation capacitor (C

CCI

) integrates the difference between the main and secondary current-sense voltages. The internal compensation resistor (R

CCI

= 20kΩ) improves transient response

by increasing the phase margin. This allows the dynamics of the current-balance loop to be optimized. Excessively large capacitor values increase the integration time constant, resulting in larger current differences between the phases during transients. Excessively small capacitor values allow the current loop to respond cycle-by-cycle but can result in small DC current variations between the phases. Likewise, excessively large resistor values can also cause DC current variations between the phases. Small resistor values reduce the phase margin, resulting in marginal stability in the current-balance loop. For most applications, a 470pF capacitor from CCI to the switching regulator’s output works well.

Connecting the compensation network to the output (V

OUT

) allows the controller to feed forward the output voltage signal, especially during transients. To reduce noise pickup in applications that have a widely distributed layout, it is sometimes helpful to connect the compensation network to the quiet analog ground rather than V

OUT

Setting Voltage Positioning

Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the processor’s power dissipation. When the output is loaded, an op amp (Figure 5) increases the signal fed back to the Quick-PWM controller’s feedback input. The adjustable amplification allows the use of standard, current-sense resistor values, and significantly reduces the power dissipated since smaller current-sense resistors can be used. The load-transient response of this control loop is extremely fast, yet well controlled, so the amount of voltage change can be accurately confined within the limits stipulated in the microprocessor powersupply guidelines.

The voltage-positioned circuit determines the load current from the voltage across the current-sense resistors (R

SENSE

= RCM= RCS) connected between the inductors and output capacitors, as shown in Figure 10. The voltage drop can be determined by the following equation:

where

SUM

is the number of phases summed together

for voltage-positioning feedback, and

TOTAL

is the total number of active phases. When the slave controller is disabled, the current-sense summation maintains the proper voltage-positioned slope. Select the positive input summing resistors so R

FBS

= RFand RA= RB.

Minimum Input Voltage Requirements

and Dropout Performance

The nonadjustable minimum off-time one-shot and the number of phases restrict the output voltage adjustable range for continuous-conduction operation. For best dropout performance, use the slower (200kHz) on-time settings. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. This error is greater at higher frequencies (Table 6). Also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the V

SAG

equation in the

Design Procedure section).

The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆I

DOWN

)

as much as it ramps up during the on-time (∆IUP). The ratio h = ∆IUP/∆I

DOWN

is an indicator of the ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle and V

SAG

greatly increases

unless additional output capacitance is used.

A reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between V

SAG

, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as:

where η

OUTPH

is the total number of out-of-phase

switching regulators, V

VPS

is the voltage-positioning

droop, V

DROP1

and V

DROP2

are the parasitic voltage drops in the discharge and charge paths (see the On- Time One-Shot section), t

OFF(MIN)

is from the Electrical Characteristics, and K is taken from Table 6. The absolute minimum input voltage is calculated with h = 1.

VAIR

VPS VPS LOAD SENSE

VPS

TOTAL

SUM

IN MIN

()

OUTPH

VVV

+−+

 

VV V

−+

FB VPS DROP

 

−



OUTPH



DROP DROP VPS

hxt







OFF MIN

 

 



()









MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

______________________________________________________________________________________ 37

If the calculated V

IN(MIN)

is greater than the required minimum input voltage, then reduce the operating frequency or add output capacitance to obtain an acceptable V

SAG

. If operation near dropout is anticipated,

calculate V

SAG

to be sure of adequate transient

response.

Dropout design example:

= 1.4V

MIN

= 3µs for fSW= 300kHz

OFF(MIN)

= 400ns

VPS

= 3mV/A × 30A = 90mV

DROP1

= V

DROP2

= 150mV (30A load)

h = 1.5 and η

OUTPH

= 2

Calculating again with h = 1 gives the absolute limit of dropout:

Therefore, VINmust be greater than 4.1V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 5V.

Applications Information

PC Board Layout Guidelines

Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 11). If possible, mount all of the power components on the topside of the board with their ground terminals flush against one another. Follow these guidelines for good PC board layout:

1) Keep the high-current paths short, especially at

the ground terminals. This is essential for stable, jitter-free operation.

2) Connect all analog grounds to a separate solid

copper plane, which connects to the GND pin of the Quick-PWM controller. This includes the V

bypass capacitor, REF and GNDS bypass capacitors, compensation (CC_) components, and the resistive dividers connected to ILIM and OFS.

3) Each slave controller should also have a separate analog ground. Return the appropriate noise-sensitive slave components to this plane. Since the reference in the master is sometimes connected to the slave, it may be necessary to couple the analog ground in the master to the analog ground in the slave to prevent ground offsets. A low-value (≤10Ω) resistor is sufficient to link the two grounds.

4) Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PC boards (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single mΩ of excess trace resistance causes a measurable efficiency penalty.

5) Keep the high-current, gate-driver traces (DL, DH, LX, and BST) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shoot-through currents.

6) C_P, C_N, OAIN+, and OAIN- connections for current limiting and voltage positioning must be made using Kelvin-sense connections to guarantee the current-sense accuracy.

7) When trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the low-side MOSFET or between the inductor and the output filter capacitor.

8) Route high-speed switching nodes away from sensitive analog areas (REF, CCV, CCI, FB, C_P, C_N, etc). Make all pin-strap control input connections (SHDN, ILIM, SKIP, SUS, S_, TON) to analog ground or V

rather than power ground or VDD.

Layout Procedure

Place the power components first, with ground terminals adjacent (low-side MOSFET source, CIN, C

OUT

, and D1 anode). If possible, make all these connections on the top layer with wide, copper-filled areas:

1) Mount the controller IC adjacent to the low-side

MOSFET. The DL gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC).

IN MIN()





1 2 04 15 30



+−+=

150 150 90 4 96

mV mV mV V



 

+−+=

150 150 90 4 07

−+

1 4 90 150

VmV mV

−

1 4 90 150

−

1 2 04 10 30

mV mV mV V

µµ

(. . / .

xsx s

−+

VmV mV

µµ

(. . / .

xsx s

  

MAX1519/MAX1545

2) Group the gate-drive components (BST diodes and capacitors, VDDbypass capacitor) together near the controller IC.

3) Make the DC-to-DC controller ground connections as shown in the Standard Application Circuits. This diagram can be viewed as having four separate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the PGND pin and VDDbypass capacitor go; the master’s analog ground plane, where sensitive analog components, the master’s GND pin, and VCCbypass capacitor go; and the slave’s analog ground plane, where the slave’s GND pin and VCCbypass capacitor go. The master’s GND plane must meet the PGND plane only at a single point directly beneath the IC. Similarly, the slave’s GND plane must meet the PGND plane only at a single point directly beneath the IC. The respective master and slave ground planes should connect to the high-power output ground with a short metal trace from PGND to the source of the low-side MOSFET (the middle of the star ground). This point must also be very close to the output capacitor ground terminal.

4) Connect the output power planes (V

CORE

and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-to-DC converter circuit as close to the CPU as is practical.

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

38 ______________________________________________________________________________________

Chip Information

TRANSISTOR COUNT: 11,015

PROCESS: BiCMOS

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

______________________________________________________________________________________ 39

Figure 11. PC Board Layout Example

KELVIN SENSE VIAS UNDER

THE SENSE RESISTOR

(REFER TO EVALUATION KIT)

CPU

MAIN PHASE

INDUCTOR

PLACE CONTROLLER ON

BACK SIDE WHEN POSSIBLE,

USING THE GROUND PLANE

TO SHIELD THE IC FROM EMI

SENSE

OUT

OUTCOUTCOUTCOUTCOUT

POWER

GROUND

CINCINC

INPUT

VIAS TO POWER

GROUND

OUTPUT

CINCINC

POWER GROUND

(2ND LAYER)

SECONDARY PHASE

SENSE

INDUCTOR

CONNECT THE

EXPOSED PAD TO

ANALOG GND

VIAS TO ANALOG

GROUND

POWER GROUND

(2ND LAYER)

CONNECT GND

AND PGND TO THE

CONTROLLER AT ONE POINT

ONLY AS SHOWN

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

40 ______________________________________________________________________________________

Figure 12a. Standard 4-Phase Desktop P4 Application Circuit (1st and 2nd Phases—MAX1519/MAX1545 Master)

5V BIAS SUPPLY

BST1

0.22µF

3.0kΩ ±1%

CCI

470pF

BST2

0.22µF

2.2µF

BST DIODES

INPUT*

1kΩ

±1%

1kΩ

±1%

7V TO 24V

SENSE1

1.5mΩ

SENSE2

1.5mΩ

R10

10Ω

R11

100kΩ

POWER-

GOOD

DAC INPUTS

SUSPEND INPUTS

(FOUR-LEVEL LOGIC)

OFF

REF

0.22µF

30.1kΩ

REF

100pF

STP_CPU#

PWM

SKIP

±1%

1µF

64.9kΩ

REF (300kHz)

100kΩ

±1%

TIME

CCV

47pF

R28 182kΩ ±1%

R27 20kΩ ±1%

VROK

D0 D1 D2 D3 D4

CODEGND (DESKTOP P4) S0 S1

SHDN

TIME

CCV

TON

REF

ILIM

OFS

SKIP

SUS

MAX1519 MAX1545

BSTM

DHM

LXM

DLM

PGND

GND

CMN

CMP

OAIN+

OAIN-

CCI

CSP

CSN

BSTS

DHS

LXS

DLS

GNDS

V+

R3 1kΩ ±1%

3.0kΩ

R5 1kΩ ±1%

±1%

OUT

OUTPUT

OUT

POWER GROUND

ANALOG GROUND

*LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE.

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

______________________________________________________________________________________ 41

Figure 12b. Standard 4-Phase Desktop 4 Application Circuit (3rd Phase—MAX1980 Slave)

5V BIAS SUPPLY

BST3

0.22µF

C7 1000pF

C8 1000pF

1µF

R13

100Ω

R14

100Ω

R15

100Ω

R16

100Ω

MAX1519/MAX1545

INPUT* 7V TO 24V

CMP

CMN

CONNECT TO

(SEE FIGURE 12a)

SENSE3

1.5mΩ

*LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE.

OUTPUT

OUT

OUTPUT

REF

(MASTER)

POWER GROUND

ANALOG GROUND (MASTER)

ANALOG GROUND (SLAVE)

200kΩ

FLOAT

(300kHz)

0.22µF

1N4148

COMP1

270pF

R17

100pF

SKIP

CONNECT TO

MAX1519/MAX1545

(SEE FIGURE 12a)

COMP1

20kΩ

(MASTER)

R12

10Ω

R18

49.9kΩ

DLM

(MASTER)

POL

COMP

ILIM

LIMIT

TRIG

MAX1980

BST

PGND

GND

CS+

CS-

CM+

CM-

V+

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

42 ______________________________________________________________________________________

Figure 12c. Standard 4-Phase Desktop 4 Application Circuit (4th Phase—MAX1980 Slave)

5V BIAS SUPPLY

C10

BST4

0.22µF

C12 1000pF

C13 1000pF

1µF

R20

100Ω

R21

100Ω

R22

100Ω

R23

100Ω

MAX1519/MAX1545

INPUT* 7V TO 24V

CSP

CSN

CONNECT TO

(SEE FIGURE 12a)

*LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE.

SENSE4

1.5mΩ

R19

10Ω

C11

0.22µF

1N4148

OUTPUT

REF

(MASTER)

200kΩ

270pF

R24

100pF

COMP2

C14

COMP2

20kΩ

R25

49.9kΩ

FLOAT

(300kHz)

DLS

SKIP

(MASTER)

CONNECT TO

MAX1519/MAX1545

(SEE FIGURE 12a)

POWER GROUND

ANALOG GROUND (MASTER)

ANALOG GROUND (SLAVE)

POL

COMP

ILIM

LIMIT

TRIG

MAX1980

BST

PGND

GND

CS+

CS-

CM+

CM-

V+

OUTPUT

OUT

MAX1519/MAX1545

Dual-Phase, Quick-PWM Controllers for

Programmable CPU Core Power Supplies

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 43

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages

D/2

E/2

(NE-1) X e

A1 A2

(ND-1) X e

e e

PACKAGE OUTLINE 36,40L QFN THIN, 6x6x0.8 mm

D2/2

21-0141

E2/2

QFN THIN 6x6x0.8.EPS

COMMON DIMENSIONS

NOTES:

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220.

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

EXPOSED PAD VARIATIONS

PKG.

CODES

T3666-1

T4066-1

NOM.

3.703.60 3.80

4.00 4.10 4.20 4.00 4.204.10

PACKAGE OUTLINE 36, 40L QFN THIN, 6x6x0.8 mm

MAX.MIN.

21-0141

MAX.

MIN.

NOM.

3.803.703.60

Rainbow Electronics MAX1545 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual