General Description
The MAX1540/MAX1541 dual pulse-width modulation
(PWM) controllers provide the high efficiency, excellent
transient response, and high DC-output accuracy necessary for stepping down high-voltage batteries to generate low-voltage chipset and RAM power supplies in
notebook computers.
The Maxim proprietary Quick-PWM™ controllers are
free running, constant on-time with input feed forward.
This configuration provides ultra-fast transient
response, wide input-output (I/O) differential range, low
supply current, and tight load-regulation characteristics. The controllers can accurately sense the inductor
current across an external current-sense resistor in
series with the output to ensure reliable overload and
inductor saturation protection. Alternatively, the controllers can use the synchronous rectifier itself or lossless inductor current-sensing methods to provide
overload protection with lower power dissipation.
For a single step-down PWM controller with inductorsaturation protection, external-reference input voltage,
and dynamically selectable output voltages, refer to the
MAX1992/MAX1993 data sheet.
Applications
Notebook Computers
Core/IO Supplies as Low as 0.7V
0.7V to 5.5V Supply Rails
CPU/Chipset/GPU with Dynamic Voltage Core
Supplies (MAX1541)
DDR Memory Termination (MAX1541)
Active Termination Buses (MAX1541)
Features
♦ Inductor-Saturation Protection
♦ Accurate Differential Current-Sense Inputs
♦ Dual Ultra-High-Efficiency Quick-PWMs with
100ns Load-Step Response
♦ MAX1540
1.8V/1.2V Fixed or 0.7V to 5.5V Adjustable
Output (OUT1)
2.5V/1.5V Fixed or 0.7V to 5.5V Adjustable
Output (OUT2)
Fixed 5V, 100mA Linear Regulator
♦ MAX1541
External Reference Input (REFIN1)
Dynamically Selectable Output Voltage—0.7V
to 5.5V (OUT1)
2.5V/1.8V Fixed or 0.7V to 5.5V Adjustable
Output (OUT2)
Optional Power-Good and Fault Blanking
During Transitions
Fixed 5V or Adjustable 100mA Linear Regulator
♦ 1% V
OUT
Accuracy over Line and Load
♦ 2V to 28V Battery Input Range
♦ 170kHz to 620kHz Selectable Switching
Frequency
♦ Overvoltage/Undervoltage-Protection Option
♦ 1.7ms Digital Soft-Start
♦ Drives Large Synchronous-Rectifier FETs
♦ 2V ±0.7% Reference Output
♦ Separate Power-Good Window Comparators
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
________________________________________________________________ Maxim Integrated Products 1
THIN QFN
TOP VIEW
32313029282726
ON1
ON2
CSP1
CSN1
FB1
OUT1
PGOOD1
25 DH1
9
1011121314
15
CSP2
CSN2
FB2
OUT2
PGOOD2
DH2
LX2
16BST2
17
18
19
20
21
22
23
GND
DL2
V+
LDOOUT
DL1
LDOON
BST1
8
7
6
5
4
3
2
REF
ILIM2
ILIM1
V
CC
TON
LSAT
SKIP
MAX1540
1OVP/UVP
24 LX1
Pin Configurations
19-2861; Rev 0; 10/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
*Future product—contact factory for availability.
Ordering Information
Pin Configurations continued at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX1540ETJ -40°C to +85°C 32 Thin QFN 5mm x 5mm
MAX1541ETL* -40°C to +85°C 40 Thin QFN 6mm x 6mm
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: For the MAX1540, the gate-driver input supply (VDD) is internally connected to the fixed 5V linear-regulator output (LDOOUT),
and the linear-regulator input supply (LDOIN) is internally connected to the battery voltage input (V+).
V+, LDOON to GND ...............................................-0.3V to +28V
LDOOUT to GND (MAX1540, Note 1) ......................-0.3V to +6V
LDOOUT to GND (MAX1541, Note 1) ....................-0.3V to +28V
V
DD
to GND (MAX1541, Note 1) ..............................-0.3V to +6V
V
CC
, ON_ to GND.....................................................-0.3V to +6V
SKIP, PGOOD_ to GND............................................-0.3V to +6V
FB_, CSP_, ILIM_ to GND.........................................-0.3V to +6V
TON, OVP/UVP, LSAT to GND ...................-0.3V to (V
CC
+ 0.3V)
REF, OUT_ to GND.....................................-0.3V to (V
CC
+ 0.3V)
LDOIN to GND (MAX1541).....................................-0.3V to +28V
REFIN1, GATE, OD, FBLDO to GND (MAX1541).....-0.3V to +6V
FBLANK, CC1 to GND (MAX1541).............-0.3V to (V
CC
+ 0.3V)
DL_ to GND (Note 1) ..................................-0.3V to (V
DD
+ 0.3V)
CSN_ to GND ............................................................-2V to +30V
DH_ to LX_..................................................-0.3V to (BST + 0.3V)
LX_ to GND................................................................-2V to +30V
BST_ to LX_ ..............................................................-0.3V to +6V
REF Short Circuit to GND ...........................................Continuous
Continuous Power Dissipation (T
A
= +70°C)
32-Pin 5mm x 5mm Thin QFN (derated 21.3mW/°C
above +70°C).............................................................1702mW
40-Pin 6mm x 6mm Thin QFN (derated 26.3mW/°C
above +70°C).............................................................2105mW
Operating Temperature Range
MAX154_ET_ ...................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
INPUT SUPPLIES (Note 1)
Quiescent Supply Current (VCC)I
Quiescent Supply Current
(V
Quiescent Supply Current (V+) I
Quiescent Supply Current
(LDOIN, MAX1541 Only)
Standby Supply Current (VCC) ON1 = ON2 = GND, V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1540: battery voltage, V+ > V
IN
MAX1541: battery voltage, V+ > V
V
MAX1541: LDO input supply,
V
FB1 and FB2 forced above the regulation
point, LSAT = GND
FB1 and FB2 forced above the regulation
point, ON1 or ON2 = V
FB1 and FB2 forced above the regulation
point, ON1 or ON2 = V
MAX1540: FB1 and FB2 forced above the
regulation point, ON1 or ON2 = V
V
MAX1541: ON1 or ON2 = VCC,
V
FB1 and FB2 forced above the regulation
point, ON1 or ON2 = V
V
CC, VDD
LDOIN
LDOON
LDOON
LDOON
(MAX1541) 4.5 5.5Input Voltage Range
> V
LDOOUT
= V+ = 28V
= V+ = 28V
= V+ = 28V
, MAX1541 Only)
DD
V
V
BIAS
V
LDOIN
CC
I
DD
V+
I
LDOIN
LDOOUT
LDOOUT
, V
CC
CC
CC
LDOON
> 0.5V
LSAT
,
CC
,
= V+ = 28V <1 5 µA
5.5 28
228
4.5 28
0.7 1.5
1.8
<1 5 µA
150
25 40
110 µA
V
mA
µA
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
Standby Supply Current
(V
Standby Supply Current (V+)
Standby Supply Current
(LDOIN, MAX1541 Only)
Shutdown Supply Current (VCC) ON1 = ON2 = LDOON = GND <1 5 µA
Shutdown Supply Current
(V
Shutdown Supply Current (V+)
Shutdown Supply Current
(LDOIN, MAX1541 Only)
PWM CONTROLLERS
MAX1540 Main Output-Voltage
Accuracy (OUT1) (Note 2)
MAX1540 Secondary OutputVoltage Accuracy (OUT2)
(Note 2)
MAX1541 Main FeedbackVoltage Accuracy (FB1)
MAX1541 Secondary OutputVoltage Accuracy (OUT2)
(Note 2)
Load-Regulation Error I
Line-Regulation Error VCC = 4.5V to 5.5V, V+ = 4.5V to 28V 0.25 %
FB_ Input Bias Current IFB_ -0.1 +0.1 µA
Output Adjust Range 0.7 5.5 V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
, MAX1541 Only)
DD
, MAX1541 Only)
DD
V
V
V
V
V
V
V
OUT1
FB1
OUT2
FB2
FB1
OUT2
FB2
ON1 = ON2 = GND, V
MAX1540: ON1 = ON2 = GND,
LDOON = V+ = 28V, V
MAX1541: ON1 = ON2 = GND,
LDOON = V+ = 28V, V
ON1 = ON2 = GND, V
ON1 = ON2 = LDOON = GND <1 5 µA
MAX1540: ON1 = ON2 = LDOON = GND,
V+ = 28V, V
MAX1541: ON1 = ON2 = LDOON = GND,
V+ = 28V, V
LDOON = GND 4 10 µA
Preset output,
V+ = 5.5V to 28V,
SKIP = V
Adjustable output, V+ = 5.5V to 28V,
SKIP = V
Preset output,
V+ = 5.5V to 28V,
SKIP = V
Adjustable output, V+ = 5.5V to 28V,
SKIP = V
V+ = 4.5V to 28V,
SKIP = V
Preset output,
V+ = 4.5V to 28V,
SKIP = V
Adjustable output, V+ = 4.5V to 28V,
SKIP = V
= 0 to 3A, SKIP = V
LOAD
= 0 or 5V
CC
= VDD = 0 or 5V
CC
CC
CC
CC
CC
CC
CC
CC
= V+ = 28V <1 5 µA
LDOON
= 0 or 5V
CC
= VDD = 0 or 5V
CC
= V+ = 28V 100 µA
LDOON
FB1 = GND 1.782 1.80 1.818
FB1 = V
CC
FB2 = GND 2.475 2.50 2.525
FB2 = V
CC
REFIN1 = 0.35 x REF 0.693 0.70 0.707 V
FB2 = GND 2.475 2.50 2.525
FB2 = V
CC
CC
1.188 1.20 1.212
0.693 0.70 0.707
1.485 1.50 1.515
0.693 0.70 0.707
1.782 1.80 1.818
0.693 0.70 0.707
<1 5
415
<1 5
0.1 %
105
µA
µA
V
V
V
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
)
OUT_ Input Resistance R
OUT_ Discharge Mode OnResistance
OUT_ Synchronous-Rectifier
Discharge-Mode Turn-On Level
Soft-Start Ramp Time t
DH1 On-Time t
DH2 On-Time t
On-Time Tracking t
Minimum Off-Time t
LINEAR REGULATOR (LDO) (Note 1)
MAX1540 LDO Output-Voltage
Accuracy
MAX1541 LDO Output-Voltage
Accuracy (Fixed V
MAX1541 LDO Feedback
Accuracy (Adjustable V
MAX1541 LDO Output
Adjust Range
LDOOUT Short-Circuit Current 130 mA
FBLDO Input Bias Current I
Dropout Voltage
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FB_ = GND 70 145 350
OUT
R
D IS C H ARGE
MAX1540
_
MAX1541
FB_ = V
adjustable
CC
or
50 115 220
FB1 = OUT1 400 700 1500
FB2 = GND 90 170 350
CC
or
60 130 270
FB2 = V
adjustable
10 25 Ω
0.2 0.3 0.4 V
SS
ON1
Rising edge on ON_ to full current limit 1.7 ms
V+ = 15V,
= 1.5V
V
OUT1
(Note 3)
TON = GN D ( 620kH z)
TON = REF (485kHz) 191 216 242
TON = op en ( 345kH z) 274 304 335
TON = V
(235kHz) 402 447 491
CC
149 169 190
TON = GN D ( 460kH z) 201 228 256
LDOOUT
LDOOUT
V+ = 15V,
= 1.5V
V
ON2
OUT2
(Note 3)
with respect to t
ON2
OFF(MIN
V
LDOOUT
(Note 3) 400 500 ns
ON1 = ON2 = GND,
V+ = 6V to 28V
FBLDO = ON1 =
V
)
LDOOUT
ON2 = GND,
V
= 6V to 28V
LDOIN
FBLDO = LDOOUT,
V
FBLDO
)
ON1 = ON2 = GND,
V
= 4.5V to
LDOIN
28V
TON = REF (355kHz) 260 296 331
TON = op en ( 255kH z) 371 412 453
TON = V
(Note 3) 120 135 150 %
ON1
0 < I
0 < I
0 < I
0 < I
0 < I
0 < I
(170kHz) 556 618 679
CC
LDOOUT
LD OOU T
LDOOUT
LD OOU T
LDOOUT
LD OOU T
< 10mA 4.85 5.0 5.10
< 100m A 4.70 5.10
< 10mA 4.85 5.0 5.10
< 100m A 4.70 5.10
< 10mA 1.212 1.25 1.275
< 100m A 1.175 1.275
1.175 24 V
FBLDO
MAX1540: V+ - V
MAX1541: V
LDOIN
LDOOUT
- V
LDOOUT
-0.1 +0.1 µA
500 800
500 800
kΩ
ns
ns
V
V
V
mV
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
)
)
REFERENCE (REF)
Reference Voltage V
Reference Load Regulation ∆V
REF Lockout Voltage V
REFIN1 (MAX1541)
Voltage Range
REFIN1 (MAX1541)
Input Bias Current
FAULT DETECTION
Overvoltage Trip Threshold
Overvoltage Fault-Propagation
Delay
Output Undervoltage-Protection
Trip Threshold
Output Undervoltage-Protection
Blanking Time
Output Undervoltage FaultPropagation Delay
PGOOD_ Lower Trip Threshold
PGOOD_ Upper Trip Threshold
PGOOD_ Propagation Delay t
PGOOD_ Output Low Voltage I
PGOOD_ Leakage Current I
Fault-Blanking Time
(MAX1541 Only)
Thermal-Shutdown Threshold T
VCC Undervoltage-Lockout
Threshold
CURRENT LIMIT
ILIM_ Adjustment Range 0.25 2 V
Current-Limit Input Range
CSP_/CSN_ Input Current 0.5 µA
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REF
REFIREF
REF(UVLO
V
REFIN
I
REFIN1
t
OVP
t
BLANK
t
UVP
PGOOD
PGOOD
t
FBLANK
SHDN
V
UVLO(VCC
VCC = 4.5V to 5.5V,
= 0V
I
REF
= -10µA to +50µA -0.01 +0.01 V
Rising edge, hysteresis = 350mV 1.95 V
With respect to error-comparator threshold,
OVP/UVP = V
FB forced 2% above trip threshold 10 µs
With respect to error-comparator threshold,
OVP/UVP = V
From rising edge of ON_ 10 35 ms
With respect to error-comparator threshold,
hysteresis = 1%
With respect to error-comparator threshold,
hysteresis = 1%
FB forced 2% beyond P GOOD _ trip threshold
_
= 4mA 0.3 V
SINK
FB = REF (PGOOD high impedance),
_
PGOOD forced to 5.5V
FBLANK = V
FBLANK = open 80 140 205
FBLANK = REF 35 65 95
Hysteresis = 10°C
Rising edge, PWM disabled below this
level, hysteresis = 20mV
CSP_ 0 2.7
CSN_ -0.3 +28
CC
CC
CC
TA = + 25° C to + 85° C 1.986 2.00 2.014
T
= 0° C to +85°C 1.983 2.00 2.017
A
0.7 V
0.01 0.05 µA
12 16 20 %
65 70 75 %
10 µs
-13 -10 -7 %
+7 +10 +13 %
10 µs
120 220 320
LDOON = V
LDOON = GND +160
CC
4.1 4.25 4.4 V
+150
REF
1µA
V
V
µs
°C
V
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
6 _______________________________________________________________________________________
Dual Mode is a trademark of Maxim Integrated Products, Inc.
)
)
)
(
)
)
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
Valley Current-Limit Threshold
(Fixed)
Valley Current-Limit Threshold
(Adjustable)
Current-Limit Threshold
(Negative)
Current-Limit Threshold
(Zero Crossing)
Inductor-Saturation Current-Limit
Threshold
ILIM_ Saturation Fault Sink
Current
ILIM_ Leakage Current
GATE DRIVERS
DH_ Gate-Driver On-Resistance R
DL_ Gate-Driver On-Resistance R
DH_ Gate-Driver Source/Sink
Current
DL_ Gate-Driver Source Current
DL_ Gate-Driver Sink Current I
Dead Time t
INPUTS AND OUTPUTS
OD On-Resistance R
OD Leakage Current GATE = GND, OD forced to 5.5V 1 200 nA
Logic Input Threshold
LDOON Input Trip Level Rising edge, hysteresis = 250mV 1.20 1.25 1.30 V
Logic Input Current ON1, ON2, LDOON, SKIP, GATE -1 +1 µA
Dual Mode™ Threshold Voltage
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
LIM_ (VAL
V
LIM_ (VAL
V
NEG
CSP
V
CSP
V
CSP
= +25°C
T
A
_ - V
_ - V
_ - V
_, ILIM_ = V
CSN
_
CSN
_, SKIP = ILIM_ = VCC,
CSN
CC
V
_ = 250mV 15 25 35
ILIM
V
_ = 2.00V 170 200 230
ILIM
45 50 55 mV
-90 -65 -45 mV
V
With respect to valley current-limit
V
ZX
I
ILIM_ (LSAT
DH
DL
I
DH
I
DL
SOURCE
DL (SINK
DEAD
OD
CC
CSP
_ - V
threshold, V
ILIM_ = V
With respect to
valley currentlimit threshold,
ILIM_ = V
V
CSP
limit, 0.25V < V
V
CSP
CC
- V
> inductor saturation current
CSN
ILIM
_ - V
< inductor saturation current
CSN _
limit
BST_-LX_ forced to 5V 1.5 5 Ω
DL_, high state 1.5 5
DL_, low state 0.6 3
DH_ forced to 2.5V, BST_-LX_ forced to 5V 1 A
DL_ forced to 2.5V 1 A
DL_ forced to 2.5V 3 A
DL_ rising 35
DH_ rising 26
GATE = V
CC
ON1, ON2, SKIP, GATE rising edge,
hysteresis = 225mV
FB1 (MAX1540),
_, SKIP = GND,
CSN
LSAT = V
CC
180 200 220
2.5 mV
LSAT = open 157 175 193
LSAT = REF 135 150 165
_ < 2.0V
468µA
0.1 µA
10 25 Ω
1.2 1.7 2.2 V
High 1.9 2.0 2.1
FB2 (MAX1540/
MAX1541)
Low 0.05 0.1 0.15
mV
%
Ω
ns
V
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, TA= 0°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
ELECTRICAL CHARACTERISTICS
(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, TA= -40°C to +85°C, unless otherwise noted.) (Note 4)
PARAMETER
CONDITIONS
INPUT SUPPLIES (Note 1)
MAX1540: battery voltage, V+ > V
LDOOUT
5.5 28
V
IN
MAX1541: battery voltage, V+ > V
LDOOUT
228
V
BIAS
V
CC, VDD
(MAX1541) 4.5 5.5Input Voltage Range
V
LDOIN
MAX1541: LDO input supply,
V
LDOIN
> V
LDOOUT
4.5 28
V
FB1 and FB2 forced above the regulation
point, LSAT = GND
1.5
Quiescent Supply Current (VCC)I
CC
FB1 and FB2 forced above the regulation
point, ON1 or ON2 = V
CC
, V
LSAT
> 0.5V
1.8
mA
Quiescent Supply Current
(V
DD
, MAX1541 Only)
I
DD
FB1 and FB2 forced above the regulation
point, ON1 or ON2 = V
CC
5µA
MAX1540: FB1 and FB2 forced above the
regulation point, ON1 or ON2 = V
CC
,
V
LDOON
= V+ = 28V
150
Quiescent Supply Current (V+) I
V+
MAX1541: ON1 or ON2 = VCC, V
LDOON
=
V+ = 28V
40
µA
Quiescent Supply Current
(LDOIN, MAX1541 Only)
I
LDOIN
FB1 and FB2 forced above the regulation
point, ON1 or ON2 = V
CC
,
V
LDOON
= V+ = 28V
110 µA
Standby Supply Current (VDD) ON1 = ON2 = GND, V
LDOON
= V+ = 28V 5 µA
Standby Supply Current
(V
DD
, MAX1541 Only)
ON1 = ON2 = GND, V
LDOON
= V+ = 28V 5 µA
MAX1540: ON1 = ON2 = GND, LDOON =
V+ = 28V, V
CC
= 0 or 5V
105
Standby Supply Current (V+)
MAX1541: ON1 = ON2 = GND, LDOON =
V+ = 28V, V
CC
= VDD = 0 or 5V
5
µA
Standby Supply Current
(LDOIN, MAX1541 Only)
ON1 = ON2 = GND, V
LDOON
= V+ = 28V 100 µA
Four-Level Input Logic Levels
Four-Level Logic Input Current
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TON, OVP/UVP,
LSAT, SKIP,
FBLANK
TON, OVP/UVP, LSAT, SKIP, FBLANK
forced to GND or V
SYMBOL
V
High
Open 3.15 3.85
REF 1.65 2.35
Low 0.5
CC
CC
0.4V
-3 +3 µA
MIN MAX UNITS
-
V
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
8 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, TA= -40°C to +85°C, unless otherwise noted.) (Note 4)
PARAMETER
CONDITIONS
UNITS
Shutdown Supply Current (VCC) ON1 = ON2 = LDOON = GND 5 µA
Shutdown Supply Current
(V
DD
, MAX1541 Only)
ON1 = ON2 = LDOON = GND 5 µA
MAX1540: ON1 = ON2 = LDOON = GND,
V+ = 28V, V
CC
= 0 or 5V
15
Shutdown Supply Current (V+)
MAX1541: ON1 = ON2 = LDOON = GND,
V+ = 28V, V
CC
= VDD = 0 or 5V
5
µA
Shutdown Supply Current
(LDOIN, MAX1541 Only)
LDOON = GND 10 µA
PWM CONTROLLERS
FB1 = GND
V
OUT1
Preset output,
V+ = 5.5V to 28V,
SKIP = V
CC
FB1 = V
CC
MAX1540 Main Output-Voltage
Accuracy (OUT1) (Note 2)
V
FB1
Adjustable output, V+ = 5.5V to 28V,
SKIP = V
CC
V
FB2 = GND
V
OUT2
Preset output,
V+ = 5.5V to 28V,
SKIP = V
CC
FB2 = V
CC
MAX1540 Secondary OutputVoltage Accuracy (OUT2)
(Note 2)
V
FB2
Adjustable output, V+ = 5.5V to 28V,
SKIP = V
CC
V
MAX1541 Main Feedback
Voltage Accuracy (FB1)
V
FB1
V+ = 4.5V to 28V,
SKIP = V
CC REFIN1 = REF
V
FB2 = GND
V
OUT2
Preset output,
V+ = 4.5V to 28V,
SKIP = V
CC
FB2 = V
CC
MAX1541 Secondary OutputVoltage Accuracy (OUT2)
(Note 2)
V
FB2
Adjustable output, V+ = 4.5V to 28V,
SKIP = V
CC
V
190
242
335
DH1 On-Time (Note 3) t
ON1
V+ = 15V,
V
OUT1
= 1.5V
491
ns
256
331
453
DH2 On-Time (Note 3) t
ON2
V+ = 15V,
V
OUT2
= 1.5V
679
ns
On-Time Tracking t
ON2
with respect to t
ON1
(Note 3)
152 %
Minimum Off-Time
)
(Note 3) 500 ns
LINEAR REGULATOR (LDO) (Note 1)
MAX1540 LDO Output-Voltage
Accuracy
ON1 = ON2 = GND,
V+ = 6V to 28V
V
SYMBOL
MIN MAX
t
OFF(MIN
V
LDOOUT
1.773 1.827
1.182 1.218
0.689 0.711
2.462 2.538
1.477 1.523
0.689 0.711
REFIN1 = 0.35 x REF 0.689 0.711
1.97 2.03
2.462 2.538
1.773 1.827
0.689 0.711
TON = G N D ( 620kH z) 149
TON = RE F ( 485kH z) 191
TON = op en ( 345kH z) 274
TON = V CC ( 235kH z) 402
TON = G N D ( 460kH z) 201
TON = RE F ( 355kH z) 260
TON = op en ( 255kH z) 371
TON = V CC ( 170kH z) 556
0 < I
0 < I
LDOOUT
L D OOU T
< 10mA 4.85 5.10
< 100m A 4.65 5.10
118
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
_______________________________________________________________________________________ 9
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, TA= -40°C to +85°C, unless otherwise noted.) (Note 4)
PARAMETER
CONDITIONS
UNITS
MAX1541 LDO Output-Voltage
Accuracy (Fixed V
LDOOUT
)
FBLDO = ON1 =
ON2 = GND,
V
MAX1541 LDO Feedback
Accuracy (Adjustable V
LDOOUT
)
FBLDO = LDOOUT,
ON1 = ON2 = GND,
V
LDOIN
= 4.5V to
28V
V
MAX1540: V+ - V
LDOOUT
800
Dropout Voltage
MAX1541: V
LDOIN
- V
LDOOUT
800
mV
REFERENCE (REF)
Reference Voltage V
REF
VCC = 4.5V to 5.5V, I
REF
= 0
V
REFIN1 Input Bias Current I
REFIN1
µA
FAULT DETECTION
Overvoltage Trip Threshold
With respect to error-comparator threshold,
OVP/UVP = V
CC
10 21 %
Output Undervoltage-Protection
Trip Threshold
With respect to error-comparator threshold,
OVP/UVP = V
CC
64 76 %
PGOOD_ Lower Trip Threshold
With respect to error-comparator threshold,
hysteresis = 1%
-14 -5 %
PGOOD_ Upper Trip Threshold
With respect to error-comparator threshold,
hysteresis = 1%
+5
%
PGOOD_ Output Low Voltage I
SINK
= 4mA 0.3 V
VCC Undervoltage-Lockout
Threshold
)
Rising edge, PWM disabled below this
level, hysteresis = 20mV
4.1 4.4 V
CURRENT LIMIT
CSP_ 0 2.7
Current-Limit Input Range
CSN_
V
Valley Current-Limit Threshold
(Fixed)
)
V
CSP
_ - V
CSN
_, ILIM_ = V
CC
40 60 mV
Valley Current-Limit Threshold
(Adjustable)
)
V
CSP
_ - V
CSN
_, V
ILIM
_ = 2.00V
240 mV
INPUTS AND OUTPUTS
Logic Input Threshold
ON1, ON2, SKIP, GATE, rising edge,
hysteresis = 225mV
1.2 2.2 V
LDOON Input Trip Level Rising edge, hysteresis = 250mV 1.2 1.3 V
High 1.9 2.1
Dual Mode Threshold Voltage
FB1 (MAX1540),
FB2 (MAX1540/MAX1541)
Low
V
SYMBOL
V
LDOOUT
V
FBLDO
V
UVLO(VCC
V
LIM_ (VAL
V
LIM_ (VAL
V
= 6V to 28V
LDOIN
0 < I
0 < I
L D OOU T
0 < I
0 < I
L D OOU T
< 10mA 4.85 5.10
LDOOUT
< 100m A 4.65 5.10
< 10mA 1.212 1.275
LDOOUT
< 100m A 1.175 1.275
MIN MAX
1.98 2.02
-0.3 +28.0
160
0.05 0.15
0.05
+14
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
10 ______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, VCC= VDD= ON1 = ON2 = 5V, SKIP = GND, TA= -40°C to +85°C, unless otherwise noted.) (Note 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
High
V
CC
-
Open
REF
Four-Level Input Logic Levels
TON, OVP/UVP, LSAT, SKIP,
FBLANK
Low 0.5
V
Note 1: For the MAX1540, the gate-driver input supply (VDD) is internally connected to the fixed 5V linear-regulator output (LDOOUT),
and the linear-regulator input supply (LDOIN) is internally connected to the battery voltage input (V+).
Note 2: When the inductor is in continuous conduction, the output voltage has a DC regulation level higher than the error-comparator
threshold by 50% of the ripple. In discontinuous conduction (SKIP = GND, light load), the output voltage has a DC regulation
level higher than the trip level by approximately 1.5% due to slope compensation.
Note 3: On-time and off-time specifications are measured from 50% point to 50% point at the DH_ pin with LX_ = GND, VBST_ = 5V,
and a 250pF capacitor connected from DH_ to LX_. Actual in-circuit times may differ due to MOSFET switching speeds.
Note 4: Specifications to -40°C are guaranteed by design, not production tested.
OUT2 EFFICIENCY vs. LOAD CURRENT
(V
OUT2
= 2.5V)
MAX1540 toc01
LOAD CURRENT (A)
EFFICIENCY (%)
10.1
55
60
65
70
75
80
85
90
95
100
50
0.01 10
SKIP = GND
SKIP = V
CC
VIN = 7V
VIN = 12V
VIN = 20V
2.5V OUTPUT VOLTAGE (OUT2)
vs. LOAD CURRENT
MAX1540 toc02
LOAD CURRENT (A)
OUTPUT VOLTAGE (V)
4321
2.49
2.50
2.51
2.52
2.53
2.54
2.55
2.48
05
SKIP = GND
SKIP = V
CC
OUT1 EFFICIENCY vs. LOAD CURRENT
(V
OUT1
= 1.0V)
MAX1540 toc03
LOAD CURRENT (A)
EFFICIENCY (%)
10.1
55
60
65
70
75
80
85
90
95
100
50
0.01 10
SKIP = GND
SKIP = V
CC
VIN = 7V
VIN = 12V
VIN = 20V
Typical Operating Characteristics
(MAX1541 Circuit of Figure 12, V
IN
= 12V, VDD= VCC= 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.)
0.4V
3.15 3.85
1.65 2.35
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 11
)
Typical Operating Characteristics (continued)
(MAX1541 Circuit of Figure 12, V
IN
= 12V, VDD= VCC= 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.)
1.0V OUTPUT VOLTAGE (OUT1)
vs. LOAD CURRENT
1.02
1.01
1.00
OUTPUT VOLTAGE (V)
0.99
0.98
05
LOAD CURRENT (A)
SWITCHING FREQUENCY
vs. INPUT VOLTAGE
450
2.5V OUTPUT
SKIP = V
400
350
300
SWITCHING FREQUENCY (kHz)
250
200
CC
4A LOAD
NO LOAD
028
INPUT VOLTAGE (V)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE
(PULSE-SKIPPING OPERATION)
1.4
SKIP = GND
1.2
ON1 = ON2 = V
1.0
0.8
0.6
SUPPLY CURRENT (mA)
0.4
0.2
0
028
CC
INPUT VOLTAGE (V)
SKIP = GND
SKIP = V
431 2
CC
2420161284
600
500
MAX1540 toc04
400
300
200
SWITCHING FREQUENCY (kHz)
100
0
05
6.0
2.5V OUTPUT
5.8
MAX1540 toc07
5.6
5.4
5.2
5.0
4.8
4.6
4.4
MAXIMUM OUTPUT CURRENT (A)
4.2
4.0
028
2.0V REFERENCE LOAD REGULATION
4
MAX1540 toc10
I
BIAS
I
IN
2420161284
3
2
1
0
-1
-2
REFERENCE VOLTAGE DEVIATION (mV)
-3
-4
-20
OUT2 SWITCHING FREQUENCY
vs. LOAD CURRENT
= 2.5V)
(V
OUT2
SKIP = GND
SKIP = V
CC
4321
LOAD CURRENT (A)
MAXIMUM OUTPUT CURRENT
vs. INPUT VOLTAGE
INPUT VOLTAGE (V
0
REFERENCE LOAD CURRENT (µA)
40
20
80
60
OUT1 SWITCHING FREQUENCY
vs. LOAD CURRENT
= 1.0V)
(V
600
500
MAX1540 toc05
400
300
200
SWITCHING FREQUENCY (kHz)
100
0
05
20
MAX1540 toc08
16
12
8
SUPPLY CURRENT (mA)
4
SKIP = ON1 = ON2 = V
0
242012 1684
MAX1540 toc11
100
028
50
SAMPLE SIZE = 50
40
30
20
SAMPLE PERCENTAGE (%)
10
0
1.990 2.010
OUT1
SKIP = GND
SKIP = V
4321
LOAD CURRENT (A)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE
(FORCED-PWM OPERATION)
I
BIAS
I
IN
CC
INPUT VOLTAGE (V)
REFERENCE DISTRIBUTION
2.0052.0001.995
REFERENCE VOLTAGE (V)
MAX1540 toc06
CC
MAX1540 toc09
2420161284
MAX1540 toc12
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
12 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(MAX1541 Circuit of Figure 12, V
IN
= 12V, VDD= VCC= 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.)
LINEAR-REGULATOR OUTPUT (LDOOUT)
vs. LOAD CURRENT
MAX1540 toc13
LDO LOAD CURRENT (mA)
LDO OUTPUT VOLTAGE (V)
806020 40
3.22
3.24
3.26
3.28
3.30
3.32
3.34
3.36
3.20
0 100
V
LDOIN
= 5V
V
LDOIN
= 12V
STARTUP WAVEFORM
(HEAVY LOAD)
MAX1540 toc14
3.3V
0
2.5V
0
B
D
C
A
400µs/div
4A
2A
0
0
A. ON2, 5V/div
B. INDUCTOR CURRENT,
2A/div
0.5Ω LOAD
C. OUT2, 2V/div
D. PGOOD2, 5V/div
STARTUP WAVEFORM
(LIGHT LOAD)
MAX1540 toc15
3.3V
0
2.5V
0
B
D
C
A
200µs/div
4A
2A
0
0
A. ON2, 5V/div
B. INDUCTOR CURRENT,
2A/div
100Ω LOAD
C. OUT2, 2V/div
D. PGOOD2, 5V/div
SHUTDOWN WAVEFORM
(DISCHARGE MODE DISABLED)
MAX1540 toc16
3.3V
0
5V
0
B
D
C
A
10ms/div
2.5V
0
0
0
A. ON2, 5V/div
B. OUT2, 2V/div
C. INDUCTOR CURRENT,
2A/div
100Ω LOAD, OVP/UVP = REF OR GND
D. DL2, 5V/div
E. PGOOD2, 5V/div
5V
E
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 13
Typical Operating Characteristics (continued)
(MAX1541 Circuit of Figure 12, V
IN
= 12V, VDD= VCC= 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.)
SHUTDOWN WAVEFORM
(DISCHARGE MODE ENABLED)
MAX1540 toc17
3.3V
0
5V
0
B
D
C
A
1ms/div
2.5V
0
0
0
A. ON2, 5V/div
B. OUT2, 2V/div
C. INDUCTOR CURRENT,
2A/div
100Ω LOAD, OVP/UVP = V
CC
OR OPEN
D. DL2, 5V/div
E. PGOOD2, 5V/div
5V
E
2.5V OUTPUT LOAD TRANSIENT
(FORCED PWM)
MAX1540 toc18
4A
0
4A
0
B
D
C
A
40µs/div
2.5V
2.4V
2.6V
A. I
OUT2
= 0 TO 4A, 5A/div
B. V
OUT2
= 2.5V, 100mV/div
SKIP = V
CC
C. INDUCTOR CURRENT, 5A/div
D. LX2, 10V/div
12V
0
2.5V OUTPUT LOAD TRANSIENT
(PULSE SKIPPING)
MAX1540 toc19
4A
0
4A
0
B
D
C
A
40µs/div
2.5V
2.4V
2.6V
A. I
OUT2
= 0.1A TO 4A, 5A/div
B. V
OUT2
= 2.5V, 100mV/div
SKIP = GND
C. INDUCTOR CURRENT, 5A/div
D. LX2, 10V/div
12V
0
LINEAR-REGULATOR
LOAD TRANSIENT
MAX1540 toc20
100mA
0
B
A
100µs/div
3.3V
3.2V
3.4V
A. I
LDOOUT
= 1mA TO 100mA, 50mA/div
B. V
LDOOUT
= 3.3V, 100mV/div
SKIP = GND
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
14 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(MAX1541 Circuit of Figure 12, V
IN
= 12V, VDD= VCC= 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.)
LINEAR-REGULATOR
LINE TRANSIENT
MAX1540 toc21
20V
10V
20V
10V
3.8V
3.3V
2.8V
C
A
B
200µs/div
A. INPUT (V
IN
), 10V/div
B. LDOIN (10V TO 20V), 10V/div
C. LDOOUT (3.3V), 500mV/div
20mA LOAD
OUTPUT OVERLOAD
(UVP DISABLED)
MAX1540 toc22
20A
0
2.5V
10A
B
D
C
A
40µs/div
0
5A
0
5V
A. LOAD (0 TO 150mΩ), 10A/div
B. INDUCTOR CURRENT, 10A/div
OVP/UVP = OPEN OR GND
C. 2.5V OUTPUT, 2V/div
D. PGOOD2, 5V/div
0
OUTPUT OVERLOAD
(UVP ENABLED)
MAX1540 toc23
20A
0
2.5V
10A
B
D
C
A
20µs/div
0
5A
0
5V
A. LOAD (0 TO 150mΩ), 10A/div
B. INDUCTOR CURRENT, 10A/div
C. DL2, 5V/div
OVP/UVP = V
CC
OR REF
D. 2.5V OUTPUT, 2V/div
E. PGOOD2, 5V/div
E
0
5V
INDUCTOR-SATURATION PROTECTION
(LSAT DISABLED)
MAX1540 toc24
0
2.5V
B
D
C
A
20µs/div
5A
7.5A
A. I
OUT2
= 0 TO 5A, 5A/div
B. 2.5V OUTPUT, 200mV/div
LSAT = GND, L = 3.3µH 3.5A
C. ILIM, 100mV/div
D. INDUCTOR CURRENT, 5A/div
0.67V
0
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 15
Typical Operating Characteristics (continued)
(MAX1541 Circuit of Figure 12, V
IN
= 12V, VDD= VCC= 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.)
INDUCTOR-SATURATION PROTECTION
(∆V
ILIM
= 200mV)
MAX1540 toc25
0
2.5V
B
D
C
A
20µs/div
5A
7.5A
A. I
OUT2
= 0 TO 5A, 5A/div
B. 2.5V OUTPUT, 200mV/div
LSAT = REF, L = 3.3µH 3.5A
C. ILIM, 200mV/div
D. INDUCTOR CURRENT, 5A/div
0.67V
0
0.47V
INDUCTOR-SATURATION PROTECTION
(∆V
ILIM
= 400mV)
MAX1540 toc26
0
2.5V
1.5V
B
D
C
A
20µs/div
5A
5A
A. I
OUT2
= 0 TO 5A, 5A/div
B. 2.5V OUTPUT, 1V/div
C. PGOOD, 5V/div
LSAT = REF, L = 3.3µH 3.5A
D. ILIM, 400mV/div
E. INDUCTOR CURRENT, 5A/div
5V
0
0.67V
E
0.27V
MAX1541
DYNAMIC OUTPUT-VOLTAGE TRANSITION
(C
REFIN1
= 100pF)
MAX1540 toc27
-5A
1.5V
B
D
C
A
40µs/div
5A
5A
A. GATE, 5V/div
B. OUT1 (1.0V TO 1.5V), 0.5V/div
C. REFIN1, 0.5V/div
200mA LOAD, SKIP = GND
D. PGOOD1, 5V/div
E. INDUCTOR CURRENT, 5A/div
1.5V
0
1V
E
5V
0
MAX1541
DYNAMIC OUTPUT-VOLTAGE TRANSITION
(C
REFIN1
= 1nF)
MAX1540 toc28
-5A
1.5V
B
D
C
A
100µs/div
5A
5A
A. GATE, 5V/div
B. OUT1 (1.0V TO 1.5V), 0.5V/div
C. REFIN1, 0.5V/div
200mA LOAD, SKIP = GND
D. PGOOD1, 5V/div
E. INDUCTOR CURRENT, 5A/div
1.5V
0
1V
E
5V
0
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
16 ______________________________________________________________________________________
Pin Description
PIN
MAX1540 MAX1541
1 1 OVP/UVP
22SKIP
3 3 LSAT
4 4 TON
55V
NAME FUNCTION
Overvoltage/Undervoltage Protection and Discharge-Mode Control Input. This fourlevel logic input selects between various output fault-protection options (Table 7) by
selectively enabling OVP protection and UVP protection. When enabled, the OVP limit
defaults at 116% of the nominal output voltage, and the UVP limit defaults at 70% of
the nominal output voltage. Discharge mode is enabled when OVP protection is also
enabled. Connect OVP/UVP to the following pins for the desired function:
V
Open = enable OVP and discharge mode, disable UVP.
REF = disable OVP and discharge mode, enable UVP.
GND = disable OVP and discharge mode, disable UVP.
See the Fault Protection and Shutdown and Output Discharge sections.
Pulse-Skipping Control Input. This four-level logic input enables or disables the lightload pulse-skipping operation of each output:
V
Open = OUT1 in forced-PWM mode, OUT2 in pulse-skipping mode.
REF = OUT1 in pulse-skipping mode, OUT2 in forced-PWM mode.
GND = OUT1 and OUT2 in pulse-skipping mode.
Inductor-Saturation Control Input. This four-level logic input sets the inductor-current
saturation limit as a multiple of the valley current-limit threshold set by ILIM, or
disables the function if not required. Connect LSAT to the following pins to set the
saturation current limit:
VCC = 2 x I
Open = 1.75 x I
GND = disable LSAT protection
See the Inductor Saturation Limit and Setting the Current Limit sections.
On-Time Selection Control Input. This four-level logic input sets the K-factor value
used to determine the DH_ on-time (see the On-Time One-Shot section). Connect to
analog ground (GND), REF, or V
nominal switching frequencies:
V
Open = 345kHz (OUT1) / 255kHz (OUT2)
REF = 485kHz (OUT1) / 355kHz (OUT2)
GND = 620kHz (OUT1) / 460kHz (OUT2)
Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through
CC
a series 20Ω resistor. Bypass V
capacitor.
= enable OVP and discharge mode, enable UVP.
CC
= OUT1 and OUT2 in forced-PWM mode.
CC
LIM(VAL)
REF = 1.5 x I
= 235kHz (OUT1) / 170kHz (OUT2)
CC
LIM(VAL)
LIM(VAL)
; or leave TON unconnected to select the following
CC
to analog ground with a 1µF or greater ceramic
CC
Buffered N-Channel MOSFET Gate Input. A logic low on GATE turns off the internal
— 6 GATE
— 7 CC1
MOSFET so OD appears as high impedance. A logic high on GATE turns on the
internal MOSFET, pulling OD to ground.
Integrator Capacitor Connection for Controller 1. Connect a 47pF to 470pF (47pF typ)
capacitor from CC1 to analog ground (GND) to set the integration time constant for
the main MAX1541 controller (OUT1).
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 17
Pin Description (continued)
PIN
MAX1540 MAX1541
6 8 ILIM1
7 9 ILIM2
8 10 REF
— 11 REFIN1
— 12 OD Open-Drain Output. Controlled by GATE.
9 13 CSP2
NAME FUNCTION
Valley Current-Limit Threshold Adjustment for Controller 1. The valley current-limit
threshold defaults to 50mV if ILIM1 is tied to V
current-limit threshold across CSP1 and CSN1 is precisely 1/10 the voltage seen at
ILIM1 over a 250mV to 2.5V range. The logic threshold for switchover to the 50mV
default value is approximately V
threshold is exceeded, ILIM1 sinks 6µA. See the Current-Limit Protection section.
Valley Current-Limit Threshold Adjustment for Controller 2. The valley current-limit
threshold defaults to 50mV if ILIM2 is tied to V
current-limit threshold across CSP2 and CSN2 is precisely 1/10th the voltage seen at
ILIM2 over a 250mV to 2.5V range. The logic threshold for switchover to the 50mV
default value is approximately V
threshold is exceeded, ILIM2 sinks 6µA. See the Current-Limit Protection section.
2.0V Reference Voltage Output. Bypass REF to analog ground with a 0.1µF or greater
ceramic capacitor. The reference can source up to 50µA for external loads. Loading
REF degrades output voltage accuracy according to the REF load-regulation error.
The reference is disabled when the MAX1540/MAX1541 are shut down.
External Reference Input for Controller 1. REFIN1 sets the main feedback regulation
voltage (V
Positive Current-Sense Input for Controller 2. Connect to the positive terminal of the
current-sense element. Figure 14 and Table 9 describe several current-sensing
options. The PWM controller does not begin a cycle unless the current sensed is less
than the valley current-limit threshold programmed at ILIM2.
FB1
= V
) of the MAX1541.
REFIN1
. In adjustable mode, the valley
CC
- 1V. When the inductor-saturation protection
CC
. In adjustable mode, the valley
CC
- 1V. When the inductor-saturation protection
CC
10 14 CSN2
11 15 FB2
12 16 OUT2
Negative Current-Sense Input for Controller 2. Connect to the negative terminal of the
current-sense element. Figure 14 and Table 9 describe several current-sensing
options. The PWM controller does not begin a cycle unless the current sensed is less
than the valley current-limit threshold programmed at ILIM2.
Feedback Input for Controller 2:
M AX 1540: C onnect to V
+ 2.5V fi xed outp ut. For an ad j ustab l e outp ut ( 0.7V to 5.5V ) , connect FB2 to a r esi sti ve
d i vi d er fr om OU T2. The FB2 r eg ul ati on l evel i s + 0.7V .
M AX 1541: C onnect to V
+ 2.5V fi xed outp ut. For an ad j ustab l e outp ut ( 0.7V to 5.5V ) , connect FB2 to a r esi sti ve
d i vi d er fr om OU T2. The FB2 r eg ul ati on l evel i s + 0.7V .
Output Voltage-Sense Connection for Controller 2. Connect directly to the positive
terminal of the output capacitors as shown in the standard application circuits
(Figures 1 and 12). OUT2 senses the output voltage to determine the on-time for the
high-side switching MOSFET. OUT2 also serves as the feedback input when using
the preset internal output voltages as shown in Figure 10. When discharge mode is
enabled by OVP/UVP, the output capacitor is discharged through an internal 10Ω
resistor connected between OUT2 and ground.
for a + 1.5V fi xed outp ut or to anal og g r ound ( G N D ) for a
C C
for a + 1.8V fi xed outp ut or to anal og g r ound ( G N D ) for a
C C
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
18 ______________________________________________________________________________________
Pin Description (continued)
PIN
MAX1540 MAX1541
13 17 PGOOD2
14 18 DH2 High-Side Gate-Driver Output for Controller 2. DH2 swings from LX2 to BST2.
15 19 LX2
16 20 BST2
17 21 GND Analog and Power Ground. Connect backside pad to GND.
18 22 DL2
19 23 V+
— 24 LDOIN
— 25 V
NAME FUNCTION
Open-Drain Power-Good Output. PGOOD2 is low when the output voltage is more
than 10% (typ) above or below the normal regulation point, during soft-start, and in
shutdown. After the soft-start circuit has terminated, PGOOD2 becomes high
impedance if the output is in regulation.
Inductor Connection for Controller 2. Connect to the switched side of the inductor.
LX2 serves as the lower supply rail for the DH2 high-side gate driver.
Boost Flying-Capacitor Connection for Controller 2. Connect to an external capacitor
and diode as shown in Figure 8. An optional resistor in series with BST2 allows the
DH2 pullup current to be adjusted.
Low-Side Gate-Driver Output for Controller 2. DL2 swings from GND to LDOOUT
(MAX1540) or GND to V
Battery Voltage Input. The controller uses V+ to set the on-time one-shot timing. The
DH on-time is inversely proportional to input voltage over a range of 2V to 28V. For
the MAX1540, V+ also serves as the linear-regulator input supply.
Internal Linear-Regulator Input Supply. Connect to V+ or a voltage source from 4.5V
to 28V through a 1Ω resistor. Bypass LDOIN to GND with a 4.7µF or greater
capacitor. For the MAX1540, LDOIN is internally connected to V+.
MAX1541 Supply Voltage Input for the DL_ Gate Driver. Connect to the system
DD
supply voltage (+4.5V to +5.5V). Bypass V
ceramic capacitor. For the MAX1540, LDOOUT supplies the DL_ gate drivers
(V
= LDOOUT).
DD
(MAX1541).
DD
to power ground with a 1µF or greater
DD
Linear Regulator Output. Bypass LDOOUT with a 1µF or greater capacitor per 5mA of
20 26 LDOOUT
— 27 FBLDO
21 28 DL1
22 29 LDOON
23 30 BST1
load (internal and external), with a minimum of 4.7µF. For the MAX1540, LDOOUT
powers the DL_ gate drivers (V
Feedback Input for the Linear Regulator. Connect to GND for a fixed 5V output. For
an adjustable output (1.25V to V
divider from LDOOUT to analog ground (GND). The FBLDO regulation voltage is
+1.25V. For the MAX1540, FBLDO is internally connected to GND for a fixed 5V
output.
Low-Side Gate-Driver Output for Controller 1. DL1 swings from GND to LDOOUT
(MAX1540) or GND to V
Linear-Regulator Enable Input. For automatic startup, connect to V+ or LDOIN
(MAX1541). Connect to GND to shut down the linear regulator.
Boost Flying-Capacitor Connection for Controller 1. Connect to an external capacitor
and diode as shown in Figure 8. An optional resistor in series with BST1 allows the
DH1 pullup current to be adjusted.
DD
internally connected to LDOOUT).
DD
- 0.6V), connect FBLDO to a resistive voltage-
LDOIN
(MAX1541).
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 19
Pin Description (continued)
PIN
MAX1540 MAX1541
24 31 LX1
25 32 DH1 High-Side Gate-Driver Output for Controller 1. DH1 swings from LX1 to BST1.
26 33 PGOOD1
27 34 OUT1
28 35 FB1
29 36 CSN1
NAME FUNCTION
Inductor Connection for Controller 1. Connect to the switched side of the inductor.
LX1 serves as the lower supply rail for the DH1 high-side gate driver.
Open-Drain Power-Good Output. PGOOD1 is low when the output voltage is more
than 10% (typ) above or below the normal regulation point, during soft-start, and in
shutdown. After the soft-start circuit has terminated, PGOOD1 becomes high
impedance if the output is in regulation. For the MAX1541, PGOOD1 is
blanked—forced high-impedance state—when FBLANK is enabled and the controller
detects a transition on GATE.
Output Voltage-Sense Connection for Controller 1. Connect directly to the positive
terminal of the output capacitors as shown in the standard application circuits
(Figures 1 and 12). OUT1 senses the output voltage to determine the on-time for the
high-side switching MOSFET. For the MAX1540, OUT1 also serves as the feedback
input when using the preset internal output voltages as shown in Figure 10. When
discharge mode is enabled by OVP/UVP, the output capacitor is discharged through
an internal 10Ω resistor connected between OUT1 and ground.
Feedback Input for Controller 1:
M AX 1540: C onnect to V
+ 1.8V fi xed outp ut. For an ad j ustab l e outp ut ( 0.7V to 5.5V ) , connect FB1 to a r esi sti ve
d i vi d er fr om OU T1. The FB1 r eg ul ati on l evel i s + 0.7V .
M AX 1541: The FB1 r eg ul ati on l evel i s set b y the vol tag e at RE FIN 1.
Negative Current-Sense Input for Controller 1. Connect to the negative terminal of the
current-sense element. Figure 14 and Table 9 describe several current-sensing
options. The PWM controller does not begin a cycle unless the current sensed is less
than the valley current-limit threshold programmed at ILIM1.
for a + 1.2V fi xed outp ut or to anal og g r ound ( G N D ) for a
C C
30 37 CSP1
— 38 FBLANK
Positive Current-Sense Input for Controller 1. Connect to the positive terminal of the
current-sense element. Figure 14 and Table 9 describe several current-sensing
options. The PWM controller does not begin a cycle unless the current sensed is less
than the valley current-limit threshold programmed at ILIM1.
Fault-Blanking Control Input. This four-level logic input enables or disables fault
blanking, and sets the forced-PWM operation time (t
enabled, PGOOD1 and the OVP/UVP protection for controller 1 are blanked for the
selected time period after the MAX1541 detects a transition on GATE. Additionally,
controller 1 enters forced-PWM mode for the duration of t
changes states. Connect FBLANK as follows:
V
= 220µs t
CC
Open = 140µs t
REF = 65µs t
GND = 140µs t
See the Electrical Characteristics table for the t
FBLANK
, fault blanking enabled.
FBLANK
, fault blanking enabled.
FBLANK
, fault blanking enabled.
, fault blanking disabled.
FBLANK
FBLANK
). When fault blanking is
FBLANK
anytime GATE
FBLANK
limits.
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
20 ______________________________________________________________________________________
Pin Description (continued)
Table 1. Component Selection for Standard Applications
PIN
MAX1540 MAX1541
31 39 ON2
32 40 ON1
NAME FUNCTION
OUT2 Enable Input. Pull ON2 to GND to shut down controller 2 (OUT2). Connect to
V
for normal operation. When discharge mode is enabled by OVP/UVP, the output
CC
is discharged through a 10Ω resistor between OUT2 and GND, and DL2 is forced
high after V
OUT2 remains a high-impedance input and DL2 is forced low so LX2 also appears as
a high impedance. A rising edge on ON1 or ON2 clears the fault-protection latch.
OUT1 Enable Input. Pull ON1 to GND to shut down controller 1 (OUT1). Connect to
for normal operation. When discharge mode is enabled by OVP/UVP, the output
V
CC
is discharged through a 10Ω resistor between OUT1 and GND, and DL1 is forced
high after V
OUT1 remains a high-impedance input and DL1 is forced low so LX1 also appears as
high impedance. A rising edge on ON1 or ON2 clears the fault-protection latch.
drops below 0.3V. When discharge mode is disabled by OVP/UVP,
OUT2
drops below 0.3V. When discharge mode is disabled by OVP/UVP,
OUT1
COMPONENT
Input Voltage (VIN) 7V to 24V 7V to 24V 7V to 24V 7V to 24V
Output Voltage (V
Load Current (I
S w i tchi ng Fr eq uency
_)
( f
S W
Input Capacitor (CIN)
_) 1.8V 2.5V 1.0V/1.5V 2.5V
OUT
_) 4A 8A 4A 4A
OUT
PWM1 PWM2 PWM1 PWM2
TON = REF (485kHz) TON = REF (355kHz) TON = REF (485kHz) TON = REF (355kHz)
Taiyo Yuden TMK432BJ106KM
MAX1540 MAX1541
(2) 10µF, 25V
Taiyo Yuden TMK325BJ475KM
(2) 4.7µF, 25V
Output Capacitor
_)
(C
OUT
High-Side MOSFET
(N
_)
H
Low-Side MOSFET
(N
_)
L
Low-Side Schottky
_)
(D
L
(if needed)
Inductor (L_)
R
SENSE_
220µF, 6.3V, 12mΩ
Sanyo POSCAP
6TPD220M
35mΩ, 30V
Fairchild 1/2 FDS6982S
22mΩ, 30V
Fairchild 1/2 FDS6982S
1A, 30V Schottky
Nihon EP10QS03L
2.5µH, 6.2A, 15mΩ
Sumida
CDEP105(H)-2R5
15mΩ ±1%, 0.5W
IRC LR2010-01-R015F
or Dale WSL-2010-R015F
330µF, 4V, 12mΩ
Sanyo POSCAP
4TPD330M
20mΩ, 30V
Fairchild FDS6690
12.5mΩ, 30V
Fairchild FDS6670S
1A, 30V Schottky
Nihon EP10QS03L
2.2µH, 10A, 4.4mΩ
Sumida
CDEP105(L)-2R2
5mΩ ±1%, 0.5W
IRC LR2010-01-R005F
or Dale WSL-2010-R005F
470µF, 4V, 10mΩ
Sanyo POSCAP
4TPD470M
35mΩ, 30V
Fairchild 1/2 FDS6982S
22mΩ, 30V
Fairchild 1/2 FDS6982S
1A, 30V Schottky
Nihon EP10QS03L
1.8µH, 9.0A, 6.2mΩ
Sumida
CDEP105(S)-1R8
15mΩ ±1%, 0.5W
IRC LR2010-01-R015F
or Dale WSL-2010-R015F
Fairchild 1/2 FDS6982S
Fairchild 1/2 FDS6982S
4.3µH, 6.8A, 8.7mΩ
IRC LR2010-01-R015F
or Dale WSL-2010-R015F
220µF, 6.3V, 12mΩ
Sanyo POSCAP
6TPD220M
35mΩ, 30V
22mΩ, 30V
1A, 30V Schottky
Nihon EP10QS03L
Sumida
CDEP105(L)-4R3
15mΩ ±1%, 0.5W
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 21
Figure 1. MAX1540 Standard Application Circuit
+5V BIAS
OUTPUT 1
1.8V, 4A (MAX)
SUPPLY
2.5µH
R
15mΩ
)*
INPUT (V
IN
7V TO 20V
C
C1
22µF
LDOOUT
D
BST
N
H1
C
BST1
0.1µF
N
D
L1
L1
CS1
C
OUT1
220µF
L1
MAX1540
DH1
BST1
LX1
DL1
CSP1
CSN1
OUT1
FB1
SKIP
DH2
BST2
DL2
GND
CSP2
CSN2
OUT2
OVP/UVP
LX2
FB2
V+
D
BST
N
H2
C
BST2
0.1µF
N
L2
IN
(2) 10µF
D
L2
L2
2.2µH
R
CS2
5mΩ
OUTPUT 2
2.5V, 8A (MAX)
C
OUT2
330µF
C
REF
(485kHz/355kHz)
0.22µF
R2
C3
100kΩ
470pF
R3
49.9kΩ
C4
200kΩ
470pF
49.9kΩ
POWER GROUND
ANALOG GROUND
*LOWER INPUT VOLTAGES REQUIRE
ADDITIONAL INPUT CAPACITANCE.
REF
TON
REF
ILIM1
R4
ILIM2
R5
LSAT
LDOON
ON1
ON2
V
PGOOD1
PGOOD2
CC
C2
1µF
OPEN (I
R1
20Ω
100kΩ
x 1.75)
LIM(VAL)
ON
OFF
+5V BIAS
SUPPLY
R6
SEE TABLE 1 FOR COMPONENT SPECIFICATIONS.
R7
100kΩ
POWER-GOOD
MAX1540/MAX1541
Standard Application Circuits
The MAX1540 Standard Application Circuit (Figure 1)
generates a 1.8V and 2.5V rail for general-purpose use
in a notebook computer. The MAX1541 Standard
Application Circuit (Figure 12) generates a dynamically
adjustable output voltage (OUT1), typical of a graphicsprocessor core requirement, and a fixed 2.5V output
(OUT2).
See Table 1 for component selections. Table 2 lists the
component manufacturers.
Detailed Description
The MAX1540/MAX1541 provide three independent outputs with independent enable controls. They contain two
Quick-PWM step-down controllers ideal for low-voltage
power supplies for notebook computers, and a 100mA
linear regulator. Maxim’s proprietary Quick-PWM pulsewidth modulators in the MAX1540/ MAX1541 are specifically designed for handling fast load steps while
maintaining a relatively constant operating frequency and
inductor operating point over a wide range of input voltages. The Quick-PWM architecture circumvents the poor
load-transient timing problems of fixed-frequency currentmode PWMs, while also avoiding the problems caused
by widely varying switching frequencies in conventional
constant-on-time and constant-off-time PWM schemes.
The MAX1540 linear regulator draws power from the
battery voltage and generates a preset 5V, which can
be used to bootstrap the buck controllers for automatic
startup. The MAX1541’s linear regulator can be connected to any input source from 4.5V to 28V to generate an adjustable output voltage as low as 1.25V, or as
high as the input source with 600mV of dropout.
Single-stage buck conversion allows the MAX1540/
MAX1541 to directly step down high-voltage batteries
for the highest possible efficiency. Alternatively, twostage conversion (stepping down from another system
supply rail instead of the battery at a higher switching
frequency) allows the minimum possible physical size.
The MAX1540 generates chipset, dynamic randomaccess memory (DRAM), CPU I/O, or other low-voltage
supplies down to 0.7V. The MAX1541 powers chipsets
and graphics processor cores that require dynamically
adjustable output voltages, or generates the active termination bus that must track the input reference. The
MAX1540 is available in a 32-pin thin QFN package
with optional inductor-saturation protection and overvoltage/undervoltage protection. The MAX1541 is available in a 40-pin thin QFN package with optional
inductor-saturation protection and overvoltage/undervoltage protection.
+5V Bias Supply (VCCand VDD)
The MAX1540/MAX1541 require a 5V bias supply in
addition to the battery. This 5V bias supply is either the
MAX1540/MAX1541s’ internal linear regulator or the
notebook’s 95%-efficient 5V system supply. Keeping the
bias supply external to the IC can improve efficiency
and allows the fixed 5V or adjustable linear regulator
(MAX1541) to be used for other applications. For the
MAX1540, the gate-driver input supply (VDD) is connected internally to the fixed 5V linear-regulator output
(LDOOUT).
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
22 ______________________________________________________________________________________
Table 2. Component Suppliers
SUPPLIER PHONE WEBSITE
Central
Semiconductor
Coilcraft
Fairchild
Semiconductor
International
Rectifier
Kemet
Panasonic
Sanyo
Siliconix
(Vishay)
Sumida
Taiyo Yuden
TDK
TOKO
631-435-1110
(USA)
800-322-2645
(USA)
888-522-5372
(USA)
310-322-3331
(USA)
408-986-0424
(USA)
65-6231-3226
(Singapore),
408-749-9714
(USA)
619-661-6835
(USA)
203-268-6261
(USA)
408-982-9660
(USA)
03-3667-3408
(Japan),
408-573-4150
(USA)
847-803-6100
(USA),
81-3-5201-7241
(Japan)
858-675-8013
(USA)
www.centralsemi.com
www.coilcraft.com
www.fairchildsemi.com
www.irf.com
www.kemet.com
www.panasonic.com
www.sanyovideo.com
www.vishay.com
www.sumida.com
www.t-yuden.com
www.component.tdk.com
www.tokoam.com
The 5V bias supply must provide VCC(PWM controller)
and VDD(gate-drive power), so the maximum current
drawn is:
I
BIAS
= ICC+ fSW(Q
G(LOW)
+ Q
G(HIGH)
)
= 4mA to 50mA (typ)
where ICCis 1.1mA (typ), fSWis the switching frequency,
and Q
G(LOW)
and Q
G(HIGH)
are the MOSFET data
sheet’s total gate-charge specification limits at V
GS
= 5V.
The V+ battery input and 5V bias inputs (V
CC
and VDD)
can be connected together if the input source is a fixed
4.5V to 5.5V supply. If the 5V bias supply powers up
prior to the battery supply, the enable signals (ON1 and
ON2 going from low to high) must be delayed until the
battery voltage is present in order to ensure startup.
Free-Running, Constant On-Time, PWM
Controller with Input Feed Forward
The Quick-PWM control architecture is a pseudofixedfrequency, constant on-time, current-mode regulator
with voltage feed forward (Figure 2). This architecture
relies on the output filter capacitor’s ESR to act as a
current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The Quick-PWM algorithm
is simple: the high-side switch on-time relies solely on
an adjustable one-shot whose pulse width is inversely
proportional to input voltage and directly proportional to
output voltage. Another one-shot sets a fixed minimum
off-time (400ns typ). The controller triggers the on-time
one-shot when the error comparator is low, the inductor
current is below the valley current-limit threshold, and
the minimum off-time one-shot has timed out.
On-Time One-Shot (TON)
The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to the battery and output voltages. The highside switch on-time is inversely proportional to the battery voltage as measured by the V+ input (VIN= V+),
and proportional to the output voltage as measured by
the OUT_ input:
where K (switching period) is set by the TON pin-strap
connection (Table 3). This algorithm results in a nearly
constant switching frequency despite the lack of a fixedfrequency clock generator. The benefits of a constant
switching frequency are twofold: 1) the frequency can
be selected to avoid noise-sensitive regions such as the
455kHz IF band and 2) the inductor ripple-current operating point remains relatively constant, resulting in easy
design methodology and predictable output voltage ripple. The on-time for the main controller (DH1) is set 15%
higher than the nominal frequency setting (200kHz,
300kHz, 420kHz, or 540kHz), while the on-time for the
secondary controller (DH2) is set 15% lower than the
nominal setting. This prevents audio-frequency “beating” between the two asynchronous regulators.
The on-time one-shot has good accuracy at the operating points specified in the Electrical Characteristics
(approximately ±12.5% at 540kHz and 420kHz nominal
settings, and ±10% with the 300kHz and 200kHz settings). On-times at operating points far removed from
the conditions specified in the Electrical Characteristics
can vary over a wider range.
The constant on-time translates only roughly to a constant
switching frequency. The on-times guaranteed in the
Electrical Characteristics are influenced by resistive losses and by switching delays in the high-side MOSFET.
Resistive losses—including the inductor, both MOSFETs,
and PC board copper losses in the output and ground—
tend to raise the switching frequency as the load increases. The dead-time effect increases the effective on-time,
reducing the switching frequency as one or both dead
times add to the effective on-time. It occurs only in PWM
mode (SKIP = V
CC
) and during dynamic output-voltage
transitions when the inductor current reverses at light- or
negative-load currents. With reversed inductor current,
the inductor’s EMF causes LX_ to go high earlier than
normal, extending the on-time by a period equal to the
driver dead time.
For loads above the critical conduction point, where the
dead-time effect no longer occurs, the actual switching
frequency is:
where V
DROP1
is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; V
DROP2
is
the sum of the resistances in the charging path, including the high-side switch, inductor, and PC board resistances; and tONis the on-time calculated by the
MAX1540/MAX1541.
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 23
On- Time
=
K
V
OUT
V
IN
f
SW
V+V
=
tV+V -V
OUT_ DROP1
()
ON IN DROP1 DROP2
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
24 ______________________________________________________________________________________
Figure 2. MAX1540/MAX1541 Functional Diagram
*V+
TON
SKIP
MAX1540/MAX1541
LSAT
ILIM1
CSP1
CSN1
VALLEY
CURRENT
BST1
DH1
LX1
*V
DD
GND
**CC1
**REFIN1
OUT1
DL1
FB1
INTERNAL
MAX1540/MAX1541
OPTION
LIMIT
CROSSING
INT FB1
CURRENT
LIMIT 1
(FIGURE 5)
ZERO
SATURATION
PWM
CONTROLLER 1
(FIGURE 3)
INT REF1
LIMIT
FB1 DECODE
(FIGURE 10)
FAULT1
FAULT2
SATURATION
LIMIT
INT FB2
FB2 DECODE
(FIGURE 10)
CURRENT
LIMIT 2
(FIGURE 5)
ZERO
CROSSING
PWM
CONTROLLER 2
(FIGURE 3)
INT REF2
VALLEY
CURRENT
LIMIT
0.7V
ILIM2
CSP2
CSN2
BST2
DH2
LX2
*V
DD
DL2
GND
REF
2.0V
V
REF
13R
7R
CC
FB2
OUT2
ON1
PGOOD1
**FBLANK
**OD
**GATE
*FOR THE MAX1540:
LDOIN IS CONNECTED TO V+.
LDOOUT IS CONNECTED TO V
**MAX1541 CONTROLLER ONLY.
POWER-GOOD AND
FAULT PROTECTION 1
(FIGURE 9)
QUAD-LEVEL
DECODE AND
TIMER
MAX1541
CONTROLLER 1
ONLY
.
DD
BLANK
POWER-GOOD AND
FAULT PROTECTION 2
(FIGURE 9)
ENABLE OVP
ENABLE UVP
LINEAR REGULATOR
QUAD-LEVEL
DECODE
(FIGURE 13)
ON2
PGOOD2
OVP/UVP
*LDOIN
*LDOOUT
**FBLDO
LDOON
Light-Load Operation (
SSKKIIPP
)
The four-level SKIP input selects light-load, pulse-skipping operation by independently enabling or disabling
the zero-crossing comparator for each controller (Table
4). When the zero-crossing comparator is enabled, the
controller forces DL_ low when the current-sense inputs
detect zero inductor current. This keeps the inductor
from discharging the output capacitors and forces the
controller to skip pulses under light-load conditions to
avoid overcharging the output. When the zero-crossing
comparator is disabled, the controller maintains PWM
operation under light-load conditions (see the Forced-
PWM Mode section).
Automatic Pulse-Skipping Mode
In skip mode, an inherent automatic switchover to PFM
takes place at light loads (Figure 3). This switchover is
affected by a comparator that truncates the low-side
switch on-time at the inductor current’s zero crossing.
The zero-crossing comparator differentially senses the
inductor current across the current-sense inputs (CSP_
to CSN_). Once V
CSP_
- V
CSN_
drops below 5% of the
current-limit threshold (2.5mV for the default 50mV current-limit threshold), the comparator forces DL_ low
(Figure 3). This mechanism causes the threshold
between pulse-skipping PFM and nonskipping PWM
operation to coincide with the boundary between continuous and discontinuous inductor-current operation
(also known as the “critical-conduction” point). The
load-current level at which PFM/PWM crossover
occurs, I
LOAD(SKIP)
, is equal to half the peak-to-peak
ripple current, which is a function of the inductor value
(Figure 4). This threshold is relatively constant, with
only a minor dependence on battery voltage:
where K is the on-time scale factor (Table 3). For example, in the MAX1541 Standard Application Circuit
(Figure 12) (K = 3.0µs, V
OUT2
= 2.5V, VIN= 12V, and L
= 4.3µH), the pulse-skipping switchover occurs at:
The crossover point occurs at an even lower value if a
swinging (soft-saturation) inductor is used. The switching waveforms may appear noisy and asynchronous
when light loading causes pulse-skipping operation,
but this is a normal operating condition that results in
high light-load efficiency. Trade-offs in PFM noise vs.
light-load efficiency are made by varying the inductor
value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in
higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple.
Penalties for using higher inductor values include larger
physical size and degraded load-transient response
(especially at low input-voltage levels).
DC-output accuracy specifications refer to the threshold of the error comparator. When the inductor is in
continuous conduction, the MAX1540/MAX1541 regulate the valley of the output ripple, so the actual DC output voltage is higher than the trip level by 50% of the
output ripple voltage. In discontinuous conduction
(I
OUT
< I
LOAD(SKIP)
), the output voltage has a DC regulation level higher than the error-comparator threshold
by approximately 1.5% due to slope compensation.
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 25
Table 3. Approximate K-Factor Errors
*See the Step-Down Converter Dropout Performance section (h = 1.5 and worst-case K-factor value used).
Table 4. SKIP Configuration Table
NOMINAL TON
SETTING (kHz)
200kHz (TON = VCC) ±10 4.5 (235kHz) 2.28 6.2 (170kHz) 2.96
300kHz (TON = open) ±10 3.0 (345kHz) 2.52 4.1 (255kHz) 3.18
420kHz (TON = REF) ±12.5 2.2 (485kHz) 2.91 3.0 (355kHz) 3.48
540kHz (TON = GND) ±12.5 1.7 (620kHz) 3.42 2.3 (460kHz) 3.87
SKIP OUT1 MODE OUT2 MODE
V
CC
Open Forced PWM Pulse skipping
REF Pulse skipping Forced PWM
GND Pulse skipping Pulse skipping
K-FACTOR
ERROR (%)
Forced PWM Forced PWM
CONTROLLER 1 (OUT1) CONTROLLER 2 (OUT2)
TYPICAL
K-FACTOR
(µs)
MINIMUM V
V
= 1.8V*
OUT1
(V)
AT
IN
TYPICAL
K-FACTOR
(µs)
I
LOAD(SKIP)
VK2LV-V
≈
OUT IN OUT
MINIMUM V
V
OUT2
V
IN
2.5V 3 s
2 4.3 H
×
.
×
µ
µ
12V -2.5V
12V
=0069
.
IN
= 2.5V*
(V)
A
AT
MAX1540/MAX1541
Forced-PWM Mode
The low-noise forced-PWM mode disables the zerocrossing comparator, which controls the low-side
switch on-time. This forces the low-side gate-drive
waveform to be constantly the complement of the highside gate-drive waveform, so the inductor current
reverses at light loads while DH_ maintains a duty factor of V
OUT_
/ VIN. The benefit of forced-PWM mode is
to keep the switching frequency fairly constant.
However, forced-PWM operation comes at a cost: the
no-load 5V bias current remains between 4mA to
40mA, depending on the external MOSFETs and
switching frequency.
Forced-PWM mode is most useful for reducing audiofrequency noise, improving load-transient response,
and providing sink-current capability for dynamic output-voltage adjustment. The MAX1541 uses forcedPWM operation during all dynamic output-voltage
transitions (GATE transition detected) in order to ensure
fast, accurate transitions. Since forced-PWM operation
disables the zero-crossing comparator, the inductor
current reverses under light loads, quickly discharging
the output capacitors. FBLANK determines how long
the MAX1541 maintains forced-PWM operation—typically 220µs (FBLANK = V
CC
), 140µs (FBLANK = open
or GND), or 65µs (FBLANK = REF).
Current-Limit Protection (ILIM_)
Valley Current Limit
The current-limit circuit employs a unique “valley” current-sensing algorithm that uses a current-sense resistor
between CSP_ and CSN_ as the current-sensing element (Figure 1). If the magnitude of the current-sense
signal is above the valley current-limit threshold, the
PWM controller is not allowed to initiate a new cycle
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
26 ______________________________________________________________________________________
Figure 3. MAX1540/MAX1541 PWM-Controller Functional Diagram
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
*MAIN MAX1541
CONTROLLER (OUT1) ONLY
Q
t
OFF(MIN)
1-SHOT
SLOPE COMP
TRIG
INT FB_
INT REF_
CC1
CC1
= 80
G
m
R
A
V
7R
ERROR
AMP
VALLEY CURRENT
LIMIT
SATURATION
LIMIT
TON
OUT_
V+
∆I
V
- V
IN
OUT
=
∆t
INDUCTOR CURRENT
L
ON-TIME0 TIME
I
PEAK
I
LOAD
= I
PEAK
/2
Q
1-SHOT
ON-TIME
COMPUTE
S
Q DH DRIVER
R
t
ON
TRIG
S
Q
R
DL DRIVER
FAULT
PROTECTION
ZERO
CROSSING
(Figures 3 and 5). The actual peak current is greater
than the valley current-limit threshold by an amount
equal to the inductor ripple current. Therefore, the exact
current-limit characteristic and maximum load capability
are a function of the current-sense resistance, inductor
value, and battery voltage. When combined with the
undervoltage protection circuit, this current-limit method
is effective in almost every circumstance. Figure 6
shows the valley current-limit threshold point.
In forced-PWM mode, the MAX1540/MAX1541 also
implement a negative current limit to prevent excessive
reverse inductor currents when V
OUT
is sinking current.
The negative current-limit threshold is set to approximately 120% of the positive current limit and tracks the
positive current limit when ILIM is adjusted.
The current-limit threshold is adjusted with an external
resistor-divider at ILIM_. A 2µA to 20µA divider current
is recommended for accuracy and noise immunity. The
current-limit threshold adjustment range is from 25mV
to 200mV. In the adjustable mode, the current-limit
threshold voltage is precisely 1/10th the voltage seen at
ILIM_. The threshold defaults to 50mV when ILIM_ is
connected to V
CC
. The logic threshold for switchover to
the 50mV default value is approximately VCC- 1V.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the differential current-sense signals seen by CSP_ and
CSN_. Place the IC close to the sense resistor with
short, direct traces, making a Kelvin-sense connection
to the current-sense resistor.
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 27
Figure 5. MAX1540/MAX1541 Current-Limit Functional Diagram
Figure 6. Valley Current-Limit Threshold Point
SATURATION
LIMIT
DH DRIVER
S
VALLEY CURRENT
LIMIT
ZERO
CROSSING
Q
R
QUAD-LEVEL
DECODE
9R
R
0.5V
INDUCTOR CURRENT
0 TIME
I
LIM(VAL)
LSAT
- 1.0V
V
CC
ILIM_
6µA
CSP_
CSN_
SKIP
I
PEAK
I
LOAD
I
LIMIT
= I
LOAD(MAX)
LIR
1-
()
2
MAX1540/MAX1541
Inductor-Saturation Limit
The LSAT connection selects an upper current-sense
limit as the inductor-saturation threshold, or disables
the inductor-saturation protection feature altogether
(LSAT = GND). When enabled, the inductor-saturation
threshold is a multiple of the positive valley current-limit
threshold (Table 5) and tracks the valley current limit
when ILIM is adjusted. The selected inductor-saturation
threshold should give sufficient headroom above the
peak inductor current so switching noise does not accidentally trip the saturation protection. Selecting an
excessively high threshold may allow inductor saturation to go undetected. For an inductor with a low LIR
(the ratio of the inductor ripple current to the designed
maximum load current) near 20%, select the lowest saturation threshold of 1.5 x I
LIM(VAL)
(LSAT = REF). When
using an inductor with a higher LIR, increase the inductor-saturation threshold accordingly.
When inductor-saturation protection is enabled, the
MAX1540/MAX1541 continuously monitor the inductor
current through the voltage across the current-sense
resistor. When the inductor-saturation threshold is
exceeded, the MAX1540/MAX1541 immediately turn off
the high-side gate driver and enable a 6µA discharge
current on ILIM_ (Figure 7) at the beginning of the next
DH_ on-time. This reduces the voltage on ILIM_ by
∆V
ILIM
where:
where the ILIM saturation fault sink current (I
ILIM(LSAT)
)
is typically 6µA (see the Electrical Characteristics
table). When using the default 50mV valley current-limit
threshold (ILIM_ = VCC), the ILIM_ saturation fault sink
current does not lower the current-limit threshold
(Figure 5).
If the inductor current remains below the saturation
threshold during the next cycle, the controller disables
the ILIM_ discharge current, allowing the ILIM_ voltage
to return to its nominal set point. The inductor should
not remain in saturation once the controller reduces the
valley current limit. If the inductor remains saturated,
the output voltage may drop low enough to trip the
undervoltage fault protection (UVP enabled), causing
the MAX1540/MAX1541 to set the fault latch and shut
down both outputs. Adding a capacitor from ILIM_ to
GND slows the ILIM_ voltage change by the time constant τ = (RA//RB) x C
ILIM
, where τ is between 5 to 10
switching periods. If the inductor saturation occurs only
during a short load transient, the time constant allows
the power supply to recover before the output voltage
drops below the output undervoltage threshold.
Set ∆V
ILIM
to be at least 30% of the ILIM_ set voltage.
Calculate RAand RBusing the equations below:
Inductor-saturation sensing works best when using a current-sense resistor in series with the inductor. See the
Setting the Current Limit section for various current-sense
configurations (Figure 14) and LSAT recommendations.
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
28 ______________________________________________________________________________________
Figure 7. Adjustable Current-Limit Threshold
Table 5. LSAT Configuration Table
∆VI
ILIM
-
=
R+R
RR
AB
AB
ILIM(LSAT)
REF
∆∆
V
ILIM(SET)
R
=
A
V
I
ILIM(LSAT)
R with set at
B
V
ILIM
=
V
V
ILIM(SET)
R
REF
A
V
ILIM(SET)
-
V
ILIM
301%
MAX1540
MAX1541
REF
C
REF
R
A
C
TO VALLEY
CURRENT-LIMIT
COMPARATOR
(FIGURE 2)
FROM LSAT
COMPARATOR
AND LOGIC
(FIGURE 2)
ILIM
6µA
ILIM
R
B
LSAT INDUCTOR-SATURATION THRESHOLD
V
CC
Open 1.75 x I
REF 1.50 x I
GND Disabled
2.00 x I
LIM(VAL)
LIM(VAL)
LIM(VAL)
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving moderate-sized high-side, and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications where a large VIN- V
OUT
differential exists. An adaptive dead-time circuit monitors the DL_ output and prevents the high-side MOSFET
from turning on until DL_ is off. A similar adaptive deadtime circuit monitors the DH_ output, preventing the lowside MOSFET from turning on until DH_ is off. There
must be a low-resistance, low-inductance path from the
DL_ and DH_ drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; otherwise, the
sense circuitry in the MAX1540/MAX1541 interprets the
MOSFET gates as “off” while charge actually remains.
Use very short, wide traces (50 mils to 100 mils wide if
the MOSFET is 1in from the driver).
The internal pulldown transistor that drives DL_ low is
robust, with a 0.6Ω (typ) on-resistance. This helps prevent DL_ from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs
when the inductor node (LX_) quickly switches from
ground to VIN. Applications with high input voltages and
long inductive driver traces may require additional gateto-source capacitance to ensure fast-rising LX_ edges
do not pull up the low-side MOSFETs gate, causing
shoot-through currents. The capacitive coupling
between LX_ and DL_ created by the MOSFET’s gate-todrain capacitance (C
RSS
), gate-to-source capacitance
(C
ISS-CRSS
), and additional board parasitics should not
exceed the following minimum threshold:
Lot-to-lot variation of the threshold voltage can cause
problems in marginal designs. Alternatively, adding a
resistor less than 10Ω in series with BST_ can remedy the
problem by increasing the turn-on time of the high-side
MOSFET without degrading the turn-off time (Figure 8).
POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when VCCrises above
approximately 2V, resetting the fault latch and soft-start
counter, powering-up the reference, and preparing the
PWM for operation. Until VCCreaches 4.25V (typ), V
CC
undervoltage lockout (UVLO) circuitry inhibits switching.
The controller inhibits switching by pulling DH_ low, and
holding DL_ low when OVP and shutdown discharge are
disabled or forcing DL_ high when OVP and shutdown
discharge are enabled (Table 7). When VCCrises above
4.25V and ON_ is driven high, the controller activates the
PWM controller and initializes soft-start.
Soft-start allows a gradual increase of the internal currentlimit level during startup to reduce the input surge currents. The MAX1540/MAX1541 divide the soft-start period
into five phases. During the first phase, the controller limits the current limit to only 20% of the full current limit. If
the output does not reach regulation within 425µs, softstart enters the second phase, and the current limit is
increased by another 20%. This process is repeated until
the maximum current limit is reached after 1.7ms or when
the output reaches the nominal regulation voltage,
whichever occurs first (see the soft-start waveforms in the
Typical Operating Characteristics).
Power-Good Output (PGOOD_)
PGOOD_ is the open-drain output for a window comparator that continuously monitors the output. PGOOD_
is actively held low in shutdown and during soft-start.
After the digital soft-start terminates, PGOOD_ becomes
high impedance as long as the respective output voltage is within ±10% of the nominal regulation voltage set
by FB_. When the output voltage drops 10% below or
rises 10% above the nominal regulation voltage, the
MAX1540/MAX1541 pull the respective power-good output (PGOOD_) low by turning on the MOSFET (Figure
9). Any fault condition forces both PGOOD1 and
PGOOD2 low until the fault latch is cleared by toggling
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________________________ 29
Figure 8. Optional Gate-Driver Circuitry
VV
GS(TH) IN
<
C
C
RSS
ISS
C
BYP
V
MAX1540
MAX1541
V
(R
)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING
BST
THE SWITCHING NODE RISE TIME.
)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
(C
NL
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
DD
D
BST
)*
(R
BST
DD
PGND
BST
N
N
INPUT (VIN)
H
L
L
C
BST
DH
LX
DL
)*
(C
NL
MAX1540/MAX1541
ON1 or ON2, or cycling VCCpower below 1V. For logiclevel output voltages, connect an external pullup resistor between PGOOD_ and VCC. A 100kΩ resistor works
well in most applications.
Note that the power-good window detectors are completely independent of the overvoltage and undervoltage-protection fault detectors.
Fault Blanking (MAX1541 FBLANK)
The main MAX1541 controller (OUT1) automatically
enters forced-PWM operation during all dynamic outputvoltage transitions (GATE transition detected) in order to
ensure fast, accurate transitions. FBLANK determines
how long the main MAX1541 controller maintains forcedPWM operation (Table 6—typically 220µs (FBLANK =
VCC), 140µs (FBLANK = open or GND), or 65µs
(FBLANK = REF).
When fault blanking is enabled (FBLANK = VCC, open,
or REF), the MAX1541 also disables the overvoltage
and undervoltage fault protection for OUT1, and forces
PGOOD1 to a high-impedance state during the transition period selected by FBLANK (Table 6). This prevents fault protection from latching off the MAX1541
and the PGOOD1 signal from going low when the output voltage change (∆V
OUT1
) cannot occur as fast as
the REFIN1 voltage change (∆V
REFIN1
).
Shutdown and Output Discharge (ON_)
When the output discharge mode is enabled (OVP/UVP
connected to VCCor left open), and either ON_ is
pulled low or an OVP fault or thermal fault sets the fault
latch (Table 7), the controller discharges each output
through an internal 10Ω switch connected between
OUT_ and ground. While the output discharges, DL_ is
forced low and the PWM controller is disabled. Once
the output voltage drops below 0.3V, the low-side driver
pulls DL_ high, effectively clamping the output and LX_
switching node to ground. The reference remains active
until both output voltages are below 0.3V to provide an
accurate 0.3V discharge threshold.
When OVP/UVP is connected to REF or GND, the controller does not actively discharge either output, and the
DL_ driver remains low until the system reenables the
controller. Under these conditions, the output discharge
rate is determined by the load current and output
capacitance.
The controller detects and latches the discharge-mode
state set by OVP/UVP on startup.
Fault Protection
The MAX1540/MAX1541 provide over/undervoltage
fault protection (Figure 9). Drive OVP/UVP to enable
and disable fault protection as shown in Table 7. Once
activated, the controller continuously monitors the output for undervoltage and overvoltage fault conditions.
Overvoltage Protection (OVP)
When the output voltage rises above 116% of the nominal regulation voltage and OVP is enabled (OVP/UVP =
V
CC
or open), the OVP circuit sets the fault latch, shuts
down both the Quick-PWM controllers, immediately
pulls DH1 and DH2 low, and forces DL1 and DL2 high.
This turns on the synchronous-rectifier MOSFETs with
100% duty, rapidly discharging the output capacitors
and clamping both outputs to ground. Note that immediately latching DL_ high can cause the output voltages
to go slightly negative due to energy stored in the output LC at the instant the OV fault occurs. If the load
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
30 ______________________________________________________________________________________
Figure 9. Power-Good and Fault Protection
Table 6. FBLANK Configuration Table
POWER-GOOD FAULT PROTECTION
0.9 x
INT REF_
1.1 x
INT REF_
20ms
TIMER
POR
0.7 x
INT REF_
1.14 x
INT REF_
FAULT
LATCH
INT FB_
ENABLE OVP
ENABLE UVP
*BLANK
FAULT
POWERGOOD
*MAIN MAX1541 CONTROLLER (OUT1) ONLY
FBLANK
V
CC
Open Enabled 80/140
REF Enabled 35/65
GND Disabled 80/140
OUT1 FAULT
BLANKING
Enabled 120/220
FORCED-PWM
DURATION (MIN/TYP)
(µs)
cannot tolerate a negative voltage, place a power
Schottky diode across the output to act as a reversepolarity clamp. If the condition that caused the overvoltage persists (such as a shorted high-side MOSFET),
the input fuse blows. The MAX1541 ignores OVP faults
on OUT1 when it detects a transition on GATE
(FBLANK enabled). Toggle ON1 or ON2, or cycle V
CC
power below 1V to clear the fault latch and restart the
controller.
OVP is disabled when OVP/UVP is connected to REF or
GND (Table 7).
Undervoltage Protection (UVP)
When the output voltage drops below 70% of the nominal regulation voltage and UVP is enabled (OVP/UVP =
V
CC
or REF), the controller sets the fault latch and activates the output discharge sequence (see the
Shutdown and Output Discharge section) of both outputs. When the output voltage drops to 0.3V, the driver
pulls DL high so the synchronous rectifier turns on,
clamping the output to GND. UVP is ignored for at least
10ms (min) after startup (ON_ rising edge), and when
transitions are detected on GATE (MAX1541 only,
FBLANK enabled). Toggle ON1 or ON2, or cycle V
CC
power below 1V to clear the fault latch and restart the
controller.
UVP is disabled when OVP/UVP is left open or connected to GND (Table 7).
Thermal Fault Protection
The MAX1540/MAX1541 feature a thermal fault-protection circuit. When the linear regulator is disabled
(LDOON = GND), the controller sets the thermal limit at
+160°C. When the linear regulator is enabled (LDOON
= VCC), the controller sets the thermal limit at +150°C to
protect the internal linear regulator from continuous
short-circuit conditions. Once the junction temperature
exceeds the thermal limit, the thermal-protection circuit
activates the fault latch, pulls PGOOD1 and PGOOD2
low, disables the linear regulator, and activates the output discharge sequence of both outputs regardless of
the OVP/UVP setting. Toggle ON1 or ON2, or cycle V
CC
power below 1V to reactivate the controller after the
junction temperature cools by 10°C.
Output Voltage
Preset Output Voltages
The MAX1540/MAX1541s’ Dual Mode operation allows
the selection of common voltages without requiring
external components (Figure 10). For the main controller (OUT1) of the MAX1540, connect FB1 to GND for
a fixed 1.8V output, to VCCfor a fixed 1.2V output, or
connect FB1 directly to OUT1 for a fixed 0.7V output.
For the secondary controller (OUT2) of the MAX1540,
connect FB2 to GND for a fixed 2.5V output, to V
CC
for
a fixed 1.5V output, or connect FB2 directly to OUT2 for
a fixed 0.7V output. The main controller (OUT1) of the
MAX1541 regulates to the voltage set at REFIN1 (V
FB1
= V
REFIN1
) and does not support Dual Mode operation.
For the secondary controller (OUT2) of the MAX1541,
connect FB2 to GND for a fixed 2.5V output, to V
CC
for
a fixed 1.8V output, or connect FB2 directly to OUT2 for
a fixed 0.7V output. Table 8 shows the output voltage
configuration.
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 31
Table 7. Fault Protection and Shutdown Setting Truth Table
*Discharge-mode state latched on power-up.
OVP/UVP ON_ DISCHARGE* UVP PROTECTION OVP PROTECTION THERMAL PROTECTION
Yes. Output discharged
V
CC
Open
REF
GND
through a 10Ω resistor,
and DL forced high when
output drops below 0.3V.
Yes. Output discharged
through a 10Ω resistor,
and DL forced high when
output drops below 0.3V.
No. DL forced low when
shut down.
No. DL forced low when
shut down.
Yes. UVP fault activates
the discharge sequence.
No. UVP disabled.
Yes. UVP fault activates
the discharge sequence.
No. UVP disabled. No. OVP disabled.
Yes. DH pulled low and DL
forced high immediately.
Yes. DH pulled low and DL
forced high immediately.
No. OVP disabled.
Yes. Thermal fault activates
the discharge sequence.
Yes. Thermal fault activates
the discharge sequence.
Yes. Thermal fault activates
the discharge sequence.
Yes. Thermal fault activates
the discharge sequence.
MAX1540/MAX1541
Setting V
OUT
with a Resistive Voltage-Divider at FB_
The output voltage can be adjusted from 0.7V to 5.5V
using a resistive voltage-divider (Figure 11). The
MAX1540 regulates FB1 and FB2 to a fixed 0.7V reference voltage. The MAX1541 regulates FB1 to the voltage set at REFIN1 and regulates FB2 to a fixed 0.7V
reference voltage. This makes the main MAX1541 controller (OUT1) ideal for memory applications where the
termination supply must track the supply voltage. The
adjusted output voltage is:
where V
FB_
= 0.7V for the MAX1540, and V
FB1
=
V
REFIN1
and V
FB2
= 0.7V for the MAX1541.
Dynamic Output Voltages (MAX1541 OUT1 Only)
The MAX1541 regulates FB1 to the voltage set at
REFIN1. By changing the voltage at REFIN1, the
MAX1541 can be used in applications that require
dynamic output-voltage changes between two set
points. Figure 12 shows a dynamically adjustable resistive voltage-divider network at REFIN1. Using the GATE
signal and open-drain output (OD), a resistor can be
switched in and out of the REFIN1 resistor-divider,
changing the voltage at REFIN1. A logic high on GATE
turns on the internal N-channel MOSFET, forcing OD to
a low-impedance state. A logic low on GATE disables
the N-channel MOSFET, so OD is high impedance. The
two output voltages (FB1 = OUT1) are determined by
the following equations:
The main MAX1541 controller (OUT1) automatically
enters forced-PWM operation on the rising and falling
edges of GATE, and remains in forced-PWM mode for a
minimum time selected by FBLANK (Table 6). ForcedPWM operation is required to ensure fast, accurate
negative voltage transitions when REFIN1 is lowered.
Since forced-PWM operation disables the zero-crossing
comparator, the inductor current may reverse under
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
32 ______________________________________________________________________________________
Figure 10. MAX1540/MAX1541 Dual Mode Feedback Decoder
Table 8. Output Voltage Configuration
TO ERROR
AMPLIFIER
FB_
REF
(2.0V)
9R
R
MAX1540 MAX1541 MAX1540 MAX1541
FB_ = V
CC
FB_ = GND
FB_ = OUT_
or adjustable
OUT1 OUT2
Fixed
1.2V
Fixed
1.8V
0.7V V
VV
OUT_ FB_
Not
allowed
Not
allowed
REFIN1
R
C
=+
1
R
D
Fixed
1.5V
Fixed
2.5V
0.7V 0.7V
Fixed
1.8V
Fixed
2.5V
MAX1540
MAX1541
OUT_
FIXED OUTPUT
FB = V
CC
FIXED OUTPUT
FB = GND
R9
VV
OUT1(LOW) REF
VV
OUT1(HIGH) REF
=
=
R8+ R9
(R9+ R10)
R8+ (R9+R10)
light loads, quickly discharging the output capacitors. If
fault blanking is enabled, the MAX1541 also disables
the main controller’s (OUT1) overvoltage and undervoltage fault protection, and forces PGOOD1 to a highimpedance state for the period selected by FBLANK
(Table 6).
For a step-voltage change at REFIN1, the rate of
change of the output voltage is limited by the inductor
current ramp, the total output capacitance, the current
limit, and the load during the transition. The inductor
current ramp is limited by the voltage across the inductor and the inductance. The total output capacitance
determines how much current is needed to change the
output voltage. Additional load current slows down the
output-voltage change during a positive REFIN1 voltage change, and speeds up the output-voltage change
during a negative REFIN1 voltage change. For fast positive output-voltage transitions, the current limit must be
greater than the load current plus the transition current:
Adding a capacitor across REFIN1 and GND filters
noise and controls the rate of change of the REFIN1
voltage during dynamic transitions. With the additional
capacitance, the REFIN1 voltage slews between the
two set points with a time constant given by REQx
C
REFIN1
, where REQis the equivalent parallel resistance seen by the slew capacitor. Looking at Figure 12,
the time constant for a positive REFIN1 voltage transition is:
and the time constant for a negative REFIN1 voltage
transition is:
Linear Regulator (LDO)
The maximum input voltage for the linear regulator is
28V, while the minimum input voltage is determined by
the 600mV (max) dropout voltage (V
LDOIN(MIN)
=
V
LDOOUT
+ V
DROPOUT
). Bypass the linear regulator’s
output (LDOOUT) with a 4.7µF or greater capacitor,
providing at least 1µF per 5mA of internal and external
load on the linear regulator. The LDO can source up to
100mA for powering the controller or supplying a small
external load.
For the MAX1540, the linear regulator provides the 5V
bias supply that powers the gate drivers and analog
controller (Figure 1), providing stand-alone capability.
The linear regulator’s input is internally connected to
the battery voltage input (LDOIN = V+), and the gatedriver input supply is internally connected to the linear
regulator’s output (VDD= LDOOUT). Figure 13 is the
internal linear-regulator functional diagram.
For the MAX1541, the linear regulator supports Dual
Mode operation to allow the selection of a 5V output
voltage without requiring external components (Figure
1). Connect FBLDO to GND for a fixed 5.0V output. The
linear regulator’s output voltage can be adjusted from
1.25V to 5.5V using a resistive voltage-divider (Figure
12). The MAX1541 regulates FBLDO to a 1.25V feedback voltage. The adjusted output voltage is:
where V
FBLDO
= 1.25V. If unused, disable the MAX1541
linear regulator by connecting LDOON to GND.
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 33
Figure 11. Setting V
OUT
with a Resistive Voltage-Divider at FB_
R
LX_
MAX1540
MAX1541
DL_
GND
CSP_
CSN_
OUT_
FB_
L
N
L
SENSE
C
OUT
R
C
R
D
d
IIC
>+
LIMIT L
OAD OUT
V
d
t
τ
R8 (R9+R10)
POS = REFIN1
×
R8+ (R9+R10)
C
R8 R9
×
τ
=
NEG REFIN1
R8+ R9
C
11
R
VV
LDOOUT FBLDO
=+
1
12
R
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
34 ______________________________________________________________________________________
Figure 12. MAX1541 Standard Application Circuit
INPUT (V
)*
IN
+5V BIAS
SUPPLY
C1
1µF
V
DD
V+
C
IN
(2) 4.7µF
7V TO 20V
D
L1
L1
1.8µH
R
CS1
15mΩ
OUTPUT 1
= 1.5V
V
OUT(HIGH)
= 1.0V
V
OUT(LOW)
V
OUT(HIGH)
V
OUT(LOW)
R9
= V
REF
()
()
R8 + R9
(R9 + R10)
= V
REF
[]
R8 + (R9 + R10)
REF
C
OUT1
470µF
C
REF
0.22µF
C
ILIM1
470pF
C
ILIM2
470pF
V
OUT(LOW)
(ENABLED, 140µs)
V
75kΩ
C
REFIN
470pF
OUT(HIGH)
OPEN
R8
D
C
BST1
0.1µF
R2
100kΩ
R3
49.9kΩ
100kΩ
49.9kΩ
75kΩ
R10
150kΩ
D
BST
N
H1
N
L1
C
CC1
47pF
R4
R5
R9
DH1
BST1
LX1
DL1
SKIP
CSP1
CSN1
OUT1
FB1
CC1
REF
ILIM1
ILIM2
GATE
FBLANK
REFIN1
OD
MAX1541
DH2
BST2
GND
CSP2
CSN2
OUT2
OVP/UVP
LSAT
LDOON
ON1
ON2
PGOOD1
PGOOD2
LDOIN
LDOOUT
FBLDO
BST
N
H2
C
BST
0.1µF
LX2
N
L2
DL2
FB2
OPEN (I
REF (485kHz/355kHz)TON
V
CC
C2
1µF
C3
4.7µF
R11
32.4kΩ
R12
20kΩ
R1
20Ω
100kΩ
LIM(VAL)
R6
ON
D
L2
x 1.75)
R13
10Ω
L2
4.3µH
R
CS2
15mΩ
OUTPUT 2
= 2.5V
V
OUT2
C
OUT2
220µF
OFF
+5V BIAS
SUPPLY
R7
100kΩ
POWER-GOOD
+5V BIAS
SUPPLY
LDO OUTPUT
= 3.3V
V
LDOOUT
C4
22µF
POWER GROUND
SEE TABLE 1 FOR COMPONENT SPECIFICATIONS.
ANALOG GROUND
*LOWER INPUT VOLTAGES REQUIRE
ADDITIONAL INPUT CAPACITANCE.
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design:
• Input voltage range: The maximum value (V
IN(MAX)
)
must accommodate the worst-case, high AC-adapter
voltage. The minimum value (V
IN(MIN)
) must account
for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there
is a choice at all, lower input voltages result in better
efficiency.
• Maximum load current: There are two values to
consider. The peak load current (I
LOAD(MAX)
) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor
selection, inductor saturation rating, and the design of
the current-limit circuit. The continuous load current
(I
LOAD
) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and
other critical heat-contributing components.
• Switching frequency: This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage due to MOSFET switching losses that
are proportional to frequency and V
IN2
. The optimum frequency is also a moving target, due to
rapid improvements in MOSFET technology that are
making higher frequencies more practical.
• Inductor operating point: This choice provides
trade-offs between size vs. efficiency and transient
response vs. output ripple. Low inductor values
provide better transient response and smaller physical size, but also result in lower efficiency and
higher output ripple due to increased ripple currents. The minimum practical inductor value is one
that causes the circuit to operate at the edge of critical conduction (where the inductor current just
touches zero with every cycle at maximum load).
Inductor values lower than this grant no further sizereduction benefit. The optimum operating point is
usually found between 20% and 50% ripple current.
When pulse skipping (SKIP low and light loads), the
inductor value also determines the load-current
value at which PFM/PWM switchover occurs.
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 35
Figure 13. Internal Linear-Regulator Functional Diagram
V+
*LDOIN
LDOON
*FBDLO
INTERNAL FBLDO
OPTION BETWEEN
THE MAX1540/MAX1541
*MAX1541 ONLY.
VL REG
AND REF
INTERNAL LDOIN
OPTION BETWEEN
THE MAX1540/MAX1541
GATE DRIVER
AND ERROR
0.2V
AMP
FIXED 5V
LDOOUT
INTERNAL V
DD
OPTION BETWEEN
THE MAX1540/MAX1541
*V
DD
MAX1540/MAX1541
Inductor Selection
The switching frequency and inductor operating point
determine the inductor value as follows:
For example: I
LOAD(MAX)
= 4A, VIN= 12V, V
OUT2
=
2.5V, fSW= 355kHz, 30% ripple current or LIR = 0.3:
Find a low-loss inductor with the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
inductor current (I
PEAK
):
Most inductor manufacturers provide inductors in standard values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc.
Also look for nonstandard values, which can provide a
better compromise in LIR across the input voltage
range. If using a swinging inductor (where the no-load
inductance decreases linearly with increasing current),
evaluate the LIR with properly scaled inductance values.
Transient Response
The inductor ripple current also impacts transientresponse performance, especially at low VIN- V
OUT
differentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The amount of output sag is also a function of the maximum duty factor, which can be calculated from the ontime and minimum off-time:
where t
OFF(MIN)
is the minimum off-time (see the
Electrical Characteristics) and K is from Table 3.
The amount of overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as:
Setting the Current Limit
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The valley of the inductor current occurs at I
LOAD(MAX)
minus
half the ripple current; therefore:
where I
LIM(VAL)
equals the minimum valley current-limit
threshold voltage divided by the current-sense resistance (R
SENSE
). For the 50mV default setting, the mini-
mum valley current-limit threshold is 40mV.
Connect ILIM_ to VCCfor a default 50mV valley currentlimit threshold. In adjustable mode, the valley currentlimit threshold is precisely 1/10th the voltage seen at
ILIM_. For an adjustable threshold, connect a resistive
divider from REF to analog ground (GND) with ILIM_
connected to the center tap. The external 250mV to 2V
adjustment range corresponds to a 25mV to 200mV
valley current-limit threshold. When adjusting the
current limit, use 1% tolerance resistors and a divider
current of approximately 10µA to prevent significant
inaccuracy in the valley current-limit tolerance.
The current-sense method (Figure 14) and magnitude
determine the achievable current-limit accuracy and
power loss (Table 9). Typically, higher current-sense
voltage limits provide tighter accuracy, but also dissipate more power. Most applications employ a valley
current-sense voltage (V
LIM(VAL)
) of 50mV to 100mV,
so the sense resistor may be determined by:
R
SENSE
= V
LIM(VAL)
/ I
LIM(VAL)
For the best current-sense accuracy and overcurrent
protection, use a 1% tolerance current-sense resistor
between the inductor and output as shown in Figure
14a. This configuration constantly monitors the inductor
current, allowing accurate valley current-limiting and
inductor-saturation protection.
For low-output-voltage applications that require higher
efficiency, the current-sense resistor can be connected
between the source of the low-side MOSFET (NL_) and
power ground (Figure 14b) with CSN_ connected to the
drain of NL_and CSP_ connected to power ground. In
this configuration, the additional current-sense resistance only dissipates power when NL_is conducting
current. Inductor-saturation protection must be disabled with this configuration (LSAT = GND) since the
inductor current is only properly sensed when the lowside MOSFET is turned on.
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
36 ______________________________________________________________________________________
L
=
.L
=
VVV
OUT IN OUT
××
V f x I LIR
IN SW LOAD(MAX)
×
2.5V (12V - 2.5V)
kHz x A
××
12V 3 4 0
55 3
-
()
=
4.65 H
µ
II
PEAK LOAD(MAX)
=+
LIR
1
2
L)
(∆I
LOAD(MAX)
V
=
SAG
×
CV2
OUT OUT
VK
2
OUT
V-V K
()
IN OUT
×
+t
OFF(MIN)
V
IN
×
-t
OFF(MIN)
V
IN
IL
∆
()
V
SOAR
LOAD(MAX)
≈
CV
2
OUT OUT
2
×
II
LIM(VAL) LOAD(MAX)
>
VV V
OUT IN MIN OUT
-
2
()
VfL
IN MIN SW
()
-
()
For high-power applications that do not require highaccuracy current sensing or inductor-saturation protection, the MAX1540/MAX1541 can use the low-side
MOSFET’s on-resistance as the current-sense element
(R
SENSE
= R
DS(ON)
) by connecting CSN_ to the drain
of NL_and CSP_ to the source of NL_(Figure 14c). Use
the worst-case maximum value for R
DS(ON)
from the
MOSFET data sheet, and add some margin for the rise
in R
DS(ON)
with temperature. A good general rule is to
allow 0.5% additional resistance for each °C of temperature rise. Inductor-saturation protection must be disabled with this configuration (LSAT = GND) since the
inductor current is only properly sensed when the lowside MOSFET is turned on.
Alternatively, high-power applications that require
inductor saturation can constantly detect the inductor
current by connecting a series RC circuit across the
inductor (Figure 14d) with an equivalent time constant:
where RLis the inductor’s series DC resistance. In this
configuration, the current-sense resistance is equivalent to the inductor’s DC resistance (R
SENSE
= RL). Use
the worst-case inductance and RLvalues provided by
the inductor manufacturer, adding some margin for the
inductance drop over temperature and load.
In all cases, ensure an acceptable valley current-limit
threshold voltage and inductor-saturation configurations despite inaccuracies in sense-resistance values.
Output Capacitor Selection
The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
For processor-core voltage converters and other applications where the output is subject to violent load transients, the output capacitor’s size depends on how
much ESR is needed to prevent the output from dipping
too low under a load transient. Ignoring the sag due to
finite capacitance:
In applications without large and fast load transients,
the output capacitor’s size often depends on how much
ESR is needed to maintain an acceptable level of output voltage ripple. The output ripple voltage of a stepdown controller equals the total inductor ripple current
multiplied by the output capacitor’s ESR. Therefore, the
maximum ESR required to meet ripple specifications is:
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tantalums, OS-CONs, polymers, and other electrolytics).
When using low-capacity filter capacitors, such as
ceramic capacitors, size is usually determined by the
capacity needed to prevent V
SAG
and V
SOAR
from
causing problems during load transients. Generally,
once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge
is no longer a problem (see the V
SAG
and V
SOAR
equations in the Transient Response section). However, lowcapacity filter capacitors typically have high-ESR zeros
that may affect the overall stability (see the Output-
Capacitor Stability Considerations section).
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 37
Table 9. Current-Sense Configurations
L
=C R
R
L
×
EQ EQ
R
ESR
V
≤
∆
I
LOAD(MAX)
STEP
R
ESR
V
≤
RIPPLE
I LIR
LOAD(MAX)
×∆
METHOD
a) Output current-sense resistor High
b) Low-side current-sense resistor High
c) Low-side MOSFET on-resistance Low
d) Equivalent inductor DC resistance Low Allowed No additional loss
CURRENT-SENSE
ACCURACY
INDUCTOR-SATURATION
PROTECTION
Allowed
(highest accuracy)
Not allowed
(LSAT = GND)
Not allowed
(LSAT = GND)
CURRENT-SENSE POWER LOSS
(EFFICIENCY)
R
x I
SENSE
V
OUT
1-
V
IN
No additional loss
OUT
RI
××
SENSE OUT
2
2
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
38 ______________________________________________________________________________________
Figure 14. Current-Sense Configurations
V
IN
C
DH
LX
MAX1540
MAX1541
CONNECT TO
PREFERRED
LSAT SETTING
LSAT
a) OUTPUT SERIES RESISTOR SENSING
DL
GND
CSP
CSN
IN
R
L
SENSE
MAX1540
MAX1541
C
CSN
V
OUT
OUT
V
IN
C
DH
LX
DL
R
SENSE
IN
L
V
OUT
C
OUT
MAX1540
MAX1541
DISABLE
LSAT
LSAT
c) LOW-SIDE MOSFET SENSING
CSN
CSP
GND
DISABLE
LSAT
LSAT
b) LOW-SIDE SERIES RESISTOR SENSING
V
IN
C
DH
LX
DL
IN
L
V
OUT
C
OUT
MAX1540
MAX1541
CONNECT TO
PREFERRED
LSAT SETTING
LSAT
d) LOSSLESS INDUCTOR SENSING
CSP
GND
GND
CSP
CSN
V
IN
C
DH
LX
DL
IN
R
BIAS
= R
EQ
R
EQ
INDUCTOR
L
R
L
C
EQ
V
OUT
C
OUT
Output-Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation:
For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz.
Tantalum and OS-CON capacitors in widespread use
at the time of publication have typical ESR zero frequencies of 25kHz. In the design example used for
inductor selection, the ESR needed to support 25mV
P-P
ripple is 25mV/1.2A = 20.8mΩ. One 220µF/4V Sanyo
polymer (TPE) capacitor provides 15mΩ (max) ESR.
This results in a zero at 48kHz, well within the bounds
of stability.
Do not put high-value ceramic capacitors directly
across the feedback sense point without taking precautions to ensure stability. Large ceramic capacitors can
have a high-ESR zero frequency and cause erratic,
unstable operation. However, it is easy to add enough
series resistance by placing the capacitors a couple of
inches downstream from the feedback sense point,
which should be as close as possible to the inductor.
Unstable operation manifests itself in two related but
distinctly different ways: double pulsing and fast-feedback loop instability. Double pulsing occurs due to
noise on the output or because the ESR is so low that
there is not enough voltage ramp in the output voltage
signal. This “fools” the error comparator into triggering
a new cycle immediately after the 400ns minimum offtime period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than
increased output ripple. However, it can indicate the
possible presence of loop instability due to insufficient
ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise
above or fall below the tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for overshoot and ringing. It can help to monitor simultaneously
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
Input-Capacitor Selection
The input capacitor must meet the ripple current
requirement (I
RMS
) imposed by the switching currents:
For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their
resistance to power-up surge currents typical of systems with a mechanical switch or connector in series
with the input. If the MAX1540/MAX1541 are operated
as the second stage of a two-stage power conversion
system, tantalum input capacitors are acceptable. In
either configuration, choose a capacitor that has less
than 10°C temperature rise at the RMS input current for
optimal reliability and lifetime.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention.
The high-side MOSFET (NH) must be able to dissipate
the resistive losses plus the switching losses at both
V
IN(MIN)
and V
IN(MAX)
. Ideally, the losses at V
IN(MIN)
should be roughly equal to the losses at V
IN(MAX)
, with
lower losses in between. If the losses at V
IN(MIN)
are
significantly higher, consider increasing the size of NH.
Conversely, if the losses at V
IN(MAX)
are significantly
higher, consider reducing the size of NH. If VINdoes
not vary over a wide range, maximum efficiency is
achieved by selecting a high-side MOSFET (NH) that
has conduction losses equal to the switching losses.
Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (R
DS(ON)
), comes in a moderate-sized
package (i.e., 8-pin SO, DPAK, or D2PAK), and is reasonably priced. Ensure that the MAX1540/MAX1541 DL_
gate driver can supply sufficient current to support the
gate charge and the current injected into the parasitic
drain-to-gate capacitor caused by the high-side MOSFET
turning on; otherwise, cross-conduction problems may
occur. Switching losses are not an issue for the low-side
MOSFET since it is a zero-voltage switched device when
used in the step-down topology.
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 39
where
f
ESR
f
≤
ESR
=
π
2R C
ESR OUT
f
SW
π
1
I
RMS
2
() ( )
IVVV
OUT OUT IN OUT
1
() ( )
=
2
IVVV
OUT OUT IN OUT
2
−+
11
−
22
V
IN
MAX1540/MAX1541
Power-MOSFET Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at
minimum input voltage:
Generally, use a small high-side MOSFET to reduce
switching losses at high input voltages. However, the
R
DS(ON)
required to stay within package power-dissipation limits often restricts how small the MOSFET can
be. The optimum occurs when the switching losses
equal the conduction (R
DS(ON)
) losses. High-side
switching losses do not become an issue until the input
is greater than approximately 15V.
Calculating the power dissipation in high-side
MOSFETs (NH) due to switching losses is difficult, since
it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors
include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PC board
layout characteristics. The following switching loss calculation provides only a very rough estimate and is no
substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH:
where C
RSS
is the reverse transfer capacitance of NH,
and I
GATE
is the peak gate-drive source/sink current
(1A typ).
Switching losses in the high-side MOSFET can become
a heat problem when maximum AC adapter voltages
are applied due to the squared term in the switchingloss equation (C ✕V
IN
2
✕
fSW). If the high-side MOS-
FET chosen for adequate R
DS(ON)
at low-battery
voltages becomes extraordinarily hot when subjected
to V
IN(MAX)
, consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (NL), the worst-case power
dissipation always occurs at maximum battery voltage:
The absolute worst case for MOSFET power dissipation
occurs under heavy overload conditions that are
greater than I
LOAD(MAX)
but are not high enough to
exceed the current limit and cause the fault latch to trip.
To protect against this possibility, “overdesign” the circuit to tolerate:
where I
VALLEY(MAX)
is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and sense-resistance variation. The
MOSFETs must have a relatively large heatsink to handle the overload power dissipation.
Choose a Schottky diode (DL) with a forward-voltage
drop low enough to prevent the low-side MOSFET’s
body diode from turning on during the dead time. As a
general rule, select a diode with a DC current rating
equal to 1/3 the load current. This diode is optional and
can be removed if efficiency is not critical.
Applications Information
Step-Down Converter Dropout
Performance
The output-voltage adjustable range for continuousconduction operation is restricted by the nonadjustable
minimum off-time one-shot. For best dropout performance, use the slower (200kHz) on-time setting. When
working with low input voltages, the duty-factor limit
must be calculated using worst-case values for on- and
off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor.
This error is greater at higher frequencies (Table 3).
Also, keep in mind that transient-response performance
of buck regulators operated too close to dropout is
poor, and bulk output capacitance must often be
added (see the V
SAG
equation in the Design Procedure
section).
The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆I
DOWN
)
as much as it ramps up during the on-time (∆I
UP
). The
ratio h = ∆I
UP
/∆I
DOWN
indicates the controller’s ability
to slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
each switching cycle, and V
SAG
greatly increases
unless additional output capacitance is used.
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
40 ______________________________________________________________________________________
PD (N Resistance)
H
=
V
OUT
V
IN
(I ) R
2
LOAD DS(ON)
×
()
PD (N Switching)
H
IN(MAX) RSS SW LOAD
=
2
××VCfI
I
GATE
PD (N Resistance) -
L
V
=
V
IN(MAX)
OUT
(I ) R
2
LOAD DS(ON)
×1
II
LOAD VALLEY(MAX)
( )
VV V
OUT IN OUT
+=
−
2
Vf L
IN SW
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows trade-offs between V
SAG
, output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
where V
DROP1
is the parasitic voltage drop in the
charge path (see the On-Time One-Shot section),
t
OFF(MIN)
is from the Electrical Characteristics, and K is
taken from Table 3. The absolute minimum input voltage
is calculated with h = 1.
If the calculated V
IN(MIN)
is greater than the required
minimum input voltage, then operating frequency must
be reduced or output capacitance added to obtain an
acceptable V
SAG
. If operation near dropout is anticipat-
ed, calculate V
SAG
to be sure of adequate transient
response.
Dropout Design Example
• V
OUT2
= 2.5V
• f
SW
= 355kHz
• K = 3.0µs, worst-case K
MIN
= 3.3µs
• t
OFF(MIN)
= 500ns
• V
DROP1
= 100mV
• h = 1.5
Calculating again with h = 1 and the typical K-factor
value (K = 3.3µs) gives the absolute limit of dropout:
Therefore, V
IN
must be greater than 3.06V, even with
very large output capacitance, and a practical input voltage with reasonable output capacitance would be 3.47V.
Multi-Output Voltage Settings
(MAX1541 OUT1 Only)
While the main MAX1541 controller (OUT1) is optimized
to work with applications that require two dynamic out-
put voltages, it can produce three or more output voltages if required by using discrete logic or a DAC.
Figure 15 shows an application circuit providing four
voltage levels using discrete logic. Switching resistors
in and out of the resistor network changes the voltage
at REFIN1. An edge-detection circuit is added to generate a 1µs pulse on GATE to trigger the fault blanking
and forced-PWM operation. When using PWM mode
(SKIP = V
CC
or open) on the main controller, the edgedetection circuit is only required if fault blanking is
enabled. Otherwise, leave OD unconnected.
Active Bus Termination
(MAX1541 OUT1 Only)
Active-bus-termination power supplies generate a voltage rail that tracks a set reference. They are required to
source and sink current. DDR memory architecture
requires active bus termination. In DDR memory architecture, the termination voltage is set at exactly half the
memory supply voltage. Configure the main MAX1541
controller (OUT1) to generate the termination voltage
using a resistive voltage-divider at REFIN1. In such an
application, the main MAX1541 controller (OUT1) must
be kept in PWM mode (SKIP = VCCor open) in order
for it to source and sink current. Figure 16 shows the
main MAX1541 controller configured as a DDR termination regulator. Connect GATE and FBLANK to GND
when unused.
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 41
Figure 15. Multi-Output Voltage Settings
MAX1541
REF
REFIN1
GND
GATE
R4
R3
A
C1
R2
R1
B
1000pF
1.5kΩ
1000pF
1.5kΩ
V
IN(MIN)
VV
OUT DROP1
=
ht
×
1
-
+
OFF(MIN)
K
V
IN(MIN)
=
VV
..
25 01
×
.
1 5 500
-
1
30
+
.
ns
s
µ
=
.
347
V
V
IN(MIN)
=
+
VV
..
25 01
×
1 500
-
1
.
33
µ
.
ns
s
=
306
V
MAX1540/MAX1541
Voltage Positioning
In applications where fast load transients occur, the output voltage changes instantly by ESR
COUT
x ∆I
LOAD
.
Voltage positioning allows the use of fewer output
capacitors for such applications, and maximizes the output voltage AC and DC tolerance window in tight-tolerance applications.
Figure 17 shows the connection of OUT_ and FB_ in
voltage-positioned and nonvoltage-positioned circuits.
In nonvoltage-positioned circuits, the MAX1540/
MAX1541 regulate at the output capacitor. In voltagepositioned circuits, the MAX1540/MAX1541 regulate on
the inductor side of the current-sense resistor. V
OUT_
is
reduced to:
V
OUT(VPS)
= V
OUT(NO LOAD)
- R
SENSE
x I
LOAD
Figure 18 shows the voltage-positioning transient
response.
PC Board Layout Guidelines
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 19). If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Follow these
guidelines for good PC board layout:
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable, jitter-free operation.
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
• Minimize current-sensing errors by connecting
CSP_ and CSN_ directly across the current-sense
resistor (R
SENSE_
).
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.
• Route high-speed switching nodes (BST_, LX_,
DH_, and DL_) away from sensitive analog areas
(REF, FB_, CSP_, CSN_).
Layout Procedure
1) Place the power components first, with ground terminals adjacent (N
L _
source, CIN, C
OUT
_, and DL_
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET, preferably on the back side opposite N
L
_
and N
H
_ in order to keep LX_, GND, DH_, and the
DL_ gate-drive lines short and wide. The DL_ and
DH_ gate traces must be short and wide (50 mils to
100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for
proper adaptive dead-time sensing.
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
42 ______________________________________________________________________________________
Figure 16. Active Bus Termination
V
DDQ
10nF
V
CC
SKIP
10kΩ
REFIN1
10kΩ
MAX1541
OD
GATE
FBLANK
CSP1
CSN1
OUT1
DH1
LX1
DL1
GND
FB1
V
IN
C
IN
R
L
= DDR MEMORY SUPPLY VOLTAGE
V
DDQ
= TERMINATION SUPPLY VOLTAGE
V
TT
SENSE
V
DDQ
VTT =
C
OUT
2
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 43
Figure 17. Voltage Positioning
Figure 18. Voltage-Positioning Transient Response
V
OUT(VPS)
= V
OUT(NO LOAD)
C1
- R
SENSEIOUT
V
FB
CC
R1
MAX1540
MAX1541
V
BST_
DH_
LX_
DL_
GND
CSP_
OUT_
CSN_
+5V BIAS
SUPPLY
C2
DD
D
BST
V+
C
IN
N
H
C
BST
N
L
D
L
L1
INPUT (VIN)
R
SENSE
VOLTAGE-POSITIONED
OUTPUT (V
OUT(VPS)
C
OUT
)
VOLTAGE POSITIONING THE OUTPUT
1.4
1.4
50mV/div
A. CONVENTIONAL CONVERTER
B. VOLTAGE-POSITIONED OUTPUT
CAPACITIVE SOAR
ESR VOLTAGE STEP
x R
(I
A
V
OUT
B
CAPACITIVE SAG
(dV/dt = I
OUT/COUT
I
LOAD
STEP
)
ESR
(dV/dt = I
)
RECOVERY
OUT/COUT
)
MAX1540/MAX1541
3) Group the gate-drive components (BST_ diode and
capacitor, VDDbypass capacitor) together near the
controller IC.
4) Make the DC-DC controller ground connections as
shown in Figures 1 and 12. This diagram can be
viewed as having two separate ground planes:
power ground, where all the high-power components go, and an analog ground plane for sensitive
analog components. The analog ground plane and
power ground plane must meet only at a single
point directly at the IC.
5) Connect the output power planes directly to the output filter capacitor positive and negative terminals
with multiple vias. Place the entire DC-DC converter
circuit as close to the load as is practical.
Chip Information
TRANSISTOR COUNT: 8612
PROCESS: BiCMOS
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
44 ______________________________________________________________________________________
Figure 19. PC Board Layout
VIA TO POWER
GROUND
CONNECT THE
EXPOSED PAD TO
ANALOG GROUND
VIA TO V
BYPASS CAPACITOR
CC
MAX1540
TOP LAYER
SINGLE
N-CHANNEL
MOSFETS
INDUCTOR
C
IN
C
C
OUT
OUT
CONNECT GND
AND PGND TO THE
CONTROLLER AT
ONE POINT ONLY
AS SHOWN
VIA TO REF
BYPASS CAPACITOR
KELVIN-SENSE VIAS
UNDER THE SENSE RESISTOR
(REFER TO EVALUATION KIT)
OUTPUT
INPUT
VIA TO V
CC
PIN
MAX1540
BOTTOM LAYER
INDUCTOR
C
IN
C
OUT
VIA TO REF PIN
DUAL
N-CHANNEL
MOSFET
DH
LX
DL
INPUT
HIGH-POWER LAYOUT LOW-POWER LAYOUT
GROUND
OUTPUT
GROUND
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 45
Pin Configurations (continued)
TOP VIEW
SKIP
LSAT
GATE
ILIM1
ILIM2
TON
V
CC1
REF
1OVP/UVP
2
3
4
5
CC
6
7
8
9
10
FBLANK
CSP1
CSN1
ON1
ON2
40393837363534
FB1
MAX1541
11121314151617
OD
REFIN1
CSP2
CSN2
FB2
OUT2
THIN QFN
OUT1
PGOOD2
33 PGOOD1
18
DH2
32 DH1
19
LX2
31 LX1
20BST2
30 BST1
29
LDOON
28
DL1
27
FBLDO
26
LDOOUT
25
V
DD
24
LDOIN
23
V+
DL2
2122GND
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
46 ______________________________________________________________________________________
0.15 C A
E/2
PIN # 1
I.D.
D
D/2
C
A3
A1
D2
b
0.10 M
PIN # 1 I.D.
0.35x45
E2/2
C
L
k
L
21-0140
C A B
E2
CC
L
REV.
QFN THIN.EPS
L
1
C
2
C
L
0.15
C B
E
0.10
C
A
0.08 C
(NE-1) X e
DETAIL A
k
L
D2/2
e
(ND-1) X e
L
e e
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
______________________________________________________________________________________ 47
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
21-0140
REV.DOCUMENT CONTROL NO.APPROVAL
2
C
2
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
48 ______________________________________________________________________________________
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
D
D/2
A1 A2
D2
C
L
k
E/2
E
A
(NE-1) X e
C
L
D2/2
(ND-1) X e
e e
b
E2/2
C
E2
L
k
L
e
C
L
QFN THIN 6x6x0.8.EPS
LL
PACKAGE OUTLINE
36,40L QFN THIN, 6x6x0.8 mm
21-0141
1
C
2
MAX1540/MAX1541
Dual Step-Down Controllers with Saturation
Protection, Dynamic Output, and Linear Regulator
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 49
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
COMMON DIMENSIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
EXPOSED PAD VARIATIONS
PKG.
CODES
T3666-1
T4066-1
D2
MAX.MIN.
NOM.
3.703.60 3.80
4.00 4.10 4.20 4.00 4.204.10
PACKAGE OUTLINE
36, 40L QFN THIN, 6x6x0.8 mm
MIN.
21-0141
E2
NOM.
MAX.
3.803.703.60
2
C
2
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