Rainbow Electronics MAX152 User Manual

19-0119; Rev. 1; 12/93

Evaluation Kit Manual

Follows Data Sheet

+3V, 8-Bit ADC with 1µA Power-Down

_______________General Description

The MAX152 high-speed, microprocessor (µP)-com­patible, 8-bit analog-to-digital converter (ADC) uses a
half-flash technique to achieve a 1.8µs conversion
time, and digitizes at a rate of 400k samples per sec­ond (ksps). It operates with single +3V or dual ±3V
supplies and accepts either unipolar or bipolar inputs.
A–P—O—W—E—R—D—O—W—N–pin reduces current consumption to
a typical value of 1µA. The part returns from power­down and acquires an input signal in less than 900ns,
providing large reductions in supply current in applica­tions with burst-mode input signals.

The MAX152 is DC and dynamically tested. Its µP inter­face appears as a memory location or input/output port that
requires no external interface logic. The data outputs use
latched, three-state buffered circuitry for direct connection
to a µP data bus or system input port. The ADC's input/ref­erence arrangement enables ratiometric operation. A fully-

___________________________Features

♦ Single +3.0V to +3.6V Supply
♦ 1.8µs Conversion Time
♦ Power-Up in 900ns
♦ Internal Track/Hold
♦ 400ksps Throughput
♦ Low Power: 1.5mA (Operating Mode)

1µA (Power-Down Mode)

♦ 300kHz Full-Power Bandwidth
♦ 20-Pin DIP, SO and SSOP Packages
♦ No External Clock Required
♦ Unipolar/Bipolar Inputs
♦ Ratiometric Reference Inputs
♦ 2.7V Version Available – Contact Factory

assembled evaluation kit provides a proven PC board lay­out to speed prototyping and design.

_______________________Applications

Cellular Telephones
Portable Radios
Battery-Powered Systems
Burst-Mode Data Acquisition
Digital Signal Processing
Telecommunications
High-Speed Servo Loops

________________Functional Diagram

V

DD

20

THREE-

STATE

DRIVERS

MAX152

19

V

SS

18

PWRDN

D0-D7
DATA
OUT
PINS
2-5,
14-17

VREF+
VREF-

V

12
11

1

IN

GND

4-BIT

FLASH

ADC

4-BIT

DAC



VREF+

4-BIT

16

FLASH

ADC

(4LSB)

TIMING AND CONTROL CIRCUITRY

6

7

10

MODE

WR

/RDY

13

CS

89

RD INT

________________________________________________________________

______________Ordering Information

PART TEMP. RANGE

MAX152CPP 0°C to +70°C
MAX152CWP 0°C to +70°C
MAX152CAP 0°C to +70°C
MAX152C/D 0°C to +70°C
MAX152EPP -40°C to +85°C
MAX152EWP -40°C to +85°C
MAX152EAP -40°C to +85°C
MAX152MJP -55°C to +125°C

* Contact factory for dice specifications.
** Contact factory for availability and processing to MIL-STD-883.

__________________Pin Configuration

TOP VIEW

D0 (LSB)

WR

/RDY

MODE

GND

V

D1
D2

D3

RD

INT

IN

10

1
2
3
4
5

MAX152

6
7
8
9

DIP/SO/SSOP

Call toll free 1-800-998-8800 for free samples or literature.

PIN-PACKAGE

20 Plastic DIP
20 Wide SO
20 SSOP
Dice*
20 Plastic DIP
20 Wide SO
20 SSOP
20 CERDIP**

V

20

DD

V

19

SS

PWRDN

18
17

D7 (MSB)

16

D6

15

D5

14

D4

13

CS

VREF+

12

VREF-

11

Maxim Integrated Products

MAX152

1

+3V, 8-Bit ADC with 1µA Power-Down

ABSOLUTE MAXIMUM RATINGS

VDDto GND.............................................................-0.3V to +7V

VSSto GND..............................................................+0.3V to -7V

Digital Input Voltage to GND........................-0.3V, (VDD+ 0.3V)

Digital Output Voltage to GND .....................-0.3V, (VDD+ 0.3V)

VREF+ to GND................................(VSS- 0.3V) to (VDD+ 0.3V)

VREF- to GND.................................(VSS- 0.3V) to (VDD+ 0.3V)

VINto GND.....................................(VSS- 0.3V) to (VDD+ 0.3V)

MAX152

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(Unipolar input range, VDD= 3.0V to 3.6V, GND = 0V, VSS= GND, VREF+ = 3.0V, VREF- = GND, specifications are given for RD
mode (pin 7 = GND), T

PARAMETER SYMBOL CONDITIONS UNITS

ACCURACY (Note 1)

Resolution N Bits
Total Unadjusted Error TUE Unipolar range LSB
Differential Nonlinearity DNL No-missing-codes guaranteed LSB
Zero-Code Error (Note 2) Unipolar and bipolar modes LSB
Full-Scale Error (Note 2) Unipolar and bipolar modes LSB
DYNAMIC PERFORMANCE (Note 3)

Signal-to-Noise Plus
Distortion Ratio

Total Harmonic Distortion

Spurious-Free Dynamic Range dB

Input Full-Power Bandwidth VIN= 3.0V
Maximum Input Slew Rate, Tracking V/µs

ANALOG INPUT

Input Voltage Range V
Input Leakage Current I
Input Capacitance C

REFERENCE INPUT

Reference Resistance RREF kΩ
VREF+ Input Voltage Range V
VREF- Input Voltage Range V

2 _______________________________________________________________________________________

= T

to T

A

MIN

, unless otherwise noted.)

MAX

MAX152C/E, f

IN

IN

400kHz, f
MAX152M, f

f

= 30.725kHz

IN

MAX152C/E, f
400kHz, f

MAX152M, f
f

= 30.725kHz

IN

MAX152C/E, f
400kHz, f

MAX152M, f
f

= 30.725kHz

IN

VSS< VIN< V

S/(N+D)

THD dB

IN

Continuous Power Dissipation (TA= +70°C)

Plastic DIP (derate 11.11mW/°C above +70°C) ..........889mW

Wide SO (derate 10.00mW/°C above +70°C)..............800mW

SSOP (derate 8.00mW/°C above +70°C) ....................640mW

CERDIP (derate 11.11mW/°C above +70°C)...............889mW

Operating Temperature Ranges:

MAX152C__ ........................................................0°C to +70°C

MAX152E__ .....................................................-40°C to +85°C

MAX152MJP ..................................................-55°C to +125°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

MIN TYP MAX

8

±1
±1
±1
±1

=

SAMPLE

= 30.273kHz

IN

SAMPLE

SAMPLE

= 30.273kHz

IN

SAMPLE

SAMPLE

= 30.273kHz

IN

SAMPLE

p-p

= 340kHz,

=

= 340kHz,

=

= 340kHz,

45

45

-50

-50

50

50

0.3

0.28 0.5

VREF- VREF+

DD

±3

22

12 4

VREF- V

V

SS

DD

VREF+

dB

MHz

V
µA
pF

+3V, 8-Bit ADC with 1µA Power-Down

ELECTRICAL CHARACTERISTICS (continued)

(Unipolar input range, VDD= 3.0V to 3.6V, GND = 0V, VSS= GND, VREF+ = 3.0V, VREF- = GND, specifications are given for RD
mode (pin 7 = GND), T

PARAMETER CONDITIONS UNITS

LOGIC INPUTS

Input High Voltage

Input Low Voltage

Input High Current

Input Low Current
Input Capacitance (Note 4)

LOGIC OUTPUTS

Output Low Voltage

Output High Voltage
Floating-State Current

Floating Capacitance (Note 4)

POWER REQUIREMENTS

Positive Supply Voltage
Negative Supply Voltage

Positive Supply Current

Power-Down VDDCurrent
(Note 5)

Negative Supply Current
Power-Down VSSCurrent

Power-Supply Rejection PSR

Note 1: Accuracy measurements performed at VDD= 3.0V, unipolar mode. Operation over supply range is guaranteed by power-

supply rejection test.

Note 2: Bipolar tests are performed with VREF+ = +1.5V, VREF- = -1.5V, VSS= -3.0V.
Note 3: Unipolar input range, VIN= 3.0V
Note 4: Guaranteed by design.
Note 5: Power-down current increases if control inputs are not driven to ground or VDD.

= T

to T

A

MIN

, unless otherwise noted.)

MAX

SYMBOL MIN TYP MAX

V

V

CS, WR, RD, PWRDN

INH

MODE 2.4
CS, WR, RD, PWRDN

INL

MODE 0.8
CS, RD, PWRDN

I

INH

WR

2.0

0.66

±1
±3

µA

MODE 15 100

I

INL

C

CS, WR, RD, PWRDN, MODE
CS, WR, RD, PWRDN, MODE

IN

INT, D0-D7, I

V

V
I

LKG

C

OUT

V

V

INT, D0-D7, I

OL

RDY, I

SINK

INT, D0-D7, I

OH

INT, D0-D7, I
D0-D7, RDY ±3 µA
D0-D7, RDY 58pF

DD

Unipolar operation GND

SS

Bipolar operation (Note 2) -3.6 -3.0

VDD= 3.6V

I

DD

VDD= 3.0V

CS = RD = VDD,

PWRDN = 0

I

CS = RD = 0, PWRDN = V

SS

CS = RD = VDD, PWRDN = 0
VDD= 3.3V ±10%

, WR-RD mode, VDD= 3.0V

P-P

= 20µA

SINK

= 400µA

SINK

= 1mA

= 20µA

SOURCE

= 400µA

SOURCE

MAX152C, CS = RD = 0,
PWRDN = V

MAX152E/M, CS = RD = 0,
PWRDN = V

MAX152C, CS = RD = 0,
PWRDN = V

MAX152E/M, CS = RD = 0,
PWRDN = V

MAX152C/E/M

VDD-0.1
VDD-0.4

3.0 3.6 V

DD

DD

DD

DD

DD

±1/16 ±1/4 LSB

±1 µA

58pF

0.1

0.4

0.4

2.5 5

2.5 6

1.5 3

1.5 3.5

150

150µA
125µA

mA

µA

MAX152

V

V

V

V

V

_______________________________________________________________________________________ 3

+3V, 8-Bit ADC with 1µA Power-Down

TIMING CHARACTERISTICS

(Unipolar input range, VDD= 3V, VSS= 0V, TA= +25°C, unless otherwise noted.) (Note 6)

PARAMETER SYMBOL CONDITIONS

Conversion Time
(WR-RD Mode)

MAX152

Conversion Time
(RD Mode)

Power-Up Time
CS to RD,WR

Setup Time
CS to RD,WR

Hold Time
CS to RDY

Delay
Data Access Time

(RD Mode) (Note 7)
RD to INT Delay

(RD Mode)
Data Hold Time

(Note 8)
Delay Time Between

Conversions
WR Pulse Width

Delay Time Between

WR and RD Pulses

RD Pulse Width

Data Access Time
(Note 7)

RD to INT Delay
WR to INT Delay

RD Pulse Width

Data Access Time
(Note 7)

WR to INT Delay
Data Access Time

After INT (Note 7)

t

CWR

t

CRD

t

UP

t

CSS

t

CSH

t

RDY

t

ACC0CL

t

INTH

t

DH

t

P

t

WR

t

RD

t

READ1

t

ACC1

t

RI

t

INTL

t

READ2

t

ACC2

t

IHWR

t

ID

tRD< t
C

CL= 50pF,
R

INTL

= 100pF

L

= 5.1kΩ to V

L

,

DD

= 100pF

CL= 50pF

WR-RD mode,
determined by t
(Figure 6)

WR-RD mode,
t

< t

RD

INTL

(Figure 6)

ACC1

, CL= 100pF

CL= 50pF
WR-RD mode,

t

> t

,

RD

INTL

determined by t
(Figure 5)

WR-RD mode,
t

< t

RD

INTL

(Figure 5)
Stand-alone mode,

C

= 50pF

L

Stand-alone mode,
C

= 100pF

L

ACC2

, CL= 100pF

ALL GRADES

= +25°C

T

A

MIN TYP MAX

1.8 2.06 2.4 µs

2.0 2.3 2.6 µs

0.9 1.2 1.4 µs

0 0 0 ns

0 0 0 ns

100 120 140 ns

t

CRD

+100

100 160 170 180 ns

100 130 150 ns

450 600 700 ns

0.6 10 0.66 10 0.8 10 µs

0.8 0.9 1.0 µs

400 500 600 ns

400 500 600 ns

300 340 400 ns

0.7 1.45 1.6 1.8

180 220 250 ns

180 220 250 ns

180 200 240 ns

100 130 150 ns

MAX152C/E

= T

T

A

MIN

MIN MAX

to T

t

CRD

+130

MAX

Note 6: Input control signals are specified with tr= tf= 5ns, 10% to 90% of +3.0V, and timed from a voltage level of 1.3V. Timing

delays get shorter at higher supply voltages. See the Converson Time vs. Supply Voltage graph in the

Characteristics

to extrapolate timing delays at other power-supply voltages.

Note 7: See Figure 1 for load circuit. Parameter defined as the time required for the output to cross 0.66V or 2.0V.
Note 8: See Figure 2 for load circuit. Parameter defined as the time required for the data lines to change 0.5V.

MAX152M

= T

T

A

MIN

MIN MAX

Typical Operating

to T

t

CRD

+150

MAX

UNITS

ns

µs

_________________________________________________________________________________________

4 _______________________________________________________________________________________

+3V, 8-Bit ADC with 1µA Power-Down

0

MAX186

5

__________________________________________Typical Operating Characteristics

(TA=+25°C, unless otherwise noted).

CONVERSION TIME

vs. AMBIENT TEMPERATURE

1.6

1.4

1.2
VDD = 3.6V

1.0

0.8

(NORMALIZED TO VALUE AT +25°C)

0.6

CRD

t

0.4

1400

1300

1200

(ns)

1100

CRD

t

1000

900

800

2.8 4.0

VDD = 3.0V

-60 140

-20 20 100
TEMPERATURE (°C)

CONVERSION TIME

vs. SUPPLY VOLTAGE

3.0 3.4 3.8
SUPPLY VOLTAGE (V)

60

3.2

6

5

4

3.6

VDD = 3.3V

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

CS

= RD = 0V

MILITARY

SIGNAL-TO-NOISE RATIO

0

-20

-40

-60

RATIO (dB)

-80

-100

-120
0 200

40 80 160

vs. SUPPLY VOLTAGE

1.1

= 3.0V)

DD

1.0

0.9

0.8

TIMING (NORMALIZED TO V

0.7

2.8 3.8

3.0 3.2 3.6 4.0

EXTENDED



fIN = 30.27 kHz

= 400ksps

f

SAMPLE

SNR = 48.2dB

120

FREQUENCY (kHz)

NORMALIZED TIMING

3.4

SUPPLY VOLTAGE (V)

5

4

3

8.0

7.5

7.0

6.5

6.0

5.5

EFFECTIVE BITS

5.0

4.5

4.0

10,000

1000

100

SUPPLY CURRENT (µA)

10

1

ERROR

vs. POWER-UP TIME

VDD = 3.0V

EFFECTIVE BITS vs. 

INPUT FREQUENCY, WR-RD MODE

VDD = 3.0V
f

= 400kHz

SAMPLE
VIN = 2.98Vp-p
TA = T

to T

MIN

MAX

1k 10k 100k

INPUT FREQUENCY (Hz)

AVERAGE POWER CONSUMPTION

vs. CONVERSION RATE USING PWRDN

VDD = 3.0V

1 100k

10 100 10k 1M

1k

CONVERSIONS/SEC

-

1M

MAX152

3

SUPPLY CURRENT (mA)

2

1

2.8 3.0 3.4 3.8

_________________________________________________________________________________________________

COMMERCIAL

+25°C

3.2 3.6

SUPPLY VOLTAGE (V)

2

ERROR (LSBs)

1

VDD = 3.6V

0

120 160 240 32

200 280

tUP (ns)

5

+3V, 8-Bit ADC with 1µA Power-Down

DATA

OUTPUTS

3k

V

DD

DATA

OUTPUTS

C

L

3k

C

L

DATA

OUTPUTS

3k

10pF

DATA

OUTPUTS

V

DD

3k

10pF

MAX152

A. HIGH-Z TO V

OH

Figure 1. Load Circuits for Data-Access Time Test

____________________Pin Description _______________Detailed Description

PIN NAME FUNCTION

Analog Input. Range is

1
2 D0 Three-State Data Output (LSB)

3-5 D1-D3 Three-State Data Outputs

6

7 MODE

8

9

10 GND Ground

11 VREF-

12 VREF+

13

14-16 D4-D6 Three-State Data Outputs

17 D7 Three-State Data Output (MSB)
18

19
20

*See

V

IN

WR/RDY

RD

INT

CS

PWRDN

V

SS

V

DD

Digital Inferface

VREF- ≤ V

Write Control Input/Ready Status
Output*

Mode Selection Input is internally
pulled low with a 15µA current source.
MODE = 0 activates read mode
MODE = 1 activates write-read mode*

Read Input must be low to access
data.*

Interrupt Output goes low to indicate
end of conversion.*

Lower limit of reference span. Sets the
zero-code voltage. Range is
V

≤ VREF- < VREF+.

SS

Upper limit to reference span. Sets the
full-scale input voltage. Range is
VREF- < VREF+ ≤ V

Chip-Select Input must be low for the
device recognize WR or RD inputs.

Powerdown Input reduces supply
current when low.

Negative Supply. Unipolar: VSS= 0V,
Bipolar: V

Positive Supply, +3V.

Section.

≤ VREF+.

IN

= -3V.

SS

B. HIGH-Z TO V

.

DD

A. V

OL

TO HIGH-Z B. V

OH

OL

TO HIGH-Z

Figure 2. Load Circuits for Data-Hold TIme Test

Converter Operation

The MAX152 uses a half-flash conversion technique
(see

Functional Diagram

) in which two 4-bit flash ADC
sections achieve an 8-bit result. Using 15 compara­tors, the flash ADC compares the unknown input volt­age to the reference ladder and provides the upper 4
data bits.

An internal digital-to-analog converter (DAC) uses the
4 most significant bits (MSBs) to generate the analog
result from the first flash conversion and a residue volt­age that is the difference between the unknown input
and the DAC voltage. The residue is then compared
again with the flash comparators to obtain the lower 4
data bits (LSBs).

The MAX152 is characterized for operation between
+3.0V and +3.6V. Conversion times decrease as the
supply voltage increases. The supply current decreas­es rapidly with decreasing supply voltage. (See

Typical Operating Characteristics

.)

Power-Down Mode

In burst-mode or low sample-rate applications, the
MAX152 can be shut down between conversions,
reducing supply current to microamp levels (see

Typical Operating Characteristics

PWRDN pin shuts the device down, reducing supply
current to typically 1µA when powered from a single 3V
supply. A logic high on PWRDN wakes up the
MAX152. A new conversion can be started within
900ns of the PWRDN pin being driven high (this
includes both the power-up delay and the track/hold
acquisition time). If power-down mode is not required,
connect PWRDN to V

DD

.

). A logic low on the

6 _______________________________________________________________________________________

+3V, 8-Bit ADC with 1µA Power-Down

Once the MAX152 is in power-down mode, lowest sup­ply current is drawn with MODE low (RD mode) due to
an internal pull-down resistor at this pin. In addition, for
minimum current consumption, other digital inputs
should remain high in power-down. Refer to the

Reference

section for information on reducing refer-

ence current during power-down.

___________________Digital Interface

The MAX152 has two basic interface modes set by the
status of the MODE input pin. When MODE is low, the
converter is in the RD mode; when MODE is high, the
converter is set up for the WR-RD mode.

Read Mode (MODE = 0)

In RD mode, conversion control and data access are
controlled by the RD input (Figure 3). The comparator
inputs track the analog input voltage for the duration of
tP. A conversion is initiated by driving RD low. With µPs
that can be forced into a wait state, hold RD low until
output data appears. The µP starts the conversion,
waits, and then reads data with a single read instruction.

WR/RDY is configured as a status output (RDY) in RD
mode, where it can drive the ready or wait input of a
µP. RDY is an open-collector output (with no internal
pull-up) that goes low after the falling edge of CS and
goes high at the end of the conversion. If not used, the
WR/RDY pin can be left unconnected. The INT output
goes low at the end of the conversion and returns high
on the rising edge of CS or RD.

Write-Read Mode (MODE = 1)

Figures 4 and 5 show the operating sequence for the
write-read (WR-RD) mode. The comparator inputs
track the analog input voltage for the duration of tP.
The conversion is initiated by a falling edge of WR.
When WR returns high, the 4 MSBs' flash result is
latched into the output buffers and the 4 LSBs' conver­sion begins. INT goes low, indicating conversion end,
and the lower 4 data bits are latched into the output
buffers. The data is then accessible after RD goes low
(see

Timing Characteristics

PWRDN

WR

RD

INT

D0-D7

Figure 4. WR-RD Mode Timing (tRD> t

CS

t

CSS

t

UP

t

WR

).

t

t

ACC2

) (MODE= 1)

P
t

READ2

VALID DATA

t

DH

t

INTL

t

CSH

t

RD

INTL

MAX152

PWRDN

CS

RD

RDY

INT

D0-D7

t

RDY

t

UP

t

t

CSS

CSH

WITH EXTERNAL

PULL-UP

t

CRD

t

ACCO

Figure 3. RD Mode Timing (MODE= 0)

_______________________________________________________________________________________ 7

VALID DATA

t

DH

PWRDN

t

P

t

INTH

Figure 5. WR-RD Mode Timing (tRD< t

CS

WR

RD

INT

t

CSS

t

UP

t

WR

t

CWR

t

ACC1

t

CSH

t

t

RD

P

t

READ1

t

RI

VALID DATA

t

DH

),

Fastest Operating

INTL

t

INTH

Mode (MODE = 1)

+3V, 8-Bit ADC with 1µA Power-Down

t

WR

INT

MAX152

D0-D7

WR

OLD DATA

t

IHWR

t

INTL

t

P

t

ID

NEW DATA

+3V

0.1µF

4.7µF

VIN+
VIN-

1

V

IN

10

GND

MAX152

20

V

DD

12

VREF+

11

VREF-

Figure 6. Stand-Alone Mode Timing (CS= RD= 0) (MODE = 1)

A minimum acquisition time (tP) is required from INT
going low to the start of another conversion (WR going
low).

Options for reading data from the converter include the
following:

Using Internal Delay

The µP waits for the INT output to go low before read­ing the data (Figure 4). INT goes low after the rising
edge of WR, indicating that the conversion is complete
and the result is available in the output latch. With CS
low, data outputs D0-D7 can be accessed by pulling

RD low. INT is then reset by the rising edge of CS or
RD.

Fastest Conversion: Reading Before Delay

An external method of controlling the conversion time is
shown in Figure 5. The internally generated delay
t

varies slightly with temperature and supply volt-

INTL

age, and can be overridden with RD to achieve the
fastest conversion time. RD is brought low after the ris­ing edge of WR, but before INT goes low. This com­pletes the conversion and enables the output buffers
(D0-D7) that contain the conversion result. INT also
goes low after the falling edge of RD and is reset on the
rising edge of RD or CS. The total conversion time is
therefore: t

= tWR(600ns) + tRD(800ns) + t

CWR

ACC1

(400ns) = 1800ns.

Stand-Alone Operation

Besides the two standard WR-RD mode options, stand­alone operation can be achieved by connecting CS
and RD low (Figure 6). A conversion is initiated by
pulling WR low. Output data can be read by either
edge of the next WR pulse.

Figure 7a. Power Supply as Reference

VIN+

+3V

VIN-

20

V

34.8k

3.01k

DD

12

VREF+

0.1
µF

VREF-

11

4.7

0.1

7

6

µF

µF

8
1

LM10

3

4

+2.5V

2

10

GND

MAX152

1

V

IN

Figure 7b. External Reference, +2.5V Full Scale

1

V

IN

10

GND

20

MAX152

V

DD

12

VREF+

11

VREF-

0.1µF

+3V

0.1µF

4.7µF

*CURRENT PATH MUST STILL 
EXIST FROM VIN- TO GND.

VIN+

1.2V

V

IN-

0.1µF

Figure 7c. Input Not Referenced to GND

+3V

MAX872

PWRDN

MTD3055EL

C1

2.2µF

+

N

V

DD

MAX152

VREF+

VREF-

PWRDN

Figure 7d. An N-channel MOSFET switches off the reference
load during power-down.

8 _______________________________________________________________________________________

+3V, 8-Bit ADC with 1µA Power-Down

____________Analog Considerations

Reference

Figures 7a-7c show some reference connections.
VREF+ and VREF- inputs set the full-scale and zero­input voltages of the ADC. The voltage at VREF­defines the input that produces an output code of all
zeros, and the voltage at VREF+ defines the input that
produces an output code of all ones.

The internal resistance from VREF+ to VREF- may be as
low as 1kΩ, and current will flow through it even when
the MAX152 is shut down. Figure 7d shows how an N­channel MOSFET may be connected to VREF- to break
this path during power-down. The FET should have an
on resistance < 2Ω with a 3V gate drive.

Although VREF+ is frequently connected to VDD, this
circuit uses a low current, low-dropout, 2.5V voltage
reference – the MAX872. Since the MAX872 cannot
continuously furnish enough current for the reference
resistance, this circuit is intended for applications where
the MAX152 is normally in standby and is turned on in
order to make measurements at intervals greater than
20µs. The capacitor C1 connected to VREF+ is slowly
charged by the MAX872 during the standby period and
furnishes the reference current during the short measure­ment period.

The 2.2µF value of C1 is chosen so that its voltage drops
by less than 1/2LSB during the conversion process.
Larger capacitors reduce the error still further. Use
ceramic or tantalum capacitors for C1.

When VREF- is switched, as in Figure 7d, a new conver­sion can be initiated after waiting a time equal to the
power-up delay (tUP) plus the turn-on time of the N-chan-

nel FET.

Bypassing

A 4.7µF electrolytic in parallel with a 0.1µF ceramic
capacitor should be used to bypass VDDto GND.
These capacitors should have minimal lead length.

The reference inputs should be bypassed with 0.1µF
capacitors, as shown in Figures 7a-7c.

Input Current

Figure 8 shows the equivalent circuit of the converter
input. When the conversion starts and WR is low, V
connected to sixteen 0.6pF capacitors. During this acqui­sition phase, the input capacitors charge to the input volt­age through the resistance of the internal analog switches.
In addition, about 12pF of stray capacitance must be
charged. The input can be modeled as an equivalent RC
network (Figure 9). As source impedance increases, the
capacitors take longer to charge.

The typical 22pF input capacitance allows source resis­tance as high as 2.2kΩ without setup problems. For larg­er resistances, the acquisition time (t

MAX152

R

IN

V

IN

Figure 8. Equivalent Input Circuit

V

IN

Figure 9. RC Network Equivalent Input Model

R

ON

V

1

IN

C

R

1

4k

V

IN

12pF

) must be increased.

P

10pF

MAX152

IN

MAX152

is

_______________________________________________________________________________________ 9

+3V, 8-Bit ADC with 1µA Power-Down

Conversion Rate

The maximum sampling rate (f
achieved in the WR-RD mode (tRD< t
culated as follows:

f

=

max

MAX152

e.g. at T 25 C, V 3.0V:

where t Write pulse width

tttt

=+ ° =+

ADD

f

=

max

600ns 800ns 300ns 450ns

f 465kHz

=

max

=

WR

t Delay between WR and RD pulses

=

RD

t = RD to INT delay

RI

t = Delay time between conversons.

P

1

+++

WR RD RI P

+++

) for the MAX152 is

max

INTL

1

) and is cal-

Signal-to-Noise Ratio and Effective

Number of Bits

Signal-to-noise plus distortion ratio (SINAD) is the ratio
of the fundamental input frequency's RMS amplitude to
the RMS amplitude of all other ADC output signals. The
output band is limited to frequencies above DC and
below one-half the ADC sample rate.

The theoretical minimum A/D noise is caused by quan­tization error, and results directly from the ADC's reso­lution: SNR = (6.02N + 1.76)dB, where N is the number
of bits of resolution. Therefore, a perfect 8-bit ADC can
do no better than 50dB.

The FFT plot (
the result of sampling a pure 30.27kHz sinusoid at a
400kHz rate. This FFT plot of the output shows the out­put level in various spectral bands.

The effective resolution, or "effective number of bits,"
the ADC provides can be measured by transposing the
equation that converts resolution to SNR: N = (SINAD -

1.76)/6.02 (see

Typical Operation Characteristics

Typical Operating Characteristics

) shows

).

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal (in the frequen­cy band above DC and below one-half the sample rate)
to the fundamental itself. This is expressed as:

2

2



(V

V

++++

THD 20 log

=

where V
VNare the amplitudes of the 2nd through Nth harmonics.

is the fundamental RMS amplitude, and V2to

1

2






2

V

3

4

V

1

V

L

2

N



)






Spurious-Free Dynamic Range

Spurious-free dynamic range is the ratio of the funda­mental RMS amplitude to the amplitude of the next
largest spectral component (in the frequency band
above DC and below one-half the sample rate).
Usually the next largest spectral component occurs at
some harmonic of the input frequency. However, if the
ADC is exceptionally linear, it may occur only at a ran­dom peak in the ADC's noise floor. See "Signal to Noise
Ratio" plot in

Typical Operating Characteristics

.

10 ______________________________________________________________________________________

+3V, 8-Bit ADC with 1µA Power-Down

___________________Chip Topography

MAX152

D0

D1

D2

D3

WR/RDY

MODE

RD INT GND VREF- VREF+

TRANSISTOR COUNT: 1856
SUBSTRATE CONNECTED TO V

V

IN

DD

V

0.098"

2.49mm

V

SS

DD

PWRDN

D7
D6

0.104"

2.64mm

D5
D4

CS

________________________________________________________Package Information

INCHES MILLIMETERS

DIM



A

D1

E

E1

A2

A

D

A3

B1

α

e

A

e

B

A1

L

e

B

A1
A2
A3

B

B1

C
D

D1

E

E1

e



e

A



e

B

L

α

C

MAX

MIN

–

0.015

0.125

0.055

0.016

0.050

0.008

1.015

0.040

0.300

0.240

0.100 BSC



0.300 BSC



–

0.115
0˚

0.200
–

0.150

0.080

0.022

0.065

0.012

1.045

0.070

0.325

0.280

0.400

0.150

15˚

MIN

–

0.38

3.18

1.40

0.41

1.27

0.20

25.78

1.02

7.62

6.10

2.54 BSC





7.62 BSC





–

2.92
0˚

20-PIN PLASTIC

DUAL-IN-LINE

PACKAGE

MAX

5.08
–

3.81

2.03

0.56

1.65

0.30

26.54

1.78

8.26

7.11




10.16

3.81

15˚

21-333A

MAX152

______________________________________________________________________________________ 11

+3V, 8-Bit ADC with 1µA Power-Down

__________________________________________Package Information (continued)

INCHES MILLIMETERS

DIM

MAX152



A

A1

B
C
D

HE

E

e

H

h
L

α

MIN

0.093

0.004

0.014

0.009

0.496

0.291

0.394

0.010

0.016
0˚

MAX

MIN

0.104

2.35

0.012

0.10

0.019

0.35

0.013

0.23

0.512

12.60

0.299

7.40





0.419

10.00

0.030

0.25

0.050

0.40

8˚

MAX

2.65

0.30

0.49

0.32

13.00

7.60

1.27 BSC0.050 BSC





10.65

0.75

1.27

0˚

8˚

21-334A

D

h x 45˚

α

A

0.127mm

0.004in.

e

B

A1

C

L

20-PIN PLASTIC

SMALL-OUTLINE

PACKAGE

12 ______________________________________________________________________________________