Rainbow Electronics MAX15046B User Manual

19-4719; Rev 0; 7/09

Typical Operating Circuit

40V, High-Performance, Synchronous

General Description

The MAX15046 synchronous step-down controller oper­ates from a 4.5V to 40V input voltage range and gener­ates an adjustable output voltage from 85% of the input
voltage down to 0.6V, supporting loads up to 25A. The
device allows monotonic startup into a prebiased bus
without discharging the output and features adaptive
internal digital soft-start.

The MAX15046 offers the ability to adjust the switching
frequency from 100kHz to 1MHz with an external resis­tor. The MAX15046’s adaptive synchronous rectifica­tion eliminates the need for an external freewheeling
Schottky diode. The device also utilizes the external
low-side MOSFET’s on-resistance as a current-sense
element, eliminating the need for a current-sense resis­tor. This protects the DC-DC components from damage
during output overloaded conditions or output short­circuit faults without requiring a current-sense resistor.
Hiccup-mode current limit reduces power dissipation
during short-circuit conditions. The MAX15046 includes
a power-good output and an enable input with precise
turn-on/turn-off threshold, which can be used for input
supply monitoring and for power sequencing.

Additional protection features include sink-mode current
limit, and thermal shutdown. Sink-mode current limit pre­vents reverse inductor current from reaching dangerous
levels when the device is sinking current from the output.

Buck Controller

Features

S Input Voltage Ranges from 4.5V to 40V or 5V

Q10%

S Adjustable Outputs from 0.85 x V
S Adjustable Switching Frequency (100kHz to 1MHz)

with Q10% (1MHz) Accuracy

S Adaptive Internal Digital Soft-Start
S Up to 25A Output Capability
S Cycle-by-Cycle Valley-Mode Current Limit with

Adjustable, Temperature-Compensated Threshold
(30mV to 300mV)

S Monotonic Startup into Prebiased Output
S Q1% Accurate Voltage Reference
S 3A-Peak Gate Drivers
S Hiccup-Mode Short-Circuit Protection (Patent-

Pending Architecture)

S Overtemperature Shutdown
S Power-Good (PGOOD) Output and Enable Input

(EN) with Q5% Accurate Threshold

S Thermally Enhanced 16-Pin QSOP Package

Applications

Industrial Power Supplies (PLC, Industrial
Computers, Fieldbus Components, Fieldbus
Couplers)

Telecom Power Supplies
Base Stations

Ordering Information

Down to 0.6V

IN

MAX15046

The MAX15046 is available in a 16-pin QSOP or 16-pin
QSOP-EP package and operates over the -40NC to +125NC
temperature range.

Pin Configurations appear at end of data sheet.

4.5V TO 40V
V

IN

ON

OFF

R4

C1

IN

MAX15046

V

CC

PGOOD

EN

LIM

C5

R3

C6

C7

R1

COMP

FB

RT

R3

+
*EP = Exposed pad.

CSP

DH

LX

BST

DL

DRV

PGND

GND

R2

PART TEMP RANGE PIN-PACKAGE

MAX15046AAEE+ -40°C to +125°C 16 QSOP
MAX15046BAEE+ -40°C to +125°C 16 QSOP-EP*

Denotes a lead(Pb)-free/RoHS-compliant package.

Q1

C3

0.6V TO 0.85V x V
V

OUT

IN

L1

C2

D1

C4

R5

Q2

_______________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

40V, High-Performance, Synchronous
Buck Controller

ABSOLUTE MAXIMUM RATINGS

IN to GND ..............................................................-0.3V to +45V

VCC to GND ..................... -0.3V to lower of (VIN + 0.6V) and 6V

EN, DRV to GND ..................................................... -0.3V to +6V

PGOOD to GND ....................................................-0.3V to +45V

PGND to GND ......................................................-0.3V to +0.3V

DL to PGND .............................................-0.3V to (V

BST to PGND .......................................................-0.3V to +50V

LX and CSP to PGND ...............................................-1V to +45V

LX and CSP to PGND ............................-2V (50ns max) to +45V

MAX15046

BST to LX .................................................................-0.3V to +6V

CSP to LX .............................................................-0.3V to +0.3V

DH to LX .................................................. -0.3V to (V

All Other Pins to GND .............................. -0.3V to (VCC + 0.3V)

VCC Short Circuit to GND ..........................................Continuous

PGOOD Maximum Sink Current .........................................20mA

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-lay-

er board. For detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-tutorial.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

DRV

BST

+ 0.3V)

+ 0.3V)

ELECTRICAL CHARACTERISTICS

(VIN = 24V, VEN = 5V, V
noted. Typical values are at TA = +25NC.) (Note 2)

GND

= V

= 0V, CIN = 1FF, C

PGND

VCC

Continuous Power Dissipation (TA = +70NC):

16-Pin QSOP (derate 9.6mW/NC above +70NC) .......771.5mW

16-Pin QSOP-EP (derate 22.7mW/NC above +70NC) 1818.2mW
Junction-to-Case Thermal Resistance (θJC) (Note 1)

16-Pin QSOP ................................................................37NC/W

16-Pin QSOP-EP ............................................................6NC/W

Junction-to-Ambient Thermal Resistance (θJA) (Note 1)

16-Pin QSOP ...........................................................103.7NC/W

16-Pin QSOP-EP ..........................................................44NC/W

Operating Temperature Range ........................ -40NC to +125NC

Junction Temperature .....................................................+150NC

Storage Temperature Range ............................ -65NC to +150NC

Lead Temperature (soldering, 10s) ................................+300NC

= 4.7FF, RRT = 49.9kI, TA = TJ = -40NC to +125NC, unless otherwise

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SYSTEM SPECIFICATIONS

Input-Voltage Range V

Quiescent Supply Current I

Shutdown Supply Current I

VCC REGULATOR

Output Voltage V
VCC Regulator Dropout VIN = 4.5V, I
VCC Short-Circuit Output Current VIN = 5V 30 55 90 mA
VCC Undervoltage Lockout V

VCC Undervoltage Lockout
Hysteresis

ERROR AMPLIFIER (FB, COMP)

FB Input-Voltage Set Point V
FB Input Bias Current I
FB to COMP Transconductance g
Open-Loop Gain 80 dB

Unity-Gain Bandwidth

IN

IN_Q

IN_SBY

VCC

CCUVLO

FB

FB

M

VIN = VCC = V
VIN = 24V, VFB = 0.9V, no switching 2 3 mA

VIN = 24V, VEN = 0V, I
PGOOD = unconnected

6V ≤ VIN ≤ 40V, I

V

rising 3.8 4 4.2 V

VCC

VFB = 0.6V -250 +250 nA
I

= Q20FA

COMP

Capacitor from COMP to GND =
47pF

DRV

= 0,

VCC

= 6mA 5 5.25 5.5 V

LOAD

= 25mA 0.18 0.45 V

LOAD

4.5 40

4.5 5.5

0.35 0.55 mA

400 mV

584 590 596 mV

600 1200 1800

5 MHz

V

FS

2 ______________________________________________________________________________________

40V, High-Performance, Synchronous

Buck Controller

ELECTRICAL CHARACTERISTICS (continued)

(VIN = 24V, VEN = 5V, V
noted. Typical values are at TA = +25NC.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

V

COMP-RAMP

COMP Source/Sink Current I

ENABLE (EN)

EN Input High V
EN Input Low V
EN Input Leakage Current I

OSCILLATOR

Switching Frequency (100kHz) f
Switching Frequency (300kHz) f
Switching Frequency (1MHz) f

Switching Frequency Adjustment
Range

RT Voltage V

PWM MODULATOR

PWM Ramp Peak-to-Peak
Amplitude

PWM Ramp Valley V
Minimum Controllable On-Time 70 125 ns
Maximum Duty Cycle
Minimum Low-Side On-Time

OUTPUT DRIVERS/DRIVERS SUPPLY (V

Undervoltage Lockout V

DRV Undervoltage Lockout
Hysteresis

DH On-Resistance

DL On-Resistance

DH Peak Current C

Minimum Voltage 200 mV

GND

= V

= 0V, CIN = 1FF, C

PGND

COMP

EN_H

EN_L

EN

SW

SW

SW

RT

V

RAMP

VALLEY

DRV

DRV_UVLOVDRV

= 4.7FF, RRT = 49.9kI, TA = TJ = -40NC to +125NC, unless otherwise

VCC

V

= 1.4V 50 80 110

COMP

VEN rising 1.14 1.20 1.26 V
VEN falling 1.05 V
VEN = 5.5V -1 +1

RRT = 150kI
RRT = 49.9kI
RRT = 14.3kI

(Note 3) 100 1000 kHz

RRT = 49.9kI

fSW = 300kHz (RRT = 49.9kI)
fSW = 1MHz (RRT = 49.9kI)

)

rising 4.0 4.2 4.4 V

Low, sinking 100mA,
V

- VLX = 5V

BST

High, sourcing 100mA,
V

- VLX = 5V

BST

Low, sinking 100mA,
V

= VCC = 5.25V

DRV

High, sourcing 100mA,
V

= VCC = 5.25V

DRV

Sinking,
V

- VLX = 5V

LOAD

= 10nF

BST

Sourcing,
V

- VLX = 5V

BST

80 100 120 kHz

270 300 330 kHz

0.9 1 1.1 MHz

1.15 1.2 1.25 V

1.5 V

1.5 V

85 87.5 %

110 ns

400 mV

1 3

1.5 4

1 3

1.5 4

3

2

MAX15046

FA

FA

I

A

_______________________________________________________________________________________ 3

40V, High-Performance Synchronous
Buck Controller

ELECTRICAL CHARACTERISTICS (continued)

(VIN = 24V, VEN = 5V, V
noted. Typical values are at TA = +25NC.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

DL Peak Current C

MAX15046

DH, DL Break-Before-Make Time
(Dead Time)

SOFT-START

Soft-Start Duration 2048

Reference Voltage Steps 64 Steps

CURRENT LIMIT/HICCUP

Cycle-by-Cycle Valley Current­Limit Threshold Adjustment
Range

GND

= V

= 0V, CIN = 1FF, C

PGND

= 4.7FF, RRT = 49.9kI, TA = TJ = -40NC to +125NC, unless otherwise

VCC

= 10nF

LOAD

V

- V

CSP

PGND

valley limit =
V

/10

LIM

Sinking, V
= 5.25V

Sourcing, V
VCC = 5.25V

V

LIM

,

V

LIM

= VCC

DRV

=

DRV

= 0.3V 30

= 3V 300

3

2

10 ns

Switching

A

Cycles

mV

LIM Reference Current I

LIM Reference Current
Temperature Coefficient

CSP Input Bias Current V

Number of Consecutive Current­Limit Events to Hiccup

Hiccup Timeout 4096

Peak Low-Side Sink Current-Limit
Threshold

POWER-GOOD (PGOOD)

PGOOD Threshold VFB rising 90 94 97.5 %V
PGOOD Threshold Hysteresis VFB falling 2.65 %V
PGOOD Output Low Voltage V
PGOOD Output Leakage Current I

THERMAL SHUTDOWN

Thermal Shutdown Threshold Temperature rising +150
Thermal Shutdown Hysteresis 20

Note 2: All devices are 100% tested at room temperature and guaranteed by design over the specified temperature range.

Note 3: Select RRT as:

R

=

RT

f (1 x 10 )(f )

+

SW SW

LIM

PGOOD_LIPGOOD

LEAK_PGOODVPGOOD

×

-7 2

9

17.3 10

V

= 0.3V to 3V, TA = +25NC

LIM

= 40V -1 +1

CSP

7 Events

V

- V

CSP

R

= 30kI, V

ILIM

TA = +25NC

, where fSW is in Hertz.

, sink limit = V

PGND

= 1.5V,

LIM

= 2mA, VEN = 0V 0.4 V

= 40V, VEN = 5V, VFB = 1V -1 +1

LIM

/20,

45 50 55

2300

75 mV

ppm/NC

Switching

Cycles

FA

FA

FB

FB

FA

NC
NC

4 ______________________________________________________________________________________

40V, High-Performance Synchronous

EFFICIENCY vs. LOAD CURRENT

EFFICIENCY (%)

EFFICIENCY vs. LOAD CURRENT

EFFICIENCY (%)

V

(V)

FREQUENCY (kHz)

FREQUENCY (kHz)

Buck Controller

Typical Operating Characteristics

(VIN = 24V, TA = +25NC, unless otherwise noted.)

MAX15046

(VIN = 24V)

100

90

80

70

60

50

40

30

20

10

0

V

= 3.3V

OUT

V

= 1.8V

OUT

V

= 5V

OUT

0 15

LOAD CURRENT (A)

VCC vs. LOAD CURRENT

5.256

5.254

5.252

5.250

(V)

CC

V

5.248

5.246

5.244

5.242

LOAD CURRENT (mA)

(VIN = 12V)

100

90

MAX15046 toc01

80

70

V

= 1.2V

OUT

12963

60

50

40

30

20

10

0

0 15

V

= 1.2V

OUT

V

= 1.8V

OUT

V

OUT

LOAD CURRENT (A)

= 3.3V

V

= 5V

OUT

12963

0.50

0.45

MAX15046 toc02

0.40

0.35

0.30

0.25

0.20

0.15

% OUTPUT FROM NORMAL

0.10

0.05

0

VCC LINE REGULATION

MAX15046 toc05

(V)
V

CC

5.266

5.265

5.264

5.263

5.262

5.261

5.260

4035302520151050 45

MAX15046 toc04

5.2

I

= 5mA, 10mA, 20mA, 30mA

5.0

4.8

CC

4.6

4.4

4.2

4.0
0 40

VCC

I

VCC

= 40mA

VIN (V)

3530252015105

V

vs. LOAD CURRENT

OUT

0 12

LOAD CURRENT (A)

108642

VCC vs. TEMPERATURE

I

= 5mA

LOAD

-40 125
TEMPERATURE (NC)

1109580655035205-10-25

MAX15046 toc03

MAX15046 toc06

SWITCHING FREQUENCY

vs. R

1000

900

800

700

600

500

400

300

200

100

0

0 160

RT

RRT (kI)

_______________________________________________________________________________________ 5

SWITCHING FREQUENCY

vs. TEMPERATURE

1200

1000

MAX15046 toc07

800

600

400

200

0

1208040

-40 125

RT = 25.5kI

TEMPERATURE (NC)

RT = 14.3kI

RT = 49.9kI

RT = 150kI

MAX15046 toc08

1109580655035205-10-25

2.8
CDH = CDL = 0

2.7

2.6

(mA)

2.5

IN

I

2.4

2.3

2.2

100 1000

IIN vs.

SWITCHING FREQUENCY

MAX15046 toc09

FREQUENCY (kHz)

40V, High-Performance, Synchronous
Buck Controller

Typical Operating Characteristics (continued)

(VIN = 24V, TA = +25NC, unless otherwise noted.)

LIM REFERENCE CURRENT

vs. TEMPERATURE

80

75

70

MAX15046

65

60

CURRENT (FA)

55

50

45

40

-40 125
TEMPERATURE (NC)

LOAD TRANSIENT ON OUT (1A TO 15A)

200Fs/div

11095-25 -10 5 35 50 6520 80

MAX15046 toc12b

SINK AND SOURCE CURRENT LIMIT

THRESHOLDS vs. RESISTANCE (R

0.20

0.15

0.10

MAX15046 toc10

0.05

0

-0.05

-0.10

-0.15

-0.20

CURRENT-LIMIT THRESHOLD (V)

-0.25

-0.30

-0.35
0 70

LOAD TRANSIENT ON OUT (1A TO 6A)

V

OUT

200mV/div

I

OUT

5A/div

SINK CURRENT LIMIT

SOURCE CURRENT LIMIT

RESISTANCE (kI)

200Fs/div

ILIM

605030 402010

MAX15046 toc12c

)

MAX15046 toc11

V

OUT

100mV/div

I

OUT

5A/div

LOAD TRANSIENT ON OUT (1A TO 10A)

200Fs/div

MAX15046 toc12a

STARTUP DISABLE FROM EN

= 3.3I)

(R

LOAD

4ms/div

MAX15046 toc13

V

OUT

200mV/div

I

OUT

5A/div

IN
20V/div

EN
5V/div

V

OUT

2V/div

PGOOD
5V/div

STARTUP AND DISABLE FROM IN

= 3.3kI)

(R

LOAD

20ms/div

MAX15046 toc14

IN
10V/div

V

OUT

2V/div

PGOOD
5V/div

STARTUP WITH PREBIASED

OUTPUT (4.0V)

4ms/div

MAX15046 toc15a

24V

IN
10V/div

4V

V

OUT

2V/div

PGOOD
5V/div

STARTUP WITH PREBIASED

OUTPUT (1.0V)

4ms/div

6 ______________________________________________________________________________________

MAX15046 toc15b

24V

IN
10V/div

1V

V

OUT

2V/div

PGOOD
5V/div

40V, High-Performance, Synchronous

STARTUP WITH PREBIASED

Buck Controller

Typical Operating Characteristics (continued)

(VIN = 24V, TA = +25NC, unless otherwise noted.)

MAX15046

OUTPUT (2V)

4ms/div

MAX15046 toc15c

V

OUT

= 3.3V

DH_ AND DL_ DISOVERLAP

40ns/div

24V

IN
10V/div

2V

V

OUT

2V/div

PGOOD
5V/div

MAX15046 toc17a

STARTUP WITH PREBIASED

OUTPUT (0.5V)

V

DH

20V/div

V

DL

5V/div

V

LX

20V/div

4ms/div

MAX15046 toc15d

V

OUT

= 3.3V

SINK CURRENT-LIMIT WAVEFORMS

24V

V

IN

10V/div

0.5V

V

OUT

2V/div

PGOOD
5V/div

DH_ AND DL_ DISOVERLAP

40ns/div

(5V PREBIASED)

200Fs/div

MAX15046 toc17b

MAX15046 toc16

V

DH

20V/div

V

DL

5V/div

V

LX

20V/div

V

OUT

500mV/div

V

LX

50V/div

I

LX

5A/div

OUTPUT SHORT-CIRCUIT BEHAVIOUR

OUTPUT VOLTAGE AND CURRENT

10ms/div

MAX15046 toc18

V

OUT

200mV/div

I

OUT

10A/div

LINE-TRANSIENT RESPONSE

10ms/div

MAX15046 toc19

24V

V

IN

200mV/div

5V

V

OUT

(AC-COUPLED)
200mV/div

_______________________________________________________________________________________ 7

MONITOR

40V, High-Performance, Synchronous
Buck Controller

Pin Description

PIN NAME FUNCTION

1 IN

2 V

MAX15046

3 PGOOD

4 EN

5 LIM

6 COMP Error-Amplifier Output. Connect compensation network from COMP to FB or from COMP to GND.

7 FB

8 RT

9 GND Analog Ground. Connect PGND and AGND together at a single point.

10 PGND Power Ground. Use PGND as a return path for the low-side MOSFET gate driver.

11 DRV

12 DL Low-Side External MOSFET Gate-Driver Output. DL swings from DRV to PGND.

13 BST

14 LX

15 DH High-Side External MOSFET Gate-Driver Output. DH swings from BST to LX.
16 CSP Current-Sense Positive Input. Connect to the drain of low-side MOSFET with Kelvin connection.

— EP

CC

Regulator Input. Connect to the input rail of the buck converter. Bypass IN to PGND with a 100nF
minimum ceramic capacitor. When operating in the 5V Q10% range, connect IN to VCC.

5.25V Linear Regulator Output. Bypass VCC to PGND with a ceramic capacitor of at least 4.7FF
when VCC supplies MOSFET gate-driver current at DRV or 2.2FF when VCC is not used to power
DRV.

Open-Drain Power-Good Output. Pull up PGOOD to an external power supply or output with an
external resistor.

Active-High Enable Input. Pull EN to GND to disable the buck converter output. Connect to VCC
for always-on operation. EN can be used for power sequencing and as a UVLO adjustment input.

Current-Limit Input. Connect a resistor from LIM to GND to program the current-limit threshold from
30mV (R

Feedback Input (Inverting Input of Error Amplifier). Connect FB to a resistive divider between the
buck converter output and GND to adjust the output voltage from 0.6V up to 0.85 x IN.

Oscillator-Timing Resistor Input. Connect a resistor from RT to GND to set the oscillator frequency
from 100kHz to 1MHz.

Gate-Driver Supply Voltage. DRV is internally connected to the low-side driver supply. Bypass DRV to
PGND with a 2.2FF minimum ceramic capacitor (see the Typical Application Circuits).

Boost Flying Capacitor Connection. Internally connected to the high-side driver supply. Connect a
ceramic capacitor of at least 100nF between BST and LX and a diode between BST and DRV for
the high-side MOSFET gate-driver supply.

Inductor Connection. Also serves as a return terminal for the high-side MOSFET driver current.
Connect LX to the switching side of the inductor.

Exposed Pad. EP is internally connected to ground. Connect EP to a large copper ground plane to
maximize thermal performance.

= 6kI) to 300mV (R

LIM

= 60kI).

LIM

8 ______________________________________________________________________________________

40V, High-Performance, Synchronous

Buck Controller

Functional Diagram

MAX15046

VREF

RT

ENABLE

EN

VREF

V_BGAP

VIN_OK

V_BGAP

V

CC

BGAP_OK

BGAP_OK

V_DRV

VIN_OK

LIM

IN

COMPARATOR

BGAP_OK

BANDGAP

OK

GENERATOR

INTERNAL

VOLTAGE

REGULATOR

V

CC

UVLO

DRV

UVLO

THERMAL

SHUTDOWN

AND ILIM
CURRENT

GENERATOR

IN

UVLO

MAX15046

EN_INT

BGAP_OK

VL_OK

VDRV_OK

SHUTDOWN

VIN_OK

OSCILLATOR

V

REF

V

BGAP

OSC ENABLE

DC-DC

OSCILLATOR

ENABLE

LOGIC

VIN_OK

I

BIAS

= 0.6V

= 1.24V

CK

AND

MAIN

BIAS

CURRENT

GENERATOR

BANDGAP

REFERENCE

HICCUP

VREF

CK

ENABLE

VREF

CK

DH_DL_ENABLE

HICCUP TIMEOUT

CURRENT-LIMIT

RAMP GENERATOR

CK

SINK

CURRENT-LIMIT

COMPARATOR

VALLEY

COMPARATOR

SOFT-START/STOP

AND

HICCUP

LOGIC

PWM

CONTROL

LOGIC

HICCUP TIMEOUT

RAMP

LIM/20

LIM/10

FB

DAC_VREF

DH_DL_ENABLE

HICCUP

VREF

G

M

PWM
COMPARATOR

PWM

HIGH-

SIDE

DRIVER

LOW-

SIDE

DRIVER

ENABLE

PGOOD
COMPARATOR

COMP

BST

DH

LX

CSP

DRV

DL

PGND

FB

PGOOD

GND

_______________________________________________________________________________________ 9

40V, High-Performance, Synchronous
Buck Controller

Detailed Description

The MAX15046 synchronous step-down controller oper­ates from a 4.5V to 40V input-voltage range and gener­ates an adjustable output voltage from 85% of the input­voltage down to 0.6V while supporting loads up to 25A.
As long as the device supply voltage is within 5.0V to

5.5V, the input power bus (VIN) can be as low as 3.3V.

The MAX15046 offers adjustable switching frequency
from 100kHz to 1MHz with an external resistor. The

MAX15046

adjustable switching frequency provides design flex­ibility in selecting passive components. The MAX15046
adopts an adaptive synchronous rectification to elimi­nate external freewheeling Schottky diodes and improve
efficiency. The device utilizes the on-resistance of the
external low-side MOSFET as a current-sense element.
The current-limit threshold voltage is resistor-adjustable
from 30mV to 300mV and is temperature-compensated,
so that the effects of the MOSFET R
over temperature are reduced. This current-sensing
scheme protects the external components from damage
during output overloaded conditions or output short­circuit faults without requiring a current-sense resistor.
Hiccup-mode current limit reduces power dissipation
during short-circuit conditions. The MAX15046 includes
a power-good output and an enable input with precise
turn-on/-off threshold to be used for monitoring and for
power sequencing.

The MAX15046 features internal digital soft-start that
allows prebias startup without discharging the output. The
digital soft-start function employs sink current limiting to
prevent the regulator from sinking excessive current when
the prebias voltage exceeds the programmed steady­state regulation level. The digital soft-start feature prevents
the synchronous rectifier MOSFET and the body diode of
the high-side MOSFET from experiencing dangerous lev­els of current while the regulator is sinking current from the
output. The MAX15046 shuts down at a +150NC junction
temperature to prevent damage to the device.

DS(ON)

DC-DC PWM Controller

The MAX15046 step-down controller uses a PWM volt­age-mode control scheme (see the Functional Diagram).
Control-loop compensation is external for providing max­imum flexibility in choosing the operating frequency and
output LC filter components. An internal transconduc­tance error amplifier produces an integrated error volt­age at COMP that helps to provide higher DC accuracy.
The voltage at COMP sets the duty cycle using a PWM

variation

comparator and a ramp generator. On the rising edge
of an internal clock, the high-side n-channel MOSFET
turns on and remains on until either the appropriate duty
cycle or the maximum duty cycle is reached. During
the on-time of the high-side MOSFET, the inductor cur­rent ramps up. During the second-half of the switching
cycle, the high-side MOSFET turns off and the low-side
n-channel MOSFET turns on. The inductor releases the
stored energy as the inductor current ramps down, pro­viding current to the output. Under overload conditions,
when the inductor current exceeds the selected valley
current-limit threshold (see the Current-Limit Circuit (LIM)
section), the high-side MOSFET does not turn on at the
subsequent clock rising edge and the low-side MOSFET
remains on to let the inductor current ramp down.

Internal 5.25V Linear Regulator

An internal linear regulator (VCC) provides a 5.25V nomi­nal supply to power the internal functions and to drive the
low-side MOSFET. Connect IN and V
using an external 5V Q10% power supply. The maximum
regulator input voltage (VIN) is 40V. Bypass IN to GND
with a 1FF ceramic capacitor. Bypass the output of the
linear regulator (VCC) with a 4.7FF ceramic capacitor to
GND. The VCC dropout voltage is typically 180mV. When
VIN is higher than 5.5V, V
MAX15046 also employs an undervoltage lockout circuit
that disables the internal linear regulator when V
falls below 3.6V (typical). The 400mV UVLO hysteresis
prevents chattering on power-up/power-down.

is typically 5.25V. The

VCC

together when

CC

VCC

MOSFET Gate Drivers (DH, DL)

DH and DL are optimized for driving large-size n-channel
power MOSFETs. Under normal operating conditions and
after startup, the DL low-side drive waveform is always
the complement of the DH high-side drive waveform,
with controlled dead time to prevent crossconduction or
“shoot-through.” An adaptive dead-time circuit monitors
the DH and DL outputs and prevents the opposite-side
MOSFET from turning on until the MOSFET is fully off.
Thus, the circuit allows the high-side driver to turn on
only when the DL gate driver has turned off preventing
the low side (DL) from turning on until the DH gate driver
has turned off.

The adaptive driver dead time allows operation without
shoot-through with a wide range of MOSFETs, minimiz­ing delays and maintaining efficiency. There must be a
low-resistance, low-inductance path from DL and DH to
the MOSFET gates for the adaptive dead-time circuits

10 _____________________________________________________________________________________

40V, High-Performance, Synchronous

to function properly. The stray impedance in the gate
discharge path can cause the sense circuitry to interpret
the MOSFET gate as “off” while the VGS of the MOSFET
is still high. To minimize stray impedance, use very short,
wide traces.

Synchronous rectification reduces conduction losses in
the rectifier by replacing the normal low-side Schottky
catch diode with a low-resistance MOSFET switch. The
MAX15046 features a robust internal pulldown transistor
with a typical 1I R
resistance prevents DL from being pulled up during the
fast rise time of the LX node, due to capacitive coupling
from the drain to the gate of the low-side synchronous
rectifier MOSFET.

High-Side Gate-Drive Supply (BST)

An external Schottky diode between BST and DH is
required to boost the gate voltage above LX providing
the necessary gate-to-source voltage to turn on the high­side MOSFET. The boost capacitor connected between
BST and LX holds up the voltage across the floating gate
driver during the high-side MOSFET on-time.

to drive DL low. This low on-

DS(ON)

Buck Controller

The charge lost in the boost capacitor for delivering the
gate charge is replenished when the high-side MOSFET
turns off and the LX node goes to ground. When LX is
low, the external diode between V
es the boost capacitor. See the Boost Capacitor and
Diode Selection section in the Applications Information
to choose the right boost capacitor and diode.

Enable Input (EN), Soft-Start, and Soft-Stop

Drive EN high to turn on the MAX15046. A soft-start
sequence starts to increase (step-wise) the reference
voltage of the error amplifier. The duration of the soft­start ramp is 2048 switching cycles and the resolution is
1/64th of the steady-state regulation voltage allowing a
smooth increase of the output voltage. A logic-low on EN
initiates a soft-stop sequence by stepping down the ref­erence voltage of the error amplifier. After the soft-stop
sequence is completed, the MOSFET drivers are both
turned off. See Figure 1.

Connect EN to VCC for always-on operation. Owing to
the accurate turn-on/-off thresholds, EN can be used
as a UVLO adjustment input, and for power sequencing
together with the PGOOD outputs.

and BST recharg-

DRV

MAX15046

UVLO

V

V

OUT

DAC_VREF

B

CC

EN

DH

DL

SYMBOL DEFINITION

DAC_VREF

Undervoltage threshold value is provided in

UVLO

the Electrical Characteristics table.

V

Internal 5.25V linear regulator output.

CC

Active-high enable input.

EN

V

Regulator output voltage.

OUT

Regulator internal soft-start and soft-stop signal.
Regulator high-side gate-driver output.

DH

Regulator low-side gate-driver output.

DL

V

rising while below the UVLO threshold.

A

CC

EN is low.

C D

E

2048 CLOCK

CYCLES

F

SYMBOL DEFINITION

B
C
D
E

F

G

H

I

G

2048 CLOCK
CYCLES

VCC is higher than the UVLO threshold. EN is low.

EN is pulled high. DH and DL start switching.
Normal operation.
V

drops below UVLO.

CC

V

goes above the UVLO threshold. DH and DL

CC

start switching. Normal operation.

EN is pulled low. V

EN is pulled high. DH and DL start switching.
Normal operation.

V

drops below UVLO.

CC

H IA

enters soft-stop.

OUT

Figure 1. Power On-Off Sequencing

______________________________________________________________________________________ 11

40V, High-Performance, Synchronous
Buck Controller

When the valley current limit is reached during soft-start,
the MAX15046 regulates to the output impedance times
the limited inductor current and turns off after 4096 clock
cycles. When starting up into a large capacitive load (for
example), the inrush current will not exceed the current­limit value. If the soft-start is not completed before 4096
clock cycles, the device turns off. The device remains
off for 8192 clock cycles before trying to soft-start again.
This implementation allows the soft-start time to be
automatically adapted to the time necessary to keep the

MAX15046

inductor current below the limit while charging the output
capacitor.

Power-Good Output (PGOOD)

The MAX15046 includes a power-good comparator to
monitor the output voltage and detect the power-good
threshold, fixed at 93% of the nominal FB voltage. The
open-drain PGOOD output requires an external pullup
resistor. PGOOD sinks up to 2mA of current while low.

PGOOD goes high (high-Z) when the regulator output
increases above 93% of the designed nominal regulated
voltage. PGOOD goes low when the regulator output volt­age drops to below 90% of the nominal regulated voltage.
PGOOD asserts low during the hiccup timeout period.

Startup into a Prebiased Output

When the MAX15046 starts into a prebiased output, DH
and DL are off so that the converter does not sink current
from the output. DH and DL do not start switching until
the PWM comparator commands the first PWM pulse.
The first PWM pulse occurs when the ramping reference
voltage increases above the FB voltage.

When the output voltage is biased above the output set
point, the controller tries to pull the output down to the
set point once the internal soft-start is complete. This
pulldown is controlled by the sink current limit, which is
slowly increased to its normal value to minimize output
undershoot.

Current-Limit Circuit (LIM)

The current-limit circuit employs a ‘valley’ and sink
current-sensing algorithm that uses the on-resistance
of the low-side MOSFET as a current-sensing element,
to eliminate costly sense resistors. The current-limit
circuit is also temperature compensated to track the
on-resistance variation of the MOSFET overtemperature.
The current limit is adjustable with an external resistor at
LIM and accommodates MOSFETs with a wide range of
on-resistance characteristics (see the Setting the Valley
Current Limit section). The adjustment range is from 0.3V

to 3V for the valley current limit, corresponding to resistor
values of 6kI to 60kI. The valley current-limit threshold
across the low-side MOSFET is precisely 1/10th of the
voltage at LIM, while the sink current-limit threshold is
1/20th of the voltage at LIM.

Valley current limit acts when the inductor current flows
towards the load, and CSP is more negative than PGND
during the low-side MOSFET on-time. If the magnitude of
the current-sense signal exceeds the valley current-limit
threshold at the end of the low-side MOSFET on-time, the
MAX15046 does not initiate a new PWM cycle and lets
the inductor current decay in the next cycle. The control­ler also ‘rolls back’ the internal reference voltage so that
the controller finds a regulation point determined by the
current-limit value and the resistance of the short. In this
manner, the controller acts as a constant current source.
This method greatly reduces inductor ripple current
during the short event, which reduces inductor sizing
restrictions and reduces the possibility for audible noise.
After 4096 clock cycles, the device goes into hiccup
mode. Once the short is removed, the internal reference
voltage soft-starts back up to the normal reference volt­age and regulation continues.

Sink current limit is implemented by monitoring the volt­age drop across the low-side MOSFET when CSP is
more positive than PGND. When the voltage drop across
the low-side MOSFET exceeds 1/20th of the voltage at
LIM at any time during the low-side MOSFET on-time, the
low-side MOSFET turns off and the inductor current flows
from the output through the body diode of the high-side
MOSFET. When the sink current limit activates, the DH/
DL switching sequence is no longer complementary and
both MOSFETs are turned off.

Carefully observe the PCB layout guidelines to ensure
that noise and DC errors do not corrupt the current­sense signals at CSP and PGND. Mount the MAX15046
close to the low-side MOSFET with short, direct traces
making a Kelvin-sense connection so that trace resis­tance does not add to R

of the low-side MOSFET.

DS(ON)

Hiccup Mode Overcurrent Protection

Hiccup mode overcurrent protection reduces power
dissipation during prolonged short-circuit or severe
overload conditions. An internal 3-bit counter counts up
on each switching cycle when the valley current-limit
threshold is reached. The counter counts down on each
switching cycle when the threshold is not reached, and
stops at zero (000). When the current-limit condition
persists and the counter reaches 111 (= 7 events), the

12 _____________________________________________________________________________________

40V, High-Performance, Synchronous

MAX15046 stops both DL and DH drivers and waits for
4096 switching cycles (hiccup timeout delay) before
attempting a new soft-start sequence. The hiccup-mode
protection remains active during the soft-start time.

Undervoltage Lockout

The MAX15046 provides an internal undervoltage lock­out (UVLO) circuit to monitor the voltage on VCC. The
UVLO circuit prevents the MAX15046 from operating
when VCC is lower than VUVLO. The UVLO threshold is
4V, with 400mV hysteresis to prevent chattering on the
rising/falling edge of the supply voltage. DL and DH stay
low to inhibit switching when the device is in undervolt­age lockout.

Thermal-Overload Protection

Thermal-overload protection limits total power dissipa­tion in the MAX15046. When the junction temperature of
the device exceeds +150NC, an on-chip thermal sensor
shuts down the device, forcing DL and DH low, which
allows the device to cool. The thermal sensor turns the
device on again after the junction temperature cools by
20NC. The regulator shuts down and soft-start resets
during thermal shutdown. Power dissipation in the LDO
regulator and excessive driving losses at DH/DL trigger
thermal-overload protection. Carefully evaluate the total
power dissipation (see the Power Dissipation section) to
avoid unwanted triggering of the thermal-overload pro­tection in normal operation.

Applications Information

Buck Controller

The maximum voltage conversion ratio is limited by the
maximum duty cycle (D

V D V (1-D ) V

OUT max DROP2 max DROP1

<

D -

V V

IN IN

where V

max

is the sum of the parasitic voltage drops

DROP1

in the inductor discharge path, including synchronous
rectifier, inductor, and PCB resistance. V
sum of the resistance in the charging path, including
high-side switch, inductor, and PCB resistance. In prac­tice, provide adequate margin to the above conditions
for good load-transient response.

Set the MAX15046 output voltage by connecting a resis­tive divider from the output to FB to GND (Figure 2).
Select R2 from between 4kI and 16kI. Calculate R1
with the following equation:

R R -1

1 2

where VFB = 0.59V (see the Electrical Characteristics
table) and V

can range from 0.6V to (0.85 O VIN).

OUT

Resistor R1 also plays a role in the design of the Type
III compensation network. Review the values of R1 and
R2 when using a Type III compensation network (see the
Type III Compensation Network (Figure 4) section).

):

max

× + ×

is the

DROP2

Setting the Output Voltage

 

 

V

=

OUT

 

 

V

 

FB

 

 

MAX15046

Effective Input-Voltage Range

The MAX15046 operates from 4.5V to 40V input supplies
and regulates output down to 0.6V. The minimum voltage
conversion ratio (V

OUT/VIN

) is limited by the minimum
controllable on-time. For proper fixed-frequency PWM
operation, the voltage conversion ratio must obey the
following condition:

V

OUT

t f

> ×

IN

ON(MIN) SW

is the switching fre-

SW

where t

ON(MIN)

V

is 125ns and f

quency in Hertz. Pulse skipping occurs to decrease the
effective duty cycle when the desired voltage conversion
does not meet the above condition. Decrease the switch­ing frequency or lower the input voltage VIN to avoid
pulse skipping.

______________________________________________________________________________________ 13

FB

MAX15046

Figure 2. Adjustable Output Voltage

OUT

R

1

R

2

40V, High-Performance, Synchronous
Buck Controller

Setting the Switching Frequency

An external resistor connecting RT to GND sets the
switching frequency (fSW). The relationship between fSW
and RRT is:

R

=

RT

17.3 10

f (1x10 ) x (f )

+

SW SW

where fSW is in kHz and R
300kHz switching frequency is set with R
Higher frequencies allow designs with lower inductor

MAX15046

9

×

-7 2

is in kI. For example, a

RT

= 49.9kI.

RT

values and less output capacitance. Peak currents and
I2R losses are lower at higher switching frequencies, but
core losses, gate-charge currents, and switching losses
increase.

Inductor Selection

Three key inductor parameters must be specified for
operation with the MAX15046: inductance value (L),
inductor saturation current (I

), and DC resistance

SAT

(RDC). To determine the inductance, select the ratio of
inductor peak-to-peak AC current to DC average cur­rent (LIR) first. For LIR values that are too high, the RMS
currents are high, and therefore I2R losses are high.
Use high-valued inductors to achieve low LIR values.
Typically, inductor resistance is proportional to induc­tance for a given package type, which again makes I2R
losses high for very low LIR values. A good compromise
between size and loss is a 30% peak-to-peak ripple cur­rent to average-current ratio (LIR = 0.3). The switching
frequency, input voltage, output voltage, and selected
LIR determine the inductor value as follows:

V (V - V )

OUT IN OUT

L

=

V f I LIR

× × ×

IN SW OUT

saturation current rating (I

) must be high enough to

SAT

ensure that saturation cannot occur below the maximum
current-limit value (I

CL(MAX)

), given the tolerance of the
on-resistance of the low-side MOSFET and of the LIM
reference current (I
select an inductor with a saturation current (I

where I

CL(TYP)

is the typical current-limit set point. The

factor 1.35 includes R

). Combining these conditions,

LIM

≥ ×

I 1.35 I

SAT CL(TYP)

DS(ON)

variation of 25% and 10%

SAT

) of:

for the LIM reference current error. A variety of inductors
from different manufacturers are available to meet this
requirement (for example, Vishay IHLP-4040DZ-1-5 and
other inductors from the same series).

Setting the Valley Current Limit

The minimum current-limit threshold must be high enough
to support the maximum expected load current with the
worst-case low-side MOSFET on-resistance value as the
R

of the low-side MOSFET is used as the current-

DS(ON)

sense element. The inductor’s valley current occurs at
I

LOAD(MAX)

minus one half of the ripple current. The

minimum value of the current-limit threshold voltage
(V

) must be higher than the voltage on the low-side

ITH

MOSFET during the ripple-current valley,

LIR

> × ×

V R I 1

ITH DS(ON,MAX) LOAD(MAX)

where R

DS(ON,MAX)

in I is the maximum on-resistance

 

−

 

2

 

of the low-side MOSFET at maximum load current
I

LOAD(MAX)

and is calculated from the following equation:

R R [1 TC (T - T )]= × + ×

where VIN, V

OUT

, and I

are typical values. The

OUT

DS(ON,MAX) DS(ON) MOSFET MAX AMB

switching frequency is set by RT (see Setting the
Switching Frequency section). The exact inductor value
is not critical and can be adjusted to make trade-offs
among size, cost, and efficiency. Lower inductor val­ues minimize size and cost, but also improve transient
response and reduce efficiency due to higher peak cur­rents. On the other hand, higher inductance increases
efficiency by reducing the RMS current.

where R

(in I is the on-resistance of the low-

DS(ON)

side MOSFET at ambient temperature T
Celsius), TC

MOSFET

is the temperature coefficient of
the low-side MOSFET in ppm/NC, and T
Celsius) is the temperature at maximum load current
I

LOAD(MAX)

. Obtain the R

DS(ON)

and TC

MOSFET data sheet.

Find a low-loss inductor with the lowest possible DC
resistance that fits in the allotted dimensions. The

14 _____________________________________________________________________________________

(in degrees

AMB

(in degrees

MAX

MOSFET

from the

40V, High-Performance, Synchronous

Connect an external resistor (R
to adjust the current-limit threshold, which is temper­ature-compensated with a temperature coefficient of

-2300ppm/NC. The relationship between the current-limit
threshold (V

R

LIM

where R

) and R

ITH

=

50 10 1 2300 (T - T

× × + ×

is in I, V

LIM

is:

LIM

10 V

6

−

 
 

is in V, T

ITH

NC.

An R

resistance range of 6kI to 60kI corresponds

LIM

to a current-limit threshold of 30mV to 300mV. Use 1%
tolerance resistors when adjusting the current limit to
minimize error in the current-limit threshold.

The input filter capacitor reduces peak current drawn
from the power source and reduces noise and voltage
ripple on the input caused by the switching circuitry. The
input capacitor must meet the ripple current requirement
(I

) imposed by the switching currents as defined by

RMS

the following equation:

I IV=

RMS LOAD(MAX)

I

attains a maximum value when the input volt-

RMS

age equals twice the output voltage (VIN = 2V
so I

RMS(MAX)

= I

LOAD(MAX)/2

nontantalum capacitors (ceramic, aluminum, polymer, or
OS-CON) are preferred at the inputs due to the robust­ness of nontantalum capacitors to accommodate high
inrush currents of systems being powered from very low
impedance sources. Additionally, two (or more) smaller­value low-ESR capacitors should be connected in paral­lel to reduce high-frequency noise.

The key selection parameters for the output capacitor
are capacitance value, ESR, and voltage rating. These
parameters affect the overall stability, output ripple volt­age, and transient response. The output ripple has two
components: variations in the charge stored in the output
capacitor, and the voltage drop across the capacitor’s
ESR caused by the current flowing into and out of the
capacitor:

DV

RIPPLE

= DV

) from LIM to GND

LIM

×

ITH

MAX AMB)

MAX

and T

AMB

are in

Input Capacitor

V (V - V )

OUT IN OUT

IN

. For most applications,

Output Capacitor

+ DV

ESR

Q

OUT

),

Buck Controller

The output-voltage ripple as a consequence of the ESR
and the output capacitance is:

V I ESR

∆ = ×

ESR P-P

I

V

∆ =

Q

I

= ×

P-P

where I

is the peak-to-peak inductor current ripple

P-P

(see the Inductor Selection section). Use these equa­tions for initial capacitor selection. Decide on the final
values by testing a prototype or an evaluation circuit.

Check the output capacitor against load-transient
response requirements. The allowable deviation of the
output voltage during fast load transients determines
the capacitor output capacitance, ESR, and equivalent
series inductance (ESL). The output capacitor supplies
the load current during a load step until the controller
responds with a higher duty cycle. The response time
(t

RESPONSE

) depends on the closed-loop bandwidth of
the converter (see the Compensation Design section).
The resistive drop across the ESR of the output capaci­tor, the voltage drop across the ESL (DV
capacitor, and the capacitor discharge, cause a voltage
droop during the load step.

Use a combination of low-ESR tantalum/aluminum elec­trolytic and ceramic capacitors for improved transient
load and voltage ripple performance. Nonleaded capac­itors and capacitors in parallel help reduce the ESL.
Keep the maximum output-voltage deviation below the
tolerable limits of the load. Use the following equations to
calculate the required ESR, ESL, and capacitance value
during a load step:

=

ESR

C

OUT

=

ESL

t

RESPONSE

where I
load step, t

is the load step, t

STEP

RESPONSE

ler, and fO is the closed-loop crossover frequency.

P-P

8 C f

× ×

OUT SW

 

V - V V

IN OUT OUT

 

f L V

×

SW IN

 

∆

V

ESR

I

STEP

I t

STEP RESPONSE

=

∆ ×

V t

ESL STEP

I

STEP

≅

 
 
 

×

∆

V

Q

1

×

3 f

O

is the rise time of the

STEP

ESL

) of the

is the response time of the control-

MAX15046

______________________________________________________________________________________ 15

40V, High-Performance, Synchronous
Buck Controller

Compensation Design

The MAX15046 provides an internal transconductance
amplifier with the inverting input and the output available
for external frequency compensation. The flexibility of
external compensation offers wide selection of output
filtering components, especially the output capacitor.
Use high-ESR aluminum electrolytic capacitors for cost­sensitive applications. Use low-ESR tantalum or ceramic
capacitors at the output for size-sensitive applications.

MAX15046

The high switching frequency of the MAX15046 allows
the use of ceramic capacitors at the output. Choose all
passive power components to meet the output ripple,
component size, and component cost requirements.
Choose the compensation components for the error
amplifier to achieve the desired closed-loop bandwidth
and phase margin.

To choose the appropriate compensation network type,
the power-supply poles and zeros, the zero-crossover
frequency, and the type of the output capacitor must be
determined first.

In a buck converter, the LC filter in the output stage intro­duces a pair of complex poles at the following frequency:

OUT OUT

π × ×

f

SW

f

≤

O

10

1

1

OUT

=

f

PO

π × ×

2 L C

The output capacitor introduces a zero at:

=

f

ZO

2 ESR C

where ESR is the equivalent series resistance of the
output capacitor.

The loop-gain crossover frequency (fO), where the loop
gain equals 1 (0dB) should be set below 1/10th of the
switching frequency:

Choosing a lower crossover frequency reduces the
effects of noise pickup into the feedback loop, such as
jittery duty cycle.

To maintain a stable system, two stability criteria must
be met:

1) The phase shift at the crossover frequency, fO, must
be less than 180N. In other words, the phase margin
of the loop must be greater than zero.

2) The gain at the frequency where the phase shift is

-180N (gain margin) must be less than 1.

Maintain a phase margin of around 60N to achieve a robust
loop stability and well-behaved transient response.

When using an electrolytic or large-ESR tantalum output
capacitor, the capacitor ESR zero fZO typically occurs
between the LC poles and the crossover frequency fO
(fPO < fZO < fO). Choose the Type II (PI-Proportional,
Integral) compensation network.

When using a ceramic or low-ESR tantalum output
capacitor, the capacitor ESR zero typically occurs above
the desired crossover frequency fO, that is fPO < f
fZO. Choose the Type III (PID- Proportional, Integral, and
Derivative) compensation network.

<

O

Type II Compensation Network

(Figure 3)

If fZO is lower than fO and close to fPO, the phase lead of
the capacitor ESR zero almost cancels the phase loss of
one of the complex poles of the LC filter around the cross­over frequency. Use a Type II compensation network with
a midband zero and a high-frequency pole to stabilize
the loop. In Figure 3, RF and CF introduce a midband
zero (fZ1). RF and CCF in the Type II compensation net­work provide a high-frequency pole (fP1), which mitigates
the effects of the output high-frequency ripple.

Use the following steps to calculate the component
values for Type II compensation network as shown in
Figure 3:

1) Calculate the gain of the modulator (GAIN
comprised of the regulator’s pulse-width modulator,
LC filter, feedback divider, and associated circuitry
at crossover frequency:

V V

IN FB

GAIN

where VIN is the input voltage of the regulator, V
is the amplitude of the ramp in the pulse-width modula­tor, VFB is the FB input voltage set point (0.6V typically,
see the Electrical Characteristics table), and V
desired output voltage.

The gain of the error amplifier (GAINEA) in midband
frequencies is:

where gM is the transconductance of the error amplifier.

= × ×

MOD

V 2 f L V

RAMP O OUT OUT

GAINEA = gM x R

ESR

π × ×

( )

F

OUT

MOD

RAMP

is the

),

16 _____________________________________________________________________________________

40V, High-Performance, Synchronous

I 1 I

1

1

The total loop gain, which is the product of the modulator
gain and the error-amplifier gain at fO, is:

1) GAIN GAIN 1

So :

V V

IN FB

V (2 f L ) V

OSC O OUT OUT

Solving for R :

R

=

F

× =

MOD EA

× × × × =

V 2 f L V

OSC O OUT OUT

ESR

π × ×

F

× π × × ×

( )

V V g ESR

× × ×

FB IN M

g R 1

M F

Buck Controller

Type III Compensation Network

(See Figure 4)

When using a low-ESR tantalum or ceramic type, the
ESR-induced zero frequency is usually above the tar­geted zero crossover frequency (fO). Use Type III com­pensation. Type III compensation provides two zeros
and three poles at the following frequencies:

=

f

Z1

π × ×

2 R C

F F

=

f

Z2

2 C (R R )

1

π × × +

MAX15046

2) Set a midband zero (fZ1) at 0.75 x fPO (to cancel one
of the LC poles):

= = ×

f 0.75 f

Z1 PO

1

π × ×

2 R C

F F

Solving for CF:

=

C

F

π × × ×

2 R f 0.75

1

F PO

3) Place a high-frequency pole at fP1 = 0.5 x fSW (to
attenuate the ripple at the switching frequency fSW)
and calculate CCF using the following equation:

=

C

CF

π × ×

V

OUT

R

1

R

2

V

REF

1

R f -

F SW

g

M

R

C

1

C

F

COMP

F

C

F

CF

Two midband zeros (fZ1 and fZ2) cancel the pair of com­plex poles introduced by the LC filter:

f

= 0

P1

fP1 introduces a pole at zero frequency (integrator) for
nulling DC output-voltage errors:

1

=

f

P2

π × ×

2 R C

I I

Depending on the location of the ESR zero (fZO), use fP2
to cancel fZO, or to provide additional attenuation of the
high-frequency output ripple:

=

f

P3

π × ×

2 R

F

×

C C

F CF

+

C C

F CF

fP3 attenuates the high-frequency output ripple.

Place the zeros and poles such that the phase margin
peaks around fO.

Ensure that RF >> 2/gM and the parallel resistance of
R1, R2, and RI is greater than 1/gM. Otherwise, a 180N
phase shift is introduced to the response making the
loop unstable.

Use the following compensation procedures:

1) With RF >> 10kI, place the first zero (fZ1) at 0.8 x
fPO:

= = ×

f 0.8 f

Z1 PO

1

π × ×

2 R C

F F

Figure 3. Type II Compensation Network

______________________________________________________________________________________ 17

40V, High-Performance, Synchronous
Buck Controller

So:

Once fP2 is known, calculate RI:

MAX15046

=

C

F

π × × ×

2 R 0.8 f

2) The gain of the modulator (GAIN
the pulse-width modulator, LC filter, feedback divider,
and associated circuitry at crossover frequency is:

MAX15046

GAIN

MOD

The gain of the error amplifier (GAINEA) in midband
frequencies is:

The total loop gain as the product of the modulator gain
and the error amplifier gain at fO is 1.

So :

V

IN

V

Solving for C :

3) Use the second pole (fP2) to cancel f
< fZO < f
does not flatten out soon after the 0dB crossover, and
maintains -20dB/decade slope up to 1/2 of the switching
frequency. This is likely to occur if the output capacitor
is low-ESR tantalum. Set fP2 = fZO.

When using a ceramic capacitor, the capacitor ESR
zero (fZO) is likely to be located even above one half
of the switching frequency, fPO < fO < f
this case, place the frequency of the second pole (fP2)
high enough in order not to significantly erode the phase
margin at the crossover frequency. For example, set fP2
at 5 x fO so that the contribution to phase loss at the
crossover frequency fO is only about 11N:

× × π × × × =

RAMP

(2 f ) C L

C

=

I

SW/2

V

IN

= ×

V

RAMP

GAIN 2 f C R

EA O I F

GAIN GAIN 1

MOD EA

1

2

π × × ×

O OUT OUT

I

V 2 f L C

× π × × ×

RAMP O OUT OUT

. The frequency response of the loop gain

( )

fP2 = 5 x f

1

F PO

), comprised of

MOD

1

2

π × × ×

(2 f ) L C

O OUT OUT

= π × × ×

× =

2 f C R 1

V R

×

IN F

ZO

SW/2

O

O I F

when fPO < f

< fZO. In

1

=

R

I

π × ×

2 f C

P2 I

4) Place the second zero (fZ2) at 0.2 x fO or at fPO,

whichever is lower and calculate R1 using the following
equation:

R - R

1 I

5) Place the third pole (fP3) at one half the switching

frequency and calculate CCF:

C

=

CF

2 0.5 f R C - 1

π × × × ×

( )

6) Calculate R2 as:

R R

= ×

2 1

1

=

2 f C

π × ×

Z2 I

V

FB

V V

OUT FB

C

F

SW F F

−

MOSFET Selection

The MAX15046 step-down controller drives two exter­nal logic-level n-channel MOSFETs. The key selection
parameters to choose these MOSFETs include:

U On-resistance (R

U Maximum Drain-to-Source Voltage (V

O

U Minimum Threshold Voltage (V

U Total Gate Charge (QG)

U Reverse Transfer Capacitance (C

U Power Dissipation

The two n-channel MOSFETs must be a logic-level
type with guaranteed on-resistance specifications at
VGS = 4.5V. For maximum efficiency, choose a high­side MOSFET that has conduction losses equal to the
switching losses at the typical input voltage. Ensure that
the conduction losses at minimum input voltage do not
exceed the MOSFET package thermal limits, or violate
the overall thermal budget. Also ensure that the conduc­tion losses plus switching losses at the maximum input
voltage do not exceed package ratings or violate the

DS(ON)

)

DS(MAX)

TH(MIN)

)

RSS

)

18 _____________________________________________________________________________________

40V, High-Performance, Synchronous

R

F

g

G_TOTAL

Q

=

∆

V

C

CF

C

F

M

x f

G

BST

= 100mV to 300mV)

BST

COMP

SW

V

OUT

R

R

I

1

C

I

R

2

Figure 4. Type III Compensation Network

V

REF

overall thermal budget. Ensure that the DL gate driver
can drive the low-side MOSFET. In particular, check
that the dv/dt caused by the high-side MOSFET turning
on does not pull up the low-side MOSFET gate through
the drain-to-gate capacitance of the low-side MOSFET,
which is the most frequent cause of crossconduction
problems.

Check power dissipation when using the internal linear
regulator to power the gate drivers. Select MOSFETs
with low gate charge so that VCC can power both drivers
without overheating the device:

P

= VCC x Q

DRIVE

where Q

G_TOTAL

is the sum of the gate charges of the

two external MOSFETs.

Boost Capacitor and Diode Selection

The MAX15046 uses a bootstrap circuit to generate
the necessary gate-to-source voltage to turn on the
high-side MOSFET. The selected n-channel high-side
MOSFET determines the appropriate boost capacitance
value (C

in the Typical Application Circuits) accord-

BST

ing to the following equation:

C

BST

where QG is the total gate charge of the high-side
MOSFET and DV

is the voltage variation allowed

BST

on the high-side MOSFET driver after turn-on. Choose
DV

such that the available gate-drive voltage is not

BST

significantly degraded (e.g. DV
when determining C

BST

.

Buck Controller

Use a low-ESR ceramic capacitor as the boost capacitor
with a minimum value of 100nF.

A small-signal diode can be used for the bootstrap cir­cuit and must have a minimum voltage rating of VIN +
3V to withstand the maximum BST voltage. The average
forward current of the diode should meet the following
requirement:

IF > Q

where Q

is the gate charges of the low-side MOSFET.

GATE

The maximum power dissipation of the device depends
on the thermal resistance from the die to the ambient
environment and the ambient temperature. The thermal
resistance depends on the device package, PCB copper
area, other thermal mass, and airflow.

The power dissipated into the package (PT) depends
on the supply configuration (see the Typical Application
Circuits). Use the following equation to calculate power
dissipation:

PT = VIN x [Q

where IQ is the quiescent supply current at the switching
frequency. See the IIN vs. Switching Frequency graph in
the Typical Operating Characteristics for the IQ.

Use the following equation to estimate the temperature
rise of the die:

TJ = TA + (PT x BJA)

where BJA is the junction-to-ambient thermal impedance
of the package, PT is power dissipated in the device,
and TA is the ambient temperature. The B
for the 16-pin QSOP and 53NC/W for the 16-pin QSOP­EP package on multilayer boards, with the conditions
specified by the respective JEDEC standards (JESD51-5,
JESD51-7). An accurate estimation of the junction tem­perature requires a direct measurement of the case
temperature (TC) when actual operating conditions
significantly deviate from those described in the JEDEC
standards. The junction temperature is then:

TJ = TC + (PT x BJC)

Use 37NC/W as BJC thermal impedance for the 16-pin
QSOP package and 6NC/W for the 16-pin QSOP-EP
package. The case-to-ambient thermal impedance (BCA)
is dependent on how well the heat is transferred from the
PCB to the ambient. Use large copper areas to keep the
PCB temperature low.

x f

GATE

G_TOTAL

SW

Power Dissipation

x fSW + IQ]

is 103.7NC/W

JA

MAX15046

______________________________________________________________________________________ 19

40V, High-Performance, Synchronous
Buck Controller

PCB Layout Guidelines

Careful PCB layout is critical to achieve clean and stable
operation. The switching power stage requires particular
attention. Follow these guidelines for good PCB layout:

1) Place decoupling capacitors as close as possible to
the IC. Connect the power ground plane (connected
to PGND) and signal ground plane (connected to
GND) at one point near the device.

2) Connect input and output capacitors to the power

MAX15046

ground plane; connect all other capacitors to the sig­nal ground plane.

3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current (C2 to
IN and C2 to PGND) short. Avoid vias in the switching
paths.

4) Connect CSP to the drain of the low-side FET using a
Kelvin connection for accurate current-limit sensing.

5) Ensure all feedback connections are short and direct.
Place the feedback resistors as close as possible to the
IC.

6) Route high-speed switching nodes (BST, LX, DH, and
DL) away from sensitive analog areas (RT, FB, COMP,
and LIM).

24V Supply, 3.3V Output Operation

Typical Application Circuit 1 in the Typical Application
Circuits section shows an application circuit that oper-

ates out of 24V and outputs up to 10A at 3.3V. R5 sets
the switching frequency to 350kHz.

Single 4.5V to 5.5V Supply Operation

Typical Application Circuit 2 in the Typical Application
Circuits section shows an application circuit for a single

+4.5V to +5.5V power-supply operation.

Auxiliary 5V Supply Operation

Typical Application Circuit 3 in the Typical Application
Circuits section shows an application circuit for a +24V

supply to drive the external MOSFETs and an auxiliary
+5V supply to power the device

20 _____________________________________________________________________________________

40V, High-Performance, Synchronous

Buck Controller

Typical Application Circuits

TYPICAL APPLICATION CIRCUIT 1

V

IN

+24V

330FF

C1

10FF

C2

10FF

C3

C4

0.1FF

MAX15046

ON

OFF

R9

32.4kI

Q1: VISHAY SILICONIX Si7850DP
Q2: VISHAY SILICONIX Si7460DP
D1: DIODES INC. ZHCS506
L1: COILCRAFT MSS1278-142ML
C1: PANASONIC EEVFK1H331Q
C8: SANYO 6CE470EX

C13
68pF

R7
51kI

22.6kI

C14

1500pF

10.7kI

R4

45.3kI

R3

CSP

DRV

PGND

GND

BST

Q1

R1
1kI

C7
2700pF

L1

1.4mH

470FF

C8

C9

22FF

22FF

DH

LX

DL

C5

0.47FF

C6

2.2FF

D1

R2

2.2I

C11

4.7FF

Q2

C10

V

+3.3V

OUT

R6
10kI

R5

32.4kI

IN

V

CC

PGOOD

EN

LIM

COMP

FB

RT

MAX15046

C12

1200pF

C16
1FF

R8

C15
15pF

______________________________________________________________________________________ 21

40V, High-Performance, Synchronous
Buck Controller

Typical Application Circuits (continued)

TYPICAL APPLICATION CIRCUIT 2

V

IN

+4.5V TO +5.5V

C1

C2

MAX15046

PGOOD

ENABLE

R4

C7

V

AUX

+4.5V TO +5.5V

C1

PGOOD

ENABLE

R4

C7

IN

MAX15046

V

CC

PGOOD

EN

LIM

COMP

R3

C8

C9

R1

FB

RT

R3

CSP

DH

LX

C3

BST

DL

D1

DRV

C6

PGND

GND

R2

Q1

L1

Q2

C4

V

OUT

C5

TYPICAL APPLICATION CIRCUIT 3

V

IN

+24V

C2

IN

MAX15046

V

CC

PGOOD

EN

LIM

COMP

R3

C8

C9

R1

FB

RT

R3

CSP

BST

DRV

PGND

GND

Q1

DH

LX

C3

DL

D1

C6

L1

Q2

C4

V

OUT

C5

R2

22 _____________________________________________________________________________________

40V, High-Performance, Synchronous

Buck Controller

Pin Configurations

MAX15046

TOP VIEW

+

V

PGOOD

LIM

COMP

IN

1

2

CC

3

MAX15046A

4

EN

5

6

7

FB

RT

8

16

CSP

15

DH

14

LX

13

BST

12

DL

DRV

11

10

PGND

9

GND

QSOP

Chip Information

PROCESS: BiCMOS

+

V

PGOOD

LIM

COMP

IN

1

2

CC

3

4

EN

MAX15046B

5

6

EXPOSED

7

FB

RT

8

PAD

16

CSP

15

DH

14

LX

13

BST

12

DL

DRV

11

10

PGND

9

GND

QSOP-EP

Package Information

For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

16 QSOP E16+4

16 QSOP-EP E16E+9

21-0055

21-0112

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 23

©

2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.