General Description
The MAX15040 high-efficiency switching regulator
delivers up to 4A load current at output voltages from
0.6V to (0.9 x V
IN
). The device operates from 2.4V to
3.6V, making it ideal for on-board point-of-load and
postregulation applications. Total output-voltage accuracy is within ±1% over load, line, and temperature.
The MAX15040 features 1MHz fixed-frequency PWM
mode operation. The high operating frequency allows
for small-size external components.
The low-resistance on-chip nMOS switches ensure high
efficiency at heavy loads while minimizing critical parasitic
inductances, making the layout a much simpler task with
respect to discrete solutions. Following a simple layout
and footprint ensures first-pass success in new designs.
The MAX15040 incorporates a high-bandwidth
(> 15MHz) voltage-error amplifier. The voltage-mode
control architecture and the voltage-error amplifier permit a Type III compensation scheme to achieve maximum loop bandwidth, up to 200kHz. High loop
bandwidth provides fast transient response, resulting in
less required output capacitance and allowing for allceramic capacitor designs.
The MAX15040 features an output overload hiccup protection and peak current limit on both high-side (sourcing current) and low-side (sinking and sourcing current)
MOSFETs, for ultra-safe operations in case of high output prebias, short-circuit conditions, severe overloads,
or in converters with bulk electrolytic capacitors.
The MAX15040 features an adjustable output voltage.
The output voltage is adjustable by using two external
resistors at the feedback or by applying an external reference voltage to the REFIN/SS input. The MAX15040
offers programmable soft-start time using one capacitor
to reduce input inrush current. A built-in thermal shutdown protection assures safe operation under all conditions. The MAX15040 is available in a 2mm x 2mm,
16-bump (4 x 4 array), 0.5mm pitch WLP package.
Applications
Server Power Supplies
Point-of-Load
ASIC/CPU/DSP Core and I/O Voltages
DDR Power Supplies
Base-Station Power Supplies
Telecom and Networking Power Supplies
RAID Control Power Supplies
Features
o Internal 15mΩ R
DS(ON)
MOSFETs
o Continuous 4A Output Current
o ±1% Output-Voltage Accuracy Over Load, Line,
and Temperature
o Operates from 2.4V to 3.6V Supply
o Adjustable Output from 0.6V to (0.9 x V
IN
)
o Adjustable Soft-Start Reduces Inrush Supply
Current
o Factory-Trimmed 1MHz Switching Frequency
o Compatible with Ceramic, Polymer, and
Electrolytic Output Capacitors
o Safe Startup into Prebias Output
o Enable Input/Power-Good Output
o Fully Protected Against Overcurrent and
Overtemperature
o Overload Hiccup Protection
o Sink/Source Current in DDR Applications
o 2mm x 2mm, 16-Bump (4 x 4 Array), 0.5mm Pitch
WLP Package
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-4426; Rev 2; 7/10
EVALUATION KIT
AVAILABLE
+
Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration appears at end of data sheet.
OUTPUT
INPUT
2.4V TO 3.6V
BST
LX
IN
EN
V
DD
GND
FB
V
DD
COMP
PWRGD
REFIN/SS
GND
MAX15040
Typical Operating Circuit
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
M AX 15040E WE + - 40°C to + 85°C 16 WLP
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN= VDD= 3.3V, TA = -40°C to +85°C. Typical values are at TA= +25°C, circuit of Figure 1, unless otherwise noted.) (Note 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN, VDD, PWRGD to GND ......................................-0.3V to +4.5V
LX to GND....................-0.3V to the lower of 4.5V or (V
IN
+ 0.3V)
LX Transient ..............(V
GND
- 1.5V, <50ns), (VIN+ 1.5V, <50ns)
COMP, FB, REFIN/SS,
EN to GND..............-0.3V to the lower of 4.5V or (V
DD
+ 0.3V)
LX RMS Current (Note 1) .........................................................5A
BST to LX..................................................................-0.3V to +4V
BST to GND ..............................................................-0.3V to +8V
Continuous Power Dissipation (T
A
= +70°C)
16-Bump (4 x 4 Array), 0.5mm Pitch WLP
(derated 12.5mW/°C above +70°C)...........................1000mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Continuous Operating Temperature at
Full Load Current (Note 2) ...........................................+105°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature (reflow) .......................................+260°C
Note 1: LX has internal clamp diodes to GND and IN. Applications that forward bias these diodes should take care not to exceed
the package power dissipation limit of the device.
Note 2: Continuous operation at full current beyond +105°C may degrade product life.
IN/V
IN and V
IN Supply Current No load, no switching
VDD Supply Current No load, no switching
Total Supply Current (IN + VDD) No load
Total Shutdown Current from IN
and V
VDD Undervoltage Lockout
Threshold
VDD UVLO Deglitching 2µs
BST
BST Leakage Current
PWM COMPARATOR
PWM Comparator Propagation
Delay
COMP
COMP Clamp Voltage High V
COMP Clamp Voltage Low V
COMP Slew Rate 1.6 V/µs
PWM Ramp Valley VDD = 2.4V to 3.6V 830 mV
PWM Ramp Amplitude 1V
COMP Shutdown Resistance From COMP to GND, VEN = 0V 8 Ω
PARAMETER CONDITIONS MIN TYP MAX UNITS
DD
Voltage Range 2.40 3.60 V
DD
VIN = 2.5V 0.52 1
= 3.3V 0.8 1.5
V
IN
VIN = 2.5V 3.7 5.5
= 3.3V 4 6
V
IN
VIN = VDD = 2.5V 12
= VDD = 3.3V 23
V
IN
DD
VIN = VDD = V
LX starts/stops switching
V
= V
BST
DD
= 3.6V or 0V, VEN = 0V
V
LX
10mV overdrive 10 ns
= 2.4V to 3.6V 2.03 V
DD
= 2.4V to 3.6V 0.73 V
DD
- VLX = 3.6V, VEN = 0V 0.1 2 µA
BST
VDD rising 2 2.2
falling 1.75 1.9
V
DD
= V
IN
= 3.6V,
TA = +25°C 2
T
= +85°C 0.025
A
mA
mA
mA
V
µA
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VIN= VDD= 3.3V, TA = -40°C to +85°C. Typical values are at TA= +25°C, circuit of Figure 1, unless otherwise noted.) (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
ERROR AMPLIFIER
FB Regulation Accuracy Using internal reference 0.594 0.600 0.606 V
Open-Loop Voltage Gain 1kΩ from COMP to GND (Note 4) 115 dB
Error-Amplifier Unity-Gain
Bandwidth
Error-Amplifier Common-Mode
Input Range
Error-Amplifier Minimum Output
Current
FB Input Bias Current VFB = 0.7V, using internal reference, TA = +25°C -200 -100 nA
REFIN/SS
REFIN/SS Charging Current V
REFIN/SS Discharge Resistance 520 Ω
REFIN/SS Common-Mode Range
REFIN/SS Offset Voltage Error amplifier offset
LX (ALL BUMPS COMBINED)
LX On-Resistance, High Side ILX = -0.4A
LX On-Resistance, Low Side ILX = 0.4A
LX Peak Current-Limit Threshold VIN = 2.5V
LX Switching Frequency VIN = 2.5V to 3.3V, TA = +25°C 0.92 1 1.03 MHz
LX Maximum Duty Cycle VIN = 2.5V to 3.3V, TA = +25°C 92 96 %
LX Minimum On-Time 80 ns
RMS LX Output Current 4A
ENABLE
EN Input Logic-Low Threshold 0.7 V
EN Input Logic-High Threshold 1.7 V
EN Input Current
Series 5kΩ, 100nF from COMP to GND (Note 4) 26 MHz
V
= 2.4V to 2.6V 0 VDD - 1.80
DD
V
= 2.6V to 3.6V 0 VDD - 1.85
DD
V
= 1.2V, sinking 500
COMP
V
= 1.0V, sourcing 1000
COMP
REFIN/SS
VDD = 2.4V to 2.6V 0 V
V
DD
V
EN
V
IN
= 0.45V 7 8 9 µA
= 2.6V to 3.6V 0 V
TA = +25°C 30 µV
-4.5 +4.5 mV
= 0 or 3.6V,
= VDD = 3.6V
VIN = V
= V
V
IN
VIN = 2.5V 16
V
= 3.3V 15
IN
High-side sourcing 5.5 7
Low-side sinking 5.5 7
TA = +25°C
= +85°C 0.2
T
A
TA = +25°C 1
T
= +85°C 0.3
A
- V
BST
LX
- V
BST
LX
VLX = 0V -2
V
LX
= 2.5V 21
= 3.3V 19
= 3.6V +2LX Leakage Current VIN = 3.6V, VEN = 0V
DD
DD
- 1.80
- 1.85
V
µA
V
mΩ
mΩ
A
µA
µA
EFFICIENCY
vs. OUTPUT CURRENT
MAX15040 toc01
OUTPUT CURRENT (A)
EFFICIENCY (%)
1
50
60
70
80
90
100
40
0.1 10
VDD = VIN = 3.3V
V
OUT
= 1.2V
V
OUT
= 1.8V
V
OUT
= 1.5V
V
OUT
= 2.5V
EFFICIENCY
vs. OUTPUT CURRENT
MAX15040 toc02
OUTPUT CURRENT (A)
EFFICIENCY (%)
1
50
60
70
80
90
100
40
0.1 10
VIN = VDD = 2.5V
V
OUT
= 1.8V
V
OUT
= 1.2V
V
OUT
= 1.5V
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
4 _______________________________________________________________________________________
Note 3: Specifications are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by
design and characterization.
Note 4: Guaranteed by design.
ELECTRICAL CHARACTERISTICS (continued)
(VIN= VDD= 3.3V, TA = -40°C to +85°C. Typical values are at TA= +25°C, circuit of Figure 1, unless otherwise noted.) (Note 3)
Typical Operating Characteristics
(VIN= VDD= 3.3V, output voltage = 1.8V, I
LOAD
= 4A, and TA = +25°C, circuit of Figure 1, unless otherwise noted.)
THERMAL SHUTDOWN
Thermal-Shutdown Threshold Rising +165 °C
Thermal-Shutdown Hysteresis 20 °C
POWER-GOOD (PWRGD)
Power-Good Threshold Voltage
Power-Good Edge Deglitch VFB falling or rising 48
PWRGD Output-Voltage Low I
PWRGD Leakage Current V
OVERCURRENT LIMIT (HICCUP MODE)
Current-Limit Startup Blanking 112
Restart Time 896
FB Hiccup Threshold VFB falling 70
Hiccup Threshold Blanking Time VFB falling 36 µs
PARAMETER CONDITIONS MIN TYP MAX UNITS
VFB falling, V
rising, V
V
FB
= 4mA (sinking) 0.03 0.15 V
PWRGD
= V
DD
PWRGD
REFIN/SS
REFIN/SS
= 0.6V 87 90 93
= 0.6V 92.5
= 3.6V, V
= 0.9V 0.01 µA
FB
% of
V
RE F IN /S S
Clock
cycles
Clock
cycles
Clock
cycles
% of
V
RE F IN /S S
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
_______________________________________________________________________________________
5
Typical Operating Characteristics (continued)
(VIN= VDD= 3.3V, output voltage = 1.8V, I
LOAD
= 4A, and TA = +25°C, circuit of Figure 1, unless otherwise noted.)
EFFICIENCY
vs. OUTPUT CURRENT
100
90
80
70
EFFICIENCY (%)
V
OUT
60
50
VDD = 3.3V
= 2.5V
V
IN
40
0.1 10
V
= 1.8V
OUT
V
= 1.5V
OUT
= 1.2V
1
OUTPUT CURRENT (A)
MAX15040 toc03
LOAD REGULATION
0.10
0
-0.10
V
= 2.5V
-0.20
-0.30
OUTPUT VOLTAGE ERROR (%)
-0.40
-0.50
OUT
V
= 1.8V
OUT
V
= 1.5V
OUT
V
INTERNAL REFERENCE
04
LOAD CURRENT (A)
OUT
321
MAX15040 toc06
= 1.2V
vs. INPUT VOLTAGE
1.20
1.15
1.10
1.05
1.00
0.95
FREQUENCY (MHz)
0.90
TA = -40°C
0.85
0.80
2.4 3.6
LOAD-TRANSIENT RESPONSE
V
OUT
I
OUT
FREQUENCY
TA = +85°C
TA = +25°C
INPUT VOLTAGE (V)
40µs/div
3.43.22.6 2.8 3.0
MAX15040 toc07
0.5
0.4
MAX15040 toc04
AC-COUPLED
100mV/div
1A/div
0
0.3
0.2
0.1
-0.1
-0.2
OUTPUT VOLTAGE ERROR (%)
-0.3
-0.4
-0.5
V
LINE REGULATION
V
= 1.2V
OUT
0
V
= 1.8V
OUT
2.4 3.6
INPUT VOLTAGE (V)
SWITCHING WAVEFORMS
OUT
I
LX
V
LX
400ns/div
3.43.23.02.82.6
MAX15040 toc08
MAX15040 toc05
AC-COUPLED
50mV/div
2A/div
0
2V/div
0
SHUTDOWN WAVEFORM
V
EN
V
OUT
10µs/div
MAX15040 toc09
I
OUT
= 1.8A
2V/div
0
1V/div
0
V
EN
V
OUT
SOFT-START WAVEFORM
400µs/div
MAX15040 toc10
2V/div
0
1V/div
0
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VIN= VDD= 3.3V, output voltage = 1.8V, I
LOAD
= 4A, and TA = +25°C, circuit of Figure 1, unless otherwise noted.)
STARTING INTO PREBIAS OUTPUT
WITH 2A LOAD
MAX15040 toc16
400µs/div
V
EN
I
OUT
V
OUT
2V/div
0
0
0
0
V
PWRGD
2V/div
1V/div
2A/div
STARTING INTO PREBIAS OUTPUT
WITH NO LOAD
MAX15040 toc17
400µs/div
V
EN
V
OUT
2V/div
0
0
0
V
PWRGD
2V/div
1V/div
INPUT SHUTDOWN CURRENT
vs. INPUT VOLTAGE
20
16
12
8
4
INPUT SHUTDOWN CURRENT (nA)
0
2.4 3.6
INPUT VOLTAGE (V)
0.610
0.608
0.606
0.604
0.602
0.600
0.598
0.596
FEEDBACK VOLTAGE (V)
0.594
0.592
0.590
-40 85
V
= 0
EN
3.43.23.02.82.6
FEEDBACK VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
MAX15040 toc11
NO LOAD
603510-15
HICCUP CURRENT LIMIT
V
OUT
I
OUT
I
IN
1ms/div
MAX15040 toc12
1V/div
0
10A/div
0
5A/div
0
SOFT-START WITH REFIN/SS
I
V
REFIN/SS
V
PWRGD
IN
V
OUT
MAX15040 toc14
SHORT CIRCUIT vs. INPUT VOLTAGE
0.5
0.4
0.3
0.2
RMS INPUT CURRENT (A)
0.1
0
2.4 3.6
INPUT VOLTAGE (V)
MAX15040 toc15
2A/div
0
500mV/div
0
1V/div
0
2V/div
0
200µs/div
MAX15040 toc13
V
= 0
OUT
3.43.23.02.82.6
RMS INPUT CURRENT DURING
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(VIN= VDD= 3.3V, output voltage = 1.8V, I
LOAD
= 4A, and TA = +25°C, circuit of Figure 1, unless otherwise noted.)
Pin Description
STARTING INTO PREBIAS OUTPUT ABOVE
NOMINAL SETPOINT WITH NO LOAD
V
EN
V
OUT
V
PWRGD
1ms/div
CASE TEMPERATURE
MAX15040 toc18
2V/div
1V/div
0
2V/div
0
120
100
CASE TEMPERATURE (°C)
vs. AMBIENT TEMPERATURE
CASE = TOP SIDE OF DEVICE
MEASURED ON A MAX15040EVKIT
80
60
40
20
0
-20
-40
-40 85
AMBIENT TEMPERATURE (°C)
BUMP NAME FUNCTION
A1, A2 GND
A3, A4 IN
B1, B2,
B3
LX
B4 V
C1 BST
C2, C3 I.C. Internally Connected. Leave unconnected or connect to ground.
C4 EN Enable Input. Connect EN to GND to disable the device. Connect EN to VDD to enable the device.
D1 PWRGD
D2 FB
D3 COMP
D4 REFIN/SS
Analog/Power Ground. Connect GND to the PCB ground plane at one point near the input bypass
capacitor return terminal as close as possible to the device.
Power-Supply Input. Input supply range is from 2.4V to 3.6V. Bypass IN to GND with a 22µF ceramic
capacitor in parallel to a 0.1µ F ceramic capacitor as close as possible to the device.
Inductor Connection. All LX bumps are internally connected together. Connect all LX bumps to the
switched side of the inductor. LX is high impedance when the device is in shutdown mode.
Supply Input. VDD powers the internal analog core. Connect VDD to IN with a 10Ω resistor. Connect a 1µF
DD
ceramic capacitor from V
to GND.
DD
High-Side MOSFET Driver Supply. Bypass BST to LX with a 0.1µF capacitor.
Power-Good Output. PWRGD is an open-drain output that goes high impedance when V
of V
REFIN/SS
V
REFIN/SS
mode, V
and V
or V
DD
REFIN/SS
REFIN/SS
is below the internal UVLO threshold, or the device is in thermal shutdown.
is above 0.54V. PWRGD is internally pulled low when VFB falls below 90% of
is below 0.54V. PWRGD is internally pulled low when the device is in shutdown
Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to GND to set
the output voltage from 0.6V to 90% of V
.
IN
Voltage-Error Amplifier Output. Connect the necessary compensation network from COMP to FB and the
converter output (see the Compensation Design section). COMP is internally pulled to GND when the
device is in shutdown mode.
External Reference Input/Soft-Start Timing Capacitor Connection. Connect REFIN/SS to a system voltage to
force FB to regulate to REFIN/SS voltage. REFIN/SS is internally pulled to GND when the device is in
shutdown and thermal shutdown mode. If no external reference is applied, the internal 0.6V reference is
automatically selected. REFIN/SS is also used to perform soft-start. Connect a minimum of 1nF capacitor
from REFIN/SS to GND to set the startup time (see the Soft-Start and Reference Input (REFIN/SS) section).
MAX15040 toc19
I
= 4A
OUT
6035-15 10
exceeds 92.5%
FB
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
8 _______________________________________________________________________________________
Block Diagram
V
DD
MAX15040
EN
REFIN/SS
FB
SHUTDOWN
CONTROL
BIAS
GENERATOR
VOLTAGE
REFERENCE
SOFT-START
ERROR
AMPLIFIER
UVLO
CIRCUITRY
THERMAL
SHUTDOWN
CURRENT-LIMIT
PWM
COMPARATOR
COMPARATOR
SHDN
CONTROL
LOGIC
CURRENT-LIMIT
COMPARATOR
LX
ILIM THRESHOLD
BST SWITCH
IN
ILIM
THRESHOLD
BST
IN
LX
GND
1V
P-P
OSCILLATOR
COMP
SHDN
COMP CLAMPS
FB
0.9 x V
REFIN/SS
PWRGD
GND
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
_______________________________________________________________________________________ 9
Figure 1. All-Ceramic Capacitor Design with V
OUT
= 1.8V
Detailed Description
The MAX15040 high-efficiency, voltage-mode switching
regulator is capable of delivering up to 4A of output
current. The MAX15040 provides output voltages from
0.6V to (0.9 x VIN) from 2.4V to 3.6V input supplies,
making it ideal for on-board point-of-load applications.
The output-voltage accuracy is better than ±1% over
load, line, and temperature.
The MAX15040 features a 1MHz fixed switching frequency, allowing the user to achieve all-ceramic capacitor
designs and fast transient responses. The high operating
frequency minimizes the size of external components.
The MAX15040 is available in a 2mm x 2mm, 16-bump
(4 x 4 array), 0.5mm pitch WLP package. The REFIN/SS
function makes the MAX15040 an ideal solution for DDR
and tracking power supplies. Using internal low-R
DSON
(15mΩ) n-channel MOSFETs for both high- and low-side
switches maintains high efficiency at both heavy-load
and high-switching frequencies.
The MAX15040 employs voltage-mode control architecture with a high-bandwidth (> 15MHz) error amplifier.
The op-amp voltage-error amplifier works with Type III
compensation to fully utilize the bandwidth of the highfrequency switching to obtain fast transient response.
Adjustable soft-start time provides flexibilities to minimize input startup inrush current. An open-drain,
power-good (PWRGD) output goes high impedance
when VFBexceeds 92.5% of V
REFIN/SS
and V
REFIN/SS
is above 0.54V. PWRGD goes low when VFBfalls below
90% of V
REFIN/SS
or V
REFIN/SS
is below 0.54V.
Controller Function
The controller logic block is the central processor that
determines the duty cycle of the high-side MOSFET
under different line, load, and temperature conditions.
Under normal operation, where the current-limit and temperature protection are not triggered, the controller logic
block takes the output from the PWM comparator and
generates the driver signals for both high-side and lowside MOSFETs. The control logic block controls the
break-before-make logic and the timing for charging the
bootstrap capacitors. The error signal from the voltageerror amplifier is compared with the ramp signal generated by the oscillator at the PWM comparator to produce
the required PWM signal. The high-side switch turns on
at the beginning of the oscillator cycle and turns off when
the ramp voltage exceeds the V
COMP
signal or the current-limit threshold is exceeded. The low-side switch
then turns on for the remainder of the oscillator cycle.
Typical Application Circuit
INPUT
2.4V TO 3.6V
R1
10Ω
C5
1µF
22µF
IN
IN
V
DD
EN
REFIN/SS
MAX15040
GND
0.1µF
C3
ON
OFF
C8
0.033µF
C1
BST
BST
U1
LX
LX
LX
GND
FB
COMP
PWRGD
C9
0.1µF
0.47µH
C11
820pF
L1
C12
33pF
R4
5.1kΩ
R10
2.2Ω
R5
20kΩ
430Ω
C10
470pF
R6
V
DD
C15
1000pF
OPTIONAL
C2
22µF
OUTPUT
1.8V/4A
C4
0.01µF
R3
8.06kΩ
1%
R7
4.02kΩ
1%
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
10 ______________________________________________________________________________________
Current Limit
The internal, high-side MOSFET has a typical 7A peak current-limit threshold. When current flowing out of LX
exceeds this limit, the high-side MOSFET turns off and the
low-side MOSFET turns on. The low-side MOSFET
remains on until the inductor current falls below the lowside current limit. This lowers the duty cycle and causes
the output voltage to droop until the current limit is no
longer exceeded. The MAX15040 uses a hiccup mode to
prevent overheating during short-circuit output conditions.
During current limit, if VFBdrops below 70% of
V
REFIN/SS
and stays below this level for typically 36µs
(12µs min) or more, the device enters hiccup mode.
The high-side MOSFET and the low-side MOSFET turn
off and both COMP and REFIN/SS are internally pulled
low. The device remains in this state for 896 clock
cycles and then attempts to restart for 112 clock
cycles. If the fault-causing current limit has cleared, the
device resumes normal operation. Otherwise, the
device reenters hiccup mode.
Soft-Start and Reference Input (REFIN/SS)
The MAX15040 utilizes an adjustable soft-start function
to limit inrush current during startup. An 8µA (typ) current source charges an external capacitor connected to
REFIN/SS. The soft-start time is adjusted by the value of
the external capacitor from REFIN/SS to GND. The
required capacitance value is determined as:
where tSSis the required soft-start time in seconds.
Connect a minimum 1nF capacitor between REFIN/SS
and GND. REFIN/SS is also an external reference input
(REFIN/SS). The device regulates FB to the voltage
applied to REFIN/SS. The internal soft-start is not available when using an external reference. Figure 2 shows
a method of soft-start when using an external reference. If an external reference is not applied, the device
uses the internal 0.6V reference.
Undervoltage Lockout (UVLO)
The UVLO circuitry inhibits switching when VDDis
below 1.9V (typ). Once VDDrises above 2V (typ), UVLO
clears and the soft-start function activates. A 100mV
hysteresis is built in for glitch immunity.
BST
The gate-drive voltage for the high-side, n-channel
switch is generated by a flying-capacitor boost circuit.
The capacitor between BST and LX is charged from the
VINsupply while the low-side MOSFET is on. When the
low-side MOSFET is switched off, the voltage of the
capacitor is stacked above LX to provide the necessary
turn-on voltage for the high-side internal MOSFET.
Power-Good Output (PWRGD)
PWRGD is an open-drain output that goes high
impedance when VFBis above 92.5% x V
REFIN/SS
and
V
REFIN/SS
is above 0.54V. PWRGD pulls low when V
FB
is below 90% of V
REFIN/SS
for at least 48 clock cycles
or V
REFIN/SS
is below 0.54V. PWRGD is low during
shutdown.
Setting the Output Voltage
The MAX15040 output voltage is adjustable from 0.6V
to 90% of VINby connecting FB to the center tap of a
resistor-divider between the output and GND (Figure
3). To determine the values of the resistor-divider, first
select the value of R3 between 2kΩ and 10kΩ. Then
use the following equation to calculate R4:
R4 = (VFBx R3)/(V
OUT
- VFB)
where VFBis equal to the reference voltage at
REFIN/SS and V
OUT
is the output voltage. For V
OUT
=
0.6V, remove R4. If no external reference is applied at
REFIN/SS, the internal reference is automatically selected and VFBbecomes 0.6V.
Figure 2. Typical Soft-Start Implementation with External
Reference
Figure 3. Setting the Output Voltage with a Resistor VoltageDivider
At
×806µ
C
=
SS
V
.
LX
MAX15040
R3
R1
REFIN/SS
R2
C
MAX15040
FB
R4
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
______________________________________________________________________________________ 11
Shutdown Mode
Drive EN to GND to shut down the device and reduce
quiescent current to less than 0.1µA. During shutdown,
LX is high impedance. Drive EN high to enable the
MAX15040.
Thermal Protection
Thermal-overload protection limits total power dissipation
in the device. When the junction temperature exceeds T
J
= +165°C, a thermal sensor forces the device into shutdown, allowing the die to cool. The thermal sensor turns
the device on again after the junction temperature cools
by 20°C, causing a pulsed output during continuous
overload conditions. The soft-start sequence begins after
recovery from a thermal-shutdown condition.
Applications Information
IN and VDDDecoupling
To decrease the noise effects due to the high switching
frequency and maximize the output accuracy of
the MAX15040, decouple VINwith a 22µF capacitor in
parallel with a 0.1µF capacitor from VINto GND. Also
decouple VDDwith a 1µF capacitor from VDDto GND.
Place these capacitors as close as possible to the device.
Inductor Selection
Choose an inductor with the following equation:
where LIR is the ratio of the inductor ripple current to full
load current at the minimum duty cycle and fSis the
switching frequency (1MHz). Choose LIR between 20%
to 40% for best performance and stability.
Use an inductor with the lowest possible DC resistance
that fits in the allotted dimensions. Powdered iron or ferrite
core types are often the best choice for performance.
With any core material, the core must be large enough
not to saturate at the current limit of the MAX15040.
Output-Capacitor Selection
The key selection parameters for the output capacitor are
capacitance, ESR, ESL, and voltage-rating requirements.
These affect the overall stability, output ripple voltage,
and transient response of the DC-DC converter. The output ripple occurs due to variations in the charge stored
in the output capacitor, the voltage drop due to the
capacitor’s ESR, and the voltage drop due to the
capacitor’s ESL. Estimate the output voltage ripple due
to the output capacitance, ESR, and ESL as follows:
where the output ripple due to output capacitance,
ESR, and ESL is:
or whichever is higher.
The peak-to-peak inductor current (I
P-P
) is:
Use these equations for initial output capacitor selection. Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output voltage ripple. Since the inductor ripple current
is a factor of the inductor value, the output voltage ripple decreases with larger inductance. Use ceramic
capacitors for low ESR and low ESL at the switching
frequency of the converter. The ripple voltage due to
ESL is negligible when using ceramic capacitors.
Load-transient response depends on the selected output capacitance. During a load transient, the output
instantly changes by ESR x ∆I
LOAD
. Before the controller can respond, the output deviates further,
depending on the inductor and output capacitor values. After a short time, the controller responds by regulating the output voltage back to its predetermined
value. The controller response time depends on the
closed-loop bandwidth. A higher bandwidth yields a
faster response time, preventing the output from deviating further from its regulating value. See the
Compen-
sation Design
section for more details.
VVV
×−
()
L
OUT IN OUT
=
f V LIR I
×××
S IN OUT MAX
()
VV
RIPPLE RIPPLE C
VV
RIPPLE ESR RIPPLE ESL
V
RIPPLE C
VIx
RIPPLE ESR P P()=−
V
RIPPLE ESL
V
RIPPLE ESL( ))
I
=
PP
−
=+
+
() ()
=
()
8
=
()
=
VV
−
IN OUTSOUT
fL
×
()
I
−
PP
xC xf
OUT S
EESR
I
−
PP
x ESL or
t
ON
I
−
PP
x ESL
t
OFF
V
x
V
IN
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
Input-Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input power supply and reduces switching
noise in the device. The total input capacitance must
be equal to or greater than the value given by the following equation to keep the input ripple voltage within
the specification and minimize the high-frequency ripple current being fed back to the input source:
where V
IN-RIPPLE
is the maximum allowed input ripple
voltage across the input capacitors and is recommended to be less than 2% of the minimum input voltage, D
is the duty cycle (V
OUT/VIN
), and TSis the switching
period (1/f
S
) = 1µs.
The impedance of the input capacitor at the switching
frequency should be less than that of the input source so
high-frequency switching currents do not pass through
the input source, but are instead shunted through the
input capacitor. The input capacitor must meet the ripple
current requirement imposed by the switching currents.
The RMS input ripple current is given by:
where I
RIPPLE
is the input RMS ripple current.
Compensation Design
The power transfer function consists of one double pole
and one zero. The double pole is introduced by the
inductor, L, and the output capacitor, CO. The ESR of the
output capacitor determines the zero. The double pole
and zero frequencies are given as follows:
where RLis equal to the sum of the output inductor’s DC
resistance (DCR) and the internal switch resistance,
R
DSON
. A typical value for R
DSON
is 15mΩ. ROis the
output load resistance, which is equal to the rated output
voltage divided by the rated output current. ESR is the
total equivalent series resistance of the output capacitor.
If there is more than one output capacitor of the same
type in parallel, the value of the ESR in the above equation is equal to that of the ESR of a single output capacitor divided by the total number of output capacitors.
The MAX15040 high switching frequency allows the use
of ceramic output capacitors. Since the ESR of ceramic
capacitors is typically very low, the frequency of the
associated transfer function zero is higher than the unitygain crossover frequency, fC, and the zero cannot be
used to compensate for the double pole created by the
output inductor and capacitor. The double pole produces
a gain drop of 40dB/decade and a phase shift of 180°.
The compensation network must compensate for this
gain drop and phase shift to achieve a stable high-bandwidth closed-loop system. Therefore, use type III compensation as shown in Figure 4 and Figure 5. Type III
compensation possesses three poles and two zeros with
the first pole, f
P1_EA
, located at zero frequency (DC).
Locations of other poles and zeros of the type III compensation are given by:
The above equations are based on the assumptions that
C1 >> C2, and R3 >> R2, which are true in most applications. Placements of these poles and zeros are determined by the frequencies of the double pole and ESR
zero of the power transfer function. It is also a function
of the desired closed-loop bandwidth. The following
section outlines the step-by-step design procedure to
calculate the required compensation components for
the MAX15040.
The output voltage is determined by:
For V
OUT
= 0.6V, R4 is not needed.
12 ______________________________________________________________________________________
DxT xI
C
IN MIN
_
=
SOUT
V
IN RIPPLE
−
VVV
×−()
OUT IN OUT
V
IN
II
RIPPLE LOAD
=×
==
ff
PLC P LC
12
__
π
2
xLxC x
f
Z ESR
_
=
2π
x ESR x C
1
⎛
R ESR
O
O
⎜
⎝
RR
1
O
+
+
OL
f
ZEA1
_
f
ZEA2
_
f
PEA3
_
f
PEA
2_
=
=
1
xR xC
π
211
=
1
xR xC
π
233
1
x
π
RRxC12
2
=
1
xR xC
π
223
⎞
⎟
⎠
.
R
06 3
×
−
.
06
V
()
OUT
R
4
=
MAX15040
The zero-cross frequency of the closed-loop, fC, should
be between 10% and 20% of the switching frequency,
fS (1MHz). A higher zero-cross frequency results in
faster transient response. Once fCis chosen, C1 is calculated from the following equation:
where V
P-P
= 1V
P-P
(typ).
Due to the underdamped nature of the output LC double pole, set the two zero frequencies of the type III
compensation less than the LC double-pole frequency
to provide adequate phase boost. Set the two zero frequencies to 80% of the LC double-pole frequency.
Hence:
Setting the second compensation pole, f
P2_EA
, at
f
Z_ESR
yields:
Set the third compensation pole at 1/2 of the switching
frequency (500kHz) to gain phase margin. Calculate
C2 as follows:
The above equations provide accurate compensation
when the zero-cross frequency is significantly higher than
the double-pole frequency. When the zero-cross frequency is near the double-pole frequency, the actual zerocross frequency is higher than the calculated frequency.
In this case, lowering the value of R1 reduces the zerocross frequency. Also, set the third pole of the type III
compensation close to the switching frequency (1MHz) if
the zero-cross frequency is above 200kHz to boost the
phase margin. The recommended range for R3 is 2kΩ to
10kΩ. Note that the loop compensation remains
unchanged if only R4’s resistance is altered to set different outputs.
Soft-Starting into a Prebiased Output
The MAX15040 soft-starts into a prebiased output without
discharging the output capacitor. In safe prebiased startup, both low-side and high-side switches remain off to
avoid discharging the prebiased output. PWM operation
starts when the voltage on REFIN/SS crosses the voltage
on FB. The PWM activity starts with the low-side switch
turning on first to build the bootstrap capacitor charge.
Power-good (PWRGD) asserts 48 clock cycles after FB
crosses 92.5% of the final regulation set point. After 4096
clock cycles, the device switches from prebiased safe
startup mode to forced PWM mode.
The MAX15040 is capable of starting into a prebias voltage higher than the nominal set point without abruptly discharging the output. This is achieved by using the sink
current control of the low-side MOSFET, which has four
internally set sinking current-limit thresholds. An internal
4-bit DAC steps through these thresholds, starting from
the lowest current limit to the highest, in 128 clock cycles
on every power-up.
⎛
⎞
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
______________________________________________________________________________________ 13
Figure 4. Type III Compensation Network
Figure 5. Type III Compensation Illustration
COMPENSATION
TRANSFER
FUNCTION
POWER-STAGE
TRANSFER
FUNCTION
FIRST AND SECOND ZEROS
FREQUENCY (Hz)
DOUBLE POLE
OPEN-LOOP
GAIN
THIRD
POLE
SECOND
POLE
MAX15040
LX
COMP
L
C
OUT
R3
FB
C1
R1
R4
C2
V
OUT
R2
C3
GAIN (dB)
C
1
=
xxRx
231
.
25
V
IN
⎜
⎟
V
⎝
⎠
−
PP
R
+×
()π
R
L
f
C
R
C
1
=
3
=
1
xC
08 1
1
xR
08 3
L x C x R ESR
x
OO
RR
L x C x R ESR
x
OO
RR
C x ESR
O
R
23=
C
+
()
+.
LO
+
()
+.
LO
C
2
=
xR x f
π
1
1
S
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
14 ______________________________________________________________________________________
PCB Layout Considerations and
Thermal Performance
Careful PCB layout is critical to achieve clean and stable
operation. It is highly recommended to duplicate the
MAX15040 evaluation kit layout for optimum performance.
If deviation is necessary, follow these guidelines for good
PCB layout:
1) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the signal ground plane.
2) Place capacitors on V
DD
, IN, and REFIN/SS as close
as possible to the device and the corresponding
bump using direct traces. Keep power ground plane
and signal ground plane separate.
3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current short
and minimize the loop area formed by LX, the output capacitors, and the input capacitors.
4) Connect IN, LX, and GND separately to a large
copper area to help cool the device to further
improve efficiency and long-term reliability.
5) Ensure all feedback connections are short. Place
the feedback resistors and compensation components as close to the device as possible.
6) Route high-speed switching nodes, such as LX and
BST, away from sensitive analog areas (FB, COMP).
Chip Information
PROCESS: BiCMOS
WLP
GND IN
IN
GND
A1 A2 A3 A4
B1 B2 B3 B4
C1 C2 C3
C4
D1 D2 D3
D4
LX LX
V
DD
LX
I.C. I.C.
EN
BST
PWRGD FB COMP REFIN/SS
(BUMPS ON BOTTOM)
TOP VIEW
Pin Configuration
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
16 WLP W162B2+1
21-0200
—
MAX15040
High-Efficiency, 4A, Step-Down Regulator with
Integrated Switches in 2mm x 2mm Package
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
15
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
0 1/09 Initial release —
1 5/10 Revised the Absolute Maximum Ratings and Electrical Characteristics. 1–4
2 7/10 Revised the Absolute Maximum Ratings.2
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
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