The MAX15022 is a dual-output, pulse-width-modulated
(PWM), step-down DC-DC regulator with dual LDO controllers. The device operates from 2.5V to 5.5V and
each output can be adjusted from 0.6V to the input
supply (V
AVIN
). The MAX15022 delivers up to 4A (regulator 1) and 2A (regulator 2) of output current with two
LDO controllers that can be used to drive two external
PNP transistors to provide two additional outputs. This
device offers the ability to adjust the switching frequency from 500kHz to 4MHz and provides the capability of
optimizing the design in terms of size and performance.
The MAX15022 utilizes a voltage-mode control scheme
with external compensation to provide good noise
immunity and maximum flexibility in selecting inductor
values and capacitor types. The dual switching regulators operate 180° out-of-phase, thereby reducing the
RMS input ripple current and thus the size of the input
bypass capacitor significantly.
The MAX15022 offers the ability to track (coincident or
ratiometric) or sequence during power-up and powerdown operation. When sequencing, it powers up glitchfree into a prebiased output.
Additional features include an internal undervoltage
lockout with hysteresis and a digital soft-start/soft-stop
for glitch-free power-up and power-down. Protection
features include lossless cycle-by-cycle current limit,
hiccup-mode output short-circuit protection, and thermal shutdown.
The MAX15022 is available in a space-saving, 5mm x
5mm, 28-pin TQFN-EP package and is specified for
operation from -40°C to +125°C temperature range.
= 0V, RT= 25kΩ, and TA= TJ= -40°C to +125°C, unless otherwise noted.
Typical values are at T
A
= +25°C.) (Note 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: LX has internal diodes to PGND_ and PVIN_. Applications that forward bias these diodes should take care not to exceed
the IC’s package power dissipation limits.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations see www.maxim-ic.com/thermal-tutorial
.
AVIN, PVIN_, B_, DVDD_, EN_, FB_, RT,
SEL to SGND .........................................................-0.3V to +6V
COMP_ to SGND .....................................-0.3V to (V
AVIN
+ 0.3V)
PGND_ to SGND ...................................................-0.3V to +0.3V
Track/Sequence Select Input. Connect SEL to SGND to configure the device as a sequencer. Connect
1SEL
2, 7, 8PGND1
3, 6LX1
4, 5PVIN1
9DVDD1Switch Driver Supply for Regulator 1. Connect externally to PVIN1.
10EN1
11FB1
12COMP1Error-Amplifier Output for Regulator 1. Connect COMP1 to the compensation feedback network.
SEL to AVIN for tracking with output 1 as the master. Leave SEL unconnected for tracking with output 2
as the master. Use the output with the higher voltage as the master and the output with the lower voltage
as the slave.
Power Ground Connection for Regulator 1. Connect the negative terminals of the input and output filter
capacitors to PGND1. Connect PGND1 externally to SGND at a single point, typically at the negative
terminal of the input bypass capacitor.
Inductor Connection for Regulator 1. LX1 is the drain connection of the internal high-side p-channel
MOSFET and the drain connection of the internal synchronous n-channel MOSFET for regulator 1.
Input Supply Voltage for Regulator 1. Connect PVIN1 to an external voltage source from 2.5V to 5.5V.
Bypass PVIN1 to PGND1 with a 1μF (min) ceramic capacitor.
Enable Input for Regulator 1. When configured as a sequencer, EN1 must exceed 1.225V (typ) for the
PWM controller to begin regulating output 1. When configured as a tracker, connect EN1 to the center
tap of a resistive divider from the regulator 2 output.
Feedback Regulation Point for Regulator 1. Connect FB1 to the center tap of a resistive divider from the
regulator 1 output to SGND to set the output voltage. The FB1 voltage regulates to 0.6V (typ).
16DVDD2Switch Driver Supply for Regulator 2. Connect externally to PVIN2.
17PGND2
18LX2
19PVIN2
20EN4
21FB4
22B4
23COMP2Error-Amplifier Output for Regulator 2. Connect COMP2 to the compensation feedback network.
24FB2
25EN2
B3
FB3
EN3
Transconductance Amplifier Open-Drain Output for LDO Controller 3. Connect B3 to the base of an
external PNP transistor to regulate output 3.
Feedback Regulation Point for LDO Controller 3. Connect to the center tap of a resistive divider from the
output 3 to SGND to set the output voltage. The FB3 voltage regulates to 0.6V (typ).
LDO Enable Input for LDO Controller 3. EN3 must exceed 1.225V (typ) for the LDO controller to begin
regulating output 3.
Power Ground Connection for Regulator 2. Connect the negative terminals of the input and output filter
capacitors to PGND2. Connect PGND2 externally to SGND at a single point, typically at the negative
terminal of the input bypass capacitor.
Inductor Connection for Regulator 2. LX2 is the drain connection of the internal high-side p-channel
MOSFET and the drain connection of the internal synchronous n-channel MOSFET for Regulator 2.
Input Supply Voltage for Regulator 2. Connect to an external voltage source from 2.5V to 5.5V. Bypass
PVIN2 to PGND2 with a 1μF (min) ceramic capacitor.
LDO Enable Input for LDO Controller 4. EN4 must exceed 1.225V (typ) for the LDO controller to begin
regulating output 4.
Feedback Regulation Point for LDO Controller 4. Connect to the center tap of a resistive divider from
output 4 to SGND to set the output voltage. The FB4 voltage regulates to 0.6V (typ).
Transconductance Amplifier Open-Drain Output for LDO Controller 4. Connect B4 to the base of an
external PNP transistor to regulate output 4.
Feedback Regulation Point for Regulator 2. Connect to the center tap of a resistive divider from the
regulator 2 output to SGND to set the output voltage. The FB2 voltage regulates to 0.6V (typ).
Enable Input for Regulator 2. When configured as a sequencer, EN2 must exceed 1.225V (typ) for the
PWM controller to begin regulating output 1. When configured as a tracker, connect EN2 to the center
tap of a resistive divider from the regulator 1 output.
26SGND
27AVINInput Voltage. Bypass AVIN to SGND with a 100nF (min) ceramic capacitor.
28RT
—EP
Signal Ground. Connect SGND to PGND_ at a single point, typically near the negative terminal of the
input bypass capacitor.
Oscillator Timing Resistor Connection. Connect a 4.2kΩ to 33kΩ resistor from RT to SGND to program
the switching frequency from 500kHz to 4MHz.
Exposed Paddle. Connect EP to a large copper plane at SGND potential to improve thermal dissipation.
Do not use as the main SGND connection.
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