Rainbow Electronics MAX1494 User Manual
General Description
The MAX1492/MAX1494 low-power, 3.5- and 4.5-digit,
analog-to-digital converters (ADCs) with integrated liquid
crystal display (LCD) drivers operate from a single 2.7V
to 5.25V power supply. They include an internal reference, a high-accuracy on-chip oscillator, and a triplexed
LCD driver. An internal charge pump generates the negative supply needed to power the integrated input buffer
for single-supply operation. The ADC is configurable for
either a ±2V or ±200mV input range and outputs its conversion results to an LCD and/or to a microcontroller
(µC). µC communication is facilitated through an
SPI™-/QSPI™-/MICROWIRE™-compatible serial interface. The MAX1492 is a 3.5-digit (±1999 count) device,
and the MAX1494 is a 4.5-digit (±19,999 count) device.
The MAX1492/MAX1494 do not require external-precision integrating capacitors, autozero capacitors, crystal
oscillators, charge pumps, or other circuitry required
with dual-slope ADCs (commonly used in panel meter
circuits).
These devices also feature on-chip buffers for the differential signal and reference inputs, allowing direct
interface with high-impedance signal sources. In addition, they use continuous internal-offset calibration and
offer >100dB simultaneous rejection of 50Hz and 60Hz
line noise. Other features include data hold and peak
hold, overrange and underrange detection, and a lowbattery monitor.
The MAX1494 comes in a 32-pin, 7mm x 7mm TQFP
package, and the MAX1492 comes in 28-pin SSOP and
28-pin PDIP packages. All devices in this family operate
over the 0°C to +70°C commercial temperature range.
Applications
Digital Panel Meters
Hand-Held Meters
Digital Voltmeters
Digital Multimeters
Features
♦ High Resolution
MAX1494: 4.5 Digits (±19,999 Count)
MAX1492: 3.5 Digits (±1999 Count)
♦ Sigma-Delta ADC Architecture
No Integrating Capacitors Required
No Autozeroing Capacitors Required
>100dB of Simultaneous 50Hz and 60Hz
Rejection
♦ Operate from a Single 2.7V or 5.25V Supply
♦ Selectable Input Range of ±200mV or ±2V
♦ Selectable Voltage Reference: Internal 2.048V
or External
♦ Internal High-Accuracy Oscillator Needs No
External Components
♦ Automatic Offset Calibration
♦ Low Power
Maximum 960µA Operating Current
Maximum 400µA Shutdown Current
♦ Small 32-Pin 7mm x 7mm TQFP Package
(4.5 Digits), 28-Pin SSOP Package (3.5 Digits)
♦ Triplexed LCD Driver
♦ SPI-/QSPI-/MICROWIRE-Compatible Serial
Interface
♦ Evaluation Kit Available (Order MAX1494EVKIT)
MAX1492/MAX1494
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2959; Rev 3; 5/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART
TEMP
RANGE
PIN-
RESOLUTION
(DIGITS)
MAX1492CAI
28 SSOP 3.5
MAX1492CNI
28 PDIP 3.5
MAX1494CCJ
32 TQFP 4.5
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Pin Configurations appear at end of data sheet.
PACKAGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
MAX1492/MAX1494
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto GND............................................................-0.3V to +6V
DV
DD
to GND ...........................................................-0.3V to +6V
AIN+, AIN- to GND................................V
NEG
to +(AVDD+ 0.3V)
REF+, REF- to GND...............................V
NEG
to +(AVDD+ 0.3V)
LOWBATT to GND ...................................-0.3V to (AV
DD
+ 0.3V)
CLK,
EOC, CS, DIN, SCLK, DOUT to
GND.....................................................-0.3V to (DV
DD
+ 0.3V)
SEG_ and BP_ to GND ............................-0.3V to (DV
DD
+ 0.3V)
V
NEG
to GND ...........................................-2.6V to (AVDD+ 0.3V)
V
DISP
to GND...........................................-0.3V to (DVDD+ 0.3V)
Maximum Current into Any Pin ...........................................50mA
Continuous Power Dissipation (T
A
= +70°C)
28-Pin SSOP (derate 9.5mW/°C above +70°C) ...........762mW
28-Pin PDIP (derate 14.3mW/°C above +70°C)......1142.9mW
32-Pin TQFP (derate 20.7mW/°C above +70°C).....1652.9mW
Operating Temperature Range...............................0°C to +70°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(AVDD= DVDD= +2.7V to +5.25V, GND = 0, V
REF+
- V
REF-
= 2.048V (external reference). Internal clock mode, unless otherwise noted.
All specifications are at T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
UNITS
DC ACCURACY
MAX1494
Noise-Free Resolution
MAX1492
Count
2.000V range ±1
Integral Nonlinearity (Note 1) INL
200mV range ±1
Count
Range Change Accuracy
(V
AIN+
- V
AIN-
= 0.100V) on 200mV range /
(V
AIN+
- V
AIN-
= 0.100V) on 2.0V range
Ratio
Rollover Error (See the Definitions
Section)
V
AIN+
- V
AIN-
= full scale,
V
AIN-
- V
AIN+
= full scale
±1
Count
Output Noise 10
µV
P-P
Offset Error (Zero Input Reading)
Offset VIN = 0 (Note 2) -0 0
Reading
Gain Error (Note 3)
%FSR
Offset Drift (Zero-Reading Drift) VIN = 0 (Note 4) 0.1
µV/°C
Gain Drift ±1
ppm/°C
INPUT CONVERSION RATE
External Clock Frequency
MHz
External-Clock Duty Cycle 40 60 %
Internal clock 5
Conversion Rate
External clock, f
CLK
= 4.915MHz 5
Hz
ANALOG INPUTS (AIN+, AIN-, bypass to GND with 0.1µF or greater capacitors)
RANGE bit = 0, ±2V
AIN Input-Voltage Range
(Note 5)
RANGE bit = 1, ±200mV
V
AIN Absolute Input Voltage to
GND
V
SYMBOL
MIN TYP MAX
-19,999 +19,999
-1999 +1999
10:1
-0.5 +0.5
4.915
-2.0 +2.0
-0.2 +0.2
-2.2 +2.2
MAX1492/MAX1494
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= +2.7V to +5.25V, GND = 0, V
REF+
- V
REF-
= 2.048V (external reference). Internal clock mode, unless otherwise noted.
All specifications are at T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
UNITS
Internal clock mode, 50Hz and 60Hz ±2%
Normal-Mode 50Hz and 60Hz
Rejection (Simultaneously)
External clock mode, 50Hz and 60Hz ±2%,
f
CLK
= 4.915MHz
dB
Common-Mode 50Hz and 60Hz
Rejection (Simultaneously)
CMR
dB
Common-Mode Rejection CMR At DC
dB
Input Leakage Current 10 nA
Input Capacitance 10 pF
Dynamic Input Current (Note 6) -20
nA
LOW-BATTERY VOLTAGE MONITOR (LOWBATT)
LOWBATT TripThreshold
V
LOWBATT Leakage Current 10 pA
Hysteresis 20 mV
INTERNAL REFERENCE (INTREF BIT = 1, REF- = GND, bypass REF+ to GND with a 4.7µF capacitor)
REF Output Voltage V
REF
AVDD = 5V, TA = +25°C
V
REF Output Short-Circuit Current
1mA
REF Output Temperature
Coefficient
AVDD = 5V 40
ppm/°C
Load Regulation I
SOURCE
= 0 to 300µA, I
SINK
= 0 to 30µA 6
mV/µA
Line Regulation 50
µV/V
0.1Hz to 10Hz 25
Noise Voltage
10Hz to 10kHz
µV
P-P
EXTERNAL REFERENCE (INTREF BIT = 0, bypass REF+ and REF- to GND with 0.1µF or larger capacitors)
REF Input Voltage Differential (V
REF+
- V
REF-
)
V
Absolute REF Input Voltage to
GND
V
Internal clock mode, 50Hz and 60Hz ±2%
Normal-Mode 50Hz and 60Hz
Rejection (Simultaneously)
External clock mode, 50Hz and 60Hz ±2%,
f
CLK
= 4.915MHz
dB
Common-Mode 50Hz and 60Hz
Rejection (Simultaneously)
CMR
dB
Common-Mode Rejection CMR At DC
dB
Input Leakage Current 10 nA
Input Capacitance 10 pF
Dynamic Input Current (Note 6) -20
nA
SYMBOL
TC
VREF
For 50Hz and 60Hz ±2%, R
For 50Hz and 60Hz ±2%, R
MIN TYP MAX
100
120
< 10kΩ 150
100
2.048
2.007 2.048 2.089
400
2.048
-2.2 +2.2
< 10kΩ 150
100
120
100
SOURCE
SOURCE
+20
+20
MAX1492/MAX1494
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD= DVDD= +2.7V to +5.25V, GND = 0, V
REF+
- V
REF-
= 2.048V (external reference). Internal clock mode, unless otherwise noted.
All specifications are at T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
UNITS
CHARGE PUMP (C
NEG
= 0.1µF)
Output Voltage V
NEG
V
DIGITAL INPUTS (SCLK, DIN, CS, CLK)
Input Current I
IN
VIN = 0 or DV
DD
-10
µA
Input Low Voltage V
INL
0.3 x
V
Input High Voltage V
INH
V
Input Hysteresis V
HYST
DVDD = 3.0V
mV
DIGITAL OUTPUTS (DOUT, EOC)
Output Low Voltage V
OL
I
SINK
= 1mA 0.4 V
Output High Voltage V
OH
I
SOURCE
= 200µA
V
Tri-State Leakage Current I
L
D
OUT
only -10 +10 µA
Tri-State Output Capacitance C
OUT
D
OUT
only 15 pF
POWER SUPPLY
AVDD Voltage AV
DD
V
DVDD Voltage DV
DD
V
Power-Supply Rejection AV
DD
PSRRA(Note 7) 80 dB
Power-Supply Rejection DV
DD
PSRRD(Note 7)
dB
AVDD = 5V
660
AVDD Current (Notes 8, 9) I
AVDD
Standby
380
µA
DVDD = 5V
320
DVDD = 3.3V
180
DVDD Current (Notes 8, 9) I
DVDD
Standby 10 20
µA
LCD DRIVER
MAX1492
RMS Segment On Voltage
MAX1494
1.92 x
(DV
DD
- V
DISP
)
V
MAX1492
RMS Segment Off Voltage
MAX1494
1/3 x
(DV
DD
- V
DISP
)
V
Display Voltage Setup Resistor R
DISP
MAX1494 only
kΩ
Display Multiplex Rate
Hz
LCD Data-Update Rate 2.5 Hz
SYMBOL
MIN TYP MAX
-2.60 -2.42 -2.30
+10
DV
0.7 x DV
DD
200
DD
0.8 x DV
2.70 5.25
2.70 5.25
DD
100
580
240
260
130
1.92 x
DV
1/3 x
DV
157.5
107
DD
DD
MAX1492/MAX1494
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
_______________________________________________________________________________________ 5
TIMING CHARACTERISTICS (Notes 10, 11 and Figure 13)
(AVDD= DVDD= 2.7V to +5.25V, GND = 0, TA= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Operating Frequency f
SCLK
0 4.2
MHz
SCLK Pulse-Width High t
CH
ns
SCLK Pulse-Width Low t
CL
ns
DIN to SCLK Setup t
DS
50 ns
DIN to SCLK Hold t
DH
0ns
CS Fall to SCLK Rise Setup t
CSS
50 ns
SCLK Rise to CS Rise Hold t
CSH
0ns
SCLK Fall to DOUT Valid t
DO
C
LOAD
= 50pF (Figures 18, 19) 120 ns
CS Rise to DOUT Disable t
TR
C
LOAD
= 50pF (Figures 18, 19) 120 ns
CS Fall to DOUT Enable t
DV
C
LOAD
= 50pF (Figures 18, 19) 120 ns
Note 1: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error
and offset error.
Note 2: Offset calibrated. See the
OFFSET_CAL1
and OFFSET_CAL2 sections in the On-Chip Registers section.
Note 3: Offset nulled.
Note 4: Drift error is eliminated by recalibration at the new temperature.
Note 5: The input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pair.
Note 6: V
AIN+
or V
AIN-
= -2.2V to +2.2V. V
REF+
or V
REF-
= -2.2V to +2.2V. All input structures are identical. Production tested on
AIN+ and REF+ only.
Note 7: Measured at DC by changing the power-supply voltage from 2.7V to 5.25V and measuring the effect on the conversion
error with external reference. PSRR at 50Hz and 60Hz exceeds 120dB with filter notches at 50Hz and 60Hz (Figure 2).
Note 8: CLK and SCLK are idle.
Note 9: Power-supply currents are measured with all digital inputs at either GND or DV
DD
and with the device in internal clock mode.
Note 10: All input signals are specified with t
RISE
= t
FALL
= 5ns (10% to 90% of DVDD) and are timed from a voltage level of 50% of
DV
DD
, unless otherwise noted.
Note 11: See the serial-interface timing diagrams.
100
100
MAX1492/MAX1494
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
6 _______________________________________________________________________________________
Typical Operating Characteristics
(AVDD= DVDD= 5V, GND = 0, external reference mode, REF+ = 2.048V, REF- = GND, RANGE bit = 1, internal clock mode, TA=
+25°C, unless otherwise noted.)
MAX1494
(±200mV INPUT RANGE) INL vs. OUTPUT CODE
MAX1492/94 toc01
OUTPUT CODE
INL (COUNTS)
10,0000-10,000
-0.5
0
0.5
1.0
-1.0
-20,000 20,000
MAX1494
(±2V INPUT RANGE) INL vs. OUTPUT CODE
MAX1492/94 toc02
OUTPUT CODE
INL (COUNTS)
10,0000-10,000
-0.5
0
0.5
1.0
-1.0
-20,000 20,000
NOISE DISTRIBUTION
MAX1492/94 toc03
NOISE (LSB)
PERCENTAGE OF UNITS (%)
0.80.70.60.50.40.30.20.10-0.1
5
10
15
20
25
0
-0.2
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1492/94 toc04
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
4.754.253.753.25
100
200
300
400
500
600
700
0
2.75 5.25
ANALOG SUPPLY
DIGITAL SUPPLY
MAX1494
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1492/94 toc05
SUPPLY VOLTAGE (V)
OFFSET ERROR (LSB)
4.754.253.753.25
-0.11
-0.06
-0.01
0.04
0.09
0.14
0.19
-0.16
2.75 5.25
MAX1494
OFFSET ERROR vs. TEMPERATURE
MAX1492/94 toc06
TEMPERATURE (°C)
OFFSET ERROR (LSB)
605010 20 30 40
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
-0.2
070
MAX1494
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1492/94 toc07
SUPPLY VOLTAGE (V)
GAIN ERROR (% FULL SCALE)
4.754.253.25 3.75
-0.08
-0.04
-0.06
-0.02
0
0.02
0.04
0.06
0.08
-0.10
2.75 5.25
MAX1494
GAIN ERROR vs. TEMPERATURE
MAX1492/94 toc08
TEMPERATURE (°C)
GAIN ERROR (% FULL SCALE)
605030 402010
-0.09
-0.08
-0.07
-0.06
-0.05
-0.04
-0.03
-0.02
-0.01
0
-0.10
070
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1492/94 toc09
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
605040302010
2.046
2.045
2.047
2.049
2.048
2.051
2.050
2.053
2.052
2.054
2.044
070
MAX1492/MAX1494
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
_______________________________________________________________________________________ 7
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1492/94 toc10
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
4.754.253.753.25
2.045
2.046
2.047
2.048
2.049
2.050
2.044
2.75 5.25
SUPPLY CURRENT
vs. TEMPERATURE
MAX1492/94 toc11
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
605040302010
100
200
300
400
500
600
700
0
070
ANALOG SUPPLY
DIGITAL SUPPLY
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1492/94 toc12
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
605040302010
50
100
150
200
250
300
0
070
ANALOG SUPPLY
DIGITAL SUPPLY
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1492/94 toc13
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
4.754.253.753.25
50
100
150
200
250
300
0
2.75 5.25
ANALOG SUPPLY
DIGITAL SUPPLY
CHARGE-PUMP OUTPUT VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1492/94 toc14
SUPPLY VOLTAGE (V)
V
NEG
VOLTAGE (V)
4.754.253.753.25
-2.48
-2.46
-2.44
-2.42
-2.40
-2.50
2.75 5.25
V
NEG
STARTUP SCOPE SHOT
MAX1492/94 toc15
20ms/div
2V/div
1V/div
V
DD
V
NEG
OFFSET ERROR
vs. COMMON-MODE VOLTAGE
MAX1492/94 toc16
COMMON-MODE VOLTAGE (V)
OFFSET ERROR (LSB)
1.51.0-1.5 -1.0 -0.5 0 0.5
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
-0.20
-2.0 2.0
DATA OUTPUT RATE
vs. TEMPERATURE
MAX1492/94 toc17
TEMPERATURE (°C)
DATA OUTPUT RATE (Hz)
6035-15 10
4.92
4.98
4.96
4.94
5.00
5.02
5.04
5.06
5.08
5.10
4.90
-40 85
DATA OUTPUT RATE
vs. SUPPLY VOLTAGE
MAX1492/94 toc18
SUPPLY VOLTAGE (V)
DATA OUTPUT RATE (Hz)
4.744.233.21 3.72
4.995
4.990
4.985
5.000
5.005
5.010
5.015
5.020
4.980
2.70 5.25
Typical Operating Characteristics (continued)
(AVDD= DVDD= 5V, GND = 0, external reference mode, REF+ = 2.048V, REF- = GND, RANGE bit = 1, internal clock mode, TA=
+25°C, unless otherwise noted.)
MAX1492/MAX1494
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
8 _______________________________________________________________________________________
Pin Description
PIN
MAX1492
NAME FUNCTION
1 30 CLK
External Clock Input. When the EXTCLK bit in the control register is set, CLK is the
master clock input for the modulator and the filter (frequency = 4.9152MHz). When the
EXTCLK bit in the control register is reset, the internal clock is used. Connect CLK to
GND or DV
DD
when the internal oscillator is used.
231DV
DD
Digital Power Input. Connect DVDD to a 2.7V to 5.25V power supply. Bypass DVDD to
GND with 0.1µF and 4.7µF capacitors.
3 32 GND Ground
41AV
DD
Analog Power Input. Connect AVDD to a 2.7V to 5.25V power supply. Bypass AVDD to
GND with 0.1µF and 4.7µF capacitors.
5 2 AIN+
Positive Analog Input. Positive side of fully differential analog input. Bypass AIN+ to
GND with a 0.1µF or greater capacitor.
6 3 AIN-
Negative Analog Input. Negative side of fully differential analog input. Bypass AIN- to
GND with a 0.1µF or greater capacitor.
7 4 REF-
Negative Reference Input. During internal reference operation, connect REF- to GND.
For external reference operation, bypass REF- to GND with a 0.1µF capacitor and set
V
REF-
from -2.2V to +2.2V, provided V
REF+
> V
REF-
.
8 5 REF+
Positive Reference Input. During internal reference operation, connect a 4.7µF capacitor
from REF+ to GND. For external reference operation, bypass REF+ to GND with a 0.1µF
capacitor and set V
REF+
from -2.2V to +2.2V, provided V
REF+
> V
REF-
.
96
Low-Battery Input. When V
LOWBATT
< 2.048V (typ), the LOWBATT symbol on LCD turns
on and the LOWBATT bit latches high in the status register.
10 7 EOC
Active-Low, End-of-Conversion Logic Output. A logic-low at EOC indicates that a new
ADC result is available in the ADC result register.
11 8 CS Active-Low Chip-Select Input. Forcing CS low activates the serial interface.
12 9 DIN
Serial Data Input. Data present at DIN is shifted into the internal registers in response to
a rising edge at SCLK when CS is low.
13 10 SCLK
Serial Clock Input. Apply an external clock to SCLK to facilitate communication through
the serial bus. SCLK can idle high or low.
14 11 DOUT
Serial Data Output. DOUT presents serial data in response to register queries. Data
shifts out on the falling edge of SCLK. DOUT goes high impedance when CS is high.
15 12 SEG1 LCD Segment 1 Driver
16 13 SEG2 LCD Segment 2 Driver
17 14 SEG3 LCD Segment 3 Driver
18 15 SEG4 LCD Segment 4 Driver
19 16 SEG5 LCD Segment 5 Driver
20 17 SEG6 LCD Segment 6 Driver
21 18 SEG7 LCD Segment 7 Driver
22 19 SEG8 LCD Segment 8 Driver
23 20 SEG9 LCD Segment 9 Driver
MAX1494
LOWBATT
MAX1492/MAX1494
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
_______________________________________________________________________________________ 9
Pin Description (continued)
PIN
MAX1492
NAME
FUNCTION
24 21 SEG10 LCD Segment 10 Driver
25 25 BP3 LCD Backplane 3 Driver
26 26 BP2 LCD Backplane 2 Driver
27 27 BP1 LCD Backplane 1 Driver
28 29 V
NEG
-2.42V Charge-Pump Output. Bypass V
NEG
to GND with a 0.1µF capacitor.
— 22 SEG11 LCD Segment 11 Driver
— 23 SEG12 LCD Segment 12 Driver
— 24 SEG13 LCD Segment 13 Driver
— 28 V
DISP
Temperature-Compensation Voltage Input for LCD. If not using temperature
compensation, connect V
DISP
to GND. See the V
DISP
LCD Compensation section.
MAX1494
BINARY-TO-BCD
CONVERTERS
AND
LCD DRIVERS
ADC
INPUT
BUFFERS
-2.5V
AIN+
AIN-
REF+
REF-
+2.5V
AV
DD
DV
DD
V
DISP
2.048V
BANDGAP
REFERENCE
OSCILLATOR/
CLOCK
SCLK DIN DOUT
EOC
SEG1
SEG13
BP1
BP2
BP3
CLK
CS
SERIAL I/O AND CONTROL
+2.5V
GND
A = 1.22
TO
CONTROL
CHARGE
PUMP
-2.5V
LOWBATTV
NEG
Figure 1. MAX1494 Functional Diagram
MAX1494
MAX1492/MAX1494
Detailed Description
The MAX1492/MAX1494 low-power, highly integrated
ADCs with LCD drivers convert a ±2V differential input
voltage (one count is equal to 100µV for the MAX1494
and 1mV for the MAX1492) with a sigma-delta ADC and
output the result to an LCD or µC. An additional
±200mV input range (one count is equal to 10µV for the
MAX1494 and 100µV for the MAX1492) is available to
measure small signals with increased resolution.
The devices operate from a single 2.7V to 5.25V power
supply and offer 3.5-digit (MAX1492) or 4.5-digit
(MAX1494) conversion results. An internal 2.048V reference, an internal charge pump, and a high-accuracy
on-chip oscillator eliminate external components.
The MAX1492 and MAX1494 interface with a µC using
an SPI/QSPI/MICROWIRE-compatible serial interface.
Data can either be sent directly to the display or to the
µC first for processing before being displayed.
The devices also feature on-chip buffers for the differential input signal and external reference inputs, allowing
direct interface with high-impedance signal sources. In
addition, they use continuous internal-offset calibration
and offer >100dB of 50Hz and 60Hz line noise rejection. Other features include data hold and peak hold,
overrange and underrange detection, and a low-battery
monitor.
Analog Input Protection
Internal protection diodes limit the analog input range
from V
NEG
to (AVDD+ 0.3V). If the analog input exceeds
this range, limit the input current to 10mA.
Internal Analog Input/Reference Buffers
The MAX1492/MAX1494 analog input/reference buffers
allow the use of high-impedance signal sources. The
input buffer’s common-mode input range allows the analog inputs and the reference to range from -2.2V to +2.2V.
Modulator
The MAX1492/MAX1494 perform analog-to-digital conversions using a single-bit, 3rd-order, sigma-delta modulator. The sigma-delta modulator converts the input
signal into a digital pulse train whose average duty
cycle represents the digitized signal information. The
modulator quantizes the input signal at a much higher
sample rate than the bandwidth of the input.
The MAX1492/MAX1494 modulator provides 3rd-order
frequency shaping of the quantization noise resulting
from the single-bit quantizer. The modulator is fully differential for maximum signal-to-noise ratio and minimum susceptibility to power-supply noise. A single-bit
data stream is then presented to the digital filter to
remove the frequency-shaped quantization noise.
Digital Filtering
The MAX1492/MAX1494 contain an on-chip digital lowpass filter that processes the data stream from the
modulator using a SINC4((sinx/x)4) response. The
SINC4filter has a settling time of four output data periods (4 x 200ms).
The MAX1492/MAX1494 have 25% overrange capability
built into the modulator and digital filter.
The digital filter is optimized for f
CLK
equal to 4.9152MHz.
Lower clock frequencies can be used; however,
50Hz/60Hz noise rejection decreases. The frequency
response of the SINC4filter is measured as follows:
where N is the oversampling ratio, and fm = N
✕ output
data rate = 5Hz.
Filter Characteristics
Figure 2 shows the filter frequency response. The
SINC
4
characteristic -3dB cutoff frequency is 0.228
times the first-notch frequency (5Hz).
The output data rate for the digital filter corresponds
with the positioning of the first notch of the filter’s frequency response. The notches of the SINC4filter are
repeated at multiples of the first-notch frequency. The
SINC4filter provides an attenuation of better than
100dB at these notches. For example, 50Hz is equal to
Hz
N
z
z
Hf
N
N
f
fm
f
fm
N
()
()
()
()
sin
sin
=
−
−
=
−
−
11
1
1
1
4
4
π
π
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
10 ___________________________________________________________________________________________________
FREQUENCY (Hz)
GAIN (dB)
5040302010
-160
-120
-80
-40
0
-200
060
Figure 2. Frequency Response of the SINC4Filter (Notch at 60Hz)
ten times the first-notch frequency and 60Hz is equal to
12 times the first-notch frequency.
For large step changes at the input, allow a settling
time of 800ms before valid data is read.
Clock Modes
Configure the MAX1492/MAX1494 to use either the
internal oscillator or an externally applied clock to drive
the modulator and filter. Set the EXTCLK bit in the control register to 0 to put the device in internal clock mode.
Set the EXTCLK bit high to put the device in external
clock mode. Connect CLK to GND or DVDDwhen using
the internal oscillator. The MAX1492/MAX1494 ideally
operate with a 4.9152MHz clock to achieve maximum
rejection of 50Hz/60Hz common-mode, power-supply,
and normal-mode noise.
Internal Clock Mode
The MAX1492/MAX1494 contain an internal oscillator.
The power-up condition for the MAX1492/MAX1494 is
internal clock operation with the EXTCLK bit in the control register equal to 0. Using the internal oscillator
saves board space by removing the need for an external clock source.
External Clock Mode
For external clock operation, set the EXTCLK bit in the
control register high and drive CLK with a 4.9152MHz
clock source. Using an external clock allows for custom
conversion rates. A 2.4576MHz clock signal reduces
the conversion rate and the LCD update rate by a factor of two. The MAX1492/MAX1494 operate with an
external clock source of up to 5.05MHz.
Charge Pump
The MAX1492/MAX1494 contain an internal charge
pump to provide the negative supply voltage for the internal analog input/reference buffers. The bipolar input
range of the analog input/reference buffers allows this
device to accept negative inputs with high source impedances. Connect a 0.1µF capacitor from V
NEG
to GND.
LCD Driver
The MAX1492/MAX1494 contain the necessary backplane and segment-driver outputs to drive 3.5-digit
(MAX1492) and 4.5-digit (MAX1494) LCDs. The LCD
update rate is 2.5Hz. Figures 4–7 show the connection
schemes for a standard LCD. The MAX1492/MAX1494
automatically display the results of the ADC, if desired.
The MAX1492/MAX1494 also allow independent control
of the LCD driver through the serial interface, allowing
for data processing of the ADC result before showing
the result on the LCD. Additionally, each LCD segment
can be individually controlled (see the LCD Segment-
Display Register sections).
Triplexing
An internal resistor string comprised of three equalvalue resistors (52kΩ, 1% matching) is used to generate the display drive voltages. On the MAX1492, one
end of the string is connected to DVDDand the other
end is connected to GND. On the MAX1494, the other
end of the resistor string is connected to V
DISP
. Note
that V
LCD
should be three times the threshold voltage
for the liquid crystal material used (Figure 9).
The connection diagrams for a typical 7-segment display-font decimal point and annunciators are illustrated
in Figures 3 and 8. The MAX1494/MAX1492 numeric
display drivers (4.5 digits, 3.5 digits) use this configuration to drive a triplexed LCD with three backplanes and
13 segment-driver lines (10 for 3.5 digits). Figures 4
MAX1492/MAX1494
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
______________________________________________________________________________________ 11
a
XYZ
g
d
e
f
c
b
DP
ANNUNCIATOR
a
g
d
e
f
c
b
DP ANNUNCIATOR
BP1
BP2
BP3
Figure 3. Connection Diagrams for Typical 7-Segment Displays
MANUFACTURER WEBSITE PART NUMBER DESCRIPTION
04-0924-00 3.5 digit, 5V
04-0924-01 3.5 digit, 3V
04-0925-00 4.5 digit, 5V
DCI, Inc. www.dciincorporated.com
04-0925-01 4.5 digit, 3V
The following site has links to other custom LCD manufacturers: www.earthlcd.com/mfr.htm
Table 1. List of Custom LCD Manufacturers
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