The MAX14821 transceiver is suitable for IO-Link®
devices and 24V binary sensors/actuators. All specified
IO-Link data rates are supported. In IO-Link applications, the transceiver acts as the physical layer interface
to a microcontroller running the data-link layer protocol.
Additional 24V digital inputs and outputs are provided.
Two internal linear regulators generate common sensor
and actuator power requirements: 5V and 3.3V.
On-board C/Q and DO drivers are independently configurable for push-pull, high-side (PNP), or low-side (NPN)
operation. The device detects the IO-Link C/Q wake-up
condition and generates a wake-up signal on the activelow WU output. The C/Q and DI inputs have selectable
current loads for use in actuators.
An SPI™ interface allows configuration and monitoring of
the device. Extensive alarm conditions are detected and
communicated through the IRQ output and the SPI interface. The device features reverse-polarity, short-circuit,
and thermal protection. All power lines are monitored for
undervoltage conditions.
The C/Q and DO drivers are specified for sourcing/sinking up to 100mA.
The device is available in a 2.5mm x 2.5mm, 25-pin WLP
and a 4mm x 4mm, 24-pin TQFN package. Both are specified over the extended -40NC to +85NC temperature range.
Applications
IO-Link Sensors Industrial Sensors and Actuators
IO-Link Actuators
Features
S IO-Link Specification v.1.0 and v.1.1 Physical Layer-
Compliant
S Supports COM1, COM2, and COM3 Data Rates
S IO-Link Device Wake-Up Detection
S Push-Pull, High-Side, or Low-Side Outputs
S 100mA Specified C/Q Output Drive
S Auxiliary 24V, 100mA Digital Output
S Auxiliary 24V Digital Input
S Optional 6mA/7mA Current Loads at Both 24V Inputs
S 5V and 3.3V Linear Regulators
S Reverse-Polarity Protected 24V Supply Output
S EMI Emission Control Through Slew-Controlled Driver
S SPI Interface for Configuration and Monitoring
S 2.5V to 5V Logic Interface Levels
S Reverse-Polarity and Short-Circuit Protection on All
24V Inputs/Outputs
S High-Temperature Warning and Thermal Shutdown
S Extensive Fault Monitoring and Reporting
S -40NC to +85NC Operating Temperature Range
S 2.5mm x 2.5mm WLP and 4mm x 4mm TQFN
Packages
Ordering Information appears at end of data sheet.
Typical Operating Circuit
5V
3.3V
10kΩ
V
CC
MICROCONTROLLER
GND
IO-Link is a registered trademark of Profibus User Organization (PNO).
SPI is a trademark of Motorola, Inc.
For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/MAX14821.related
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
(VCC = 18V to 36V, VL = 2.3V to 5.5V, V
values are at VCC = 24V, VL = 3.3V, and TA = +25NC, unless otherwise noted.) (Note 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SPI TIMING (CS, SCLK, SDI, SDO) (Figure 6)
SCLK Clock Periodt
SCLK Pulse-Width Hight
SCLK Pulse-Width Lowt
CS Fall to SCLK Rise Time
SCLK Rise to CS Rise Hold Time
SDI Hold Timet
SDI Setup Timet
Output Data Propagation Delayt
SDO Rise and Fall Times t
Minimum CS Pulse
Note 2: All devices are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by
design.
Note 3: UV is an open-drain output. Connect UV to a voltage less than 5.5V through an external pullup resistor.
Note 4: Disable time measurements are load dependent.
= 0V; all logic inputs at VL or GND; TA = -40NC to +85NC, unless otherwise noted. Typical
The MAX14821 is a sensor/actuator transceiver designed
for IO-Link device applications supporting all the specified IO-Link data rates. In IO-Link applications, the
device acts as the physical layer interface to a microcontroller running the data-link layer protocol. The device
contains an additional 24V digital input and an additional
24V digital output. Two internal linear regulators generate common sensor and actuator power requirements:
5V and 3.3V.
The device detects IO-Link wake-up conditions on the C/Q
line and generates a wake-up signal on the WU output.
The C/Q and DO drivers are independently configurable to
any one of three driver output types: push-pull, high-side
(PNP), or low-side (NPN).
The C/Q and DI inputs have selectable current sinks that
can be enabled for use in actuators where the master
requires a Type 2 load. The device is configured and
monitored through an SPI interface. Extensive alarms are
available through SPI.
24V Interface
The device features an IO-transceiver interface capable
of operating with voltages up to 36V. This is the 24V interface and includes the C/Q input/output, the logic-level
digital output (DO), and the logic-level digital input (DI).
Configurable Drivers
The device features selectable push-pull, high-side (PNP),
or low-side (NPN) switching drivers at C/Q and DO.
Set the C/Q_N/P and C/Q_PP bits in the CQConfig register to select the driver mode for the C/Q driver. When
configured as a push-pull output, C/Q switches between
VP and ground. Set the C/Q_PP bit to 1 to select pushpull operation at C/Q. Set the C/Q_PP bit to 0 to configure
the C/Q output for open-drain operation. The C/Q_N/P bit
selects NPN or PNP operation when C/Q is configured as
an open-drain output.
Set the DoN/P and DoPP bits in the DIOConfig register
to select the driver mode for the DO output. When configured as a push-pull output, DO switches between VCC
and ground. Set the DoPP bit to 1 for push-pull operation.
The DoN/P bit selects NPN or PNP operation when DO is
configured as an open-drain output. Set the DoPP bit to 0
to select high-side or low-side operation at DO.
C/Q Driver and Receiver
The TXEN input enables the C/Q driver. Drive TXEN high
to enable the C/Q driver. Drive TXEN low to disable the
driver.
The C/Q driver is specified to supply up to 100mA DC
load current.
The HiSlew bit increases the slew rate of the C/Q and DO
driver outputs. Set HiSlew to 1 for data rates of 230kbps
or higher. Set HiSlew to 0 to reduce both the C/Q and DO
driver slew rates to reduce EMI emission and reflections.
The C/Q receiver is always on. Disable the RX output
through the RxDis bit in the CQConfig register. Set the
RxDis bit to 1 to set the RX output high. Set the RxDis bit
to 0 for normal receive operation.
The C/Q receiver has an analog lowpass filter to reduce
high-frequency noise present on the line. Set the RxFilter
bit in the CQConfig register to 0 to set the filter corner
frequency to 500kHz (typ). Set the RxFilter bit to 1 to set
the corner frequency of the filter to 1MHz (typ). Noise
filters are present on both the C/Q and DI receivers and
are controlled simultaneously by the RxFilter bit.
C/Q Fault Detection
The device registers a C/QFault condition under either of
two conditions:
1) When it detects a short circuit for longer than 160µs
(typ). A short condition exists when the C/Q driver’s
load current exceeds the 140mA (typ) current limit.
2) When it detects a voltage level error at the C/Q output. A voltage level error occurs when the C/Q driver
is configured for open-drain operation (NPN or PNP),
the driver is turned off, and the C/Q voltage is not
pulled to exceed the C/Q receiver’s threshold levels
(< 8V or > 13V) by the external supply.
When a C/QFault error occurs, the C/QFault and
C/QFaultInt bits are set, IRQ asserts, and the driver is
turned off 240µs (typ) after the start of the fault condition.
When a short-circuit event occurs on C/Q, the driver
enters autoretry mode. In autoretry mode the device
periodically checks whether the short is still present and
attempts to correct the driver output. Autoretry attempts
last for 350µs (typ) and occur every 26ms (typ).
The device registers a DoFault event when a short circuit
is present at the DO output for longer than 30–440Fs. A
short condition exists when the load current on the DO
driver exceeds the 135mA (typ) DO current limit. When a
short-circuit condition is detected, the DO driver enters
autoretry mode. In autoretry mode the device periodically checks whether the error is still present. Autoretry
attempts last for 440µs (typ) and occur every 26ms
(typ). When a DoFault error is detected, the DoFault and
DoFaultInt bits are set, IRQ asserts, and the driver is
turned off 440µs (typ) after the start of the DO faults.
Reverse-Polarity Protection
The device is protected against reverse-polarity connections on VCC, C/Q, DO, DI, and GND. Any combination
of these pins can be connected to DC voltages up to
40V (max). A short to 40V results in a current flow of less
than 500FA.
Ensure that the maximum voltage between any of these
pins does not exceed 40V.
5V and 3.3V Linear Regulators
The device includes two internal current-limited regulators
to generate 5V (V5) and 3.3V (LDO33). V5 is specified at
10mA when bypassed with a 0.1µF capacitor to ground.
Add the compensation network shown in Figure 7 to draw
up to 30mA from V5. LDO33 is specified at 20mA. The
input of V5, LDOIN, can be connected to VP, the protected 24V supply output, or to another voltage in the 7V
to 36V range.
V5 constitutes the supply for the logic block. The 5V LDO
can be disabled by connecting LDOIN to V5. Apply an
external voltage from 4.75V to 5.25V to V5 when the LDO
is disabled.
Use the LDO33Dis bit in the Mode register to enable/
disable LDO33. See the Mode Register [R1, R0] = [1,1]
section for more information. V5 and LDO33 are not protected against short circuits.
Power-Up
The C/Q and DO driver outputs and the UV output are
high impedance when VCC, V5, VL, and/or LDO33 voltages are below their respective undervoltage thresholds during power-up. UV goes low and the drivers are
enabled when all these voltages exceed their respective
undervoltage-lockout thresholds.
The drivers are automatically disabled if VCC, V5, or VL
falls below its threshold.
Undervoltage Detection
The device monitors VCC, V5, VL, and optionally LDO33
for undervoltage conditions. UV is high impedance when
any monitored voltage falls below its UVLO threshold.
VCC, V5, and VL undervoltage detection cannot be disabled. When VCC falls below the V
CCUVLO
threshold, the
UV24 and UV24Int bits are set, UV asserts high, and IRQ
asserts low.
The SPI register contents are unchanged while V5 is present, regardless of the state of VCC and LDO33. The SPI
interface is not accessible and IRQ is not available when
UV is asserted due to a V5 or VL undervoltage event.
When the internal 3.3V LDO regulator voltage (V
LDO33
falls below the LDO33 undervoltage-lockout threshold,
the UV33Int bit in the Status register is set and IRQ
asserts. UV asserts if the UV33En bit in the Mode register
is set to 1.
The UV output deasserts once the undervoltage condition is removed; however, bits in the Status register and
the IRQ output are not cleared until the Status register
has been read.
The device detects an IO-Link wake-up condition on the
Wake-Up Detection
C/Q line in push-pull, high-side (PNP), or low-side (NPN)
operation modes. A wake-up condition is detected when
the C/Q output is shorted for 80Fs (typ). WU pulses low
for 190Fs (typ) when the device detects a wake-up pulse
on C/Q (Figure 5).
Set the WuIntEn bit in the Mode register to set the WuInt
bit in the Status register and generate an interrupt on
IRQ when a wake-up pulse is detected. WuInt is set
and IRQ asserts immediately after C/Q is released when
WuIntEn = 1.
MAX14821
IO-Link Device Transceiver
Thermal Protection and Considerations
The internal LDOs and drivers can generate more power
than the package for the device can safely dissipate.
Ensure that the driver LDO loading is less than the package can dissipate. Total power dissipation for the device
is calculated using the following equation:
P
where P
= P
TOTAL
is the power generated in the C/Q driver,
C/Q
+ PDO + P5 + P
C/Q
P
+ P
CLCQ
CLDI
LDO33
+ PQ +
PDO is the power dissipated by the DO driver, P5 and
P
quiescent power generated by the device, and P
and P
are the power generated by the LDOs, PQ is the
LDO33
are the power generated in the C/Q and DI
CLDI
CLCQ
current sinks.
Ensure that the total power dissipation is less than the
limits listed in the Absolute Maximum Ratings section.
Use the following to calculate the power dissipation (in
mW) due to the C/Q driver:
P
C/Q
= [I
(max)] × [0.5 + 7 × I
C/Q
C/Q
(max)]
Calculate the internal power dissipation of the DO driver
using the following equation:
PDO = [IDO(max)] × [0.5 + 7 × IDO(max)]
Calculate the power dissipation in the 5V LDO, V5, using
the following equation:
P5 = (V
where I5 includes the I
LDOIN
LDO33
- V5) × I
5
current sourced from
LDO33.
Calculate the power dissipated in the 3.3V LDO, LDO33,
using the following equation:
P
LDO33
= 1.7V × I
LDO33
Calculate the quiescent power dissipation in the device
using the following equation:
PQ = 5mA × VCC(max)
If the current sinks are enabled, calculate their associated power dissipation as:
P
= 7mA × V
CLCQ
P
= 7mA × VDI(max)
CLDI
C/Q
(max)
Overtemperature Warning
Bits in the Status and Mode registers are set when the
temperature of the device exceeds +115NC (typ). The
OTempInt bit in the Status register is set and IRQ asserts
when the OTemp bit in the Mode register is set. Read the
Status register to clear the OTempInt bit and IRQ.
The OTemp bit is cleared when the die temperature falls
to +95NC.
The device continues to operate normally unless the
die temperature reaches the +150NC thermal shutdown
threshold, when the device enters thermal shutdown.
Thermal Shutdown
All regulators and the C/Q and DO output drivers are
automatically switched off when the internal die temperature exceeds the +150NC (typ) thermal shutdown threshold. SPI communication is not available during a thermal
shutdown event.
Regulators are automatically switched on when the internal die temperature falls below the thermal shutdown
threshold plus hysteresis. The internal registers return to
their default state when the V5 regulator is switched on.
BitD7D6D5D4D3D2D1D0
Bit Name
Read/Write
POR State
Reset Upon Read
X = Unknown. These bits are dependent on the DI logic and C/Q inputs.
WuIntDoFaultIntDiLvl
RRRRRRRR
00XX0000
YesYesNoNoYesYesYesYes
QLvl
QLvl
C/QFaultIntUV33IntUV24IntOTempInt
Status Register [R1, R0] = [0,0]
C/QFaultIntUV33IntUV24IntOTempInt
The Status register reflects the logic levels of C/Q and DI and shows the source of interrupts that cause an IRQ
hardware interrupt. The IRQ interrupt is asserted when an alarm condition (OTemp, UV33Int, UV24, C/QFault,
DoFault, WuInt) is detected. All bits in the Status register are read-only. The interrupt bits return to the default state
after the Status register is read. If a C/Q or DO fault condition persists, the associated interrupt bits are immediately
set after the Status register is read.
BITNAMEDESCRIPTION
D7WulntWake-Up Interrupt Request. WuInt is set when an IO-Link wake-up request pulse is
detected on C/Q and the WuIntEn bit in the Mode register is set. IRQ asserts when
WuInt is set to 1. Read the Status register to clear the WuInt bit and deassert IRQ.
D6DoFaultIntDO Fault Interrupt. DoFaultInt interrupt bit and DoFault bit (in the Mode register) are
D5DiLvlDI Logic Level. The DiLvl bit mirrors the current logic level at the DI input. It is the
set when a fault condition occurs on the DO driver output. The device registers a fault
condition when a short circuit or voltage fault is detected on DO (see the DO Fault Detection section for more information). IRQ asserts when DoFaultInt is 1. Read the
Status register to clear the DoFaultInt bit and deassert IRQ.
inverse of the LI output and is always active regardless of the state of the LiDis bit (Table
2). DiLvl does not affect IRQ. DiLvl is not changed when the Status register is read.
D3C/QFaultIntC/Q Fault Interrupt. The C/QFaultInt interrupt bit and C/QFault bit (in the Mode register)
D2UV33IntInternal 3.3V LDO (LDO33) Undervoltage Warning. Both the UV33Int interrupt bit and
D1UV24IntVCC Undervoltage Interrupt. The UV24Int interrupt bit and the UV24 bit (in the Mode
D0OTempIntOvertemperature Warning. The OTempInt interrupt bit and the OTemp bit (in the Mode
QLvlC/Q Logic Level. The QLvl bit is the inverse of the logic level at C/Q. QLvl is 1 when the
C/Q input level is low (< 8V) and is 0 when the C/Q logic level is high (> 13V) (Table 3).
QLvl remains active when the C/Q receiver is disabled (RxDis = 1). QLvl does not affect
IRQ. QLvl is not changed when the Status register is read.
are set when a short circuit or voltage fault occurs on the C/Q driver output (see the C/Q
Fault Detection section for more information). IRQ asserts when C/QFault is 1. Read the
Status register to clear the C/QFaultInt bit and deassert IRQ.
the UV33En bit (in the Mode register) are set when V
undervoltage threshold. If UV33En is set in the Mode register, IRQ asserts low when the
UV33Int bit is 1. Read the Status register to clear the UV33Int bit and deassert IRQ.
Set the UV33En bit to 1 in the Mode register to enable undervoltage monitoring for
UV33Int. When enabled, UV asserts high when the UV33Int bit is 1. UV deasserts when
V
rises above the LDO33 undervoltage threshold.
LDO33
register) are set when the VCC voltage falls below the 7.4V undervoltage threshold. IRQ
asserts low when the UV24Int bit is 1. Read the Status register to clear the UV24Int bit
and deassert IRQ. VCC undervoltage detection cannot be disabled.
register) are set when a high-temperature condition is detected by the device. OTemp
is set when the temperature of the die exceeds +115NC (typ). OTempInt is set and IRQ
asserts when the OTemp bit is 1. The OTempInt bit is cleared and IRQ deasserts when
the Status register is read.
Once cleared, OTempInt is not reset if the die temperature remains above the thermal
warning threshold and does not fall below +95°C.
falls below the 2.4V LDO33
LDO33
Table 2. DiLvl and LI OutputTable 3. QLvl and RX Output
Use the CQConfig register to control the C/Q receiver and driver parameters. All bits in the CQConfig register are
read-write and are set to 0 at power-up.
BITNAMEDESCRIPTION
D7RxFilterC/Q and DI Receiver Filter Control. The C/Q and DI receivers have analog
D6HiSlewSlew-Rate Control. The HiSlew bit increases the slew rate for the C/Q and
D5C/Q_N/PC/Q Driver NPN/PNP Mode. The C/Q_N/P bit selects between low-side (NPN)
RxFilterHiSlewC/Q_N/PC/Q_PPC/QDEnQRxDisC/QLoad
R/WR/WR/WR/WR/WR/WR/WR/W
00000000
lowpass filters to reduce high-frequency noise on the receiver inputs. Set the
RxFilter bit to 0 to set the filter corner frequency to 500kHz. Set the RxFilter
bit to 1 to set the filter corner frequency to 1MHz (this setting is used for highspeed COM3 operation).
Noise filters on C/Q and DI are controlled simultaneously by the RxFilter bit.
DO drivers and is used for high-speed COM3 (230kbps) data rates. Set
HiSlew to 0 for COM1 and COM2 operation.
and high-side (PNP) modes when the C/Q driver is configured as an opendrain output (C/Q_PP = 0). Set C/Q_N/P to 1 to configure the driver for low-side
(NPN) operation. Set C/Q_N/P to 0 for high-side (PNP) operation.
D4C/Q_PPC/Q Driver Push-Pull Operation. Set C/Q_PP to 1 to enable push-pull
operation on the C/Q driver. The C/Q output is open-drain when C/Q_PP is 0.
D3C/QDEnC/Q Driver Enable/Disable. Set the C/QDEn bit to 1 to enable the C/Q driver.
Set C/QDEn to 0 for hardware (TXEN) control. See Table 4.
D2QC/Q Driver Output Logic. The Q bit can be used to program the C/Q output
driver through software. The C/Q driver must be enabled and TXC = TXQ must
be high to control the C/Q driver through the Q bit (Figure 8). C/Q has the
same logic polarity as the Q bit.
Set the Q bit to 0 to control the C/Q driver with TXC and TXQ.
The C/Q driver output state depends on the C/Q_PP and C/Q_N/P bits as
shown in Table 5. Note that Table 5 assumes that the C/Q driver is enabled
(TXEN = VL or C/QDEn = 1).
D1RxDisC/Q Receiver Enable/Disable. Set the RxDis bit to 1 to disable the C/Q
receiver. The RX output is high when RxDis is 1.
D0C/QLoadC/Q Current Sink Enable. Set the C/QLoad bit to 1 to enable the internal
High100PNP, open drainOn, C/Q is high
High000PNP, open drainOff, C/Q is high impedance
High101NPN, open drainOff, C/Q is high impedance
High001NPN, open drainOn, C/Q is low
High11XPush-pullHigh
High01XPush-pullLow
Use the DIOConfig register to control the DI and DO interfaces. All bits in the DIOConfig register are read-write and
are set to 0 at power-up.
BITNAMEDESCRIPTION
D7DoInvDO Output Polarity. Set the DoInv bit to 1 to invert the logic of the DO
D6DoAvDO Antivalent Operation. Set the DoAv bit to 1 to enable antivalent
D5DoN/PDO Driver NPN/PNP Operation. The DoN/P bit selects between low-
DoInvDoAvDoN/PDoPPDoEnDoBitLiDisDiLoad
R/WR/WR/WR/WR/WR/WR/WR/W
00000000
output. This bit also works in conjunction with the DoAv (Table 6). DO
tracks the TXC and TXQ inputs with the opposite polarity when both the
DoAv and DoInv bits are set.
output operation on DO. DO tracks the TXC and TXQ inputs (and the Q
bit) when DoAv is 1 (Table 6).
The LO input and the DoBit are ignored when the DoAv bit is 1.
side (NPN) and high-side (PNP) modes when the DO driver is configured
as an open-drain output (DoPP = 0). Set DoN/P to 1 to configure the
driver for low-side (NPN) operation. Set DoN/P to 0 for high-side (PNP)
operation.
D4DoPPDO Driver Push-Pull Operation. Set the DoPP bit to 1 to configure the
DO driver output for push-pull operation. DO is an open-drain output
when DoPP is 0.
D3DoEnDO Driver Enable/Disable. Set the DoEn bit to 1 to enable the DO
driver. The DO driver is high impedance with a weak pulldown when
DoEn is 0.
D2DoBitDO Driver Output Logic. The DoBit bit can be used to program the
DO output driver through software. Drive LO high to activate DoBit
programming (Figure 9). The DO output state is given in Table 7. Note
that Table 7 assumes that the DoInv bit is 0.
D1LiDisLI Output Enable/Disable. Set the LiDis bit to 1 to disable the LI output.
The LI output is low when LiDis is 1.
D0DiLoadDI Current Sink Enable. Set the DiLoad bit to 1 to enable the internal
Note 1: Low is when V
Note 2: Low is when C/Q or DO < 8V; high is when C/Q or DO >13V.
TXC
, V
, OR VLO = 0V; high is when V
TXQ
TXC AND TXQ
(NOTE 1)
TXC
Table 7. DO Output Programmed by DoBit
, V
TXQ
LO
(NOTE 1)
, or VLO = VL.
DO
(NOTE 2)
C/Q
(NOTE 2)
LODoBitDoPPDoN/PDO CONFIGURATIONDO STATE
High01XPush-pullLow
High11XPush-pullHigh
High000PNPOff, DO is high impedance
High100PNPOn, DO is high
High001NPNOn, DO is low
High101NPNOff, DO is high impedance
Use the Mode register to reset the MAX14821 and manage the 3.3V LDO. The Mode register has bits that represent the current status of fault conditions. When writing to the Mode register, the contents of the fault indication bits
(bits 2 to 5) do not change.
BITNAMEDESCRIPTION
D7RSTRegister Reset. Set RST to 1 to reset all registers to their default power-up state. Then
D6WuIntEnWake-Up Interrupt Enable. Set WuIntEn to 1 to enable wake-up interrupt generation.
The Status register is cleared and IRQ deasserts (if asserted) when RST = 1. Interrupts
are not generated while RST = 1.
When WuIntEn is set, the WuInt bit in the Status register is set and IRQ asserts when
a valid wake-up condition is detected. The C/Q driver must be enabled for wake-up
detection. The state of WuIntEn does not affect the WU output. See the Wake-Up Detection section for more information.
D5DoFaultDO Fault Status. The DoFault bit is set when a short circuit or voltage fault occurs at
the DO driver output (see the DO Fault Detection section for more information). The
DoFault and DoFaultInt bits are both set when a fault occurs on DO. DoFault is cleared
when the fault is removed.
D4C/QFaultC/Q Fault Status. The C/QFault bit is set when a short circuit or voltage fault occurs at
the C/Q driver output (see the C/Q Fault Detection section for more information). The
C/QFault and C/QFaultInt bits are both set when a fault occurs on C/Q. C/QFault is
cleared when the fault is removed.
D3UV24VCC Undervoltage Condition. Both the UV24 and the UV24Int bits are set when VCC
falls below V
must be present for VCC undervoltage monitoring.
D2OTempTemperature Warning. The OTemp bit is set when a high-temperature condition
occurs on the device. Both the OTempInt interrupt in the Status register and the OTemp
bit are set when the junction temperature of the die rises to above +115NC (typ). The
OTemp bit is cleared when the junction temperature falls below +95NC (typ).
D1UV33EnLDO33 UV Enable. Set the UV33En bit to 1 to assert the UV output when LDO33 volt-
age falls below the 2.4V (typ) undervoltage-lockout threshold. The UV33En bit does
not affect the UV33Int bit in the Status register; IRQ asserts when V
V
LDO33UVLO
D0LDO33DisLDO33 Enable/Disable. Set LDO33Dis to 1 to disable the 3.3V linear regulator (LDO33).
The device communicates through an SPI-compatible
4-wire serial interface. The interface has three inputs—
clock (SCLK), chip select (CS), and data in (SDI)—and
one output, data out (SDO). The maximum SPI clock rate
CS
SCLK
SDI
Figure 10. SPI Write Cycle
W00000
R_ = REGISTER ADDRESS
D_ = DATA BIT
= CLOCK EDGE WHEN LOGIC IS LATCHED
R1
for the device is 12MHz. The SPI interface complies with
clock polarity CPOL = 0 and clock phase CPHA = 0 (see
Figure 10 and Figure 11).
The SPI interface is not available when V5 or VL are not
present.
The logic levels of the microcontroller interface I/Os
(TXC, TXQ, TXEN, and RX) are defined by VL.
TXQGPO
TXCTX
MAX14821
TXENRTS
MICROCONTROLLER
Figure 12. UART Interface
1μF
LDOIN
V
P
V
CC
MAX14821
Figure 13. MAX14821 Operating Circuit with TVS Protection
DO
C/Q
DI
GND
RXRX
1/2
SDC36C
1/2
SDC36C
0.8Ω
1μF
1/2
SDC36C
SDC36C
The device can be interfaced to microcontrollers where
the on-board UART TX output cannot be programmed as
a logic output (GPO). In this case, connect the TX output
of the UART to the TXC input for IO-Link communication
and connect a separate GPO output on the microcontroller to TXQ for standard IO (SIO) mode operation
(Figure 12). As the TXQ and TXC inputs are internally
logically ANDed, the unused input (TXC or TXQ) must be
held high while the other is in operation.
Transient Protection
Inductive load switching, surges, and bursts create high
transient voltages. C/Q, DO, and DI should be protected
against high overvoltage and undervoltage transients.
Positive voltage transients on C/Q, DO, and DI must be
limited to +55V relative to GND and negative voltage transients must be limited to -55V (relative to VCC) on DO and
C/Q and to -55V (relative to GND) on DI. Figure 12 shows
suitable protection using TVS diodes to meet both the
IEC 61000-4-4 burst and IEC 61000-4-5 surge testing.
Other protection schemes may also be suitable.
To protect against large transients at VCC, insert a
lowpass filter on VCC (see Figure 13 and the Typical
Operating Circuit).
External Power
The device is powered by VCC and the 5V regulator, V5.
VL is a reference voltage input to set the logic levels of
the microcontroller interface. The logic and SPI interface
are operational when V5 and VL are present even if VCC
is not present.
The VP output provides a reverse-polarity-protected voltage one diode drop below VCC and can be used for supplying external circuitry, like power supplies.
Connect LDOIN to V5 to power the V5 input with an
external supply (Figure 14). This configuration disables
operation of the internal 5V regulator and reduces power
consumption.
Figure 14. Use an External Supply to Power the MAX14821
Ordering Information
PARTTEMP RANGEPIN-PACKAGE
MAX14821ETG+-40°C to +85°C24 TQFN-EP*
MAX14821EWA+**-40°C to +85°C25 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
**Future product —contact factory for availability.
Chip Information
PROCESS: BiCMOS
1μF
0.8Ω
L+
1
2
4
3
L-
LDO33VLTXQ
MAX14821
5
LDOIN
V
P
V
CC
DO
C/Q
GND
DIGND
V
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 29