Rainbow Electronics MAX1471 User Manual

General Description

The MAX1471 low-power, CMOS, superheterodyne, RF
dual-channel receiver is designed to receive both ampli­tude-shift-keyed (ASK) and frequency-shift-keyed (FSK)
data without reconfiguring the device or introducing any
time delay normally associated with changing modula­tion schemes. The MAX1471 requires few external com­ponents to realize a complete wireless RF digital data
receiver for the 300MHz to 450MHz ISM bands.

The MAX1471 includes all the active components
required in a superheterodyne receiver including: a low­noise amplifier (LNA), an image-reject (IR) mixer, a fully
integrated phase-locked loop (PLL), local oscillator
(LO), 10.7MHz IF limiting amplifier with received-signal­strength indicator (RSSI), low-noise FM demodulator,
and a 3V voltage regulator. Differential peak-detecting
data demodulators are included for both the FSK and
ASK analog baseband data recovery. The MAX1471
includes a discontinuous receive (DRX) mode for low­power operation, which is configured through a serial
interface bus.

The MAX1471 is available in a 32-pin thin QFN package
and is specified over the automotive -40°C to +125°C
temperature range.

Applications

Automotive Remote Keyless Entry (RKE)

Tire Pressure Monitoring Systems

Garage Door Openers

Wireless Sensors

Wireless Keys

Security Systems

Medical Systems

Home Automation

Local Telemetry Systems

Features

♦ ASK and FSK Demodulated Data on Separate

Outputs

♦ Specified over Automotive -40°C to +125°C

Temperature Range

♦ Low Operating Supply Voltage Down to 2.4V
♦ On-Chip 3V Regulator for 5V Operation
♦ Low Operating Supply Current

7mA Continuous Receive Mode

1.1µA Deep-Sleep Mode

♦ Discontinuous Receive (DRX) Low-Power

Management

♦ Fast-On Startup Feature < 250µs
♦ Integrated PLL, VCO, and Loop Filter
♦ 45dB Integrated Image Rejection
♦ RF Input Sensitivity*

ASK: -114dBm
FSK: -108dBm

♦ Selectable IF BW with External Filter
♦ Programmable Through Serial User Interface
♦ RSSI Output and High Dynamic Range with AGC

MAX1471

315MHz/434MHz Low-Power, 3V/5V

ASK/FSK Superheterodyne Receiver

________________________________________________________________ Maxim Integrated Products 1

32 31 30 29 28 27 26

9101112131415

18

19

20

21

22

23

24

7

6

5

4

3

2

1

MAX1471

THIN QFN

TOP VIEW

DSA+

DSA-

OPA+

DFA

XTAL2

XTAL1

AV

DD

8

LNAIN

PDMAXA

PDMINA

AD

ATA

HV

IN

SCLK

DIO

25

FDATA

DV

DD

DGND

DFF

OPF+

DSF+

DSF-

PDMAXF

17

PDMINF

IFIN-

AGND

16

IFIN+

MIXOUT

MIXIN-

MIXIN+

LNAOUT

LNASRC

CS

Pin Configuration

19-3272; Rev 0; 4/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

*0.2% BER, 4kbps, Manchester-encoded data, 280kHz IF BW

Ordering Information

PART TEMP RANGE PIN-PACKAGE

MAX1471ATJ -40°C to +125°C 32 Thin QFN-EP**

**EP = Exposed pad.

MAX1471

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

High-Voltage Supply, HVINto DGND.......................-0.3V, +6.0V

Low-Voltage Supply, AV

DD

and DVDDto AGND .....-0.3V, +4.0V

SCLK, DIO,

CS, ADATA,

FDATA....................................(DGND - 0.3V) to (HV

IN

+ 0.3V)

All Other Pins.............................(AGND - 0.3V) to (AV

DD

+ 0.3V)

Continuous Power Dissipation (T

A

= +70°C)

32-Pin Thin QFN (derate 21.3mW/°C above +70°C) ...1702mW

Operating Temperature Range .........................-40°C to +125°C

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) ................................ +300°C

DC ELECTRICAL CHARACTERISTICS

(Typical Application Circuit, AVDD= DVDD= HVIN= +2.4V to +3.6V, fRF= 300MHz to 450MHz, TA= -40°C to +125°C, unless otherwise
noted. Typical values are at AV

DD

= DVDD= HVIN= +3.0V, fRF= 434 MHz, TA= +25°C, unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

GENERAL CHARACTERISTICS

Supply Voltage (5V) HV

IN

AVDD and DVDD unconnected from HVIN,
but connected together

4.5 5.0 5.5 V

Supply Voltage (3V) V

DD

HVIN, AVDD, and DVDD connected to power
supply

2.4 3.0 3.6 V

Operating 7.0 8.4 mA

Polling duty cycle: 10%
duty cycle

5.0

TA < +85°C

Deep-sleep current 1.1 7.1

µA

Operating 8.5 mA

Polling duty cycle: 10%
duty cycle

TA < +105°C
(Note 2)

Deep-sleep current

µA

Operating 8.6 mA

Polling duty cycle: 10%
duty cycle

Supply Current I

DD

TA < +125°C
(Note 2)

Deep-sleep current

µA

Startup Time t

ON

Time for final signal detection, does not
include baseband filter settling (Note 2)

µs

DIGITAL OUTPUTS (DIO, ADATA, FDATA)

Output High Voltage V

OH

I

SOURCE

= 250µA (Note 2)

HV

IN

­V

Output Low Voltage V

OL

I

SINK

= 250µA (Note 2)

V

DIGITAL INPUTS (CS, DIO, SCLK)

Input High Threshold V

IH

0.9 x
V

Input Low Threshold V

IL

.

0.1 x
V

DRX mode OFF current

DRX mode OFF current 15.5

DRX mode OFF current 44.1

705 855

200 250

0.15

0.15

HV

IN

14.2

865

13.4

900

36.4

HV

IN

MAX1471

315MHz/434MHz Low-Power, 3V/5V

ASK/FSK Superheterodyne Receiver

_______________________________________________________________________________________ 3

DC ELECTRICAL CHARACTERISTICS (continued)

(Typical Application Circuit, AVDD= DVDD= HVIN= +2.4V to +3.6V, fRF= 300MHz to 450MHz, TA= -40°C to +125°C, unless otherwise
noted. Typical values are at AV

DD

= DVDD= HVIN= +3.0V, fRF= 434 MHz, TA= +25°C, unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input-High Leakage Current I

IH

(Note 2) -10 µA

Input-Low Leakage Current I

IL

(Note 2) 10 µA

Input Capacitance C

IN

(Note 2) 2.0 pF

VOLTAGE REGULATOR

Output Voltage V

REG

HVIN = 5.0V, I

LOAD

= 7.0mA 3.0 V

AC ELECTRICAL CHARACTERISTICS

(Typical Application Circuit, AVDD= DVDD= HVIN= +2.4V to +3.6V, fRF= 300MHz to 450MHz, TA= -40°C to +125°C, unless otherwise
noted. Typical values are at AV

DD

= DVDD= HVIN= +3.0V, fRF= 434 MHz, TA= +25°C, unless otherwise noted.) (Note 1)

PARAMETER

CONDITIONS

UNITS

GENERAL CHARACTERISTICS

ASK

Receiver Sensitivity RF

IN

0.2% BER, 4kbps
Manchester Code, 280kHz
IF BW, 50Ω

FSK

dBm

Maximum Receiver Input Power
Level

RF

MAX

0

dBm

Receiver Input Frequency Range

f

RF

450

MHz

Receiver Image Rejection IR (Note 3) 45 dB

LNA/MIXER (Note 4)

LNA Input Impedance Z

11

Normalized to 50Ω

Voltage Conversion Gain (High­Gain Mode)

dB

Input-Referred 3rd-Order

Intercept Point (High-Gain Mode)

-38

dBm

Voltage Conversion Gain (Low­Gain Mode)

dB

Input-Referred 3rd-Order

Intercept Point (Low-Gain Mode)

-5

dBm

LO Signal Feedthrough to
Antenna

-90

dBm

Mixer Output Impedance Z

OUT

Ω

IF

Input Impedance Z

11

Ω

Operating Frequency f

IF

MHz

3dB Bandwidth 10

MHz

FM DEMODULATOR

Demodulator Gain G

FM

2.2

mV/kHz

SYMBOL

MIN TYP MAX

300

fRF = 315MHz 1 - j4.7

fRF = 434MHz 1 - j3.4

-114

-108

47.5

12.2

330

330

10.7

MAX1471

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver

4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

(Typical Application Circuit, AVDD= DVDD= HVIN= +2.4V to +3.6V, fRF= 300MHz to 450MHz, TA= -40°C to +125°C, unless otherwise
noted. Typical values are at AV

DD

= DVDD= HVIN= +3.0V, fRF= 434 MHz, TA= +25°C, unless otherwise noted.) (Note 1)

PARAMETER

CONDITIONS

UNITS

ANALOG BASEBAND

Maximum Data Filter Bandwidth BW

DF

50 kHz

Maximum Data Slicer Bandwidth

BW

DS

kHz

Maximum Peak Detector
Bandwidth

BW

PD

50 kHz

Manchester coded 33

Maximum Data Rate

Nonreturn to zero (NRZ) 66

kbps

CRYSTAL OSCILLATOR

Crystal Frequency f

XTAL

MHz

Frequency Pulling by V

DD

3

ppm/V

Maximum Crystal Inductance 50 µH

Crystal Load Capacitance 3pF

DIGITAL INTERFACE TIMING (see Figure 8)

Minimum SCLK Setup to Falling
Edge of CS

t

SC

30 ns

Minimum CS Falling Edge to
SCLK Rising-Edge Setup Time

t

CSS

30 ns

Minimum CS Idle Time t

CSI

ns

Minimum CS Period t

CS

µs

Maximum SCLK Falling Edge to
Data Valid Delay

t

DO

80 ns

Minimum Data Valid to SCLK
Rising-Edge Setup Time

t

DS

30 ns

Minimum Data Valid to SCLK
Rising-Edge Hold Time

t

DH

30 ns

Minimum SCLK High Pulse Width

t

CH

ns

Minimum SCLK Low Pulse Width

t

CL

ns

Minimum CS Rising Edge to
SCLK Rising-Edge Hold Time

t

CSH

30 ns

Maximum CS Falling Edge to
Output Enable Time

t

DV

25 ns

Maximum CS Rising Edge to
Output Disable Time

t

TR

25 ns

Note 1: Production tested at TA= +85°C. Guaranteed by design and characterization over entire temperature range.
Note 2: Guaranteed by design and characterization. Not production tested.
Note 3: The oscillator register (0x3) is set to the nearest integer result of f

XTAL

/ 100kHz (see the Oscillator Frequency Register section).

Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 15nH inductive degeneration

from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from the LNA
source to ground. The equivalent input circuit is 50Ω in series with 2.2pF. The voltage conversion gain is measured with the
LNA input matching inductor, the degeneration inductor, and the LNA/mixer resonator in place, and does not include the IF fil­ter insertion loss.

SYMBOL

MIN TYP MAX

100

9.04 13.728

125

2.125

100

100

MAX1471

315MHz/434MHz Low-Power, 3V/5V

ASK/FSK Superheterodyne Receiver

_______________________________________________________________________________________ 5

6.0

6.4

6.8

7.2

7.6

8.0

2.4 2.7 3.0 3.3 3.6

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX1471 toc01

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

+125°C

+105°C

+85°C

+25°C

-40°C

6.0

6.6

6.4

6.2

6.8

7.0

7.2

7.4

7.6

7.8

8.0

300 325 375350 400 425 450

SUPPLY CURRENT

vs. RF FREQUENCY

MAX1471 toc02

RF FREQUENCY (MHz)

SUPPLY CURRENT (mA)

+125°C

-40°C

+25°C

+105°C

+85°C

0

2

6

4

10

8

12

-40 10-15 35 60 85 110

DEEP-SLEEP CURRENT

vs. TEMPERATURE

MAX1471 toc03

TEMPERATURE (°C)

DEEP-SLEEP CURRENT (µA)

100

10

1

0.1

0.01

-123 -121 -119 -117 -115 -113

-111

BIT-ERROR RATE

vs. AVERAGE INPUT POWER (ASK DATA)

MAX1471 toc04

AVERAGE INPUT POWER (dBm)

BIT-ERROR RATE (%)

0.2% BER

fRF = 434MHz

fRF = 315MHz

280kHz IF BW

100

10

1

0.1

0.01

-115 -110-113 -108 -105

BIT-ERROR RATE

vs. AVERAGE INPUT POWER (FSK DATA)

MAX1471 toc05

AVERAGE INPUT POWER (dBm)

BIT-ERROR RATE

0.2% BER

fRF = 434MHz

fRF = 315MHz

280kHz IF BW
FREQUENCY DEVIATION = ±50kHz

-120

-117

-111

-114

-105

-108

-102

-40 10-15 35 60 85 110

SENSITIVITY

vs. TEMPERATURE (ASK DATA)

MAX1471 toc06

TEMPERATURE (°C)

SENSITIVITY (dBm)

280kHz IF BW

0.2% BER

fRF = 434MHz

fRF = 315MHz

-112

-110

-106

-108

-104

-102

-40 10-15 35 60 85 110

SENSITIVITY

vs. TEMPERATURE (FSK DATA)

MAX1471 toc07

TEMPERATURE (°C)

SENSITIVITY (dBm)

280kHz IF BW

0.2% BER

fRF = 434MHz

fRF = 315MHz

FREQUENCY DEVIATION = ±50kHz

-98

-112
110100

SENSITIVITY vs. FREQUENCY

DEVIATION (FSK DATA)

-108

-110

MAX1471 toc08

FREQUENCY DEVIATION (kHz)

SENSITIVITY (dBm)

-106

-102

-104

-100

280kHz IF BW

0.2% BER

RSSI vs. RF INPUT POWER

MAX1471 toc09

0

0.2

0.6

0.4

1.2

1.4

1.0

0.8

1.6

RSSI (V)

-130 -90 -70-110

-50

-30 -10 10

RF INPUT POWER (dBm)

AGC HYSTERESIS: 3dB

HIGH-GAIN MODE

LOW-GAIN MODE

AGC SWITCH
POINT

Typical Operating Characteristics

(Typical Application Circuit, AVDD= DVDD= HVIN= +3.0V, fRF= 434MHz, TA= +25°C, unless otherwise noted.)

MAX1471

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver

6 _______________________________________________________________________________________

0

0.6

0.3

1.2

0.9

1.8

1.5

2.1

-90 -50-70 -30 -10 10

RSSI AND DELTA vs. IF INPUT POWER

MAX1471 toc10

RF INPUT POWER (dBm)

RSSI (V)

-3.5

-1.5

-2.5

0.5

-0.5

2.5

1.5

3.5

DELTA (%)

RSSI

DELTA

0

0.4

0.8

1.2

1.6

2.0

10.4 10.5 10.710.6 10.8 10.9 11.0

FSK DEMODULATOR OUTPUT

vs. IF FREQUENCY

MAX1471 toc11

IF FREQUENCY (MHz)

FSK DEMODULATOR OUTPUT (V)

-10

10

0

30

20

50

40

60

010155202530

SYSTEM VOLTAGE GAIN

vs. IF FREQUENCY

MAX1471 toc12

IF FREQUENCY (MHz)

SYSTEM GAIN (dB)

45dB IMAGE
REJECTION

UPPER SIDEBAND

LOWER SIDEBAND

FROM RFIN
TO MIXOUT

f

RF

= 434MHz

38

40

44

42

46

48

-40 10-15 35 60 85 110

IMAGE REJECTION

vs. TEMPERATURE

MAX1471 toc13

TEMPERATURE (°C)

IMAGE REJECTION (dB)

fRF = 315MHz

fRF = 434MHz

5

-20
110100

NORMALIZED IF GAIN

vs. IF FREQUENCY

-15

MAX1471 toc14

IF FREQUENCY (MHz)

NORMALIZED IF GAIN (dBm)

-10

-5

0

10dB/

div

START: 50MHz STOP: 1GHz

S11 LOG-MAGNITUDE PLOT WITH

MATCHING NETWORK OF RFIN (434MHz)

MAX1471 toc15

0dB

0dB

434MHz

-16.4dB

S11 SMITH CHART OF RFIN (434MHz)

MAX1471 toc16

500MHz

200MHz

Typical Operating Characteristics (continued)

(Typical Application Circuit, AVDD= DVDD= HVIN= +3.0V, fRF= 434MHz, TA= +25°C, unless otherwise noted.)

MAX1471

315MHz/434MHz Low-Power, 3V/5V

ASK/FSK Superheterodyne Receiver

_______________________________________________________________________________________ 7

INPUT IMPEDANCE vs. INDUCTIVE

DEGENERATION

MAX1471 toc17

INDUCTIVE DEGENERATION (nH)

REAL IMPEDANCE (Ω)

10

10

20

30

40

50

60

70

80

90

0

1 100

fRF = 315MHz
L1 = 0nH

IMAGINARY IMPEDANCE

REAL IMPEDANCE

-325

-300

-275

-250

-225

-200

-175

-150

-125

-350

IMAGINARY IMPEDANCE (Ω)

INPUT IMPEDANCE vs. INDUCTIVE

DEGENERATION

MAX1471 toc18

INDUCTIVE DEGENERATION (nH)

REAL IMPEDANCE (Ω)

10

10

20

30

40

50

60

70

80

90

0

1100

fRF = 434MHz
L1 = 0nH

IMAGINARY
IMPEDANCE

-325

-300

-275

-250

-225

-200

-175

-150

-125

-350

IMAGINARY IMPEDANCE (Ω)

REAL IMPEDANCE

-50

-120
100 1k 1M 10M

PHASE NOISE vs. OFFSET FREQUENCY

-110

-90

-100

-60

-70

-80

MAX1471 toc19

OFFSET FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

10k 100k

fRF = 315MHz

-50

-120
100 1k 1M 10M

PHASE NOISE vs. OFFSET FREQUENCY

-110

-90

-100

-60

-70

-80

MAX1471 toc20

OFFSET FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

10k 100k

fRF = 434MHz

Typical Operating Characteristics (continued)

(Typical Application Circuit, AVDD= DVDD= HVIN= +3.0V, fRF= 434MHz, TA= +25°C, unless otherwise noted.)

PIN NAME FUNCTION

1 DSA- Inverting Data Slicer Input for ASK Data

2 DSA+ Noninverting Data Slicer Input for ASK Data

3 OPA+ Noninverting Op-Amp Input for the ASK Sallen-Key Data Filter

4 DFA Data-Filter Feedback Node. Input for the feedback of the ASK Sallen-Key data filter.

5 XTAL2 2nd Crystal Input

Pin Description

MAX1471

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver

8 _______________________________________________________________________________________

PIN NAME FUNCTION

6 XTAL1 1st Crystal Input

7AV

DD

Analog Power-Supply Voltage for RF Sections. AVDD is connected to an on-chip +3.0V low-dropout
regulator. Decouple to AGND with a 0.1µF capacitor.

8 LNAIN Low-Noise Amplifier Input

9 LNASRC

Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to AGND to set
LNA input impedance.

10

Low-Noise Amplifier Output. Connect to mixer through an LC tank filter.

11 MIXIN+ Differential Mixer Input. Must be AC-coupled to driving input.

12 MIXIN- Differential Mixer Input. Bypass to AGND with a capacitor.

13 MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz IF filter.

14 AGND Analog Ground

15 IFIN- Differential 330Ω IF Limiter Amplifier Input. Bypass to AGND with a capacitor.

16 IFIN+ Differential 330Ω IF Limiter Amplifier Input. Connect to output of the 10.7MHz IF filter.

17 PDMINF Minimum-Level Peak Detector for FSK Data

18

Maximum-Level Peak Detector for FSK Data

19 DSF- Inverting Data Slicer Input for FSK Data

20 DSF+ Noninverting Data Slicer Input for FSK Data

21 OPF+ Noninverting Op-Amp Input for the FSK Sallen-Key Data Filter

22 DFF Data-Filter Feedback Node. Input for the feedback of the FSK Sallen-Key data filter.

23 DGND Digital Ground

24 DV

DD

Digital Power-Supply Voltage for Digital Sections. Connect to AVDD. Decouple to DGND with a 10nF
capacitor.

25 FDATA Digital Baseband FSK Demodulator Data Output

26 CS Active-Low Chip-Select Input

27 DIO Serial Data Input/Output

28 SCLK Serial Interface Clock Input

29 HV

IN

High-Voltage Supply Input. For 3V operation, connect HVIN to AVDD and DVDD.

30 ADATA Digital Baseband ASK Demod Data Output

31 PDMINA Minimum-Level Peak Detector for ASK Output

32

Maximum-Level Peak Detector for ASK Output

EP GND Exposed Paddle. Connect to ground.

Pin Description (continued)

LNAOUT

PDMAXF

PDMAXA

MAX1471

315MHz/434MHz Low-Power, 3V/5V

ASK/FSK Superheterodyne Receiver

_______________________________________________________________________________________ 9

FSK

DEMODULATOR

RSSI

Σ

90

°

0

°

VCO

DIVIDE

BY 32

PHASE

DETECTOR

CRYSTAL

OSCILLATOR

SERIAL INTERFACE,

CONTROL REGISTERS,

AND POLLING TIMER

LOOP

FILTER

LNA

3.0V
REG

3.0V

4

DFA

3

OPA+

2

DSA+

31

PDMINA

32

PDMAXA

1

DSA-

30

ADATA

8

LNAIN

9

LNASRC

6

XTAL1

14

AGND

5

XTAL2

26

27

DIO

28

SCLK

24

23DGND

29

HV

IN

AV

DD

7

10

LNAOUT11MIXIN+12MIXIN-

13

MIXOUT15IFIN-16IFIN+

25

FDATA19DSF-18PDMAXF

17

PDMINF

20

DSF+21OPF+22DFF

DV

DD

CS

IF LIMITING
AMPS

ASK DATA FILTER

FSK DATA

FILTER

IMAGE

REJECTION

ASK

FSK

R

DF1

100kΩ

R

DF2

100kΩ

R

DF1

100kΩ

R

DF2

100kΩ

MAX1471

Functional Diagram

MAX1471

Detailed Description

The MAX1471 CMOS superheterodyne receiver and a
few external components provide a complete ASK/FSK
receive chain from the antenna to the digital output data.
Depending on signal power and component selection,
data rates as high as 33kbps using Manchester Code
(66kbps nonreturn to zero) can be achieved.

The MAX1471 is designed to receive binary FSK or
ASK data on a 300MHz to 450MHz carrier. ASK modu­lation uses a difference in amplitude of the carrier to
represent logic 0 and logic 1 data. FSK uses the differ­ence in frequency of the carrier to represent a logic 0
and logic 1.

Low-Noise Amplifier (LNA)

The LNA is a cascode amplifier with off-chip inductive
degeneration that achieves approximately 28dB of volt­age gain that is dependent on both the antenna-match­ing network at the LNA input, and the LC tank network
between the LNA output and the mixer inputs.

The off-chip inductive degeneration is achieved by con­necting an inductor from LNASRC to AGND. This induc­tor sets the real part of the input impedance at LNAIN,
allowing for a flexible match to low input impedances
such as a PC board trace antenna. A nominal value for
this inductor with a 50Ω input impedance is 15nH at
315MHz and 10nH at 434MHz, but the inductance is
affected by PC board trace length. See the Typical
Operating Characteristics to see the relationship
between the inductance and input impedance. The
inductor can be shorted to ground to increase sensitivi­ty by approximately 1dB, but the input match is not
optimized for 50Ω.

The LC tank filter connected to LNAOUT comprises L2
and C9 (see the Typical Application Circuit). Select L2
and C9 to resonate at the desired RF input frequency.
The resonant frequency is given by:

where L

TOTAL

= L2 + L

PARASITICS

and C

TOTAL

= C9 +

C

PARASITICS

.

L

PARASITICS

and C

PARASITICS

include inductance and
capacitance of the PC board traces, package pins,
mixer input impedance, LNA output impedance, etc.
These parasitics at high frequencies cannot be
ignored, and can have a dramatic effect on the tank fil­ter center frequency. Lab experimentation should be
done to optimize the center frequency of the tank.

Automatic Gain Control (AGC)

When the AGC is enabled, it monitors the RSSI output.
When the RSSI output reaches 1.28V, which corre­sponds to an RF input level of approximately -64dBm,
the AGC switches on the LNA gain reduction attenuator.
The attenuator reduces the LNA gain by 35dB, thereby
reducing the RSSI output by about 0.55V. The LNA
resumes high-gain mode when the RSSI output level
drops back below 0.68V (approximately -67dBm at the
RF input) for a programmable interval called the AGC
dwell time. The AGC has a hysteresis of approximately
3dB. With the AGC function, the RSSI dynamic range is
increased, allowing the MAX1471 to reliably produce an
ASK output for RF input levels up to 0dBm with a modu­lation depth of 18dB. AGC is not necessary and can be
disabled when utilizing only the FSK data path.

The MAX1471 features an AGC lock controlled by the
AGC lock bit (see Table 8). When the bit is set, the LNA
is locked in its present gain state.

Mixer

A unique feature of the MAX1471 is the integrated
image rejection of the mixer. This device was designed
to eliminate the need for a costly front-end SAW filter for
many applications. The advantage of not using a SAW
filter is increased sensitivity, simplified antenna match­ing, less board space, and lower cost.

The mixer cell is a pair of double-balanced mixers that
perform an IQ downconversion of the RF input to the

10.7MHz intermediate frequency (IF) with low-side
injection (i.e., fLO= fRF- fIF). The image-rejection circuit
then combines these signals to achieve approximately
45dB of image rejection. Low-side injection is required
as high-side injection is not possible due to the on-chip
image rejection. The IF output is driven by a source fol­lower, biased to create a driving impedance of 330Ω to
interface with an off-chip 330Ω ceramic IF filter. The
voltage conversion gain driving a 330Ω load is approxi-
mately 19.5dB. Note that the MIXIN+ and MIXIN- inputs
are functionally identical.

Phase-Locked Loop (PLL)

The PLL block contains a phase detector, charge
pump/integrated loop filter, voltage-controlled oscillator
(VCO), asynchronous 32x clock divider, and crystal
oscillator. This PLL does not require any external com­ponents. The relationship between the RF, IF, and refer­ence frequencies is given by:

f

REF

= (fRF- fIF)/32

To allow the smallest possible IF bandwidth (for best sen­sitivity), the tolerance of the reference must be minimized.

f

LC

TOTAL TOTAL

=

×

1

2π

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver

10 ______________________________________________________________________________________

Intermediate Frequency (IF)

The IF section presents a differential 330Ω load to pro-
vide matching for the off-chip ceramic filter. It contains
five AC-coupled limiting amplifiers with a bandpass-fil­ter-type response centered near the 10.7MHz IF fre­quency with a 3dB bandwidth of approximately 10MHz.
For ASK data, the RSSI circuit demodulates the IF to
baseband by producing a DC output proportional to
the log of the IF signal level with a slope of approxi­mately 16mV/dB. For FSK, the limiter output is fed into a
PLL to demodulate the IF.

FSK Demodulator

The FSK demodulator uses an integrated 10.7MHz PLL
that tracks the input RF modulation and determines the
difference between frequencies as logic-level ones and
zeros. The PLL is illustrated in Figure 1. The input to the
PLL comes from the output of the IF limiting amplifiers.
The PLL control voltage responds to changes in the fre­quency of the input signal with a nominal gain of

2.2mV/kHz. For example, an FSK peak-to-peak devia­tion of 50kHz generates a 110mV

P-P

signal on the con­trol line. This control line is then filtered and sliced by
the FSK baseband circuitry.

The FSK demodulator PLL requires calibration to over­come variations in process, voltage, and temperature.
For more information on calibrating the FSK demodula­tor, see the Calibration section. The maximum calibra­tion time is 120µs. In DRX mode, the FSK demodulator
calibration occurs automatically just before the IC
enters sleep mode.

Crystal Oscillator

The XTAL oscillator in the MAX1471 is used to generate
the local oscillator (LO) for mixing with the received sig­nal. The XTAL oscillator frequency sets the received
signal frequency as:

f

RECEIVE

= (f

XTAL

x 32) +10.7MHz

The received image frequency at:

f

IMAGE

= (f

XTAL

x 32) -10.7MHz

is suppressed by the integrated quadrature image­rejection circuitry.

For an input RF frequency of 315MHz, a reference fre­quency of 9.509MHz is needed for a 10.7MHz IF fre­quency (low-side injection is required). For an input RF
frequency of 433.92MHz, a reference frequency of

13.2256MHz is required.

The XTAL oscillator in the MAX1471 is designed to pre­sent a capacitance of approximately 3pF between the
XTAL1 and XTAL2. If a crystal designed to oscillate
with a different load capacitance is used, the crystal is
pulled away from its stated operating frequency, intro­ducing an error in the reference frequency. Crystals
designed to operate with higher differential load capac­itance always pull the reference frequency higher.

In actuality, the oscillator pulls every crystal. The crys­tal’s natural frequency is really below its specified fre­quency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.

Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:

where:

fpis the amount the crystal frequency pulled in ppm.

C

m

is the motional capacitance of the crystal.

C

case

is the case capacitance.

C

spec

is the specified load capacitance.

C

load

is the actual load capacitance.

When the crystal is loaded as specified, i.e., C

load

=

C

spec

, the frequency pulling equals zero.

f

C

CCCC

p

m

case load case spec

6

=

+

−
+













×

2

11

10

MAX1471

315MHz/434MHz Low-Power, 3V/5V

ASK/FSK Superheterodyne Receiver

______________________________________________________________________________________ 11

Figure 1. FSK Demodulator PLL Block Diagram

LOOP

FILTER

10.7MHz VCO

2.2mV/kHz

CHARGE

PUMP

PHASE

DETECTOR

IF

LIMITING

AMPS

TO FSK BASEBAND FILTER
AND DATA SLICER

MAX1471

Data Filters

The data filters for the ASK and FSK data are imple­mented as a 2nd-order lowpass Sallen-Key filter. The
pole locations are set by the combination of two on­chip resistors and two external capacitors. Adjusting
the value of the external capacitors changes the corner
frequency to optimize for different data rates. The cor­ner frequency in kHz should be set to approximately

1.5 times the fastest expected Manchester data rate in
kbps from the transmitter. Keeping the corner frequen­cy near the data rate rejects any noise at higher fre­quencies, resulting in an increase in receiver sensitivity.

The configuration shown in Figure 3 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very flat amplitude response in the passband

and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works well for filtering digital data. To calculate the
value of the capacitors, use the following equations,
along with the coefficients in Table 2:

where fCis the desired 3dB corner frequency.

For example, choose a Butterworth filter response with
a corner frequency of 5kHz:

C

b

akf

C

a

kf

F1

C

F2

C

=

()()()

=

()()()

100

4 100ππ

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver

12 ______________________________________________________________________________________

Figure 2. Typical Application Circuit

ASK DATA OUT

SCLK

DIO

FSK DATA OUT

MAX1471

V

CC

IN GND

Y2

OUT

CS

DFF

22

DSF-

19

PDMAXF

18

PDMINF

17

PDMAXA

32

PDMINA

31

ADATA

30

HV

IN

29

SLCK

28

DIO

27 26

FDATA

25

DSA+

2

LNASRC9LNAOUT

10

MIXOUT13AGND14IFIN+

16

CS

DV

DD

24

DGND

23

C23

V

DD

OPF+

21

C21

C22

R8

C27

DSF+

20

V

DD

OPA+

3

C3

OPF+

21

C21

DSA-

1

C5

DFA

4

R3

C4

XTAL2

5

C14

XTAL1

6

C15

AV

DD

7

C6

V

DD

C7

LNAIN

8

RF INPUT

Y1

C9

L3

MIXIN-

12

C10

C8

IFIN-

15

C12

MIXIN+

11

C11

V

DD

L2

L1

C26

3.0V

V

DD

Choosing standard capacitor values changes CF1to
470pF and C

F2

to 220pF. In the Typical Application

Circuit, C

F1

and CF2are named C4 and C3, respective-

ly, for ASK data, and C21 and C22 for FSK data.

Data Slicers

The purpose of a data slicer is to take the analog output
of a data filter and convert it to a digital signal. This is
achieved by using a comparator and comparing the ana­log input to a threshold voltage. The threshold voltage is

set by the voltage on the DSA- pin for the ASK receive
chain (DSF- for the FSK receive chain), which is connect­ed to the negative input of the data slicer comparator.

Numerous configurations can be used to generate the
data-slicer threshold. For example, the circuit in Figure
4 shows a simple method using only one resistor and
one capacitor. This configuration averages the analog
output of the filter and sets the threshold to approxi­mately 50% of that amplitude. With this configuration,
the threshold automatically adjusts as the analog signal
varies, minimizing the possibility for errors in the digital
data. The sizes of R and C affect how fast the threshold
tracks to the analog amplitude. Be sure to keep the cor­ner frequency of the RC circuit much lower than the
lowest expected data rate.

C

k kHz

pF

C

k kHz

pF

F1

F2

=

()( )()()

≈

=

()( )( )( )

≈

1 000

1 414 100 3 14 5

450

1 414

4 100 3 14 5

225

.

..

.

.

Ω

Ω

MAX1471

315MHz/434MHz Low-Power, 3V/5V

ASK/FSK Superheterodyne Receiver

______________________________________________________________________________________ 13

Table 1. Component Values for Typical Application Circuit

COMPONENT VALUE FOR 433.92MHz RF VALUE FOR 315MHz RF DESCRIPTION (%)

C3 220pF 220pF 10

C4 470pF 470pF 5

C5 0.047µF 0.047µF 10

C6 0.1µF 0.1µF 10

C7 100pF 100pF 5

C8 100pF 100pF 5

C9 1.0pF 2.2pF ±0.1pF

C10 220pF 220pF 10

C11 100pF 100pF 5

C12 1500pF 1500pF 10

C14 15pF 15pF 5

C15 15pF 15pF 5

C21 220pF 220pF 10

C22 470pF 470pF 5

C23 0.01µF 0.01µF 10

C26 0.1µF 0.1µF 10

C27 0.047µF 0.047µF 10

L1 56nH 100nH Coilcraft 0603CS

L2 16nH 30nH Coilcraft 0603CS

L3 10nH 15nH 5

R3 25kΩ 25kΩ 5
R8 25kΩ 25kΩ 5

Y1 13.2256MHz 9.509MHz Crystal

Y2 10.7MHz ceramic filter 10.7MHz ceramic filter Murata SFECV10.7 series

Note: Component values vary depending on PC board layout.

MAX1471

With this configuration, a long string of NRZ zeros or
ones can cause the threshold to drift. This configuration
works best if a coding scheme, such as Manchester
coding, which has an equal number of zeros and ones,
is used.

Figure 5 shows a configuration that uses the positive and
negative peak detectors to generate the threshold. This
configuration sets the threshold to the midpoint between
a high output and a low output of the data filter.

Peak Detectors

The maximum peak detectors (PDMAXA for ASK,
PDMAXF for FSK) and minimum peak detectors (PDMI­NA for ASK, PDMINF for FSK), in conjunction with resis­tors and capacitors shown in Figure 5, create DC
output voltages proportional to the high and low peak
values of the filtered ASK or FSK demodulated signals.
The resistors provide a path for the capacitors to dis­charge, allowing the peak detectors to dynamically fol­low peak changes of the data-filter output voltages.

The maximum and minimum peak detectors can be
used together to form a data-slicer threshold voltage at
a midvalue between the maximum and minimum volt­age levels of the data stream (see the Data Slicers sec­tion and Figure 5). The RC time constant of the peak­detector combining network should be set to at least 5
times the data period.

If there is an event that causes a significant change in
the magnitude of the baseband signal, such as an AGC
gain switch or a power-up transient, the peak detectors
may “catch” a false level. If a false peak is detected,
the slicing level is incorrect. The MAX1471 has a fea­ture called peak-detector track enable (TRK_EN),
where the peak-detector outputs can be reset (see
Figure 6). If TRK_EN is set (logic 1), both the maximum
and minimum peak detectors follow the input signal.
When TRK_EN is cleared (logic 0), the peak detectors
revert to their normal operating mode. The TRK_EN
function is automatically enabled for a short time and
then disabled whenever the IC recovers from the sleep
portion of DRX mode, or when an AGC gain switch
occurs. Since the peak detectors exhibit a fast
attack/slow decay response, this feature allows for an
extremely fast startup or AGC recovery. See Figure 7
for an illustration of a fast-recovery sequence. In addi­tion to the automatic control of this function, the
TRK_EN bits can be controlled through the serial inter­face (see the Serial Control Interface section).

Power-Supply Connections

The MAX1471 can be powered from a 2.4V to 3.6V sup­ply or a 4.5V to 5.5V supply. The device has an on-chip
linear regulator that reduces the 5V supply to 3V need­ed to operate the chip.

To operate the MAX1471 from a 3V supply, connect
DV

DD

, AVDD, and HVINto the 3V supply. When using a

5V supply, connect the supply to HV

IN

only and con-

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver

14 ______________________________________________________________________________________

Figure 3. Sallen-Key Lowpass Data Filter

MAX1471

DSA+
DSF+

OPA+
OPF+

DFA
DFF

100kΩ 100kΩ

C

F2

C

F1

RSSI OR

FSK DEMOD

Table 2. Coefficients to Calculate C

F1

and C

F2

FILTER TYPE a b

Butterworth
(Q = 0.707)

1.414 1.000

Bessel

(Q = 0.577)

1.3617 0.618

Figure 4. Generating Data-Slicer Threshold Using a Lowpass
Filter

MAX1471

DATA

SLICER

ADATA
FDATA

DSA­DSF-

DSA+
DSF+

C

R

nect AVDDand DVDDtogether. In both cases, bypass
DVDDand HVINwith a 0.01µF capacitor and AVDDwith

a 0.1µF capacitor. Place all bypass capacitors as close
to the respective supply pin as possible.

MAX1471

315MHz/434MHz Low-Power, 3V/5V

ASK/FSK Superheterodyne Receiver

______________________________________________________________________________________ 15

Figure 5. Generating Data-Slicer Threshold Using the Peak Detectors

MAXIMUM PEAK

DETECTOR

MAX1471

DATA

SLICER

PDMAXA
PDMAXF

ADATA
FDATA

C

MINIMUM PEAK

DETECTOR

PDMINA
PDMINF

RR

C

Figure 6. Peak-Detector Track Enable

TRK_EN = 1

MINIMUM PEAK

DETECTOR

PDMINA
PDMINF

TRK_EN = 1

MAXIMUM PEAK

DETECTOR

BASEBAND

FILTER

PDMAXA
PDMAXF

MAX1471

TO SLICER
INPUT

MAX1471

Serial Control Interface

Communication Protocol

The MAX1471 can use a 4-wire interface or a 3-wire
interface (default). In both cases, the data input must
follow the timing diagrams shown in Figures 8 and 9.

Note that the DIO line must be held LOW while CS is
high. This is to prevent the MAX1471 from entering dis­continuous receive mode if the DRX bit is high. The
data is latched on the rising edge of SCLK, and there­fore must be stable before that edge. The data
sequencing is MSB first, the command (C[3:0]; see
Table 3), the register address (A[3:0]; see Table 4) and
the data (D[7:0]; see Table 5).

The mode of operation (3-wire or 4-wire interface) is
selected by DOUT_FSK and/or DOUT_ASK bits in the
configuration register. Either of those bits selects the
ASKOUT and/or FSKOUT line as a SERIAL data output.
Upon receiving a read register command (0x2), the
serial interface outputs the data on either pin, accord­ing to Figure 10.

If neither of these bits are 1, the 3-wire interface is
selected (default on power-up) and the DIO line is
effectively a bidirectional input/output line. DIO is
selected as an output of the MAX1471 for the following
CS cycle whenever a READ command is received. The
CPU must tri-state the DIO line on the cycle of CS that
follows a read command, so the MAX1471 can drive
the data output line. Figure 11 shows the diagram of
the 3-wire interface. Note that the user can choose to
send either 16 cycles of SCLK, as in the case of the 4­wire interface, or just eight cycles, as all the registers
are 8-bits wide. The user must drive DIO low at the end
of the read sequence.

The MASTER RESET command (0x3) (see Table 3)
sends a reset signal to all the internal registers of the
MAX1471 just like a power-off and power-on sequence

would do. The reset signal remains active for as long as
CS is high after the command is sent.

Continuous Receive Mode (DRX = 0)

In continuous receive mode, individual analog modules
can be powered on directly through the power configu­ration register (register 0x0). The SLEEP bit (bit 0)
overrides the power settings of the remaining bits and
puts the part into deep-sleep mode when set. It is also
necessary to write the frequency divisor of the external
crystal in the oscillator frequency register (register 0x3)
to optimize image rejection and to enable accurate cali­bration sequences for the polling timer and the FSK
demodulator. This number is the integer result of f

XTAL

/

100kHz.

If the FSK receive function is selected, it is necessary to
perform an FSK calibration to improve receive sensitivi­ty. Polling timer calibration is not necessary. See the
Calibration section for more information.

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver

16 ______________________________________________________________________________________

Figure 7. Fast Receiver Recovery in FSK Mode Utilizing Peak
Detectors

200mV/div

DATA OUTPUT

2V/div

MIN PEAK DETECTOR

MAX PEAK DETECTOR

RECEIVER ENABLED, TRK_EN SET

TRK_EN CLEARED

FILTER OUTPUT

DATA OUTPUT

100µs/div

Figure 8. Digital Communications Timing Diagram

t

DH

HIGH-IMPEDANCE

DATA OUT

DATA IN

HIGH-IMPEDANCE

HI-Z

SCLK

DIO

D7

D0

CS

t

CSS

t

CH

t

DI

t

SC

t

CL

t

DV

t

CSH

t

DO

t

TR

t

CS

t

CSI

Discontinuous Receive Mode (DRX = 1)

In the discontinuous receive mode (DRX = 1), the
power signals of the different modules of the MAX1471
toggle between OFF and ON, according to internal
timers t

OFF

, t

CPU

, and tRF. It is also necessary to write
the frequency divisor of the external crystal in the oscil­lator frequency register (register 0x3). This number is
the integer result of f

XTAL

/ 100kHz. Before entering the
discontinuous receive mode for the first time, it is also
necessary to calibrate the timers (see the Calibration
section).

The MAX1471 uses a series of internal timers (t

OFF

,

t

CPU

, and tRF) to control its power-up. The timer

sequence begins when both CS and DIO are one. The
MAX1471 has an internal pullup on the DIO pin, so the
user must tri-state the DIO line when CS goes high.

The external CPU can then go to a sleep mode during
t

OFF

. A high-to-low transition on DIO, or a low level on

DIO serves as the wake-up signal for the CPU, which
must then start its wake-up procedure, and drive DIO
low before t

LOW

expires (t

CPU

+ tRF). Once tRFexpires,
the MAX1471 enables the FSKOUT and/or ASKOUT
data outputs. The CPU must then keep DIO low for as
long as it may need to analyze any received data.
Releasing DIO causes the MAX1471 to pull up DIO,
reinitiating the t

OFF

timer.

Oscillator Frequency Register (Address: 0x3)

The MAX1471 has an internal frequency divider that
divides down the crystal frequency to 100kHz. The
MAX1471 uses the 100kHz clock signal when calibrating
itself and also to set the image-rejection frequency. The
hexadecimal value written to the oscillator frequency reg­ister is the nearest integer result of f

XTAL

/ 100kHz.

MAX1471

315MHz/434MHz Low-Power, 3V/5V

ASK/FSK Superheterodyne Receiver

______________________________________________________________________________________ 17

Figure 9. Data Input Diagram

SCLK

A2 A1 D0

ADDRESS

DATA

DIO C3 A3C0C1C2 A0 D7 D6 D5 D4 D3 D2 D1

COMMAND

CS

Figure 10. Read Command on a 4-Wire SERIAL Interface

SCLK

CS

0 0 1 0 0 0 0 0 0 0 0 0A3 A2 A1 A0

DIO

C3 C2 C1 C0 A3 A2 A1 A0 D0D7

COMMAND

ADDRESS

DATA

READ

COMMAND

ADDRESS

DATA

ADATA (IF DOUT_ASK = 1)

R7 R6 R5 R4 R3 R2 R1 R0 R0R7

REGISTER DATA

REGISTER

DATA

FDATA (IF DOUT_FSK = 1)

R7 R6 R5 R4 R3 R2 R1 R0 R0R7

REGISTER DATA

REGISTER

DATA

MAX1471

For example, if data is being received at 315MHz, the
crystal frequency is 9.509375MHz. Dividing the crystal
frequency by 100kHz and rounding to the nearest inte­ger gives 95, or 0x5F hex. So for 315MHz, 0x5F would
be written to the oscillator frequency register.

AGC Dwell Timer Register (Address: 0xA)

The AGC dwell timer holds the AGC in low-gain state
for a set amount of time after the power level drops
below the AGC switching threshold. After that set
amount of time, if the power level is still below the AGC
threshold, the LNA goes into high-gain state. This is
important for ASK since the modulated data may have
a high level above the threshold and a low level below
the threshold, which without the dwell timer would
cause the AGC to switch on every bit.

The AGC dwell time is dependent on the crystal fre­quency and the bit settings of the AGC dwell timer reg-

ister. To calculate the dwell time, use the following
equation:

where Reg 0xA is the value of register 0xA in decimal.

To calculate the value to write to register 0xA, use the
following equation and use the next integer higher than
the calculated result:

Reg 0xA ≥ 3.3 x log

10

(Dwell Time x f

XTAL

)

For Manchester Code (50% duty cycle), set the dwell
time to at least twice the bit period. For nonreturn-to­zero (NRZ) data, set the dwell to greater than the peri­od of the longest string of zeros or ones. For example,
using Manchester code at 315MHz (f

XTAL

=

9.509375MHz) with a data rate of 4kbps (bit period =
125µs), the dwell time needs to be greater than 250µs:

Reg 0xA ≥ 3.3 x log

10

(250µs x 9.509375MHz) ≈11.14

Choose the register value to be the next integer value
higher than 11.14, which is 12 or 0x0C hex.

The default value of the AGC dwell timer on power-up
or reset is 0x0D.

Dfwell Time

Reg0xA

XTAL

=

2

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver

18 ______________________________________________________________________________________

Figure 11. Read Command in 3-Wire Interface

0 0 1 0 0 0 0 0 0 0 0 0A3 A2 A1 A0

READ

COMMAND

ADDRESS DATA

DIO

R7 R6 R5 R4 R3 R2 R1 R0 R0R7

REGISTER DATA

REGISTER

DATA

16 BITS OF DATA

CS

SCLK

0 0 1 0 0 0 0 0 0 0 0 0A3 A2 A1 A0 R7 R6 R5 R4 R3 R2 R1 A3

8 BITS OF DATA

READ

COMMAND

ADDRESS DATA

REGISTER DATA

DIO

CS

SCLK

Table 3. Command Bits

C[3:0] DESCRIPTION

0x0 No operation

0x1 Write data

0x2 Read data

0x3 Master reset

0x4–0xF Not used

Calibration

The MAX1471 must be calibrated to ensure accurate
timing of the off timer in discontinuous receive mode or
when receiving FSK signals. The first step in calibration
is ensuring that the oscillator frequency register
(address: 0x3) has been programmed with the correct
divisor value (see the Oscillator Frequency Register
section). Next, enable the mixer to turn the crystal dri­ver on.

Calibrate the polling timer by setting POL_CAL_EN = 1
in the configuration register (register 0x1). Upon com­pletion, the POL_CAL_DONE bit in the status register
(register 0x8) is 1, and the POL_CAL_EN bit is reset to
zero. If using the MAX1471 in continuous receive
mode, polling timer calibration is not needed.

FSK receiver calibration is a two-step process. Set
FSKCALLSB = 1 (register 0x1) or to reduce the calibra­tion time, accuracy can be sacrificed by setting the
FSKCALLSB = 0. Next, initiate FSK receiver calibration,
set FSK_CAL_EN = 1. Upon completion, the

FSK_CAL_DONE bit in the status register (register 0x8)
is one, and the FSK_CAL_EN bit is reset to zero.

When in continuous receive mode and receiving FSK
data, recalibrate the FSK receiver after a significant
change in temperature or supply voltage. When in dis­continuous receive mode, the polling timer and FSK
receiver (if enabled) are automatically calibrated during
every wake-up cycle.

Off Timer (t

OFF

)

The first timer, t

OFF

(see Figure 12), is a 16-bit timer
that is configured using: register 0x4 for the upper byte,
register 0x5 for the lower byte, and bits PRESCALE1
and PRESCALE0 in the configuration register (register
0x1). Table 10 summarizes the configuration of the t

OFF

timer. The PRESCALE1 and PRESCALE2 bits set the
size of the shortest time possible (t

OFF

time base). The

data written to the t

OFF

registers (0x4 and 0x5) is multi-

plied by the time base to give the total t

OFF

time. On
power-up, the off timer registers are set to zero and
must be written before using DRX mode.

MAX1471

315MHz/434MHz Low-Power, 3V/5V

ASK/FSK Superheterodyne Receiver

______________________________________________________________________________________ 19

Table 4. Register Summary

REGISTER

A[3:0]

REGISTER NAME DESCRIPTION

0x0 Power configuration

Enables/disables the LNA, AGC, mixer, baseband, peak detectors, and sleep mode
(see Table 6).

0x1 Configuration

Sets options for the device such as output enables, off-timer prescale, and
discontinuous receive mode (see Table 7).

0x2 Control

Controls AGC lock, peak-detector tracking, as well as polling timer and FSK
calibration (see Table 8).

0x3 Oscillator frequency

Sets the internal clock frequency divisor. This register must be set to the integer

result of f

XTAL

/ 100kHz (see the Oscillator Frequency Register section).

0x4

Off timer—t

OFF

(upper byte)

0x5

Off timer—t

OFF

(lower byte)

Sets the duration that the MAX1471 remains in low-power mode when DRX is active
(see Table 10).

0x6

Increases maximum time the MAX1471 stays in lower power mode while CPU wakes
up when DRX is active (see Table 11).

0x7

RF settle timer—t

RF

(upper byte)

0x8

RF settle timer—t

RF

(lower byte)

During the time set by the settle timer, the MAX1471 is powered on with the peak
detectors and the data outputs disabled to allow time for the RF section to settle.
DIO must be driven low at any time during t

LOW

= t

CPU

+ tRF or the timer sequence

restarts (see Table 12).

0x9

Provides status for PLL lock, AGC state, crystal operation, polling timer, and FSK
calibration (see Table 9).

0xA AGC dwell timer Controls the dwell (release) time of the AGC.

CPU recovery timer—t

Status register (read only)

CPU

MAX1471

During t

OFF

, the MAX1471 is operating with very low
supply current (5.0µA typ), where all of its modules are
turned off, except for the t

OFF

timer itself. Upon com-

pletion of the t

OFF

time, the MAX1471 signals the user

by asserting DIO low.

CPU Recovery Timer (t

CPU

)

The second timer, t

CPU

(see Figure 12), is used to delay
the power-up of the MAX1471, thereby providing extra
power savings and giving a CPU the time required to
complete its own power-on sequence. The CPU is sig­naled to begin powering up when the DIO line is pulled
low by the MAX1471 at the end of t

OFF

. t

CPU

then begins

counting down, while DIO is held low by the MAX1471.
At the end of t

CPU

, the tRFcounter begins.

t

CPU

is an 8-bit timer, configured through register 0x6.

The possible t

CPU

settings are summarized in Table 11.

The data written to the t

CPU

register (0x6) is multiplied

by 120µs to give the total t

CPU

time. On power-up, the
CPU timer register is set to zero and must be written
before using DRX mode.

RF Settle Timer (t

RF

)

The third timer, tRF(see Figure 12), is used to allow the
RF sections of the MAX1471 to power up and stabilize
before ASK or FSK data is received. tRFbegins count-

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver

20 ______________________________________________________________________________________

Table 5. Register Configuration

ADDRESS DATA

A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

POWER CONFIGURATION (0x0)

0 0 0 0

EN

EN

ASKBB_ENASKPD_

EN

SLEEP

CONFIGURATION (0x1)

0 0 0 1 X

GAIN

SET*

FSKCALLSBFSK_

ASK_

PS1

PS0

DRX_

MODE

CONTROL (0x2)

0 0 1 0 X

AGC

XX

FSKTRK_ENASKTRK_ENP OL_

FSK_CAL

_EN

OSCILLATOR FREQUENCY (0x3)

0 0 1 1 d7 d6 d5d4d3d2d1d0

OFF TIMER (upper byte) (0x4)

0 1 0 0 t15 t14 t13 t12 t11 t10 t9 t8

OFF TIMER (lower byte) (0x5)

0 1 0 1 t7 t6 t5t4t3t2t1t0

CPU RECOVERY TIMER (0x6)

0 1 1 0 t7 t6 t5t4t3t2t1t0

RF SETTLE TIMER (upper byte) (0x7)

0 1 1 1 t15 t14 t13 t12 t11 t10 t9 t8

RF SETTLE TIMER (lower byte) (0x8)

1 0 0 0 t7 t6 t5t4t3t2t1t0

STATUS REGISTER (read only) (0x9)

1 0 0 1

DET

CLK

XXX

P OL_C AL

FSK_CAL

_DONE

AGC DWELL TIMER (0xA)

1 0 1 0 X X X dt4 dt3* dt2* dt1 dt0*

*Power-up state = 1. All other bits, power-up state = 0.

LNA_EN AGC_EN

LOCK

MIXER_

LOCK

AGCST

ALIVE

FSKBB_ENFSKPD_

TOFF_

DOUT

DOUT

TOFF_

C AL_E N

_D O N E

ing once t

CPU

has expired. At the beginning of tRF, the
modules selected in the power control register (register
0x0) are powered up with the exception of the peak
detectors and have the tRFperiod to settle.

At the end of t

RF

, the MAX1471 stops driving DIO low
and enables ADATA, FDATA, and peak detectors if
chosen to be active in the power configuration register
(0x0). The CPU must be awake at this point, and must
hold DIO low for the MAX1471 to remain in operation.
The CPU must begin driving DIO low any time during
t

LOW

= t

CPU

+ tRF. If the CPU fails to drive DIO low,
DIO is pulled high through the internal pullup resistor,
and the timer sequence is restarted, leaving the
MAX1471 powered down. Any time the DIO line is dri­ven high while the DRX = 1, the DRX sequence is initi­ated, as defined in Figure 12.

tRFis a 16-bit timer, configured through registers 0x7
(upper byte) and 0x8 (lower byte). The possible t

RF

set-

tings are in Table 12. The data written to the t

RF

register

(0x7 and 0x8) is multiplied by 120µs to give the total t

RF

time. On power-up, the RF timer registers are set to
zero and must be written before using DRX mode.

Typical Power-Up Procedure

Here is a typical power-up procedure for receiving either
ASK or FSK signals at 315MHz in continuous mode:

1) Write 0x3000 to reset the part.

2) Write 0x10FE to enable all RF and baseband sections.

3) Write 0x135F to set the oscillator frequency register
to work with a 315MHz crystal.

4) Write 0x1120 to set FSKCALLSB for an accurate
FSK calibration.

5) Write 0x1201 to begin FSK calibration.

6) Read 0x2900 and verify that bit 0 is 1 to indicate
FSK calibration is done.

The MAX1471 is now ready to receive ASK or FSK data.

Due to the high sensitivity of the receiver, it is recom­mended that the configuration registers be changed
only when not receiving data. Receiver desensitization
may occur, especially if odd-order harmonics of the
SCLK line fall within the IF bandwidth.

MAX1471

315MHz/434MHz Low-Power, 3V/5V

ASK/FSK Superheterodyne Receiver

______________________________________________________________________________________ 21

Table 6. Power Configuration Register (Address: 0x0)

BIT ID BIT NAME

BIT LOCATION

(0 = LSB)

POWER-UP

STATE

FUNCTION

LNA_EN LNA enable 7 0

1 = Enable LNA
0 = Disable LNA

AGC_EN AGC enable 6 0

1 = Enable AGC
0 = Disable AGC

MIXER_EN Mixer enable 5 0

1 = Enable mixer
0 = Disable mixer

FSKBB_EN

FSK baseband

enable

40

1 = Enable FSK baseband
0 = Disable FSK baseband

FSKPD_EN

FSK peak

30

1 = Enable FSK peak detectors
0 = Disable FSK peak detectors

ASKBB_EN

ASK baseband

enable

20

1 = Enable ASK baseband
0 = Disable ASK baseband

ASKPD_EN

ASK peak

10

1 = Enable ASK peak detectors
0 = Disable ASK peak detectors

SLEEP Sleep mode 0 0

1 = Deep-sleep mode
0 = Normal operation

detector enable

detector enable

MAX1471

Layout Considerations

A properly designed PC board is an essential part of
any RF/microwave circuit. On high-frequency inputs
and outputs, use controlled-impedance lines and keep
them as short as possible to minimize losses and radia­tion. At high frequencies, trace lengths that are on the
order of λ/10 or longer act as antennas.

Keeping the traces short also reduces parasitic induc­tance. Generally, 1in of a PC board trace adds about
20nH of parasitic inductance. The parasitic inductance

can have a dramatic effect on the effective inductance
of a passive component. For example, a 0.5in trace
connecting a 100nH inductor adds an extra 10nH of
inductance or 10%.

To reduce the parasitic inductance, use wider traces
and a solid ground or power lane below the signal
traces. Also, use low-inductance connections to ground
on all GND pins, and place decoupling capacitors
close to all VDDor HVINconnections.

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver

22 ______________________________________________________________________________________

Table 7. Configuration Register (Address: 0x1)

BIT ID BIT NAME

BIT LOCATION

(0 = LSB)

POWER-UP

STATE

FUNCTION

X Don’t care 7 0 Don’t care.

GAINSET Gain set 6 1

0 = LNA low-gain state.
1 = LNA high-gain state.
For manual gain control, enable the AGC (AGC_EN =

1), set LNA gain state to desired setting, then disable
the AGC (AGC_EN = 0).

FSKCALLSB

FSK accurate

calibration

50

FSKCALLSB = 1 enables a longer, more accurate
FSK calibration.
FSKCALLSB = 0 provides for a quick, less accurate
FSK calibration.

DOUT_FSK

40

This bit enables the FDATA pin to act as the serial
data output in 4-wire mode. (See the Communication
Protocol section.)

DOUT_ASK

30

This bit enables the ADATA pin to act as the serial
data output in 4-wire mode. (See the Communication
Protocol section.)

TOFF_PS1

20

TOFF_PS0

10

Sets LSB size for the off timer. (See the Off Timer
section.)

DRX_MODE

00

1 = Discontinuous receive mode. (See the
Discontinuous Receive Mode section.)
0 = Continuous receive mode. (See the Continuous
Receive Mode section.)

FSKOUT enable

ASKOUT enable

Off-timer prescale

Off-timer prescale

Receive mode

MAX1471

315MHz/434MHz Low-Power, 3V/5V

ASK/FSK Superheterodyne Receiver

______________________________________________________________________________________ 23

Table 8. Control Register (Address: 0x2)

BIT ID BIT NAME

BIT LOCATION

(0 = LSB)

POWER-UP

STATE

FUNCTION

X None 7 Don’t care Don’t care.

AGCLOCK AGC lock 6 0 Locks the LNA gain in its present state.

X None 5, 4 Don’t care.

FSKTRK_EN

FSK peak

detector track

enable

30

Enables the tracking mode of the FSK peak detectors
when FSKTRK_EN = 1. (See the Peak Detectors
section.)

ASKTRK_EN

ASK peak

detector track

enable

20

Enables the tracking mode of the ASK peak detectors
when ASKTRK_EN = 1.
(See the Peak Detectors section.)

POL_CAL_EN

Polling timer

10

POL_CAL_EN = 1 starts the polling timer calibration.
Calibration of the polling timer is needed when using
the MAX1471 in discontinous receive mode.
POL_CAL_EN resets when calibration completes
properly. (See the Calibration section.)

FSK_CAL_EN

FSK calibration

enable

00

FSK_CAL_EN starts the FSK receiver calibration.
FSK_CAL_EN resets when calibration completes
properly. (See the Calibration section.)

Table 9. Status Register (Read Only) (Address: 0x9)

BIT ID BIT NAME

BIT LOCATION

(0 = LSB)

FUNCTION

LOCKDET Lock detect 7

0 = Internal PLL is not locked so the MAX1471 will not receive data.
1 = Internal PLL is locked.

AGCST AGC state 6

0 = LNA in low-gain state.
1 = LNA in high-gain state.

CLKALIVE

Clock/crystal

alive

5

0 = No valid clock signal seen at the crystal inputs.
1 = Valid clock at crystal inputs.

X None 4, 3, 2 Don’t care.

POL_CAL_DONE

Polling timer

1

0 = Polling timer calibraton in progress or not completed.
1 = Polling timer calibration is complete.

FSK_CAL_DONE

FSK calibration

done

0

0 = FSK calibration in progress or not completed.
1 = FSK calibration is compete.

calibration enable

calibration done

MAX1471

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver

24 ______________________________________________________________________________________

Figure 12. DRX Mode Sequence of the MAX1471

ADATA OR

FDATA

t

OFF

t

OFF

DIO

t

CPU

t

RF

CS

t

CPU

t

LOW

t

RF

Table 12. RF Settle Timer (tRF)
Configuration

TIME BASE

(1 LSB)

MIN t

RF

REG 0x7 = 0x00

MAX t

RF

120µs 120µs 7.86s

Table 10. Off-Timer (t

OFF

) Configuration

PRESCALE1 PRESCALE0

t

OFF

TIME BASE
(1 LSB)

MIN t

OFF

REG 0x4 = 0x00
REG 0x5 = 0x01

MAX t

OFF

REG 0x4 = 0xFF
REG 0x5 = 0xFF

00120µs 120µs 7.86s

01480µs 480µs 31.46s

101920µs 1.92ms 2 min 6s

117680µs 7.68ms 8 min 23s

Table 11. CPU Recovery Timer (t

CPU

)

Configuration

TIME BASE

(1 LSB)

MIN t

CPU

MAX t

CPU

120µs 120µs 30.72ms

Chip Information

TRANSISTOR COUNT: 21,344

PROCESS: CMOS

REG 0x6 = 0x01

REG 0x8 = 0x01

REG 0x6 = 0xFF

REG 0x7 = 0xFF
REG 0x8 = 0xFF

MAX1471

315MHz/434MHz Low-Power, 3V/5V

ASK/FSK Superheterodyne Receiver

______________________________________________________________________________________ 25

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)

QFN THIN.EPS

D2

(ND-1) X e

e

D

C

PIN # 1
I.D.

(NE-1) X e

E/2

E

0.08 C

0.10 C

A

A1 A3

DETAIL A

0.15

C B

0.15 C A

E2/2

E2

0.10 M C A B

PIN # 1 I.D.

b

0.35x45∞

L

D/2

D2/2

L

C

L

C

e e

L

CC

L

k

k

LL

E

1

2

21-0140

PACKAGE OUTLINE
16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm

DETAIL B

L

L1

e

MAX1471

315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages

.)

COMMON DIMENSIONS

3.353.15

T2855-1 3.25 3.353.15 3.25

MAX.

3.20

EXPOSED PAD VARIATIONS

3.00T2055-2 3.10

D2

NOM.MIN.

3.203.00 3.10

MIN.E2NOM. MAX.

NE

ND

PKG.

CODES

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,
T2855-3 AND T2855-6.

NOTES:

SYMBOL

PKG.

N

L1

e

E

D

b

A3

A

A1

k

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

JEDEC

T1655-1

3.203.00 3.10 3.00 3.10 3.20

0.70 0.800.75

4.90

4.90

0.25

0.250--

4

WHHB

4

16

0.350.30

5.10

5.105.00

0.80 BSC.

5.00

0.05

0.20 REF.

0.02

MIN. MAX.NOM.

16L 5x5

3.10

T3255-2

3.00

3.20

3.00 3.10 3.20

2.70

T2855-2 2.60 2.602.80 2.70 2.80

E

2

2

21-0140

PACKAGE OUTLINE
16, 20, 28, 32, 40L, THIN QFN, 5x5x0.8mm

L

0.30 0.500.40

---

---

WHHC

20

5

5

5.00

5.00

0.30

0.55

0.65 BSC.

0.45

0.25

4.90

4.90

0.25

0.65

--

5.10

5.10

0.35

20L 5x5

0.20 REF.

0.75

0.02

NOM.

0

0.70

MIN.

0.05

0.80

MAX.

---

WHHD-1

28

7

7

5.00

5.00

0.25

0.55

0.50 BSC.

0.45

0.25

4.90

4.90

0.20

0.65

--

5.10

5.10

0.30

28L 5x5

0.20 REF.

0.75

0.02

NOM.

0

0.70

MIN.

0.05

0.80

MAX.

---

WHHD-2

32

8

8

5.00

5.00

0.40

0.50 BSC.

0.30

0.25

4.90

4.90

0.50

--

5.10

5.10

32L 5x5

0.20 REF.

0.75

0.02

NOM.

0

0.70

MIN.

0.05

0.80

MAX.

-

40

10

10

5.00

5.00

0.20

0.50

0.40 BSC.

0.40

0.25

4.90

4.90

0.15

0.60

5.10

5.10

0.25

40L 5x5

0.20 REF.

0.75

NOM.

0

0.70

MIN.

0.05

0.80

MAX.

0.20 0.25 0.30

-

0.35 0.45

0.30 0.40 0.50

DOWN
BONDS
ALLOWED

NO

YES3.103.00 3.203.103.00 3.20T2055-3

3.103.00 3.203.103.00 3.20T2055-4

T2855-3 3.15 3.25 3.35 3.15 3.25 3.35

T2855-6 3.15 3.25 3.35 3.15 3.25 3.35

T2855-4 2.60 2.70 2.80 2.60 2.70 2.80

T2855-5 2.60 2.70 2.80 2.60 2.70 2.80

T2855-7 2.60 2.70

2.80

2.60 2.70 2.80

3.20

3.00 3.10T3255-3 3.203.00 3.10

3.203.00 3.10T3255-4 3.203.00 3.10

3.403.20 3.30T4055-1 3.20 3.30 3.40

NO

NO
NO

NO

NO

NO

NO

NO

YES
YES

YES

YES

YES

3.203.00T1655-2 3.10 3.00 3.10 3.20 YES