Rainbow Electronics MAX1464 User Manual
General Description
The MAX1464 is a highly integrated, low-power, lownoise multichannel sensor signal processor optimized
for industrial, automotive, and process-control applications such as pressure sensing and compensation,
RTD and thermocouple linearization, weight sensing
and classification, and remote process monitoring with
limit indication.
The MAX1464 accepts sensors with either single-ended
or differential outputs. The MAX1464 accommodates
sensor output sensitivities from 1mV/V to 1V/V. The
MAX1464 provides amplification, calibration, signal linearization, and temperature compensation that enable
an overall performance approaching the inherent
repeatability of the sensor without requiring any external trim components.
Two 16-bit voltage-output DACs and two 12-bit PWMs
can be used to indicate each of the temperature-compensated sensor signals independently, as a sum or
difference signal, or user-defined relationship between
each signal and temperature. Uncommitted op amps
are available to buffer the DAC outputs, drive heavier
external loads, or provide additional gain and filtering.
The MAX1464 incorporates a 16-bit CPU, user-programmable 4kB of FLASH program memory, 128 bytes
of FLASH user information, one 16-bit ADC, two 16-bit
DACs, two 12-bit PWM digital outputs, four rail-to-rail
op amps, one SPI™-compatible interface, two GPIOs,
and one on-chip temperature sensor.
The MAX1464 operates from a single 5.0V (typ) supply
and is packaged for automotive, industrial, and commercial temperature ranges in a 28-pin SSOP package.
Applications
Pressure Sensor Signal Conditioning
Weight Measurement Systems
Thermocouple and RTD Linearization
Transducers and Transmitters
Process Indicators
Calibrators and Controllers
GMR and MR Magnetic Direction Sensors
Features
♦ Programmable Amplification, Calibration,
Linearization, and Temperature Compensation
♦ Two Differential or Four Single-Ended ADC Input
Channels
♦ Accommodates Sensor Output Sensitivities from
1mV/V to 1V/V
♦ Two DAC/PWM Output Signal Channels
♦ Supports 4–20mA Current Loop Applications
♦ 4kB of FLASH Memory for Code and Coefficients
♦ 128 Bytes of FLASH Memory for User Information
♦ Integrated Temperature Sensing
♦ Flexible Dual Op-Amp Block
♦ Programmable Sensor Input Gain and Offset
♦ Programmable Sensor Sampling Rate and
Resolution
♦ No External Trim Components Required
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3579; Rev 0; 2/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
*Dice are tested at TA= +25°C, DC parameters only.
Functional Diagram and Detailed Block Diagram appear at
end of data sheet.
SPI is a trademark of Motorola, Inc.
Pin Configuration
PART TEMP RANGE PIN-PACKAGE
MAX1464CAI 0°C to +70°C 28 SSOP
MAX1464C/W* 0°C to +70°C Die
MAX1464EAI -40°C to +85°C 28 SSOP
MAX1464AAI -40°C to +125°C 28 SSOP
TOP VIEW
OUT1SM
AMP1M
AMP1P
OUT1LG
CKSEL
CKIO
SCLK
1
2
3
4
MAX1464
5
N.C.
6
V
DD
7
N.C.
8
9
10
CS
11
DO
12
DI
13
14
V
SS
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OUT2SM
AMP2M
AMP2P
OUT2LG
V
REF
INP1
INM1
INP2
INM2
V
SS
V
SSF
GPIO2
GPIO1
V
DDF
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
DDF
= VDD= 4.5V to 5.5V, V
SSF
= VSS= 0V, f
CLK
= 4.0MHz, TA= T
MIN
to T
MAX
. Typical values are at V
DDF
= VDD= 5.0V, V
SSF
= VSS= 0V,
T
A
= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto VSS.............................................................-0.3V to +6.0V
V
DDF
to VSS...........................................................-0.3V to +6.0V
V
SSF
to VSS............................................................-0.3V to +0.3V
All Other Pins to V
SS
...................................-0.3V to (VDD+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
28-Pin SSOP (derate 9.1mW/°C above +70°C) ..........727mW
Operating Temperature Ranges
MAX1464CAI .....................................................0°C to +70°C
MAX1464C/W.....................................................0°C to +70°C
MAX1464EAI...................................................-40°C to +85°C
MAX1464AAI ................................................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY
Supply Voltage V
DD
VSS = V
SSF
= 0V 4.5 5.0 5.5 V
FLASH Supply Voltage V
DDF
VSS = V
SSF
= 0V 4.5 5.0 5.5 V
Base Operating Current I
BO
CPU stopped (Note 2)
µA
CPU Current I
CPU
All modules off, CPU = on, additive to IBO,
I
CPU
= IDD + I
DDF
(Note 3)
µA
All modules off, ADC = on, ADC clk =
1MHz, additive to I
BO
; the CPU and ADC
are not on at the same time
ADC Current (Note 3) I
ADC
All modules off, ADC = on, ADC clk = 7kHz,
additive to I
BO
; the CPU and ADC are not
on at the same time
µA
DAC Current I
DACn
All modules off, DAC = on, additive to I
BO
(n = 1 or 2) (Note 4)
µA
Large Op-Amp Current I
OPLGn
All modules off, CPU stopped, large op
amp = on (n = 1 or 2)
µA
Small Op-Amp Current I
OPSMn
All modules off, CPU stopped, small op
amp = on (n = 1 or 2)
µA
POWER-ON RESET
V
DDF
POR Threshold VDD > V
DDF
3.6 4.0 4.3 V
V
DDF
POR Hysteresis
V
ANALOG INPUT
PGA[4:0] = 00000, CLK[2:0] = 000
PGA[4:0] = 01010, CLK[2:0] = 000 55
PGA[4:0] = 11111, CLK[2:0] = 000 36
kΩ
PGA[4:0] = 00000, CLK[2:0] = 011 3.4 MΩ
PGA[4:0] = 01010, CLK[2:0] = 011
PGA[4:0] = 11111, CLK[2:0] = 011
kΩ
PGA[4:0] = 00000, CLK[2:0] = 110 27
PGA[4:0] = 01010, CLK[2:0] = 110 3.5
Differential Input Impedance
(INP1 to INM1 and
INP2 to INM2)
R
DIN
PGA[4:0] = 11111, CLK[2:0] = 110 2.3
MΩ
575 720 890
540 840 1240
690 1040 1394
-0.85
430
440
288
465 765 1060
425 550 730
430 673 1020
110 190 265
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
DDF
= VDD= 4.5V to 5.5V, V
SSF
= VSS= 0V, f
CLK
= 4.0MHz, TA= T
MIN
to T
MAX
. Typical values are at V
DDF
= VDD= 5.0V, V
SSF
= VSS= 0V,
T
A
= +25°C, unless otherwise noted.) (Note 1)
Single-Sided Input Impedance
(INP1 to V
INP2 to V
Common-Mode Rejection Ratio CMRR Common-mode voltage VCM = V
Differential Signal-Gain Range Selectable in 17 steps (Note 5) 0.99 to 244 V/V
Differential Signal Gain A
Gain-Error Temperature
Coefficient
COARSE-OFFSET DAC
Resolution 3-bit plus sign 4 Bits
Effective Offset Adjustment at the
ADC Input
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
, INM1 to VSS,
SS
, INM2 to VSS)
SS
R
VDIFF
GETC
OA
SIN
ADC
ADC
PGA[4:0] = 00000, CLK[2:0] = 000 430
PGA[4:0] = 01010, CLK[2:0] = 000 55
PGA[4:0] = 11111, CLK[2:0] = 000 36
PGA[4:0] = 00000, CLK[2:0] = 011 3.4 MΩ
PGA[4:0] = 01010, CLK[2:0] = 011 440
PGA[4:0] = 11111, CLK[2:0] = 011 288
PGA[4:0] = 00000, CLK[2:0] = 110 27
PGA[4:0] = 01010, CLK[2:0] = 110 3.5
PGA[4:0] = 11111, CLK[2:0] = 110 2.3
PGA[4:0] = 00000 0.95 0.99 1.05
PGA[4:0] = 00001 7.3 7.7
PGA[4:0] = 01010 71 77 82
PGA[4:0] = 10100 137 153 168
PGA[4:0] = 11110 203 244 283
PGA[4:0] = 00000 -8 ppm/°C
REF = VDD,
CO[3:0] = 0111
REF = VDD,
CO[3:0] = 0011
REF = VDD,
CO[3:0] = 0000
to V
SS
PGA[4:0] =
00000 to 01000
PGA[4:0] =
01010 to 10000
PGA[4:0] =
10100 to 11110
PGA[4:0] =
00000 to 01000
PGA[4:0] =
01010 to 10000
PGA[4:0] =
10100 to 11110
PGA[4:0] =
00000 to 01000
PGA[4:0] =
01010 to 10000
PGA[4:0] =
10100 to 11110
DD
0.008 %FS
137 147 157
273 291 308
525 578 630
57 64 69
113 126 136
228 251 276
-3 -1 +1
-7 -2.4 +2
-11 -4 +3
8.2
kΩ
kΩ
MΩ
V/V
% of
ADC
Ref
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DDF
= VDD= 4.5V to 5.5V, V
SSF
= VSS= 0V, f
CLK
= 4.0MHz, TA= T
MIN
to T
MAX
. Typical values are at V
DDF
= VDD= 5.0V, V
SSF
= VSS= 0V,
T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Effective Offset Adjustment at the
ADC Input
SMALL OP AMP
Input Offset Voltage VOS_
Input Bias Current IB_
DC Gain A
Gain Bandwidth Product GBW_
Slew Rate SR_
Common-Mode Input Range CMR_
Common-Mode Rejection Ratio CMRR_SMV
Power-Supply Rejection Ratio PSRR_
Input-Referred Noise Voltage VN_
Output High Voltage VOH_
Output Low Voltage VOL_
Output Source Current I
Output Sink Current I
Maximum Output Load
Capacitance
REF = VDD,
CO[3:0] = 1000
OA
ADC
REF = VDD,
CO[3:0] = 1011
REF = VDD,
CO[3:0] = 1111
SM
SM
VOL_SM
OUTnSM = 0.5V to 4.5V (n = 1 or 2),
R
LOAD
SMAVOL_SM
A
SM
VOL_SM
SM
CM_OPAMP
At DC 70 dB
SM
0.1Hz to 1kHz 8.5
SM
0.1Hz to 1MHz 100
R
SM
SM
SRC_SMVOUTnSM
SNK_SMVOUTnSM
C
_
L
SM
LOAD
R
LOAD
R
LOAD
R
LOAD
R
LOAD
PGA[4:0] =
00000 to 01000
PGA[4:0] =
01010 to 10000
PGA[4:0] =
10100 to 11110
PGA[4:0] =
00000 to 01000
PGA[4:0] =
01010 to 10000
PGA[4:0] =
10100 to 11110
PGA[4:0] =
00000 to 01000
PGA[4:0] =
01010 to 10000
PGA[4:0] =
10100 to 11110
= ∞
= +1V/V 2.7 MHz
= +1V/V 2.2 V/µs
= VSS to V
DD
= ∞ VDD - 0.1
= 4.7kΩ to V
SS
= ∞ 0.1
= 4.7kΩ to V
= V
= V
OH_SM
OL_SM
DD
, R
, R
LOAD
= 4.7kΩ to V
LOAD
= 4.7kΩ to V
= ∞, phase margin > 55° 120 pF
-15 -10 -4
-29 -19 -10
-56 -38 -20
-79 -73 -66
-155 -145 -135
-317 -287 -257
-162 -156 -150
-327 -309 -293
-675 -614 -555
0 ±15 mV
±1 nA
100 dB
VSS + 0.02 VDD - 0.02 V
70 dB
VDD - 0.15
SS
DD
-1.04 mA
% of
ADC
Ref
µV
RMS
V
0.15
V
1.04 mA
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(V
DDF
= VDD= 4.5V to 5.5V, V
SSF
= VSS= 0V, f
CLK
= 4.0MHz, TA= T
MIN
to T
MAX
. Typical values are at V
DDF
= VDD= 5.0V, V
SSF
= VSS= 0V,
T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LARGE OP AMP
Input Offset Voltage
Input Bias Current IB_
DC Gain A
Gain Bandwidth Product GBW_
Slew Rate SR_
Common-Mode Input Range CMR_
Common-Mode Rejection Ratio CMRR_LGV
Power-Supply Rejection Ratio PSRR_
Input-Referred Noise Voltage VN_
Output-Voltage High VOH_
Output-Voltage Low VOL_
Output Source Current I
Output Sink Current I
Maximum Output Load
Capacitance
OP-AMP SWITCH
Analog Signal Range V
On-Resistance R
Off-Isolation V
DIGITAL-TO-ANALOG CONVERTER
Resolution RES
Integral Nonlinearity INL
Differential Nonlinearity DNL
Offset Error V
Bit Weight BW
Power-Supply Rejection PSR
Output Noise ON
Output Settling Time ST
PULSE-WIDTH MODULATOR
Resolution RES
Period P
V
OS_LG
LG
VOL_LG
OUTnLG = 0.5V to 4.5V (n = 1 or 2),
R
LOAD
LGAVOL_LG
A
LG
VOL_LG
LG
CM OPAMP
At DC 70 dB
LG
0.1Hz to 1kHz 19
LG
0.1Hz to 1MHz 160
R
LOAD
LG
R
LOAD
R
LOAD
LG
R
LOAD
SRC_LGVOUTnLG
SNK_LGVOUTnLG
C
_
L
SW
ON
ISO
DAC OS
DAC
PWMfCLK
R
LG
DAC
DAC
DAC
LOAD
DAC ref = VDD, DAC data = 0000h
DAC ref = 5VDC 91.55 µV/LSB
DAC
At DC, DAC ref = V
DAC
DAC buffer is the small op amp ±3 LSB
DAC
To 0.1% of final value 250 µs
(Note 6) 12 Bits
PWM
= 4.0MHz 8.192 ms
= ∞
= +1V/V 4.0 MHz
= +1V/V 3.2 V/µs
= VSS to V
= ∞ VDD - 0.1
= 1kΩ to V
= ∞ 0.03
= 1kΩ to V
= V
OH_LG
= V
OL_LG
= ∞, phase margin > 55° 200 pF
SS
DD
DD
, R
= 1kΩ to V
LOAD
, R
REF
LOAD
= 1kΩ to V
VSS + 0.02 V
VDD - 0.125
SS
DD
V
V
SS
/ 2
DD
- 0.06
0±6mV
±225 nA
100 dB
- 0.02 V
DD
70 dB
µV
RMS
V
0.13
V
-4.9 mA
4.9 mA
V
DD
V
5kΩ
80 dB
16 Bits
3 Bits
±1 Bits
V
/ 2
DD
+ 0.06
V
0.02 %FS
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DDF
= VDD= 4.5V to 5.5V, V
SSF
= VSS= 0V, f
CLK
= 4.0MHz, TA= T
MIN
to T
MAX
. Typical values are at V
DDF
= VDD= 5.0V, V
SSF
= VSS= 0V,
T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Bit Weight BW
Offset Error V
Gain Error GE
Output Jitter OJ
EXTERNAL REFERENCE INPUT
Reference Input Voltage Range V
Reference Input Resistance R
INTERNAL VOLTAGE REFERENCE
Internal Voltage Reference V
Temperature Coefficient TC
TEMPERATURE SENSOR
Sensitivity Sens
Nonlinearity Error INL
Hysteresis Hist
ANALOG-TO-DIGITAL CONVERTER
Resolution RES
Integral Nonlinearity INL
Differential Nonlinearity DNL
ADC Offset Error V
Channel-to-Channel Offset Error
Matching
ADC Offset-Supply Rejection OSR
ADC Gain-Supply Rejection GSR
Offset Temperature Coefficient TA = -40°C to +125°C 0.03 %FS
Ratiometricity PGA[4:0] = 00000 to 01000 0.02 %FS
PWM_OS
REF
REF
ADC_OS
∆V
ADC_OS
PWM
PWM
PWM
IR
IR
TS
TS
TS
ADC
ADC
ADC
ADC
ADC
PWM data = 0000h ±1 µs
(Note 7) ±0.025 %
V
= 2.5V, ADC = ON, DACs = ON 100 kΩ
REF
(Note 8) 4.5 4.92 5.35 V
PGA[4:0] = 00001, CO[3:0] = 0110
PGA[4:0] = 00000 (0.99),
CO[3:0] = 0000 (Note 9)
At DC, ADC ref = V
At DC, ADC ref = V
= 5V 0.3 %FS
REF
= 5V 0.005 %FS
REF
2 µs/LSB
1/4 LSB
2.25 2.5 2.75 V
±110 ppm/°C
+2 mV/°C
+95 LSB/°C
±0.5 %FS
±0.1 %FS
16 Bits
2 Bits
±1 LSB
4 %FS
±1 LSB
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(V
DDF
= VDD= 4.5V to 5.5V, V
SSF
= VSS= 0V, f
CLK
= 4.0MHz, TA= T
MIN
to T
MAX
. Typical values are at V
DDF
= VDD= 5.0V, V
SSF
= VSS= 0V,
T
A
= +25°C, unless otherwise noted.) (Note 1)
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to V
SS
.
Note 2: All modules are off, except internal reference, oscillator, and power-on reset (POR) and CKSEL bit is set to zero.
Note 3: The CPU and ADC are not on at the same time. The ADC and CPU currents are not additive.
Note 4: I
DACn
does not include output buffer currents (I
OPLGn
or I
OPSMn
).
Note 5: For gains above 240, an additional digital gain can be provided by the CPU.
Note 6: The PWM input data is the 12-bit left-justified data in the 16-bit input field.
Note 7: PWM gain error measured as:
Note 8: The internal reference voltage has a nominal value of 5V (4
✕ V
BG
) even when VDDis greater or less than 5VDC.
Note 9: Input-referred offset error is the ADC offset error divided by the PGA gain.
Note 10: When the CKIO is configured in output mode to observe the internal oscillator signal, the total current is above the
specified limits.
Note 11: f
CLK
must be within 5% of 4MHz.
Note 12: Allow a minimum elapsed time of 4.2ms when executing a FLASH erase command, before sending any other command.
Allow a minimum elapsed time of 80µs between FLASH write commands.
Note 13: FLASH programming current is guaranteed by design.
GE
PWM F Xh PWM Xh
PWM
OUT OUT
=
()−()
×
00 100
3584
100%
DIGITAL INPUTS (GPIO1, GPIO2, SCLK, DI, CKSEL, CKIO, CS)
Input High Threshold Voltage V
Input Low Threshold Voltage V
Input Hysteresis V
Input Leakage Current I
Input Capacitance C
DIGITAL OUTPUTS (GPIO1, GPIO2, DO, CKIO)
Output-Voltage High V
Output-Voltage Low V
FLASH MEMORY
Maximum Erase Cycles (Notes 11, 12) 10k Cycles
Minimum Erase Time t
Minimum Write Time t
FLASH Programming Current I
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IH
IL
IHYS
IN
IN
OH
OL
ERASE
WRITE
DDFP
CKSEL, CS = V
GPIO1, GPIO2, SCLK, DI, CKIO = V
R
= ∞
LOAD
R
= 2kΩ to V
LOAD
R
= ∞
LOAD
R
= 2kΩ to V
LOAD
(Notes 11, 12) 4.2 ms
(Notes 11, 12) 80 µs
Writing to the FLASH or erasing the FLASH
(Note 13)
SS
SS
DD
DD
GPIO1, GPIO2, DO VDD - 0.1
CKIO (Note 10) 4.9
GPIO1, GPIO2, DO VDD - 0.15
CKIO (Note 10) 4.6
GPIO1, GPIO2, DO 0.05
CKIO (Note 10) 0.1
GPIO1, GPIO2, DO 0.2
CKIO (Note 10) 0.4
0.8 x
V
DD
0.2 x
0.2 V
38 -90
38 +90
5pF
30 mA
V
DD
V
V
µA
V
V
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
8 _______________________________________________________________________________________
TIMING CHARACTERISTICS
(V
DDF
= VDD= 4.5V to 5.5V, V
SSF
= VSS= 0V, f
CLK
= 4.0MHz, TA= T
MIN
to T
MAX
. Typical values are at V
DDF
= VDD= 5.0V, V
SSF
= VSS= 0V,
T
A
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER
CONDITIONS
UNITS
Programming Temperature T
PROG
°C
Internal Oscillator Clock
Frequency
f
ICLK
OSC[4:0] = 00000 3.3
5.3
MHz
Min 0.2
External Clock Frequency f
ECLK
V
CKSEL
= 0
Max 5
MHz
External Master Clock Input Low
Time
t
ECLK
= 1 / f
ECLK
40 60
%
t
ECLK
External Master Clock Input High
Time
t
ECLK
= 1 / f
ECLK
40 60
%
t
ECLK
SERIAL INTERFACE (Figure 1)
SCLK Setup to Falling Edge CS t
SC
30 ns
CS Falling Edge to SCLK Rising
Edge Setup Time
t
CSS
30 ns
CS Idle Time t
CSI
f
CLK
= 4MHz 1.5 µs
CS Period t
CS
f
CLK
= 4MHz 4 µs
SCLK Falling Edge to Data Valid
Delay
t
DO
C
LOAD
= 200pF 80 ns
Data Valid to SCLK Rising Edge
Setup Time
t
DS
30 ns
Data Valid to SCLK Rising Edge
Hold Time
t
DH
30 ns
SCLK High Pulse Width t
CH
ns
SCLK Low Pulse Width t
CL
ns
CS Rising Edge to SCLK Rising
Edge Hold Time
t
CSH
30 ns
CS Falling Edge to Output
Enable
t
DV
C
LOAD
= 200pF 25 ns
CS Rising Edge to Output
Disable
t
TR
C
LOAD
= 200pF 25 ns
SYMBOL
f
ECLKIN_LO
f
ECLKIN_HI
MIN TYP MAX
125
4.15
100
100
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
_______________________________________________________________________________________ 9
Typical Operating Characteristics
(VDD= 5.0V, TA= +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1464 toc01
SUPPLY VOLTAGE, VDD (V)
SUPPLY CURRENT, I
DD
(mA)
5.35.14.7 4.9
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.25
4.5 5.5
CPU ON 2% OF TIME
ADC ON 98% OF TIME
ADC
CLK
= 1MHz
DAC1 ON
SMALL OP AMP ON
TA = +125°C
TA = +25°C
TA = -40°C
SUPPLY CURRENT
vs. INTERNAL CLOCK FREQUENCY
MAX1464 toc02
INTERNAL CLOCK FREQUENCY (MHz)
SUPPLY CURRENT, I
DD
(mA)
4.54.03.5
2.25
2.30
2.35
2.40
2.45
2.50
2.55
2.60
2.65
2.70
2.20
3.0 5.0
CPU ON 2% OF TIME
ADC ON 98% OF TIME
ADC
CLK
= 1MHz
DAC1 ON
SMALL OP AMP ON
MODULE CURRENT
vs. TEMPERATURE
MAX1464 toc03
TEMPERATURE (°C)
MODULE CURRENT (mA)
98704315-13
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
0.5
-40 125
DAC + LARGE OP AMP
DAC + SMALL OP AMP
ADC
BASE
BASE OPERATING CURRENT
vs. SUPPLY VOLTAGE
MAX1464 toc04
SUPPLY VOLTAGE, VDD (V)
BASE OPERATING CURRENT, I
BO
(mA)
5.35.14.7 4.9
0.67
0.69
0.71
0.73
0.75
0.77
0.79
0.81
0.65
4.5 5.5
TA = +125°C
TA = +25°C
TA = -40°C
ADC RATIOMETRICITY ERROR
vs. SUPPLY VOLTAGE
MAX1464 toc05
SUPPLY VOLTAGE, VDD (V)
ADC RATIOMETRICITY ERROR (%FS)
5.35.14.7 4.9
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
0.04
-0.04
4.5 5.5
ADC INPUT = 0.75 x V
DD
ADC INPUT = 0.5 x V
DD
ADC INPUT = 0
ADC INPUT = -0.75 x V
DD
ADC INPUT = -0.5 x V
DD
ADC
REF
= V
DD
PGA[4:0] = 00000
ADC INL
MAX1464 toc06
1.00.5-0.5 0-1.0
INPUT VOLTAGE NORMALIZED TO FULL SCALE
ADC NONLINEARITY ERROR (%FS)
-0.004
-0.002
0
0.002
0.004
0.006
-0.006
PGA[4:0] = 01000
Figure 1. Serial Interface Timing Diagram
CS
t
SCLK
DI
DO
CSS
t
SC
t
DS
t
DV
t
DH
tCLt
CH
t
DO
t
CS
t
CSI
t
CSS
t
CSH
t
TR
t
SC
t
DS
t
DV
t
DH
tCLt
CH
t
DO
t
CSH
t
TR
TEMPERATURE SENSOR OUTPUT
vs. TEMPERATURE
MAX1464 toc13
TEMPERATURE (°C)
TEMPERATURE SENSOR OUTPUT (ADC CODE)
97.5 125.070.042.515.0-12.5
0
-2000
4000
2000
8000
12,000
10,000
14,000
6000
16,000
-4000
-40.0
PGA[4:0] = [00001]
CO[3:0] = 0110
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD= 5.0V, TA= +25°C, unless otherwise noted.)
INTERNAL OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
MAX1464 toc12
SUPPLY VOLTAGE, VDD (V)
INTERNAL OSCILLATOR FREQUENCY (MHz)
5.35.14.94.7
3.85
3.90
3.95
4.00
4.05
4.10
4.15
3.80
4.5 5.5
TA = -40°C
TA = +125°C
T
A
= +25°C
OSCILLATOR
FREQUENCY TRIMMED
TO 4MHz AT +25°C,
V
DD
= 5V
4
3
2
1
0
-1
ADC DNL ERROR (LSB)
-2
-3
-4
-1.0 1.0
INPUT VOLTAGE NORMALIZED TO FULL SCALE
1V/div
ADC DNL
PGA[4:0] = 01000
0.50-0.5
DAC DYNAMIC RESPONSE
5
4
3
2
1
DAC CODE = C000h
0
MAX1464 toc07
DAC CODE = 4000h
200µs/div
0.04
DAC INL
0.03
0.02
0.01
0
-0.01
-0.02
DAC NONLINEARITY ERROR (%FS)
-0.03
-0.04
-0.8 0.8
INPUT NORMALIZED TO FULL SCALE
MAX1464 toc10
ERROR (%FS)
3
2
MAX1464 toc08
1
0
-1
DAC DNL ERROR (LSB)
-2
0.60.4-0.6 -0.4 -0.2 0 0.2
-3
-0.8 0.8
INPUT VOLTAGE NORMALIZED TO FULL SCALE
DAC RATIOMETRICITY ERROR
vs. SUPPLY VOLTAGE
0.05
0.04
0.03
0.02
0.01
-0.01
-0.02
-0.03
-0.04
-0.05
DAC INPUT = 5555CH (4.5V AT VDD = 5V)
DAC INPUT = 0000CH (2.5V AT VDD = 5V)
0
DAC INPUT = AAABCH (0.5V AT VDD = 5V)
4.5 5.5
SUPPLY VOLTAGE, VDD (V)
DAC DNL
MAX1464 toc09
0.60.40.20-0.2-0.4-0.6
MAX1464 toc11
5.35.14.94.7
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
______________________________________________________________________________________ 11
Pin Description
PIN NAME FUNCTION
1 OUT1SM Small Op Amp 1 Output
2 AMP1M Op Amp 1 Negative Input
3 AMP1P Op Amp 1 Positive Input
4 OUT1LG Large Op Amp 1 Output
5, 7 N.C. No Connection
6VDDPositive Supply Voltage Input. Bypass VDD to VSS with a 0.1µF ceramic capacitor.
8 CKSEL Clock-Select Digital Input
9 CKIO Clock Digital Input/Output
10 CS SPI Chip-Select Digital Input. Active low.
11 DO SPI Data Output
12 DI SPI Data Input
13 SCLK SPI Interface Clock
14, 19 V
15 V
16 GPIO1 General-Purpose Digital Input/Output 1
17 GPIO2 General-Purpose Digital Input/Output 2
18 V
20 INM2 Negative Input for ADC Channel 2
21 INP2 Positive Input for ADC Channel 2
22 INM1 Negative Input for ADC Channel 1
23 INP1 Positive Input for ADC Channel 1
24 V
25 OUT2LG Large Op Amp 2 Output
26 AMP2P Op Amp 2 Positive Input
27 AMP2M Op Amp 2 Negative Input
28 OUT2SM Small Op Amp 2 Output
SS
DDF
SSF
REF
Negative Power-Supply Input
Positive Supply Voltage for FLASH Memory. Bypass V
Negative Power-Supply Input for FLASH Memory
External Reference Voltage Input for ADC and DACs
to VSS with a 0.1µF ceramic capacitor.
DDF
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
12 ______________________________________________________________________________________
Typical Application Circuit
Analog ratiometric output configuration (Figure 2) provides an output that is proportional to the power-supply
voltage. Ratiometricity is an important consideration for
automotive, battery-operated instruments, and some
industrial applications.
Detailed Description
The MAX1464 is a highly integrated, low-power, lownoise multichannel sensor signal processor optimized
for industrial, automotive, and process-control applications, such as pressure sensing and compensation,
RTD and thermocouple linearization, weight sensing
and classification, and remote process monitoring with
limit indication.
The MAX1464 incorporates a 16-bit CPU, user-programmable 4kB of FLASH memory, 128 bytes of FLASH user
information, 16-bit ADC, two 16-bit DACs, two 12-bit
PWM digital outputs, four rail-to-rail op amps, SPI interface, two GPIOs, and one on-chip temperature sensor.
Each sensor signal can be amplified, compensated for
temperature, linearized, and the offset and full scale
can be adjusted to the desired value. The MAX1464
can provide outputs as analog voltage (DAC) or digital
(PWM, GPIOs), or simple on/off alarm indication
(GPIOs). The uncommitted op amps can be used to
implement 4–20mA current loops or for additional gain
and filtering. Each DAC output is routed to either a
small or large op amp. Large op amps are capable of
driving heavier external loads. The unused circuit functions can be turned off to save power.
All sensor linearization and on-chip temperature compensation is done by a user-defined algorithm stored in
FLASH memory. The user-defined algorithm is programmed over the serial interface and stored in 4kB of
integrated FLASH memory.
The MAX1464 uses an internal 4MHz oscillator or an
externally supplied 4MHz clock. CPU code execution
and ADC operation is fully synchronized to minimize
the noise interference of a CPU-based sensor processor system. The CPU sequentially executes instructions
stored in FLASH memory.
Sensor Input
The MAX1464 provides two differential signal inputs,
INP1-INM1 and INP2-INM2. These inputs can also be
configured as four single-ended signals. Each input
can have a common-mode range from VDDto VSSand
a 0.99V/V to 244V/V programmable-gain range. The differential input signals are summed with the output of
the coarse offset DAC (CO DAC) for offset correction
prior to being amplified by the programmable-gain
amplifier (PGA). The resulting signal is applied to the
differential input of the ADC for conversion.
The CPU can be programmed to measure one or two
differential inputs plus the internal temperature sensor
defined in user-supplied algorithm. For example, the
differential inputs can be measured many times while
the temperature can be measured less frequently.
Figure 2. Basic Bridge Sensor Ratiometric Output Configuration
22Ω
V
DD
V
DDF
INPn
OUTnSM OUT
5VDC
SENSOR
INMn
MAX1464
V
SS
0.1µF
0.1µF 100pF
GND
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
______________________________________________________________________________________ 13
On-Chip Temperature Sensing
The on-chip temperature sensor changes +2mV/°C over
the operating range. The ADC converts the temperature
sensor in a similar manner as the sensor inputs. During
an ADC conversion of the temperature sensor, the ADC
automatically uses four times the internal 1.25V reference
as the ADC full-scale reference (5V). The temperature
data format is 15-bit plus sign in two’s-complement format. Gain offset compensation can be programmed to
utilize the full-scale range of the ADC. Offset compensation by the CO DAC is provided so that the nominal temperature measurement can be centered at the ADC
output value. Use the CPU to provide additional digital
gain and offset correction.
Output Format
There are two output modules in the MAX1464—DOP1
(DAC Op Amp PWM 1) and DOP2 (DAC Op Amp PWM
2). Each of the DOP modules contains a 16-bit DAC, a
12-bit digital PWM converter, a small op amp, and a
large op amp with high-output-drive capability. Each
module can be configured in several different modes to
suit a wide range of output signal requirements. Either
the DAC or the PWM can be selected as the primary
output signal. The DAC output signal must be routed to
one of the two op amps before being made available to
a device pin. See the DAC, Op Amp, PWM Modules
(DPOn) section for details. Additional digital outputs are
available on the GPIOs.
Initialization
A user-defined initialization routine is required to configure the oscillator frequency and various analog modules,
e.g., PGA gain, ADC resolution, ADC clock settings, etc.
After the initialization routine, the CPU can start execution
of the main program.
Power-On Reset (POR)
The MAX1464 contains a POR circuit to disable CPU
execution until adequate VDDand V
DDF
voltage are
available for operation. Once the power-on state has
been reached, the MAX1464 is kept under reset condition for 250µs before the CPU starts execution. Below
the POR threshold, all internal CPU registers are set to
their POR default state. Power-on control bits for internal
modules are reset to the OFF condition.
CPU Architecture
The CPU provides a wide range of functionality to be
incorporated in an embedded system. The CPU can
compensate nonlinear and temperature-dependent sensors, check for over/underlimit conditions, output sensor
or temperature data as an analog signal or pulse-widthmodulated digital signal, and execute control strategies.
The CPU can perform a limited amount of signal processing (filtering). A timer is included so that uniform
sampling (equally spaced ADC conversions) of the
input sensors can be performed.
The CPU registers and ports are implemented in volatile,
static memory. There are several registers contained in
various peripheral modules that provide module configuration settings, control functions, and data. These module
registers are accessible through an indirect addressing
scheme as described in detail in the CPU Registers,
CPU Ports, and Modules sections. Figure 3 shows the
CPU architecture.
CPU Registers
The MAX1464 incorporates a CPU with 16 internal registers. All the CPU registers have a 16-bit data word width.
Five of the 16 registers have predefined functional operations that are dependent on the instruction being executed. The remaining registers are general purpose.
The CPU registers are embedded in the CPU itself and
are not all directly accessible by the serial interface. The
accumulator register (A), the pointer register (P), and the
instruction (FLASH data) can be read through the serial
interface when the CPU is halted. This enables a single-
Figure 3. CPU Architecture
SCLKDIDO
SERIAL INTERFACE
P0
P1
P2
P1
CPU
P3
P4
P5
P6
P7
P8
PA
PB
PC
PD
PE
PF
CPU PORTS
CS
R0 POINTER (P)
R1 ACCUMULATOR (A)
R2
R3 MULTIPLICAND (N)
R4 MULTIPLIER (M)
R5 INDEX (I)
R6
R7
R8
R9
RA
RB
RC
RD
RE
RF
CPU REGISTERS
INSTRUCTION
ADDRESS
FLASH DATA
FLASH MEMORY
(4kB)
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
14 ______________________________________________________________________________________
step mode of code execution to ease code writing and
debugging. A special program instruction sequence is
required to observe the other CPU registers. Table 1 lists
the CPU registers.
CPU Ports
The MAX1464 incorporates 16 CPU ports that are directly
accessible by the serial interface. All the CPU ports have
a 16-bit data word width. The contents of the ports can
be read and written by transferring data to and from the
accumulator register (A) using the RDX and WRX instructions. No other CPU instructions act on the CPU ports.
Three CPU ports PD, PE, and PF have uniquely defined
operation for reading and writing data to and from the
peripheral modules. All CPU ports are static and volatile.
Table 2 lists the CPU ports.
Modules
The MAX1464 modules are the functional blocks used
to process analog and digital signals to and from the
CPU. Each module is addressed through CPU ports PD,
PE, and PF, as described in the CPU Ports section. All
modules use static, volatile registers for data retention.
There are three types of module registers: configuration,
data, and control. They are used to put a module into a
particular mode of operation. Configuration registers
hold configuration bits that control static settings such
as PGA gain, coarse offset, etc. Data registers hold
input data such as DAC and PWM input words or output
data such as the result of an ADC conversion. Control
registers are used to initiate a process (such as an ADC
conversion or a timer) or to turn modules on and off
(such as op amps, DAC outputs, PWM outputs, etc.)
Table 3 lists the module registers.
ADC Module
The ADC module (Figure 4) contains a 9-bit to 16-bit
sigma-delta converter with multiplexed differential and
single-ended signal inputs, a CO DAC, four reference
voltage inputs, two differential or four single-ended
external inputs, and 15 single-ended internal voltages
for measurement. The ADC output data is 16-bit two’scomplement format. The conversion channel, modes,
and reference sources are all set in ADC configuration
registers. The conversion time is a function of the selected resolution and ADC clock frequency. The CPU can
be programmed to convert any of the inputs and the
internal temperature sensor in any desired sequence.
For example, the differential inputs may be converted
many times and conversions of temperature performed
less frequently. See Table 4.
The ADC reference can be selected as VDDfor conversions ratiometric to the power supply, 2 x V
REF
input for
conversions relative to an external voltage, and VBGx 4,
which is an internally generated bandgap reference
voltage. Note that because V
REF
external = 2.5V and
V
BG
= 1.25V, the ADC’s reference voltage is always
close to 5.0V. The ADC voltage reference is also used
by the CO DAC to maintain a signal conversion that is
completely ratiometric to the selected reference source.
The four analog inputs (INP1, INM1, INP2, INM2) and
several internal circuit nodes can be multiplexed to the
ADC for a single-ended conversion relative to V
SS
. The
selection of which circuit node is multiplexed to the ADC
is controlled by the ADC_Control register. The ADC can
measure each of the op-amp output nodes with gain for
converting user-defined circuits or incorporating system
diagnostic test functions. The DAC outputs can be converted by the ADC with either op amp arranged as
unity-gain buffers on the DAC outputs. The internal
power nodes, VDDand VSS, and the bandgap reference,
V
BG
can be multiplexed to the ADC for conversion as
well. These measurement modes are defined and initiated in the ADC_Control register. See Tables 5 and 7 for
the single-ended configuration.
ADC Registers
The ADC module has 10 registers for configuration,
control, and data output. There are three conversion
channels in the ADC; channel 1, channel 2, and temperature. Channels 1 and 2 are associated with the differential signal input pairs INP1-INM1 and INP2-INM2,
respectively. The temperature channel is associated
with the integrated temperature sensor. Each channel
has two configuration registers (ADC_Config_nA and
ADC_Config_nB where n = 1, 2, or T) for setting conversion resolution, reference input, coarse offsets, etc.
The data output from a conversion of channel 1, 2, or T
is stored in the respective data output register
ADC_Data_n where n = 1, 2, or T. Each of the channels
can be used to convert single-ended inputs as listed in
Table 7. The ADC_Control register controls which channel is to be converted and what single-ended input, if
any, is to be directed to that channel. See Tables 8
through 13.
Conversion Start
To initiate an ADC conversion, a word is written to the
ADC_Control register with either CNVT1, CNVT2, or
CNVTT bit set to a 1 (Table 6). When an ADC conversion is initiated, the CPU is halted and all CPU and
FLASH activities cease. All CNVT1, CNVT2, and CNVTT
bits are cleared after the ADC conversion is completed.
Upon completion of the conversion, the ADC result is
latched into the respective ADC_Data_n register. In
addition, the convert bits in control register 0 are all
reset to zero. The CPU clock is then enabled and program execution continues
MAX1464
Low-Power, Low-Noise Multichannel
Sensor Signal Processor
______________________________________________________________________________________ 15
Single-ended inputs can be converted by either channel
1 or 2 by initiating a conversion on the appropriate channel with the SE[3:0] bits set to the desired single-ended
input (Table 7). Several of the single-ended signals are
converted with a fixed gain. The reduced gain of 0.7V/V
allows signals at or near the supply rails to be converted
without concern of saturation. Other single-ended signals
can be converted with the full selectable PGA gain range.
Programmable-Gain Amplifier
The gain of the differential inputs and several
single-ended inputs can be set to values between
0.99V/V to 244V/V as shown in Table 14. The PGA bits
are set in ADC_Config_nA where n = 1, 2, or T. The gain
setting must be selected prior to initiating a conversion.
ADC Conversion Time and Resolution
The ADC conversion time is a function of the selected
resolution, ADC clock (f
ADC
), and system clock frequen-
cy (f
CLK
). The resolution can be selected from 9 bits to 16
bits in the ADC_Config_nA (where n = 1, 2, or T) register
by bits RESn[2:0]. The lower resolution settings (9 bit)
convert faster than the higher resolution settings (16 bit).
The ADC clock f
ADC
is derived from the primary system
clock f
CLK
by a prescalar divisor. The divisor can be set
from 4 to 512, producing a range of f
ADC
from 1MHz
down to 7.8125kHz when f
CLK
is operating at 4.0MHz.
Other values of f
CLK
produce other scaled values of
f
ADC
. See Tables 15 and 16.
Systems operating with very low power consumption
benefit from the reduced f
ADC
clock rate. Slower clock
speeds require less operating current. Systems operating from a larger power consumption budget can use
the highest f
ADC
clock rate to improve speed perfor-
mance over power performance.
The ADC conversion times for various resolution and
clock-rate settings are summarized in Table 17. The
conversion time is calculated by the formula:
t
CONVERT
= (no. of f
ADC
clocks per conversion) /
f
ADC
Figure 4. ADC Module
INP1
INM1
INP2
INM2
TEMPERATURE
SENSOR
V
DD
2 x V
REF
4 x V
BG
REF
CO
DAC
M
U
X
V
SS
NO. SINGLE-ENDED
1
V
BG
2
OUTnSM
3
OUTnLG
4
V
DD
V
5
SS
DACnOUT VIA OUTnSM
6
7
DACnOUT VIA OUTnLG
INPn
8
9
INMn
PGA
ADC
VBG
00h ADC_Control
01h ADC_Data_1
02h ADC_Config_1A
03h
ADC_Config_1B
04h ADC_Data_2
05h ADC_Config_2A
06h ADC_Config_2B
07h ADC_Data_T
08h ADC_Config_TA
09h ADC_Config_TB
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