General Description
The MAX1448 +3V, 10-bit analog-to-digital converter
(ADC) features a fully differential input, a pipelined 10stage ADC architecture with wideband track-and-hold
(T/H), and digital error correction incorporating a fully
differential signal path. The ADC is optimized for lowpower, high dynamic performance in imaging and digital communications applications. The converter
operates from a single +2.7V to +3.6V supply, consuming only 120mW while delivering a 59dB (typ) signal-tonoise ratio (SNR) at a 20MHz input frequency. The fully
differential input stage has a -3dB 400MHz bandwidth
and may be operated with single-ended inputs. In addition to low operating power, the MAX1448 features a
5µA power-down mode for idle periods.
An internal +2.048V precision bandgap reference is
used to set the ADC full-scale range. A flexible reference structure allows the user to supply a buffered,
direct, or externally derived reference for applications
requiring increased accuracy or a different input voltage range.
Lower speed, pin-compatible versions of the MAX1448
are also available. Please refer to the MAX1444 data
sheet for a 40Msps version and to the MAX1446 data
sheet for a 60Msps version.
The MAX1448 has parallel, offset binary, CMOS-compatible three-state outputs that can be operated from
+1.7V to +3.6V to allow flexible interfacing. The device
is available in a 5mm x 5mm 32-pin TQFP package and
is specified over the extended industrial (-40°C to
+85°C) temperature range.
________________________Applications
Ultrasound Imaging
CCD Imaging
Baseband and IF Digitization
Digital Set-Top Boxes
Video Digitizing Applications
Features
♦ Single +3.0V Operation
♦ Excellent Dynamic Performance
59dB SNR at f
IN
= 20MHz
74dBc SFDR at f
IN
= 20MHz
♦ Low Power
40mA (Normal Operation)
5µA (Shutdown Mode)
♦ Fully Differential Analog Input
♦ Wide 2V
p-p Differential Input Voltage Range
♦ 400MHz -3dB Input Bandwidth
♦ On-Chip +2.048V Precision Bandgap Reference
♦ CMOS-Compatible Three-State Outputs
♦ 32-Pin TQFP Package
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
________________________________________________________________ Maxim Integrated Products 1
Functional Diagram
19-5400; Rev 0; 9/00
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
EVALUATION KIT
AVAILABLE
Ordering Information
Pin Configuration appears at end of data sheet.
PART TEMP. RANGE PIN-PACKAGE
MAX1448EHJ -40°C to +85°C 32 TQFP
CLK
IN+
MAX1448
CONTROL
10
D
OUTPUT
T/H
IN-
PD
REF
PIPELINE ADC
REF SYSTEM +
BIAS
E
DRIVERS
C
V
GND
D9–D0
OV
OGND
DD
DD
REFINREFOUT REFP COM REFN OE
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= +3.0V, OVDD= +2.0V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= +2.048V, REFOUT
connected to REFIN through a 10kΩ resistor, V
IN
= 2Vp-p (differential with respect to COM), CL≈ 15pF at digital outputs (Note 5),
f
CLK
= 83.3MHz (50% duty cycle), TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
=
+25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDDto GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
IN+, IN- to GND........................................................-0.3V to V
DD
REFIN, REFOUT, REFP,
REFN, and COM to GND..........................-0.3V to (V
DD
+ 0.3V)
OE, PD, CLK to GND..................................-0.3V to (V
DD
+ 0.3V)
D9–D0 to GND.........................................-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
32-Pin TQFP (derate 11.1mW/°C above +70°C)...........889mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DC ACCURACY
Resolution 10 Bits
Integral Nonlinearity INL fIN = 7.47MHz ±0.7 ±2.2 LSB
Differential Nonlinearity DNL f
Offset Error <±1 ±1.7 %FS
Gain Error 0 ±2%FS
ANALOG INPUT
Input Differential Range V
Common-Mode Voltage Range V
Input Resistance R
Input Capacitance C
CONVERSION RATE
Maximum Clock Frequency f
Data Latency 5.5 Cycles
DYNAMIC CHARACTERISTICS (f
Signal-to-Noise Plus Distortion
(up to 5th harmonic)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIFF
COM
IN
IN
CLK
= 83.3MHz, 4096-point FFT)
CLK
SINAD
= 7.47M H z, no m i ssi ng cod es g uar anteed ±0.4 ±1.0 LSB
IN
Differential or single-ended inputs ±1.0 V
Switched capacitor load 25 kΩ
fIN = 7.47MHz 56.5 59.1
fIN = 20MHz 56 59Signal-to-Noise Ratio SNR
= 39.9MHz (Note 1) 58.5
f
IN
fIN = 7.47MHz 55.8 59
fIN = 20MHz 55.3 58.8
f
= 39.9MHz (Note 1) 58
IN
80 MHz
VDD/2
± 0.5
5pF
V
dB
dB
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +3.0V, OVDD= +2.0V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= +2.048V, REFOUT
connected to REFIN through a 10kΩ resistor, V
IN
= 2Vp-p (differential with respect to COM), CL≈ 15pF at digital outputs (Note 5),
f
CLK
= 83.3MHz (50% duty cycle), TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
=
+25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Spurious-Free Dynamic
Range
SFDR
fIN = 7.47MHz 61 74
fIN = 20MHz 61 74
= 39.9MHz (Note 1) 73
f
IN
fIN = 7.47MHz 74
Third-Harmonic Distortion HD3
Intermodulation Distortion
Two-Tone
Third-Order Intermodulation
Distortion
Total Harmonic Distortion
(first 5 harmonics)
IMD
IM3
THD
fIN = 20MHz 74
= 39.9MHz (Note 1) 73
f
IN
f
= 24MHz at -6.5dB FS, f
1
TT
-6.5dB FS (Note 2)
f
= 24MHz at -6.5dB FS, f
1
= 26MHz at
2
= 26MHz at
2
-6.5dB FS (Note 2)
fIN = 7.47MHz -72 -60
fIN = 20MHz -70 -60
= 39.9MHz (Note 1) -69
f
IN
Small-Signal Bandwidth Input at -20dB FS, differential inputs 500 MHz
Full-Power Bandwidth FPBW Input at -0.5dB FS, differential inputs 400 MHz
Aperture Delay t
Aperture Jitter t
AD
AJ
Overdrive Recovery Time For 1.5 × full-scale input 2 ns
Differential Gain ±1 %
Differential Phase ±0.25 degrees
Output Noise IN+ = IN- = COM 0.2 LSB
INTERNAL REFERENCE
Reference Output Voltage REFOUT
Reference Temperature
Coefficient
TC
REF
Load Regulation 1.25 mV/mA
EXTERNAL REFERENCE
Positive Reference REFP V
Negative Reference REFN V
Differential Reference Voltage ∆V
REFIN Resistance R
D IGIT A L IN PU T S
( C LK, P D , OE)
Input High Threshold V
REF
REFIN
IH
= +2.048V 2.012 V
REFIN
= +2.048V 0.988 V
REFIN
V
REFP
CLK
PD, OE
- V
REFN
, V
= +2.048V 0.98 1.024 1.07 V
REFIN
0.8 x
V
DD
0.8 x
OV
D D
dBc
dBc
-74 dBc
-74 dBc
dBc
1ns
2ps
2.048
±1%
RMS
V
60 ppm/°C
>50 MΩ
V
RMS
Note 1: SNR, SINAD, THD, SFDR and HD3 are based on an analog input voltage of -0.5dB FS referenced to a +1.024V full-scale
input voltage range.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better if referenced to the two-tone envelope.
Note 3: Digital outputs settle to V
IH,VIL
.
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5: Equivalent dynamic performance is obtainable over full OV
DD
range with reduced CL.
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +3.0V, OVDD= +2.0V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= +2.048V, REFOUT
connected to REFIN through a 10kΩ resistor, V
IN
= 2Vp-p (differential with respect to COM), CL≈ 15pF at digital outputs (Note 5),
f
CLK
= 83.3MHz (50% duty cycle), TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
=
+25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Low Threshold V
IL
Input Hysteresis V
Input Leakage
Input Capacitance C
DIGITAL OUTPUTS (D9–D0)
Output Voltage Low V
Output Voltage High V
Three-State Leakage Current I
HYST
I
IH
I
IL
IN
OL
OH
LEAK
CLK
PD, OE
VIH = VDD = OV
DD
VIL = 0 ±5
I
= 200µA 0.2 V
SINK
OV
-
I
SOURCE
OE = OV
= 200µA
DD
DD
0.2
0.2 x
V
D D
V
0.2 x
OV
D D
0.1 V
±5
µA
5pF
V
±10 µA
Three-State Output Capacitance C
OUT
OE = OV
DD
5pF
POWER REQUIREMENTS
Analog Supply Voltage V
Output Supply Voltage OV
Analog Supply Current I
Output Supply Current I
DD
DD
VDD
OVDD
Power-Supply Rejection PSRR
Operating, fIN = 20MHz at -0.5dB FS 40 47 mA
Shutdown, clock idle, PD = OE = OV
DD
Operating, CL = 15pF, fIN = 20MHz at
-0.5dB FS
Shutdown, clock idle, PD = OE = OV
DD
Offset ±0.2 mV/V
Gain ±0.1 %/V
2.7 3.0 3.6 V
1.7 3.0 3.6 V
415µA
8mA
110µA
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid t
OE Fall to Output Enable t
OE Rise to Output Disable t
ENABLE
DISABLE
CLK Pulse Width High t
CLK Pulse Width Low t
Wake-Up Time t
DO
CH
CL
WAKE
Figure 6 (Note 3) 5 8 ns
Figure 5 10 ns
Figure 5 15 ns
Figure 6, clock period 12ns 6±1 ns
Figure 6, clock period 12ns 6±1 ns
(Note 4) 1.5 µs
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
_______________________________________________________________________________________ 5
Typical Operating Characteristics
(VDD= +3.0V, OVDD= +2.7V, internal reference, differential input at -0.5dB FS, f
CLK
= 83.3MHz, CL≈ 10pF, TA= +25°C, unless oth-
erwise noted.)
(f
IN
0
-10
-20
-30
-40
-50
-60
AMPLITUDE (dB)
-70
-80
-90
-100
01015205 2530354045
(f
IN
0
-10
-20
-30
-40
-50
-60
AMPLITUDE (dB)
-70
-80
-90
-100
01015205 2530354045
SPURIOUS-FREE DYNAMIC RANGE vs.
80
75
70
65
60
SFDR (dBc)
55
50
45
40
110100
FFT PLOT
= 7.5MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
SFDR = 75.5dBc
SNR = 59.3dB
THD = -73.9dBc
SINAD = 59.2dB
2ND HARMONIC
3RD HARMONIC
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
= 7.5MHz, 8192-POINT FFT,
SINGLE-ENDED INPUT)
SFDR = 72.2dBc
SNR = 58.7dB
THD = -70.8dBc
SINAD = 58.4dB
2ND HARMONIC
3RD HARMONIC
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY
DIFFERENTIAL
SINGLE-ENDED
ANALOG INPUT FREQUENCY (MHz)
MAX1448-01
MAX1448-04
MAX1448-07
FFT PLOT
= 20MHz, 8192-POINT FFT,
(f
IN
DIFFERENTIAL INPUT)
0
-10
-20
-30
-40
-50
-60
AMPLITUDE (dB)
-70
-80
-90
-100
01015205 2530354045
ANALOG INPUT FREQUENCY (MHz)
SFDR = 75.2dBc
SNR = 59dB
THD = -71.8dBc
SINAD = 58.7dB
2ND HARMONIC
3RD HARMONIC
FFT PLOT
= 20MHz, 8192-POINT FFT,
(f
IN
SINGLE-ENDED INPUT)
0
-10
-20
-30
-40
-50
-60
AMPLITUDE (dB)
-70
-80
-90
-100
01015205 2530354045
ANALOG INPUT FREQUENCY (MHz)
SFDR = 67.2dBc
SNR = 58.6dB
THD = -66.5dBc
SINAD = 58dB
2ND HARMONIC
3RD HARMONIC
SIGNAL-TO-NOISE RATIO vs.
ANALOG INPUT FREQUENCY
62
61
60
DIFFERENTIAL
59
58
SNR (dB)
57
56
55
54
110100
ANALOG INPUT FREQUENCY (MHz)
SINGLE-ENDED
UNDERSAMPLING FFT PLOT
= 50MHz, 8192-POINT FFT,
(f
IN
DIFFERENTIAL INPUT)
0
SFDR = 65.8dBc
-10
MAX1448-02
SNR = 58dB
THD = -65.1dBc
-20
SINAD = 57.2dB
-30
-40
-50
2ND HARMONIC
-60
3RD HARMONIC
AMPLITUDE (dB)
-70
-80
-90
-100
01015205 2530354045
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE INTERMODULATION
(8192-POINT IMD,
DIFFERENTIAL INPUT)
0
f1 = 24MHz AT -6.5dB FS
-10
= 26MHz AT -6.5dB FS
f
MAX1448-05
2
3RD IMD = -74dBc
-20
-30
-40
-50
-60
AMPLITUDE (dB)
-70
-80
-90
-100
01015205 2530354045
ANALOG INPUT FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION vs.
ANALOG INPUT FREQUENCY
-50
MAX1448-08
-55
-60
-65
THD (dBc)
-70
-75
-80
SINGLE-ENDED
DIFFERENTIAL
110100
ANALOG INPUT FREQUENCY (MHz)
MAX1448-03
MAX1448-06
MAX1448-09
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
6 _______________________________________________________________________________________
S
Typical Operating Characteristics (continued)
(VDD= +3.0V, OVDD= +2.7V, internal reference, differential input at -0.5dB FS, f
CLK
= 83.3MHz, CL≈ 10pF, TA= +25°C, unless oth-
erwise noted.)
SIGNAL-TO-NOISE PLUS DISTORTION vs.
ANALOG INPUT FREQUENCY
65
62
59
SINAD (dB)
56
53
DIFFERENTIAL
SINGLE-ENDED
MAX1448-10
FULL-POWER INPUT BANDWIDTH vs.
ANALOG INPUT FREQUENCY
(SINGLE-ENDED)
6
4
2
0
-2
AMPLITUDE (dB)
-4
-6
MAX1448-11
MALL-SIGNAL INPUT BANDWIDTH vs.
6
4
2
0
-2
AMPLITUDE (dB)
-4
-6
ANALOG INPUT FREQUENCY
(SINGLE-ENDED)
VIN = 100mVp-p
MAX1448-12
MAX1448-14
MAX1448-17
-8
1 10 100 1000
ANALOG INPUT FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION
vs. INPUT POWER (f
-50
-55
-60
-65
THD (dBc)
-70
-75
-80
-15 -9-12 -6 -3 0
INPUT POWER (dB FS)
= 20MHz)
IN
SIGNAL-TO-NOISE RATIO
vs. TEMPERATURE
70
fIN = 20MHz
66
62
MAX1448-15
MAX1448-18
MAX1448-16
-8
1 10 100 1000
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE RATIO
vs. INPUT POWER (f
65
60
55
SNR (dB)
50
45
40
-15 -9-12 -6 -3 0
INPUT POWER (dB FS)
= 20MHz)
IN
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE
84
fIN = 20MHz
80
76
50
110100
ANALOG INPUT FREQUENCY (MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT POWER (f
80
75
70
65
SFDR (dBc)
60
55
50
-15 -9-12 -6 -3 0
INPUT POWER (dB FS)
= 20MHz)
IN
MAX1448-13
SIGNAL-TO-NOISE PLUS DISTORTION
vs. INPUT POWER (f
65
60
55
= 20MHz)
IN
SINAD (dB)
50
45
40
-15 -9-12 -6 -3 0
INPUT POWER (dB FS)
SFDR (dBc)
72
68
64
-40 10-15 35 60 85
TEMPERATURE (°C)
SNR (dB)
58
54
50
-40 10-15 35 60 85
TEMPERATURE (°C)
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(VDD= +3.0V, OVDD= +2.7V, internal reference, differential input at -0.5dB FS, f
CLK
= 83.3MHz, CL≈ 10pF, TA= +25°C, unless oth-
erwise noted.)
32
35
41
38
44
47
-40 10-15 35 60 85
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX1448-26
TEMPERATURE (°C)
I
VDD
(mA)
2
4
8
6
10
12
1.6 2.42.0 2.8 3.2 3.6
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
MAX1448-27
OVDD (V)
I
OVDD
(mA)
fIN = 7.5MHz
37
39
43
41
45
47
2.70 3.002.85 3.15 3.30 3.45 3.60
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1448-25
VDD (V)
I
VDD
(mA)
THD (dBc)
DNL (LSB)
TOTAL HARMONIC DISTORTION
vs. TEMPERATURE
-60
fIN = 20MHz
-64
-68
-72
-76
-80
-40 10-15 35 60 85
TEMPERATURE (°C)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
0400200 600 800 1000 1200
DIGITAL OUTPUT CODE
MAX1448-19
MAX1448-22
GAIN ERROR (LSB)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. TEMPERATURE
70
fIN = 20MHz
66
62
SINAD (dB)
58
54
50
-40 10-15 35 60 85
TEMPERATURE (°C)
GAIN ERROR vs. TEMPERATURE
EXTERNAL REFERENCE (V
0.05
0.04
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
-0.05
-40 10-15 35 60 85
TEMPERATURE (°C)
REFIN
= +2.048V)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
(BEST STRAIGHT LINE)
0.8
0.6
MAX1448-20
0.4
0.2
INL (LSB)
0
-0.2
-0.4
-0.6
0 400 600200 800 1000 1200
DIGITAL OUTPUT CODE
OFFSET ERROR vs. TEMPERATURE,
MAX1448-23
OFFSET ERROR (LSB)
EXTERNAL REFERENCE (V
3
2
1
0
-1
-2
-3
-40 10-15 35 60 85
TEMPERATURE (°C)
REFIN
MAX1448-21
= +2.048V)
MAX1448-24
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
8 _______________________________________________________________________________________
I
(
A)
Typical Operating Characteristics (continued)
(VDD= +3.0V, OVDD= +2.7V, internal reference, differential input at -0.5dB FS, f
CLK
= 83.3MHz, CL≈ 10pF, TA= +25°C, unless oth-
erwise noted.)
12
10
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
fIN = 7.5MHz
MAX1448-28
ANALOG POWER-DOWN CURRENT
vs. ANALOG POWER SUPPLY
6
OE = OVDD, PD = V
5
DD
DIGITAL POWER-DOWN CURRENT
vs. DIGITAL POWER SUPPLY
10
PD = VDD, OE = OVDD
MAX1448-29
8
MAX1448-30
8
(mA)
OVDD
I
6
4
2
-40 10-15 35 60 85
TEMPERATURE (°C)
4
(µA)
VDD
I
3
2
1
2.70 3.002.85 3.15 3.30 3.45 3.60
SFDR, SNR, THD, SINAD
vs. CLOCK FREQUENCY
85
fIN = 25.12MHz
80
75
SFDR
70
65
60
SFDR, SNR, THD, SINAD (dB)
55
50
70 80 8575 90 95 100
THD
SNR
SINAD
CLOCK FREQUENCY (MHz)
MAX1448-31
VDD (V)
6
µ
OVDD
4
2
0
1.2 2.41.8 3.0 3.6
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
2.10
2.08
2.06
(V)
REFOUT
V
2.04
2.02
2.00
2.70 3.002.85 3.15 3.30 3.45 3.60
VDD (V)
OVDD (V)
MAX1448-32
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.10
2.08
2.06
(V)
REFOUT
V
2.04
2.02
2.00
-40 10-15 35 60 85
TEMPERATURE (°C)
MAX1448-33
OUTPUT NOISE HISTOGRAM (DC INPUT)
140000
120000
100000
80000
COUNTS
60000
40000
20000
0
0
129377
965
N-1N-2
N
DIGITAL OUTPUT NOISE
730
N+1
MAX1448-34
0
N+2
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1 REFN
2 COM Common-Mode Voltage Output. Bypass to GND with a >0.1µF capacitor.
3, 9, 10 V
4, 5, 8, 11,
14, 30
6 IN+ Positive Analog Input. For single-ended operation, connect signal source to IN+.
7 IN- Negative Analog Input. For single-ended operation, connect IN- to COM.
12 CLK Conversion Clock Input
13 PD
15 OE
16–20 D9–D5 Three-State Digital Outputs D9–D5. D9 is the MSB.
21 OV
22 T.P. Test Point.
DD
GND Analog Ground
DD
Lower Reference. Conversion range is ±(V
capacitor.
Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with
0.1µF.
Power-Down Input
High: power-down mode
Low: normal operation
Output Enable Input
High: digital outputs disabled
Low: digital outputs enabled
Output Driver Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in
parallel with 0.1µF.
Do not connect.
REFP
- V
). Bypass to GND with a >0.1µF
REFN
23 OGND Output Driver Ground
24–28 D4–D0 Three-State Digital Outputs D4–D0. D0 is the LSB.
29 REFOUT
31 REFIN Reference Input. V
32 REFP
Internal Reference Voltage Output. May be connected to REFIN through a resistor or a
resistor-divider.
= 2 × (V
REFIN
Upper Reference. Conversion range is ±(V
capacitor.
REFP
- V
). Bypass to GND with a >0.1µF capacitor.
REFN
- V
REFP
). Bypass to GND with a >0.1µF
REFN
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
10 ______________________________________________________________________________________
_______________Detailed Description
The MAX1448 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage
every half clock-cycle. Counting the delay through the
output latch, the clock-cycle latency is 5.5.
A 1.5-bit (2-comparator) flash ADC converts the held
input voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage where the
process is repeated. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC
comparator offsets in each pipeline stage and ensures
no missing codes.
Input Track-and-Hold Circuit
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuit in both track and hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuit
samples the input signal onto the two capacitors (C2a
and C2b) through S4a and S4b. S2a and S2b set the
common mode for the amplifier input and open simulta-
neously with S1, sampling the input waveform. S4a and
S4b are then opened before S3a and S3b connect
capacitors C1a and C1b to the amplifier output, and
S4c is closed. The resulting differential voltage is held
on C2a and C2b. The amplifier is used to charge C1a
and C1b to the same values originally held on C2a and
C2b. This value is then presented to the first-stage
quantizer and isolates the pipeline from the fast-changing input. The wide-input-bandwidth T/H amplifier
allows the MAX1448 to track and sample/hold analog
inputs of high frequencies beyond Nyquist. Analog
inputs (IN+ and IN-) can be driven either differentially
or single-ended. It is recommended to match the
impedance of IN+ and IN- and set the common-mode
voltage to midsupply (V
DD
/2) for optimum performance.
Analog Input and Reference Configuration
The MAX1448 full-scale range is determined by the
internally generated voltage difference between REFP
(VDD/2 + V
REFIN
/4) and REFN (VDD/2 - V
REFIN
/4). The
ADC’s full-scale range is user-adjustable through the
REFIN pin, which provides a high input impedance for
this purpose. REFOUT, REFP, COM (VDD/2), and REFN
are internally buffered, low-impedance outputs.
Figure 1. Pipelined Architecture—Stage Blocks
Figure 2. Internal Track-and-Hold Circuit
MDAC
V
IN
T/H
FLASH
ADC
Σ
DAC
V
OUT
x2
IN+
S4a
S4c
INTERNAL
BIAS
S2a
C2a
S1
C1a
COM
S5a
S3a
OUT
1.5 BITS
V
IN
V
= INPUT VOLTAGE BETWEEN
IN
IN+ AND IN- (DIFFERENTIAL OR SINGLE-ENDED)
STAGE 1 STAGE 2
DIGITAL CORRECTION LOGIC
D9–D0
STAGE 10
10
IN-
TRACK
S4b
HOLD
TRACK
C2b
HOLD
S2b
INTERNAL
BIAS
CLK
INTERNAL
NON-OVERLAPPING
CLOCK SIGNALS
OUT
C1b
S3b
S5b
COM
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
______________________________________________________________________________________ 11
The MAX1448 provides three modes of reference operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, the internal reference output (REFOUT) can be tied to the REFIN pin through a
resistor (e.g., 10kΩ) or resistor-divider if an application
requires a reduced full-scale range. For stability purposes, it is recommended to bypass REFIN with a
>10nF capacitor to GND.
In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a
stable and accurate voltage at REFIN. In this mode,
REFOUT may be left open or connected to REFIN
through a >10kΩ resistor.
In unbuffered external reference mode, REFIN is connected to GND, thereby deactivating the on-chip
buffers of REFP, COM, and REFN. With their buffers
shut down, these pins become high impedance and
can be driven by external reference sources.
Clock Input (CLK)
The MAX1448 CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). In particular,
sampling occurs on the falling edge of the clock signal,
mandating this edge to provide lowest possible jitter.
Any significant aperture jitter would limit the SNR performance of the ADC as follows:
SNR = 20log (1 / 2πfINtAJ)
where fINrepresents the analog input frequency, and
tAJis the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any analog input or other digital signal lines.
The MAX1448 clock input operates with a voltage
threshold set to VDD/2. Clock inputs with a duty cycle
other than 50% must meet the specifications for high
and low periods as stated in the Electrical Character-
istics. See Figures 3a, 3b, 4a, and 4b for the relationship between spurious-free dynamic range (SFDR),
signal-to-noise ratio (SNR), total harmonic distortion
(THD), or signal-to-noise plus distortion (SINAD) versus
duty cycle.
Output Enable (OE), Power Down (PD),
and Output Data (D0–D9)
All data outputs, D0 (LSB) through D9 (MSB), are
TTL/CMOS-logic compatible. There is a 5.5 clock-cycle
latency between any particular sample and its valid
output data. The output coding is straight offset binary
(Table 1). With OE and PD high, the digital outputs
enter a high-impedance state. If OE is held low with PD
high, the outputs are latched at the last value prior to
the power down.
The capacitive load on the digital outputs D0–D9
should be kept as low as possible (<15pF) to avoid
large digital currents that could feed back into the analog portion of the MAX1448, degrading its dynamic performance. Using buffers on the ADC’s digital outputs
can further isolate the digital outputs from heavy
capacitive loads. To further improve the MAX1448’s
dynamic performance, small series resistors (e.g.,
100Ω) may be added to the digital output paths, close
to the ADC.
Figure 5 displays the timing relationship between output enable and data output valid as well as powerdown/wake-up and data output valid.
System Timing Requirements
Figure 6 shows the relationship between the clock
input, analog input, and data output. The MAX1448
samples at the falling edge of the input clock. Output
Table 1. MAX1448 Output Code for Differential Inputs
*V
REF
= V
REFP
= V
REFN
DIFFERENTIAL INPUT VOLTAGE* DIFFERENTIAL INPUT STRAIGHT OFFSET BINARY
V
× 511/512 +Full Scale -1LSB 11 1111 1111
REF
V
× 510/512 +Full Scale -2LSB 11 1111 1110
REF
V
× 1/512 +1LSB 10 0000 0001
REF
0 Bipolar Zero 10 0000 0000
- V
× 1/512 -1LSB 01 1111 1111
REF
- V
× 511/512 Negative Full Scale + 1LSB 00 0000 0001
REF
- V
× 512/512 Negative Full Scale 00 0000 0000
REF
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
12 ______________________________________________________________________________________
data is valid on the rising edge of the input clock. The
output data has an internal latency of 5.5 clock cycles.
Figure 6 also shows the relationship between the input
clock parameters and the valid output data.
Applications Information
Figure 7 shows a typical application circuit containing a
single-ended to differential converter. The internal reference provides a V
DD
/2 output voltage for level shifting
purposes. The input is buffered and then split to a volt-
age follower and inverter. A lowpass filter follows the op
amps to suppress some of the wideband noise associated with high-speed op amps. The user may select the
R
ISO
and CINvalues to optimize the filter performance
to suit a particular application. For the application in
Figure 7, an RISO of 50Ω is placed before the capacitive load to prevent ringing and oscillation. The 22pF
CINcapacitor acts as a small bypassing capacitor.
Figure 3a. Spurious Free Dynamic Range vs. Clock Duty
Cycle (Differential Input)
Figure 3b. Signal-to-Noise Ratio vs. Clock Duty Cycle
(Differential Input)
Figure 4a. Total Harmonic Distortion vs. Clock Duty Cycle
(Differential Input)
Figure 4b. Signal-to-Noise Plus Distortion vs. Clock Duty Cycle
(Differential Input)
100
fIN = 25.12MHz AT -0.5dB FS
90
80
SFDR (dBc)
70
60
50
20 4030 50 60 70
CLOCK DUTY CYCLE (%)
64
fIN = 25.12MHz AT -0.5dB FS
62
60
58
SNR (dB)
56
-50
fIN = 25.12MHz AT -0.5dB FS
-55
-60
-65
-70
THD (dBc)
-75
-80
-85
20 4030 50 60 70
CLOCK DUTY CYCLE (%)
64
fIN = 25.12MHz AT -0.5dB FS
62
60
58
SINAD (dB)
56
54
52
20 4030 50 60 70
CLOCK DUTY CYCLE (%)
54
52
20 4030 50 60 70
CLOCK DUTY CYCLE (%)
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution for converting a single-ended source signal to
a fully differential signal, required by the MAX1448 for
optimum performance. Connecting the transformer’s
center tap to COM provides a VDD/2 DC level shift to
the input. Although a 1:1 transformer is shown, a stepup transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the overall distortion.
In general, the MAX1448 provides better SFDR and
THD with fully differential input signals than singleended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower since both inputs (IN+, IN-) are balanced, and
each of the inputs only requires half the signal swing
compared to single-ended mode.
Single-Ended AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended application. The MAX4108 op amp provides high speed, high
bandwidth, low noise, and low distortion to maintain the
integrity of the input signal.
Grounding, Bypassing,
and Board Layout
The MAX1448 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass VDD, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OV
D
D
) to OGND. Multilayer
boards with separated ground and power planes produce the highest level of signal integrity. Consider
Figure 5. Output Enable Timing
Figure 6. System and Output Timing Diagram
______________________________________________________________________________________ 13
OE
t
ENABLE
OUTPUT
DATA D9–D0
t
DISABLE
VALID DATA
HIGH-ZHIGH-Z
N
ANALOG INPUT
CLOCK INPUT
t
D0
DATA OUTPUT
N - 6
N - 5
N + 1
5.5 CLOCK-CYCLE LATENCY
N + 2
t
CH
N - 4
N - 3
N + 3
N - 2
N + 4
t
CL
N - 1
N + 5
N
N + 6
N + 1
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
14 ______________________________________________________________________________________
using a split ground plane arranged to match the physical location of the analog ground (GND) and the digital
output driver ground (OGND) on the ADC's package.
The two ground planes should be joined at a single
point so that the noisy digital ground currents do not
interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground
planes that produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to
5Ω), a ferrite bead, or a direct short. Alternatively, all
ground pins could share the same ground plane if the
ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output
buffer or DSP ground plane). Route high-speed digital
signal traces away from sensitive analog traces. Keep
all signal lines short and free of 90° turns.
Static Parameter Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best straight-line fit or a line
drawn between the endpoints of the transfer function
once offset and gain errors have been nullified. The
MAX1448’s static linearity parameters are measured
using the best straight-line fit method.
Figure 7. Typical Application Circuit Using the Internal Reference
+5V
+5V
INPUT
MAX4108
-5V
0.1µF
0.1µF
300Ω
300Ω
300Ω
300Ω
0.1µF
600Ω
600Ω
0.1µF
MAX4108
-5V
+5V
MAX4108
-5V
600Ω
0.1µF
0.1µF
0.1µF
0.1µF
LOWPASS FILTER
R
ISO
50Ω
LOWPASS FILTER
R
ISO
50Ω
C
IN
22pF
C
IN
22pF
IN+
MAX1448
COM
IN-
300Ω
300Ω
600Ω
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
______________________________________________________________________________________ 15
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter
Figure 10 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 10).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum A/D noise is caused by quantization error only
and results directly from the ADC’s resolution (N bits):
SNR
(MAX)
= (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental
and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is computed from:
ENOB = (SINAD - 1.76dB) / 6.02dB
Figure 8. Using a Transformer for AC Coupling
Figure 9. Single-Ended AC-Coupled Input
25Ω
IN+
22pF
0.1µF
V
IN
N.C.
MINICIRCUITS
1
2
T1
TT1–6
6
5
2.2µF
43
0.1µF
25Ω
22pF
MAX1448
COM
IN-
V
IN
MAX4108
R
= 50Ω
ISO
= 22pF
C
IN
100Ω
100Ω
0.1µF
REFP
REFN
1k
R
ISO
C
1k
0.1µF
IN
R
ISO
C
IN
IN+
MAX1448
COM
IN-
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
16 ______________________________________________________________________________________
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the input
signal’s first five harmonics to the fundamental itself.
This is expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious
component, excluding DC offset.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels
are at -6.5dB full scale, and their envelope is at -0.5dB
full scale.
___________________Chip Information
TRANSISTOR COUNT: 5684
PROCESS: CMOS
Figure 10. Track-and-Hold Aperture Timing
Pin Configuration
CLK
ANALOG
INPUT
t
AD
SAMPLED
DATA (T/H)
T/H
TRACK TRACK
t
AJ
HOLD
THD VVVV V=× +++
20 1
log ( ) /
2232425
()
2
TOP VIEW
REFIN
GND
REFOUT
293031
MAX1448
D0
D1
D2
D3
27
25
26
24 D4
OGND
23
T.P.
22
OV
21
DD
D5
20
D6
19
D7
18
D8
17
COM
V
GND
GND
IN+
IN-
REFP
32 28
1REFN
2
3
DD
4
5
6
7
8GND
CLK
14
13
PD
GND
10
9
DD
DD
V
V
GND
TQFP
15
1611 12
OE
D9
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
______________________________________________________________________________________ 17
Package Information
32L,TQFP.EPS
E
MAX1448
10-Bit, 80Msps, Single +3.0V, Low-Power
ADC with Internal Reference
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
E
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