General Description
The MAX1444 10-bit, +3V analog-to-digital converter
(ADC) features a pipelined 10-stage ADC architecture
with fully differential wideband track-and-hold (T/H)
input and digital error correction incorporating a fully
differential signal path. This ADC is optimized for lowpower, high dynamic performance applications in
imaging and digital communications. The MAX1444
operates from a single +2.7V to +3.6V supply, consuming only 57mW while delivering a 59.5dB signal-tonoise ratio (SNR) at a 20MHz input frequency. The fully
differential input stage has a 400MHz -3dB bandwidth
and may be operated with single-ended inputs. In addition to low operating power, the MAX1444 features a
5µA power-down mode for idle periods.
An internal +2.048V precision bandgap reference is
used to set the ADC full-scale range. A flexible reference structure allows the user to supply a buffered,
direct, or externally derived reference for applications
requiring increased accuracy or a different input voltage range.
Higher speed, pin-compatible versions of the MAX1444
are also available. Please refer to the MAX1446 data
sheet (60Msps) and the MAX1448 data sheet
(80Msps).
The MAX1444 has parallel, offset binary, CMOS-compatible three-state outputs that can be operated from
+1.7V to +3.6V to allow flexible interfacing. The device
is available in a 5x5mm 32-pin TQFP package and is
specified over the extended industrial (-40°C to +85°C)
temperature range.
________________________Applications
Ultrasound Imaging
CCD Imaging
Baseband and IF Digitization
Digital Set-Top Boxes
Video Digitizing Applications
Features
♦ Single +3.0V Operation
♦ Excellent Dynamic Performance
59.5dB SNR at f
IN
= 20MHz
74dBc SFDR at fIN= 20MHz
♦ Low Power
19mA (Normal Operation)
5µA (Shutdown Mode)
♦ Fully Differential Analog Input
♦ Wide 2V
p-p Differential Input Voltage Range
♦ 400MHz -3dB Input Bandwidth
♦ On-Chip +2.048V Precision Bandgap Reference
♦ CMOS-Compatible Three-State Outputs
♦ 32-Pin TQFP Package
♦ Evaluation Kit Available
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
________________________________________________________________ Maxim Integrated Products 1
Pin Configuration
19-1745; Rev 0; 7/00
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
EVALUATION KIT
AVAILABLE
Ordering Information
Functional Diagram appears at end of data sheet.
PART TEMP. RANGE PIN-PACKAGE
MAX1444EHJ -40°C to +85°C 32 TQFP
TOP VIEW
REFIN
GND
REFOUT
REFP
32 28
D0
D1
D2
D3
293031
27
25
26
COM
V
GND
GND
IN+
1REFN
2
3
DD
4
5
6
7
IN-
8GND
9
V
MAX1444
CLK
14
13
15
PD
GND
10
DD
DD
V
GND
24 D4
OGND
23
22
T.P.
21
OV
DD
20
D5
19
D6
18
D7
17
D8
1611 12
OE
D9
TQFP
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= +3.0V, OVDD= +2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= +2.048V, REFOUT con-
nected to REFIN through a 10kΩ resistor, V
IN
= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs, f
CLK
= 40MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD, OVDDto GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
IN+, IN- to GND........................................................-0.3V to V
DD
REFIN, REFOUT, REFP,
REFN, and COM to GND.........................-0.3V to (V
DD
+ 0.3V)
OE, PD, CLK to GND..................................-0.3V to (V
DD
+ 0.3V)
D9–D0 to GND.........................................-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
32-Pin TQFP (derate 11.1mW/°C above +70°C)...........889mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DC ACCURACY
Resolution 10 bits
Integral Nonlinearity INL fIN = 7.51MHz ±0.6 ±1.9 LSB
Differential Nonlinearity DNL
Offset Error <±0.1 ±1.7 % FS
Gain Error 0 ±2% FS
ANALOG INPUT
Input Differential Range V
Common-Mode
Voltage Range
Input Resistance R
Input Capacitance C
CONVERSION RATE
Maximum Clock Frequency f
Data Latency 5.5 cycles
DYNAMIC CHARACTERISTICS (f
Signal-To-Noise Ratio SNR
Signal-To-Noise And Distortion
(Up to 5th harmonic)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CLK
f
= 7.51MHz, no missing codes
IN
guaranteed
DIFF
V
COM
CLK
= 40MHz, 4096-point FFT)
SINAD
Differential or single-ended inputs ±1.0 V
Switched capacitor load 50 kΩ
IN
IN
fIN = 7.51MHz 57.5 59.5
fIN = 19.91MHz 57 59.5
= 39.9MHz (Note 1) 58.5
f
IN
fIN = 7.51MHz 57 59.4
fIN = 19.91MHz 56.7 59
f
= 39.9MHz (Note 1) 58.3
IN
fIN = 7.51MHz 67 75
fIN = 19.91MHz 66 74Spurious-Free Dynamic Range SFDR
= 39.9 MHz (Note 1) 72.5
f
IN
40 MHz
±0.4 ±1.0 LSB
VDD/2
±0.5
5pF
V
dB
dB
dBc
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +3.0V, OVDD= +2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= +2.048V, REFOUT con-
nected to REFIN through a 10kΩ resistor, V
IN
= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs, f
CLK
= 40MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
fIN = 7.51MHz -75
fIN = 19.91MHz -74
Third-Harmonic Distortion HD3
f
IN
= 39.9MHz (Note 1)
dBc
Two-Tone Intermodulation
Distortion
IMD
f
1
= 11.5MHz at -6.5dBFS
f
2
= 13.5MHz at -6.5dBFS
(Note 2)
-76
dBc
Third-Order Intermodulation
Distortion
IM3
f
1
= 11.5MHz at -6.5dBFS
f
2
= 13.5MHz at -6.5dBFS
(Note 2)
-76
dBc
fIN = 7.51MHz
-65
fIN = 19.91MHz
-65
Total Harmonic Distortion
(First 5 Harmonics)
THD
f
IN
= 39.9MHz (Note 1) -70
dBc
Small-Signal Bandwidth Input at -20dBFS, differential inputs
MHz
Full-Power Bandwidth FPBW Input at -0.5dBFS, differential inputs
MHz
Aperture Delay t
AD
1ns
Aperture Jitter t
AJ
2
ps
RMS
Overdrive Recovery Time For 1.5 × full-scale input 2 ns
Differential Gain ±1%
Differential Phase
degree
Output Noise IN+ = IN- = COM 0.2
LS B
RM S
INTERNAL REFERENCE
Reference Output Voltage
2.048 ±1% V
Reference Temperature
Coefficient
60
p p m/°C
Load Regulation
mV/mA
EXTERNAL REFERENCE
Positive Reference REFP V
REFIN
= +2.048V
V
Negative Reference REFN V
REFIN
= +2.048V
V
Differential Reference Voltage
V
REFP
– V
REFN
, V
REFIN
= +2.048V
V
REFIN Resistance
MΩ
DIGITAL INPUTS (CLK, PD, OE)
CLK
0.8 ×
Input High Threshold V
IH
PD, OE
0.8 ×
V
CLK
0.2 ×
Input Low Threshold V
IL
PD, OE
0.2 ×
V
REFOUT
TC
REF
∆V
R
REFIN
REF
0.98 1.024 1.07
V
OV
-72.5
-73.8
-72.2
500
400
±0.25
1.25
2.012
0.988
>50
DD
DD
V
OV
DD
DD
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +3.0V, OVDD= +2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; V
REFIN
= +2.048V, REFOUT con-
nected to REFIN through a 10kΩ resistor, V
IN
= 2Vp-p (differential w.r.t. COM), CL= 10pF at digital outputs, f
CLK
= 40MHz (50% duty
cycle), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a +1.024V full-scale
input voltage range.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better if referenced to the two-tone envelope.
Note 3: Digital outputs settle to V
IH
/ VIL.
Note 4: REFIN is driven externally. REFP, COM, and REFN are left floating while powered down.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Hysteresis V
Input Leakage
Input Capacitance C
DIGITAL OUTPUTS (D9–D0)
Output Voltage Low V
Output Voltage High V
Three-State Leakage Current I
Three-State Output Capacitance C
POWER REQUIREMENTS
Analog Supply Voltage V
Output Supply Voltage OV
Analog Supply Current I
Output Supply Current I
Power Supply Rejection PSRR
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid t
OE Fall to Output Enable t
OE Rise to Output Disable t
CLK Pulse Width High t
CLK Pulse Width Low t
Wake-up Time t
HYST
I
I
LEAK
OUT
VDD
OVDD
VIH = VDD = OV
IH
VIL = 0 ±5
IL
IN
I
OL
OH
= 200µA 0.2 V
SINK
I
SOURCE
OE = OV
OE = OV
DD
DD
DD
= 200µA
DD
DD
Operating, fIN = 19.91MHz at -0.5dBFS 19 25 mA
Shutdown, clock idle, PD = OE = OV
DD
Operating, fIN = 19.91MHz at -0.5dBFS 4.5 mA
Shutdown, clock idle, PD = OE = OV
DD
Offset ±0.1 mV/V
Gain ±0.1 %/V
DO
ENABLE
DISABLE
CH
WAKE
Figure 6, (Note 3) 5 8 ns
Figure 5 10 ns
Figure 5 15 ns
Figure 6, clock period 25ns 12.5 ±3.8 ns
Figure 6, clock period 25ns 12.5 ±3.8 ns
CL
(Note 4) 1.7 µs
0.1 V
±5
5pF
OV
DD
- 0.2
±10 µA
5pF
2.7 3.0 3.6 V
1.7 3.0 3.6 V
415µA
110µA
µA
V
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
_______________________________________________________________________________________ 5
Typical Operating Characteristics
(VDD= +3.0V, OVDD= +2.7V, internal reference, differential input at -0.5dB FS, f
CLK
= 40MHz, CL≈ 10pF, TA= +25°C, unless other-
wise noted.)
-10
-20
-30
-40
-50
-60
AMPLITUDE (dB)
-70
-80
-90
-100
-10
-20
-30
-40
-50
-60
AMPLITUDE (dB)
-70
-80
-90
-100
FFT PLOT (fIN = 7.51MHz,
8192-POINT FFT, DIFFERENTIAL INPUT)
0
0 2 4 6 8101214161820
ANALOG INPUT FREQUENCY (MHz)
SINAD = 59dB
SNR = 59.3dB
THD = -71.6dBc
SFDR = 73dBc
3RD HARMONIC
2ND HARMONIC
FFT PLOT (fIN = 7.51MHz,
8192-POINT FFT, SINGLE-ENDED INPUT)
0
0 2 4 6 8101214161820
ANALOG INPUT FREQUENCY (MHz)
SINAD = 59.7dB
SNR = 60dB
THD = -71.8dBc
SFDR = 75dBc
3RD HARMONIC
2ND HARMONIC
MAX1444-01
MAX1444-04
FFT PLOT (fIN = 19.91MHz,
8192-POINT FFT, DIFFERENTIAL INPUT)
0
SINAD = 58.9dB
-10
SNR = 59.1dB
THD = -72.8dBc
-20
SFDR = 75.2dBc
-30
-40
-50
-60
2ND HARMONIC
AMPLITUDE (dB)
-70
-80
-90
-100
0 2 4 6 8101214161820
ANALOG INPUT FREQUENCY (MHz)
3RD HARMONIC
FFT PLOT (fIN = 19.91MHz,
8192-POINT FFT, SINGLE-ENDED INPUT)
0
SINAD = 59.1dB
-10
SNR = 59.2dB
THD = -74.6dBc
-20
SFDR = 77.6dBc
-30
-40
-50
2ND HARMONIC
-60
AMPLITUDE (dB)
-70
-80
-90
-100
0 2 4 6 8101214161820
ANALOG INPUT FREQUENCY (MHz)
3RD HARMONIC
FFT PLOT (fIN = 47MHz,
8192-POINT FFT, DIFFERENTIAL INPUT)
MAX1444-02
0
-10
-20
-30
-40
-50
-60
AMPLITUDE (dB)
-70
-80
-90
-100
0 5 10 15 20 25
2ND HARMONIC
ANALOG INPUT FREQUENCY (MHz)
SINAD = 58.1dB
SNR = 58.4dB
THD = -69.7dBc
SFDR = 72.4dBc
3RD HARMONIC
FULL-POWER INPUT BANDWIDTH vs.
ANALOG INPUT FREQUENCY (SINGLE-ENDED)
6
MAX1444-05
4
2
0
GAIN (dB)
-2
-4
-6
-8
1 100 1000
10
ANALOG INPUT FREQUENCY (MHz)
MAX1444-03
MAX1444-06
SMALL-SIGNAL INPUT BANDWIDTH vs.
ANALOG INPUT FREQUENCY (SINGLE-ENDED)
6
VIN = 100mVp-p
4
2
0
GAIN (dB)
-2
-4
-6
-8
1 100 1000
10
ANALOG INPUT FREQUENCY (MHz)
MAX1444-07
TWO-TONE INTERMODULATION
8192-POINT IMD (DIFFERENTIAL INPUT)
0
f1 = 11.5MHz AT
-10
-6.5dB FS
= 13.5MHz AT
f
2
-20
-6.5dB FS
3RD IMD = -76dBc
-30
-40
-50
-60
AMPLITUDE (dB)
-70
-80
-90
-100
0 5 10 15 20 25
ANALOG INPUT FREQUENCY (MHz)
MAX1444-08
SPURIOUS-FREE DYNAMIC RANGE vs.
ANALOG INPUT FREQUENCY
80
75
70
65
60
SFDR (dBc)
55
50
45
40
110100
DIFFERENTIAL
SINGLE-ENDED
ANALOG INPUT FREQUENCY (MHz)
MAX1444-09
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
6 _______________________________________________________________________________________
)
)
Typical Operating Characteristics (continued)
(VDD= +3.0V, OVDD= +2.7V, internal reference, differential input at -0.5dB FS, f
CLK
= 40MHz, CL≈ 10pF, TA= +25°C, unless other-
wise noted.)
SNR (dB)
SIGNAL-TO-NOISE RATIO vs.
ANALOG INPUT FREQUENCY
62
61
60
59
58
57
56
55
54
110100
DIFFERENTIAL
SINGLE-ENDED
ANALOG INPUT FREQUENCY (MHz)
MAX1444-10
-45
-50
-55
-60
THD (dBc)
-65
-70
-75
TOTAL HARMONIC DISTORTION vs.
ANALOG INPUT FREQUENCY
SINGLE-ENDED
DIFFERENTIAL
110100
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE PLUS DISTORTION vs.
ANALOG INPUT FREQUENCY
65
MAX1444-11
61
57
SINAD (dB)
53
49
45
1 10 100
DIFFERENTIAL
SINGLE-ENDED
ANALOG INPUT FREQUENCY (MHz)
MAX1444-12
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER
80
fIN = 19.91MHz
75
70
65
SFDR (dBc)
60
55
50
-15 -9-12 -6 -3 0
ANALOG INPUT POWER (dB FS)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT POWER
65
fIN = 19.91MHz
60
55
SINAD (dB)
50
MAX1444-13
MAX1444-16
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER
65
fIN = 19.91MHz
60
55
SNR (dB)
50
45
40
-15 -9-12 -6 -3 0
ANALOG INPUT POWER (dB FS)
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE
84
fIN = 19.91MHz
80
76
SFDR (dBc)
72
MAX1444-14
MAX1444-17
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER
-50
fIN = 19.91MHz
-55
-60
-65
THD (dBc)
-70
-75
-80
-15 -9-12 -6 -3 0
ANALOG INPUT POWER (dB FS)
SIGNAL-TO-NOISE RATIO
vs. TEMPERATURE
70
fIN = 19.91MHz
66
62
SNR (dB)
58
MAX1444-15
MAX1444-18
45
40
-15 -9-12 -6 -3 0
ANALOG INPUT POWER (dB FS
68
64
-40 10-15 35 60 85
TEMPERATURE (°C
54
50
-40 10-15 356085
TEMPERATURE (°C)
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
_______________________________________________________________________________________ 7
)
Typical Operating Characteristics (continued)
(VDD= +3.0V, OVDD= +2.7V, internal reference, differential input at -0.5dB FS, f
CLK
= 40MHz, CL≈ 10pF, TA= +25°C, unless other-
wise noted.)
16
14
20
18
22
24
-40 10-15 356085
MAX1444-26
TEMPERATURE (°C)
I
VDD
(mA)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
1
0
3
2
5
4
6
1.6 2.42 2.8 3.2 3.6
MAX1444-27
OVDD (V)
I
OVDD
(mA)
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
fIN = 7.51MHz
16
14
20
18
22
24
2.70 3.002.85 3.15 3.30 3.45 3.60
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1444-25
V
(V)
I
VDD
(mA)
TOTAL HARMONIC DISTORTION
vs. TEMPERATURE
-60
fIN = 19.91MHz
-64
-68
THD (dBc)
-72
-76
-80
-40 10-15 356085
TEMPERATURE (°
C
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.4
0.3
0.2
0.1
0
DNL (LSB)
-0.1
-0.2
-0.3
-0.4
0400200 600 800 1000 1200
DIGITAL OUTPUT CODE
MAX1444-19
MAX1444-22
SIGNAL-TO-NOISE PLUS DISTORTION
vs. TEMPERATURE
70
fIN = 19.91MHz
66
62
SINAD (dB)
58
54
50
-40 10-15 356085
TEMPERATURE (°C)
GAIN ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE (V
0.05
0.04
0.03
0.02
0.01
0
-0.01
GAIN ERROR (LSB)
-0.02
-0.03
-0.04
-0.05
-40 10-15 35 60 85
TEMPERATURE (°C)
REFIN
= +2.048V)
INTEGRAL NONLINEARITY vs.
DIGITAL OUTPUT CODE (BEST STRAIGHT LINE)
0.4
0.3
MAX1444-20
0.2
0.1
0
INL (LSB)
-0.1
-0.2
-0.3
-0.4
0400200 600 800 1000 1200
DIGITAL OUTPUT CODE
OFFSET ERROR vs. TEMPERATURE,
REFIN
= +2.048V)
MAX1444-23
EXTERNAL REFERENCE (V
10
8
6
4
OFFSET ERROR (LSB)
2
0
-40 10-15 356085
TEMPERATURE (°C)
MAX1444-21
MAX1444-24
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD= +3.0V, OVDD= +2.7V, internal reference, differential input at -0.5dB FS, f
CLK
= 40MHz, CL≈ 10pF, TA= +25°C, unless other-
wise noted.)
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
5
fIN = 7.51MHz
4
(mA)
OVDD
I
3
2
1
MAX1444-28
ANALOG POWER-DOWN CURRENT
vs. ANALOG POWER SUPPLY
5.0
OE = OV
DD
PD = V
DD
(µA)
I
VDD
4.5
4.0
3.5
3.0
2.5
DIGITAL POWER-DOWN CURRENT
vs. DIGITAL POWER SUPPLY
10
PD = V
DD
OE = OV
MAX1444-29
(µA)
OVDD
I
8
6
4
2
DD
MAX1444-30
0
-40 10-15 356085
TEMPERATURE (°C)
SFDR, SNR, THD, SINAD vs.
CLOCK FREQUENCY (OVER-CLOCKING)
80
fIN = 13.24MHz
75
70
65
60
SFDR, SNR, THD, SINAD (dB)
55
50
30 3834 42 46 50
CLOCK FREQUENCY (MHz)
SFDR
THD
SNR
SINAD
MAX1444-31
2.0
2.70 3.002.85 3.15 3.30 3.45 3.60
VDD (V)
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
2.10
2.08
2.06
(V)
REFOUT
2.04
V
2.02
2.00
2.70 2.85 3.00 3.15 3.30 3.45 3.60
VDD (V)
OUTPUT NOISE HISTOGRAM (DC INPUT)
70000
63000
56000
49000
42000
35000
COUNTS
28000
21000
14000
7000
0869
0
N-2 N-1 N N+1 N+2
64515
152 0
DIGITAL OUTPUT CODE
MAX1444-32
MAX1444-34
0
1.2 1.8 2.4 3.0 3.6
OVDD (V)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.10
2.08
2.06
(V)
REFOUT
2.04
V
2.02
2.00
-40 10-15 356085
TEMPERATURE (°C)
MAX1444-33
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1 REFN
2 COM Common-Mode Voltage Output. Bypass to GND with a >0.1µF capacitor.
3, 9, 10 V
4, 5, 8, 11, 14, 30 GND Analog Ground
6 IN+ Positive Analog Input. For single-ended operation, connect signal source to IN+.
7 IN- Negative Analog Input. For single-ended operation, connect IN- to COM.
12 CLK Conversion Clock Input
13 PD Power Down Input. High: Power-down mode. Low: Normal operation.
15 OE Output Enable Input. High: Digital outputs disabled. Low: Digital outputs enabled.
16–20 D9–D5 Three-State Digital Outputs D9–D5. D9 is the MSB.
21 OV
22 T.P. Test Point. Do not connect.
23 OGND Output Driver Ground
24–28 D4–D0 Three-State Digital Outputs D4–D0. D0 is the LSB.
29 REFOUT
31 REFIN Reference Input. V
32 REFP
DD
DD
Lower Reference. Conversion range is ±(V
Bypass to GND with a > 0.1µF capacitor.
Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel
with 0.1µF.
Output Driver Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in
parallel with 0.1µF.
Internal Reference Voltage Output. May be connected to REFIN through a resistor or a
resistor-divider.
= 2 × (V
REFIN
Upper Reference. Conversion range is ±(V
capacitor.
REFP
- V
- V
- V
).
REFN
). Bypass to GND with a >0.1µF
REFN
REFP
). Bypass to GND with a >0.1µF capacitor.
REFN
REFP
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
10 ______________________________________________________________________________________
Detailed Description
The MAX1444 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage
every half-clock cycle. Counting the delay through the
output latch, the clock-cycle latency is 5.5.
A 1.5-bit (2-comparator) flash ADC converts the held
input voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage where the
process is repeated until the signal has been
processed by all 10 stages. Each stage provides a
1-bit resolution. Digital error correction compensates
for ADC comparator offsets in each pipeline stage and
ensures no missing codes.
Input Track-and-Hold Circuit
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuit in both track and hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuit
samples the input signal onto the two capacitors (C2a
and C2b). Switches S2a and S2b set the common
mode for the amplifier input. The resulting differential
voltage is held on C2a and C2b. Switches S4a, S4b,
S5a, S5b, S1, S2a, and S2b are then opened before
S3a, S3b, and S4c are closed, connecting capacitors
C1a and C1b to the amplifier output. This charges C1a
and C1b to the same values originally held on C2a and
C2b. This value is then presented to the first-stage
quantizer and isolates the pipeline from the fast-changing input. The wide-input-bandwidth T/H amplifier
allows the MAX1444 to track and sample/hold analog
inputs of high frequencies beyond Nyquist. The analog
inputs (IN+ and IN-) can be driven either differentially
or single-ended. It is recommended to match the
impedance of IN+ and IN- and set the common-mode
voltage to midsupply (V
DD
/2) for optimum performance.
Analog Input and Reference Configuration
The MAX1444 full-scale range is determined by the
internally generated voltage difference between REFP
(VDD/2 + V
REFIN
/4) and REFN (VDD/2 - V
REFIN
/4). The
ADC’s full-scale range is user-adjustable through the
REFIN pin, which provides a high input impedance for
this purpose. REFOUT, REFP, COM (VDD/2), and REFN
are internally buffered, low-impedance outputs.
Figure 1. Pipelined Architecture—Stage Blocks
Figure 2. Internal T/H Circuit
V
IN
FLASH
ADC
T/H
DAC
MDAC
V
OUT
Σ
x2
IN+
S4a
S4c
C2a
INTERNAL
BIAS
S2a
S1
C1a
COM
S5a
S3a
OUT
1.5 BITS
V
IN
STAGE 1 STAGE 2
DIGITAL CORRECTION LOGIC
10
V
= INPUT VOLTAGE BETWEEN
IN
IN+ AND IN- (DIFFERENTIAL OR SINGLE-ENDED)
D9–D0
STAGE 10
IN-
S4b
TRACK
HOLD HOLD
TRACK
C2b
INTERNAL
BIAS
CLK
S2b
INTERNAL
NON-OVERLAPPING
CLOCK SIGNALS
OUT
C1b
S3b
S5b
COM
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
______________________________________________________________________________________ 11
The MAX1444 provides three modes of reference operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, the internal reference output (REFOUT) can be tied to the REFIN pin through a
resistor (e.g., 10kΩ) or resistor-divider if an application
requires a reduced full-scale range. For stability purposes, it is recommended to bypass REFIN with a
>10nF capacitor to GND.
In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a
stable and accurate voltage at REFIN. In this mode,
REFOUT may be left open or connected to REFIN
through a >10kΩ resistor.
In unbuffered external reference mode, REFIN is connected to GND, thereby deactivating the on-chip
buffers of REFP, COM, and REFN. With their buffers
shut down, these pins become high impedance and
can be driven by external reference sources.
Clock Input (CLK)
The MAX1444 CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). In particular,
sampling occurs on the falling edge of the clock signal,
mandating this edge to provide lowest possible jitter.
Any significant aperture jitter would limit the SNR performance of the ADC as follows:
SNR = 20log (1 / 2πfINtAJ)
where fINrepresents the analog input frequency, and
tAJis the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines.
The MAX1444 clock input operates with a voltage
threshold set to VDD/2. Clock inputs with a duty cycle
other than 50% must meet the specifications for high
and low periods as stated in the Electrical Character-
istics. See Figures 3a, 3b, 4a, and 4b for the relationship between spurious-free dynamic range (SFDR),
signal-to-noise ratio (SNR), total harmonic distortion
(THD), or signal-to-noise plus distortion (SINAD) versus
duty cycle.
Output Enable (OE), Power Down (PD),
and Output Data (D0–D9)
All data outputs, D0 (LSB) through D9 (MSB), are
TTL/CMOS-logic compatible. There is a 5.5 clock-cycle
latency between any particular sample and its valid
output data. The output coding is straight offset binary
(Table 1). With OE and PD (power down) high, the digital output enters a high-impedance state. If OE is held
low with PD high, the outputs are latched at the last
value prior to the power down.
The capacitive load on the digital outputs D0–D9
should be kept as low as possible (<15pF) to avoid
large digital currents that could feed back into the analog portion of the MAX1444, thus degrading its dynamic performance. The use of buffers on the ADC’s digital
outputs can further isolate the digital outputs from
heavy capacitive loads.
Figure 5 displays the timing relationship between output enable and data output valid as well as powerdown/wake-up and data output valid.
Table 1. MAX1444 Output Code for Differential Inputs
*V
REF
= V
REFP
– V
REFN
DIFFERENTIAL INPUT VOLTAGE* DIFFERENTIAL INPUT STRAIGHT OFFSET BINARY
V
× 511/512 +Full Scale -1LSB 11 1111 1111
REF
V
× 510/512 +Full Scale -2LSB 11 1111 1110
REF
V
× 1/512 +1LSB 10 0000 0001
REF
0 Bipolar Zero 10 0000 0000
- V
× 1/512 -1LSB 01 1111 1111
REF
- V
× 511/512 Negative Full Scale + 1LSB 00 0000 0001
REF
- V
× 512/512 Negative Full Scale 00 0000 0000
REF
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
12 ______________________________________________________________________________________
Figure 3a. Spurious-Free Dynamic Range vs. Clock Duty Cycle
(Differential Input)
Figure 3b. Signal-to-Noise Ratio vs. Clock Duty Cycle
(Differential Input)
Figure 4a. Total Harmonic Distortion vs. Clock Duty Cycle
(Differential Input)
Figure 4b. Signal-to-Noise Plus Distortion vs. Clock Duty Cycle
(Differential Input)
Figure 5. Output Enable Timing
90
fIN = 13.24MHz AT-0.5dB FS
85
80
75
SFDR (dBc)
70
65
60
20 4030 50 60 70
CLOCK DUTY CYCLE (%)
61
fIN = 13.24MHz AT-0.5dB FS
60
59
SNR (dB)
58
-60
fIN = 13.24MHz AT-0.5dB FS
-64
-68
THD (dBc)
-72
-76
-80
20 4030 50 60 70
CLOCK DUTY CYCLE (%)
61
fIN = 13.24MHz AT-0.5dB FS
60
59
SINAD (dB)
57
56
20 4030 50 60 70
CLOCK DUTY CYCLE (%)
OE
t
OUTPUT
DATA D9–D0
ENABLE
VALID DATA
58
57
20 4030 50 60 70
CLOCK DUTY CYCLE (%)
t
DISABLE
HIGH-ZHIGH-Z
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
______________________________________________________________________________________ 13
System Timing Requirements
Figure 6 shows the relationship between the clock
input, analog input, and data output. The MAX1444
samples at the falling edge of the input clock. Output
data is valid on the rising edge of the input clock. The
output data has an internal latency of 5.5 clock cycles.
Figure 6 also shows the relationship between the input
clock parameters and the valid output data.
__________Applications Information
Figure 7 shows a typical application circuit containing a
single-ended to differential converter. The internal reference provides a V
DD
/2 output voltage for level shifting
purposes. The input is buffered and then split to a voltage follower and inverter. A lowpass filter follows the op
amps to suppress some of the wideband noise associated with high-speed op amps. The user may select the
R
ISO
and CINvalues to optimize the filter performance
to suit a particular application. For the application in
Figure 7, an R
ISO
of 50Ω is placed before the capacitive load to prevent ringing and oscillation. The 22pF
CINcapacitor acts as a small bypassing capacitor.
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution for converting a single-ended source signal to
a fully differential signal, required by the MAX1444 for
optimum performance. Connecting the transformer’s
center tap to COM provides a VDD/2 DC level shift to
the input. Although a 1:1 transformer is shown, a step-
up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the overall distortion.
In general, the MAX1444 provides better SFDR and
THD with fully differential input signals than singleended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower since both inputs (IN+, IN-) are balanced, and
each of the inputs only requires half the signal swing
compared to single-ended mode.
Single-Ended AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended application. The MAX4108 op amp provides high speed, high
bandwidth, low noise, and low distortion to maintain the
integrity of the input signal.
Grounding, Bypassing,
and Board Layout
The MAX1444 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass VDD, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OVDD) to OGND. Multilayer
boards with separated ground and power planes pro-
Figure 6. System and Output Timing Diagram
N
ANALOG INPUT
CLOCK INPUT
t
DO
DATA OUTPUT
N - 6
N - 5
N + 1
5.5 CLOCK-CYCLE LATENCY
N + 2
N - 4
N - 3
N + 3
t
CLtCH
N - 2
N + 4
N - 1
N + 5
N
N + 6
N + 7
N + 1
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
14 ______________________________________________________________________________________
duce the highest level of signal integrity. Consider
using a split ground plane arranged to match the physical location of the analog ground (GND) and the digital
output driver ground (OGND) on the ADC's package.
The two ground planes should be joined at a single
point so that the noisy digital ground currents do not
interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground
planes that produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to
5Ω), a ferrite bead, or a direct short. Alternatively, all
ground pins could share the same ground plane if the
ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output
buffer or DSP ground plane). Route high-speed digital
signal traces away from sensitive analog traces. Keep
all signal lines short and free of 90° turns.
Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion
+5V
+5V
INPUT
MAX4108
-5V
0.1µF
0.1µF
300Ω
300Ω
300Ω
300Ω
0.1µF
600Ω
600Ω
0.1µF
MAX4108
-5V
+5V
MAX4108
-5V
600Ω
0.1µF
0.1µF
0.1µF
0.1µF
LOWPASS FILTER
R
ISO
50Ω
LOWPASS FILTER
R
ISO
50Ω
C
IN
22pF
C
IN
22pF
IN+
MAX1444
COM
IN-
300Ω
300Ω
600Ω
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
______________________________________________________________________________________ 15
Static Parameter Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best straight-line fit or a line
drawn between the endpoints of the transfer function
once offset and gain errors have been nullified. The
MAX1444’s static linearity parameters are measured
using the best straight-line fit method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Dynamic Parameter Definitions
Aperture Jitter
Figure 10 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 10).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum A/D noise is caused by quantization error only
and results directly from the ADC’s resolution (N bits):
SNR
(MAX)
= (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
Figure 8. Using a Transformer for AC Coupling
Figure 9. Single-Ended AC-Coupled Input
25Ω
22pF
0.1µF
V
IN
N.C.
MINICIRCUITS
1
2
T1
TT1–6
6
5
2.2µF
43
0.1µF
25Ω
22pF
IN+
MAX1444
COM
IN-
REFP
V
IN
MAX4108
R
= 50Ω
ISO
= 22pF
C
IN
100Ω
100Ω
0.1µF
REFN
1k
R
ISO
IN+
C
1k
0.1µF
IN
MAX1444
COM
R
ISO
IN-
C
IN
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
16 ______________________________________________________________________________________
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental
and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is computed from:
ENOB = (SINAD - 1.76dB) / 6.02dB
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the input
signal’s first five harmonics to the fundamental itself.
This is expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious
component, excluding DC offset.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels
are at -6.5dB full scale, and their envelope is at -0.5dB
full scale.
___________________Chip Information
TRANSISTOR COUNT: 5684
PROCESS: CMOS
Figure 10. T/H Aperture Timing
CLK
ANALOG
INPUT
t
AD
SAMPLED
DATA (T/H)
TRACK TRACK
T/H
THD VVVVV=× +++
20
log /
t
AJ
HOLD
2232425
()
2
1
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
______________________________________________________________________________________ 17
Functional Diagram
CLK
IN+
V
MAX1444
CONTROL
10
D
IN-
PD
T/H
REF
PIPELINE ADC
REF SYSTEM +
BIAS
REFINREFOUT REFP COM REFN OE
E
C
OUTPUT
DRIVERS
DD
GND
D9–D0
OV
DD
OGND
MAX1444
10-Bit, 40Msps, +3.0V, Low-Power
ADC with Internal Reference
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
S
32L,TQFP.EP
E
E
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