General Description
The MAX1422 +3.3V, 12-bit analog-to-digital converter
(ADC) features a fully-differential input, pipelined, 12stage ADC architecture with wideband track-and-hold
(T/H) and digital error correction incorporating a fully-differential signal path. The MAX1422 is optimized for lowpower, high dynamic performance applications in
imaging and digital communications. The converter
operates from a single +3.3V supply, consuming only
137mW while delivering a 67dB (typ) signal-to-noise
ratio (SNR) at a 5MHz input frequency and a 20Msps
sampling frequency. The fully-differential input stage
has a small signal -3dB bandwidth of 400MHz and may
be operated with single-ended inputs.
An internal +2.048V precision bandgap reference sets
the ADCs full-scale range. A flexible reference structure
accommodates an internally or externally applied
buffered or unbuffered reference for applications
requiring increased accuracy or a different input voltage range.
In addition to low operating power, the MAX1422 features two power-down modes, a reference power-down,
and a shutdown mode. In reference power-down, the
internal bandgap reference is deactivated, resulting in a
2mA (typ) supply current reduction. For idle periods, a
full shutdown mode is available to maximize power savings.
The MAX1422 provides parallel, offset binary, CMOScompatible three-state outputs.
The MAX1422 is available in a 7mm ✕ 7mm, 48-pin
TQFP package and is specified over the commercial
(0°C to +70°C) and extended industrial (-40°C to
+85°C) temperature ranges.
Pin-compatible higher-speed versions of the MAX1422
are also available. Please refer to the MAX1421 data
sheet for 40Msps and the MAX1420 data sheet for
60Msps.
________________________Applications
Medical Ultrasound Imaging
CCD Pixel Processing
Data Acquisition
Radar
IF and Baseband Digitization
Features
♦ Single +3.3V Power Supply
♦ 67dB SNR at f
IN
= 5MHz
♦ Internal +2.048V Precision Bandgap Reference
♦ Differential Wideband Input T/H Amplifier
♦ Power-Down Modes
130mW (Reference Shutdown Mode)
10µW (Shutdown Mode)
♦ Space-Saving 48-Pin TQFP Package
MAX1422
12-Bit, 20Msps, +3.3V, Low-Power ADC with
Internal Reference
________________________________________________________________ Maxim Integrated Products 1
Pin Configuration
19-1899; Rev 0; 5/01
Ordering Information
Functional Diagram appears at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP. RANGE PIN-PACKAGE
MAX1422CCM 0°C to +70°C 48 TQFP
MAX1422ECM -40°C to +85°C 48 TQFP
AGND
AVDDCML
REFN
REFP
REFIN
AGND
AV
AV
AGND
AGND
INP
INN
AGND
AGND
AV
AV
AGND
AVDDAGNDPDOE
4847464544434241403938
1
2
DD
3
DD
4
5
6
7
8
9
10
DD
11
DD
12
1314151617181920212223
DDAVDD
AV
AGND
AGND
MAX1422
CLK
CLK
AGND
DD
AV
48-TQFP
D11
D10
37
36
35
34
33
32
31
30
29
28
27
26
25
24
DD
D0
DV
D1
DGND
D9
D8
D7
D6
DV
DD
DV
DD
DGND
DGND
D5
D4
D3
D2
MAX1422
12-Bit, 20Msps, +3.3V, Low-Power ADC with
Internal Reference
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
AVDD
= V
DVDD
= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dB FS, internal reference, f
CLK
= 20MHz
(50% duty cycle), digital output load C
L
≈ 10pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD, DVDDto AGND..............................................-0.3V to +4V
DV
DD
, AVDDto DGND..............................................-0.3V to +4V
DGND to AGND.....................................................-0.3V to +0.3V
INP, INN, REFP, REFN, REFIN,
CML,CLK, CLK, ....................(AGND - 0.3V) to (AV
DD
+ 0.3V)
D0–D11, OE, PD .......................(DGND - 0.3V) to (DV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW
Operating Temperature Ranges
MAX1422CCM ....................................................0°C to +70°C
MAX1422ECM .................................................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DC ACCURACY
Resolution RES 12 bits
Differential Nonlinearity DNL
Integral Nonlinearity INL TA = T
Mid-scale Offset MSO -3 ±.75 3 %FSR
Mid-scale Offset Temperature
Coefficient
Gain Error GE
Gain Error Temperature
Coefficient
DYNAMIC PERFORMANCE (f
Signal-to-Noise Ratio SNR fIN = 5MHz, TA = +25°C6367dB
Spurious-Free Dynamic Range SFDR fIN = 5MHz, TA = +25°C 64 74 dBc
Total Harmonic Distortion THD fIN = 5MHz, TA = +25°C -72 -63 dBc
Signal-to-Noise and Distortion SINAD fIN = 5MHz, TA = +25°C6065dB
Effective Number of Bits ENOB
Two-Tone Intermodulation
Distortion
Differential Gain DG ±1%
Differential Phase DP ±0.25
ANALOG INPUTS (INP, INN, CML)
Input Resistance R
Input Capacitance C
Common-Mode Input Level
(Note 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MSOTC 3
GETC
= 20MHz, 4096-point FFT)
CLK
IMD f
IN
IN
V
CML
TA = +25°C, no missing codes -1 1
= T
T
A
Internal reference (Note 1) -5 ±0.1 5
External reference applied to REFIN, (Note 2) -5 ±0.2 5
External reference applied to REFP, CML,
and REFN (Note 3)
External reference applied to REFP, CML,
and REFN (Note 3)
f
IN
IN1
Either input to ground 61 kΩ
Either input to ground 4 pF
to T
MIN
to T
MIN
= 5MHz
= 7.028MHz, f
MAX
MAX
-1.5 1.5
= 8.093MHz (Note 4) -77 dBc
IN2
±0.5
±2 LSB
- 4
✕
10
- 6
✕
10
15
10.5 Bits
✕
V
AV DD
0.5
LSB
%/°C
%FSR
%/°C
degrees
V
MAX1422
12-Bit, 20Msps, +3.3V, Low-Power ADC with
Internal Reference
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
DVDD
= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dB FS, +2.048V internal reference, f
CLK
=
20MHz (50% duty cycle), digital output load C
L
≈ 10pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Common-Mode Input Voltage
Range (Note 5)
Differential Input Range V
Small-Signal Bandwidth BW
Large-Signal Bandwidth FPBW
Overvoltage Recovery OVR 1.5 ✕ FS input 1
INTERNAL REFERENCE (REFIN bypassed with 0.22µF in parallel with 1nF)
Common-Mode Reference
Voltage
Positive Reference Voltage V
Negative Reference Voltage V
Differential Reference Voltage V
Differential Reference
Temperature Coefficient
EXTERNAL REFERENCE (V
REFIN Input Resistance R
REFIN Input Capacitance C
REFIN Reference Input Voltage
Range
Differential Reference Voltage
Range
EXTERNAL REFERENCE (V
REFP, REFN, CML Input Current I
REFP, REFN, CML Input
Capacitance
Differential Reference Voltage
Range
CML Input Voltage Range V
REFP Input Voltage Range V
REFN Input Voltage Range V
DIGITAL INPUTS (CLK, CLK, PD, OE)
Input Logic High V
Input Logic Low V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
CMVR
V
- V
(Note 6) ±V
INN
= V
REFP
- V
REFN
AVDD
V
CML
REFP
REFN
DIFF
IN
-3dB
-3dB
INP
(Note 7) 400 MHz
(Note 7) 150 MHz
At CML V
At REFP
At REFN
V
DIFF
REFTC ±100 ppm/°C
= +2.048V)
REFIN
IN
IN
V
REFIN
V
DIFF
= AGND, reference voltage applied to REFP, REFN, and CML)
REFIN
IN
C
IN
V
DIFF
CML
REFP
REFN
IH
(Note 8) 5 kΩ
✕
V
DIFF
= (V
REFP
- V
REFN
)
0.95
V
REFIN
/2
-200 200 µA
V
= V
DIFF
IL
REFP
- V
REFN
0.7
V
DVDD
✕
V
CML
±5%
DIFF
✕ 0.5 V
V
CML
+ 0.512
V
CML
- 0.512
1.024
±5%
10 pF
2.048
±10%
✕
V
REFIN
1.05
/2
V
/2
REFIN
15 pF
1.024
±10%
1.65
±10%
V
+
CML
V
/2
DIFF
V
-
CML
/2
V
DIFF
✕
0.3
V
DVD
V
V
Clock
Cycle
V
V
V
V
V
V
V
V
V
V
V
MAX1422
12-Bit, 20Msps, +3.3V, Low-Power ADC with
Internal Reference
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
DVDD
= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dB FS, +2.048V internal reference, f
CLK
=
20MHz (50% duty cycle), digital output load C
L
≈ 10pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Note 1: Internal reference, REFIN bypassed to AGND with a combination of 0.22µF in parallel with 1nF capacitor.
Note 2: External +2.048V reference applied to REFIN.
Note 3: Internal reference disabled. V
REFIN
= 0, V
REFP
= +2.162V, V
CML
= +1.65V, and V
REFN
= +1.138V.
Note 4: IMD is measured with respect to either of the fundamental tones.
Note 5: Specifies the common-mode range of the differential input signal supplied to the MAX1422.
Note 6: V
DIFF
= V
REFP
- V
REFN.
Note 7: Input bandwidth is measured at a 3dB level.
Note 8: V
REFIN
is internally biased to +2.048V through a 10kΩ resistor.
Note 9: Measured as the ratio of the change in mid-scale offset voltage for a ±5% change in V
AVDD
, using the internal reference.
Input Current
Input Capacitance 10 pF
DIGITAL OUTPUTS (D0–D11)
Output Logic High V
Output Logic Low V
Three-State Leakage -10 10 µA
Three-State Capacitance 2pF
POWER REQUIREMENTS
Analog Supply Voltage V
Digital Supply Voltage V
Analog Supply Current I
Analog Supply Current with
Internal Reference in Shutdown
Analog Shutdown Current PD = DV
Digital Supply Current I
Digital Shutdown Current PD = DV
Power Dissipation P
Power-Supply Rejection Ratio PSRR (Note 9) ±1 mV/V
TIMING CHARACTERISTICS
Clock Frequency f
Clock High t
Clock Low t
Pipeline Delay (Latency) Figure 5 7
Aperture Delay t
Aperture Jitter t
Data Output Delay t
Bus Enable Time t
Bus Disable Time t
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OH
OL
AVDD
DVDD
AVDD
DVDD
DISS
CLK
CH
CL
AD
AJ
OD
BE
BD
CLK, CLK ±330
PD -20 20
OE -20 20
IOH = 200µA
IOL = -200µA00.5V
REFIN
Analog power dissipation 137 152 mW
Figure 5 0.1 20 MHz
Figure 5, clock period 50ns 25 ns
Figure 5, clock period 50ns 25 ns
Figure 9 2 ns
Figure 9 2 ps
Figure 5 5 10 14 ns
Figure 4 5 ns
Figure 4 5 ns
= AGND 37 44 mA
DD
DD
V
D V DD
- 0.5
3.138 3.3 3.465 V
2.7 3.3 3.63 V
V
DVDD
39 46 mA
20 µA
3mA
20 µA
µA
V
f
CLK
Cycles
MAX1422
12-Bit, 20Msps, +3.3V, Low-Power ADC with
Internal Reference
_______________________________________________________________________________________ 5
Typical Operating Characteristics
(V
AVDD
= V
DVDD
= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage, f
CLK
= 20MHz (50% duty cycle) digital out-
put load C
L
= 10pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25 °C.)
FFT PLOT, 4096-POINT RECORD
DIFFERENTIAL INPUT
0
fIN = 5.2234999MHz
= -0.53dB FS
A
IN
-20
-40
-60
AMPLITUDE (dB)
-80
-100
-120
HD3
04312 5678910
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD PLOT, 4096-POINT RECORD
DIFFERENTIAL INPUT
0
f
= 7.0283622MHz
IN1
= 8.0931176MHz
f
IN2
-20
= 20.0056789MHz
f
CLK
TWO-TONE-ENVELOPE = -0.53dBFS
= A
= -6.5dB FS
A
IN1
IMD2
IN2
f
IMD3
-40
-60
AMPLITUDE (dB)
-80
-100
FFT PLOT, 4096-POINT RECORD
DIFFERENTIAL INPUT
0
fIN = 8.1636865MHz
= -0.54dB FS
A
IN
-20
MAX1422 toc01
-40
HD2
-60
AMPLITUDE (dB)
-80
-100
-120
04312 5678910
HD2
ANALOG INPUT FREQUENCY (MHz)
HD3
SPURIOUS-FREE DYNAMIC RANGE vs.
ANALOG INPUT FREQUENCY
85
MAX1422 toc04
f
IN2
IN1
77
69
SFDR (dBc)
61
53
MAX1422 toc02
MAX1422 toc05
FFT PLOT, 4096-POINT RECORD
DIFFERENTIAL INPUT
0
fIN = 19.8051329MHz
= -0.52dB FS
A
IN
-20
-40
HD2
-60
HD3
AMPLITUDE (dB)
-80
-100
-120
04312 5678910
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE RATIO vs.
ANALOG INPUT FREQUENCY
70
66
62
SNR (dB)
58
54
MAX1422 toc03
MAX1422 toc06
-120
04312 5678910
ANALOG INPUT FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION vs.
ANALOG INPUT FREQUENCY
-50
-56
-62
THD (dBc)
-68
-74
-80
110100
ANALOG INPUT FREQUENCY (MHz)
MAX1422 toc07
45
110100
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
70
66
62
SINAD (dB)
58
54
50
110100
ANALOG INPUT FREQUENCY (MHz)
MAX1422 toc08
50
1 10 100
ANALOG INPUT FREQUENCY (MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. INPUT POWER (f
80
70
60
50
40
SFDR (dBc)
30
20
10
0
-60 -40 -30-50 -20 -10 0
INPUT POWER (dB FS)
= 5MHz)
IN
MAX1422 toc09
MAX1422
12-Bit, 20Msps, +3.3V, Low-Power ADC with
Internal Reference
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(V
AVDD
= V
DVDD
= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage, f
CLK
= 20MHz (50% duty cycle) digital out-
put load C
L
= 10pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25 °C.)
100
80
60
SNR (dB)
40
20
0
-60 -40-50 -30 -20 -10 0
SIGNAL-TO-NOISE RATIO
vs. INPUT POWER (f
INPUT POWER (dB FS)
IN
= 5MHz)
TOTAL HARMONIC DISTORTION
MAX1422 toc10
vs. INPUT POWER (f
-10
-20
-30
-40
THD (dBc)
-50
-60
-70
-80
-60 -40-50 -30 -20 -10 0
INPUT POWER (dB FS)
IN
= 5MHz)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. INPUT POWER (f
80
70
MAX1422 toc11
60
50
40
SINAD (dB)
30
20
10
0
-60 -40-50 -30 -20 -10 0
INPUT POWER (dB FS)
= 5MHz)
IN
MAX1422 toc12
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE
84
fIN = 5.52235MHz
80
76
SFDR (dBc)
72
68
64
-40 10-15 35 60 85
TEMPERATURE (°C)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. TEMPERATURE
70
fIN = 5.52235MHz
68
66
SINAD (dB)
64
62
MAX1422 toc13
MAX1422 toc16
SIGNAL-TO-NOISE RATIO
vs. TEMPERATURE
70
fIN = 5.52235MHz
68
66
SNR (dB)
64
62
60
-40 10-15 35 60 85
TEMPERATURE (°C)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
2
1
0
INL (LSB)
-1
MAX1422 toc14
MAX1422 toc17
TOTAL HARMONIC DISTORTION
vs. TEMPERATURE
-67
fIN = 5.52235MHz
-69
-71
THD (dB)
-73
-75
-77
-40 10-15 35 60 85
TEMPERATURE (°C)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.50
0.25
0
DNL (LSB)
-0.25
MAX1422 toc15
MAX1422 toc18
60
-40 10-15 35 60 85
TEMPERATURE (°C)
-2
0 20481024 3072 4096
DIGITAL OUTPUT CODE
-0.50
0 20481024 3072 4096
DIGITAL OUTPUT CODE
MAX1422
12-Bit, 20Msps, +3.3V, Low-Power ADC with
Internal Reference
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(V
AVDD
= V
DVDD
= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage, f
CLK
= 20MHz (50% duty cycle) digital
output load C
L
= 10pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25 °C.)
GAIN ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE (V
0.5
0.2
-0.1
-0.4
GAIN ERROR (%FSR)
-0.7
-1.0
-40 10-15 35 60 85
TEMPERATURE (°C)
SFDR, SNR, THD, SINAD
vs. CLOCK FREQUENCY
90
fIN = 5MHz
80
70
60
SFDR, SNR, THD, SINAD (dB)
REFIN
SNR
SINAD
= +2.048V)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
MAX1422 toc20
(mA)
DVDD
I
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
2.05
2.04
2.03
(V)
REF
V
2.02
2.01
SFDR
THD
50
MAX1422 toc19
46
42
(mA)
AVDD
I
38
34
30
-40 10-15 356085
MAX1422 toc22
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
6
CL = 10pF
5
4
3
2
1
0
-40 10-15 35 60 85
TEMPERATURE (°C)
MAX1422 toc23
MAX1422 toc21
50
08412
CLOCK FREQUENCY (MHz)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.10
2.08
2.06
(V)
REF
V
2.04
2.02
2.00
-40 10-15 35 60 85
TEMPERATURE (°C)
16 20
MAX1422 toc24
2.00
3.1 3.33.2 3.4
VDD (V)
OUTPUT NOISE HISTOGRAM (DC-INPUT)
30,000
25,000
20,000
15,000
COUNTS
10,000
5000
310
22
0
N-3
N-4
27360
16623
15029
3431
N-2
N+1
N
N-1
DIGITAL OUTPUT NOISE
2596
N+2
162
N+3
2
N+4
3.5
MAX1422 toc25
1
N+5
MAX1422
Detailed Description
The MAX1422 uses a 12-stage, fully-differential,
pipelined architecture (Figure 1), that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage
every half-clock cycle. Including the delay through the
output latch, the latency is seven clock cycles.
A 2-bit (2-comparator) flash ADC converts the heldinput voltage into a digital code. The following digital-
to-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held-input signal. The resulting error
signal is then multiplied by two and the product is
passed along to the next pipeline stage. This process
is repeated until the signal has been processed by all
12 stages. Each stage provides a 1-bit resolution.
Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no
missing codes.
12-Bit, 20Msps, +3.3V, Low-Power ADC with
Internal Reference
8 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1, 4, 5, 8, 9,
12, 13, 16,
19, 41, 48
AGND Analog Ground. Connect all return paths for analog signals to AGND.
2, 3, 10, 11,
14, 15, 20,
42, 47
AV
DD
6 INP Positive Analog Signal Input
7 INN Negative Analog Signal Input
17 CLK Clock Frequency Input. Clock frequency input ranges from 100kHz to 20MHz.
18 CLK
21, 31, 32 DV
DD
22, 29, 30 DGND Digital Ground
23–28 D0–D5 Digital Data Outputs. Data bits D0 through D5, where D0 represents the LSB.
33–38 D6–D11 Digital Data Outputs. D6 through D11, where D11 represents the MSB.
39 OE
40 PD Shutdown Input. A logic "1" on PD places the ADC into shutdown mode.
43 REFIN
44 REFP
45 REFN
Analog Supply Voltage. For optimum performance, bypass to the closest AGND with a parallel
combination of a 0.1µF, and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination
between AV
and AGND.
DD
Complementary Clock Frequency Input. This input is used for differential clock input. If the ADC is
driven with a single-ended clock, bypass CLK with 0.1µF capacitor to AGND.
Digital Supply Voltage. For optimum performance, bypass to the closest DGND with a parallel
combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination
between DV
and DGND.
DD
Output Enable Input. A logic "1" on OE places the outputs D0–D11 into a high-impedance state. A
logic "0" allows for the data bits to be read from the outputs.
External Reference Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel with
1nF. REFIN can be biased externally to adjust reference levels and calibrate full-scale errors. To
disable the internal reference, connect REFIN to AGND.
Positive Reference I/O. Bypass to AGND with a capacitor combination of 0.22µF in parallel with 1nF.
With the internal reference disabled (REFIN = AGND), REFP should be biased toV
CML
+ V
DIFF
/2.
Negative Reference I/O. Bypass to AGND with a capacitor combination of 0.22µF in parallel with
1nF. With the internal reference disabled (REFIN = AGND), REFN should be biased to
V
- V
DIFF
/2.
CML
46 CML
Common-Mode Level Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel with
1nF. With the internal reference disabled (REFIN = AGND).
Input Track-and-Hold
Transconductance Circuit
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuit in both track-and-hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuit
samples the input signal onto the two capacitors (C2a
and C2b) through-switches (S4a and S4b). Switches S2a
and S2b set the common mode for the transconductance amplifier (OTA) input and open simultaneously
with S1, sampling the input waveform. The resulting
differential voltage is held on capacitors C2a and C2b.
Switches S4a and S4b, are then opened before switches
S3a and S3b connect capacitors C1a and C1b to the
output of the amplifier, and switch S4c is closed. The
OTA is used to charge capacitors, C1a and C1b, to the
same values originally held on C2a and C2b. This value
is then presented to the first stage quantizer and isolates
the pipeline from the fast-changing input. The wide input
bandwidth, T/H amplifier allows the MAX1422 to track
and sample/hold analog inputs of high frequencies
beyond Nyquist. The analog inputs INP and INN can be
driven either differentially or single-ended. Match the
impedance of INP and INN and set the common-mode
voltage to midsupply (AVDD/2) for optimum performance.
Analog Input and Reference Configuration
The full-scale range of the MAX1422 is determined by the
internally generated voltage difference between REFP
(AVDD/2 + V
REFIN
/4) and REFN (AVDD/2 - V
REFIN
/4). The
MAX1422’s full-scale range is adjustable through REFIN,
which provides a high input impedance for this purpose.
REFP, CML (AVDD/2), and REFN are internally buffered,
low impedance outputs.
The MAX1422 provides three modes of reference operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, the on-chip +2.048V
bandgap reference is active and REFIN, REFP, CML,
and REFN, left floating. For stability purposes bypass
REFIN, REFP, REFN, and CML with a capacitor network
of 0.22µF, in parallel with a 1nF capacitor to AGND.
In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a
stable and accurate voltage at REFIN.
In unbuffered external reference mode, REFIN is connected to AGND, which deactivates the on-chip buffers
of REFP, CML, and REFN. With their buffers shut down,
MAX1422
12-Bit, 20Msps, +3.3V, Low-Power ADC with
Internal Reference
_______________________________________________________________________________________ 9
Figure 1. Pipelined Architecture
Figure 2. Internal T/H Circuit
MDAC
V
IN
V
IN
T/H
FLASH
ADC
DAC
2 BITS
STAGE 1 STAGE 2
DIGITAL CORRECTION LOGIC
Σ
D11–D0
INTERNAL
V
OUT
x2
TO NEXT
STAGE
S4a
IN+
S4c
STAGE 12
12
IN-
S4b
BIAS
S2a
C2a
S1
C2b
INTERNAL
BIAS
C1a
OTA
C1b
CML
S5a
S3a
OUT
OUT
S3b
S5bS2b
CML
MAX1422
these nodes become high impedance and can be driven
by external reference sources, as shown in Figure 3.
Clock Inputs (CLK,
CLK
)
The MAX1422’s CLK and CLK inputs accept both single-ended and differential input operation, and accept
CMOS-compatible clock signals. If CLK is driven with a
single-ended clock signal, bypass CLK with a 0.1µF
capacitor to AGND. Since the interstage conversion of
the device depends on the repeatability of the rising
and falling edges of the external clock, use a clock with
low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to have the lowest possible
jitter. Any significant aperture jitter would limit the SNR
performance of the ADC according to the following
relationship:
where fINrepresents the analog input frequency, and
tAJis the aperture jitter.
Clock jitter is especially critical for high input frequency
applications. The clock input should always be consid-
ered as an analog input and routed away from any analog or digital signal lines.
The MAX1422 clock input operates with a voltage
threshold set to AVDD/2. Clock inputs must meet the
specifications for high and low periods, as stated in the
Electrical Characteristics.
Figure 4 shows a simplified model of the clock input circuit. This circuit consists of two 10kΩ resistors to bias
the common-mode level of each input. This circuit may
be used to AC-couple the system clock signal to the
MAX1422 clock input.
Output Enable (OE), Power-Down (PD) and
Output Data (D0–D11)
With OE high, the digital outputs enter a high-impedance state. If OE is held low with PD high, the outputs
are latched at the last value prior to the power-down.
All data outputs, D0 (LSB) through D11 (MSB), are
TTL/CMOS logic compatible. There is a seven clockcycle latency between any particular sample and its
valid output data. The output coding is in offset binary
format (Table 1).
The capacitive load on the digital outputs D0 through
D11 should be kept as low as possible (≤10pF) to avoid
large digital currents that could feed back into the ana-
12-Bit, 20Msps, +3.3V, Low-Power ADC with
Internal Reference
10 ______________________________________________________________________________________
Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled
AV
DD
R
R
50Ω
AV
DD
2
MAX4284
R
AV
DD
4
R
MAX4284
0.22µF
50Ω
R
AV
DD
2
R
50Ω
R
AV
DD
4
AGND
R
+1V
0.1nF
0.1nF0.22µF
0.1nF0.22µF
CML
REFP
REFN
REFIN
AV
DD
( )
2
AV
DD
+ 1V
( )
2
MAX1422
AV
DD
+ 1V
( )
2
SNR
=×
dB
20
log
10
π
2
1
׃ ×
IN AJ
t
log portion of the MAX1421, thereby degrading its
dynamic performance. The use of digital buffers (e.g.
74LVCH16244) on the digital outputs of the ADCs can
further isolate the digital outputs from heavy capacitive
loads. To further improve the MAX1422 dynamic performance, add small 100Ω series resistors to the digital
output paths, close to the ADC. Figure 5 displays the
timing relationship between output enable and data
output.
System Timing Requirements
Figure 6 depicts the relationship between the clock
input, analog input, and data output. The MAX1422
samples the analog input signal on the rising edge of
CLK (falling edge of CLK). and output data is valid
seven clock cycles (latency) later. Figure 6 also displays the relationship between the input clock parameters and the valid output data.
Applications Information
Figure 7 depicts a typical application circuit containing
a single-ended to differential converter. The internal reference provides an AVDD/2 output voltage for levelshifting purposes. The input is buffered and then split
to a voltage follower and inverter. A lowpass filter at the
input suppresses some of the wideband noise associated with high-speed op amps. Select the R
ISO
and
CINvalues to optimize the filter performance and to suit
a particular application. For the application in Figure 7,
a R
ISO
of 50Ω is placed before the capacitive load to
prevent ringing and oscillation. The 22pF CINcapacitor
acts as a small bypassing capacitor.Connecting C
IN
from INN to INP may further improve dynamic performance.
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution to convert a single-ended signal to a fully differential signal, required by the MAX1422 for optimum
performance. Connecting the center tap of the transformer to CML provides an AVDD/2 DC level shift to the
input. Although a 1:1 transformer is shown, a 1:2 or 1:4
step-up transformer may be selected to reduce the
drive requirements.
In general, the MAX1422 provides better SFDR and
THD with fully differential input signals over singleended input signals, especially for very high input frequencies. In differential input mode, even-order
harmonics are suppressed and each of the inputs
requires only half the signal swing compared to singleended mode.
MAX1422
12-Bit, 20Msps, +3.3V, Low-Power ADC with
Internal Reference
______________________________________________________________________________________ 11
Figure 4. Simplified Clock Input Circuit
Figure 5. Output Enable Timing
Table 1. MAX1422 Output Code For
Differential Inputs
*V
REF
= V
REFP
- V
REFN
INP
INN
CLK
10kΩ
10kΩ
D11–D0
ADC
A
VDD
10kΩ
10kΩ
OUTPUT
DATA D11–D0
OE
t
BE
VALID DATA
HIGH-ZHIGH-Z
t
BD
CLK
AGND
MAX1422
DIFFERENTIAL
INPUT
VOLTAGE*
✕
V
REF
2047/2048
✕
V
REF
2046/2048
V
✕ 1/2048 +1 LSB 1000 0000 0001
REF
0 Bipolar Zero 1000 0000 0000
✕
-V
1/2048 -1 LSB 0111 1111 1111
REF
✕
-V
REF
2046/2048
✕
-V
REF
2047/2048
DIFFERENTIAL
INPUT
+FULL SCALE -
1LSB
+FULL SCALE -
2LSB
-FULL SCALE
+1 LSB
-FULL SCALE 0000 0000 0000
OFFSET BINARY
1111 1111 1111
1111 1111 1110
0000 0000 0001
MAX1422
Single-Ended, AC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended application, using a MAX4108 op amp. This configuration provides high-speed, high-bandwidth, low noise, and low
distortion to maintain the integrity of the input signal.
Grounding, Bypassing and
Board Layout
The MAX1422 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side of
the board as the ADC, using surface-mount devices for
minimum inductance. Bypass REFP, REFN, REFIN, and
CML with a parallel network of 0.22µF capacitors and
1nF to AGND. AV
DD
should be bypassed with a similar
network of a 10µF bipolar capacitor in parallel with two
ceramic capacitors of 1nF and 0.1µF. Follow the same
rules to bypass the digital supply DVDDto DGND.
Multilayer boards with separate ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arrangement
to match the physical location of the analog ground
(AGND) and the digital output driver ground (DGND)
on the ADCs package. The two ground planes should
be joined at a single point such that the noisy digital
ground currents do not interfere with the analog ground
plane. Alternatively, all ground pins could share the
same ground plane if the ground plane is sufficiently
isolated from any noisy, digital systems ground plane
(e.g., downstream output buffer DSP ground plane).
Route high-speed digital signal traces away from sensitive analog traces, and remove digital ground and
power planes from underneath digital outputs. Keep all
signal lines short and free of 90 degree turns.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This
straight-line can be either a best straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1422 are measured using the best straight-line fit method.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step-width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes.
Dynamic Parameter Definitions
Aperture Jitter
Figure 10 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
12-Bit, 20Msps, +3.3V, Low-Power ADC with
Internal Reference
12 ______________________________________________________________________________________
Figure 6. System and Output Timing Diagram
7 CLOCK-CYCLE LATENCY
N
ANALOG INPUT
DATA OUTPUT
CLK
CLK
t
DO
N + 1
N - 7 N - 8
N - 6
N + 2
N - 5
N + 3
t
CH
N - 4
N + 4
N - 3
N + 5
t
CL
N - 2
N + 6 N + 7
N - 1 N
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 10).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical,
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADCs resolution (N-Bits):
SNR
(MAX)
= (6.02 ✕N + 1.76)dB
In reality, there are other noise sources besides quantization noise e.g., thermal noise, reference noise, clock
jitter, etc. SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spec-
tral components minus the fundamental, the first four
harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental
and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADCs error consists of quantization noise only. ENOB is
computed from:
MAX1422
12-Bit, 20Msps, +3.3V, Low-Power ADC with
Internal Reference
______________________________________________________________________________________ 13
Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion
INPUT
MAX4108
300Ω
+5V
-5V
300Ω
0.1µF
0.1µF
300Ω
300Ω
300Ω
300Ω
0.1µF
600Ω
0.1µF
600Ω
+5V
MAX4108
-5V
+5V
MAX4108
-5V
600Ω
0.1µF
0.1µF
0.1µF
0.1µF
300Ω
LOWPASS FILTER
INP
R
ISO
50Ω
LOWPASS FILTER
R
ISO
50Ω
*TWO C
(22pF) CAPS MAY BE REPLACED BY
IN
ONE 44pF CAP, TO IMPROVE PERFORMANCE.
44pF*
C
IN
22pF
1nF0.22µF
C
IN
22pF
*
MAX1422
CML
INN
*
ENOB
SINADdB dB
=
-176
602..
DdB
MAX1422
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious
component, excluding DC offset.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels
are at -6.5dB full scale and their envelope is at -0.5dB
full scale.
12-Bit, 20Msps, +3.3V, Low-Power ADC with
Internal Reference
14 ______________________________________________________________________________________
Figure 9. Single-Ended AC-Coupled Input
Figure 8. Using a Transformer for AC-Coupling
Figure 10. T/H Aperature Timing
Functional Diagram
THD
=×
20
log
VVVV
+++
2232425
10
V
1
2
25Ω
*
22pF
0.1µF
V
IN
N.C.
1
T1
2
MINICIRCUITS
T1–1T–KK81
6
5
0.22µF
43
25Ω
22pF
44pF
1nF
*
INP
*
MAX1422
CML
INN
R
1kΩ
0.22µF
50Ω
ISO
C
22pF
1nF
IN
R
50Ω
C
22pF
ISO
IN
INP
MAX1422
CML
INN
V
IN
MAX4108
0.1µF
100Ω
100Ω
*REPLACE BOTH 22pF CAPS WITH 44pF BETWEEN
INP AND INN TO IMPROVE DYNAMIC PERFORMANCE.
CLK
CLK
ANALOG
INPUT
t
SAMPLED
DATA (T/H)
T/H
AD
TRACK TRACK
t
AJ
HOLD
CLK
CLK
INTERFACE
INP
INN
T/H
BANDGAP
PD
REFERENCE
PIPELINE ADC
REF SYSTEM +
BIAS
REFIN REFP CML REFN OE
MAX1422
OUTPUT
DRIVERS
AV
DD
AGND
D11–D0
DV
DD
DGND
MAX1422
12-Bit, 20Msps, +3.3V, Low-Power ADC with
Internal Reference
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
32L/48L,TQFP.EPS
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