Rainbow Electronics MAX1421 User Manual

Page 1

General Description

The MAX1421 is a +3.3V, 12-bit analog-to-digital converter (ADC), featuring a fully-differential input, pipelined, 12-stage ADC architecture with wideband track-and-hold (T/H) and digital error correction incorporating a fully-differential signal path. The MAX1421 is optimized for low-power, high-dynamic performance applications in imaging and digital communications. The converter operates from a single +3.3V supply, consuming only 188mW while delivering a typical signal-to-noise ratio (SNR) of 66dB at an input frequency of 15MHz and a sampling frequency of 40Msps. The fully-differential input stage has a small signal -3dB bandwidth of 400MHz and may be operated with single-ended inputs.

An internal +2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure accommodates an internal or externally applied buffered or unbuffered reference for applications requiring increased accuracy or a different input voltage range.

In addition to low operating power, the MAX1421 features two power-down modes, a reference power-down and a shutdown mode. In reference power-down, the internal bandgap reference is deactivated, resulting in a typical 2mA supply current reduction. For idle periods, a full shutdown mode is available to maximize power savings.

The MAX1421 provides parallel, offset binary, CMOScompatible three-state outputs.

The MAX1421 is available in a 7mm x 7mm, 48-pin TQFP package, and is specified over the commercial (0°C to +70°C) and the extended industrial (-40°C to +85°C) temperature ranges.

Pin-compatible higher- and lower-speed versions of the MAX1421 are also available. Please refer to the MAX1420 data sheet for a frequency of 60Msps and the MAX1422 data sheet for a frequency of 20Msps.

________________________Applications

Medical Ultrasound Imaging

CCD Pixel Processing

Data Acquisition

Radar

IF and Baseband Digitization

Features

♦ Single +3.3V Power Supply

♦ 67dB SNR at f

= 5MHz

♦ 66dB SNR at f

= 15MHz

♦ Internal, +2.048V Precision Bandgap Reference

♦ Differential, Wideband Input T/H Amplifier

♦ Power-Down Modes

180mW (Reference Shutdown Mode) 10µW (Shutdown Mode)

♦ Space-Saving 48-Pin TQFP Package

MAX1421

12-Bit, 40Msps, +3.3V, Low-Power ADC

with Internal Reference

________________________________________________________________ Maxim Integrated Products 1

Pin Configuration

19-1900; Rev 0; 5/01

Ordering Information

48 TQFP

PIN-PACKAGETEMP. RANGE

0°C to +70°CMAX1421CCM

PART

Functional Diagram appears at end of data sheet.

48 TQFP-40°C to +85°CMAX1421ECM

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

AGND

AVDDCML

REFN

REFP

REFIN

AGND

AV AGND AGND

INP

INN AGND AGND

AV AV

AGND

AVDDAGNDPDOE

4847464544434241403938

1314151617181920212223

DDAVDD

AGND

MAX1421

CLK

AGND

48-TQFP

CLK

AGND

DDDVDD

DGND

D11

D10

D9 D8

DGND

Page 2

MAX1421

12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

AVDD

= V

DVDD

= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dB FS, internal reference,

CLK

= 40MHz (50% duty cycle), digital output load CL≈ 10pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AVDD, DVDDto AGND..............................................-0.3V to +4V

, AVDDto DGND..............................................-0.3V to +4V

DGND to AGND.....................................................-0.3V to +0.3V

INP, INN, REFP, REFN, REFIN,

CML, CLK, CLK,....................(AGND - 0.3V) to (AV

+ 0.3V)

D0–D11, OE, PD .......................(DGND - 0.3V) to (DV

+ 0.3V)

Continuous Power Dissipation (T

= +70°C)

48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW

Maximum Junction Temperature .....................................+150°C

Operating Temperature Ranges

MAX1421CCM ...................................................0°C to +70°C

MAX1421ECM ................................................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

DC ACCURACY

Resolution RES 12 Bits

Differential Nonlinearity DNL

Integral Nonlinearity INL TA = T

Mid-scale Offset MSO -3 ±.75 3 %FSR

Mid-scale Offset Temperature Coefficient

Gain Error GE

Gain Error Temperature Coefficient

DYNAMIC PERFORMANCE (f

Signal-to-Noise Ratio SNR

Spurious-Free Dynamic Range SFDR

Total Harmonic Distortion THD

Signal-To-Noise Plus Distortion SINAD

Effective Number of Bits ENOB

Two-Tone Intermodulation Distortion

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

TA = +25°C, no missing codes -1 1

= T

MSOTC 3

Internal reference (Note 1) -5 0.1 5

External reference applied to REFIN (Note 2) -5 ±3 5

External reference applied to REFP, CML, and REFN (Note 3)

GETC

= 40MHz, 4096-point FFT)

CLK

IMD

External reference applied to REFP, CML, and REFN, (Note 3)

fIN = 5MHz 67

fIN = 5MHz 73

fIN = 5MHz -74

fIN = 5MHz 66

fIN = 5MHz 10.7

IN1

(Note 4)

to T

MIN

MAX

to T

MIN

MAX

= 15MHz, TA = +25°C6266

= 15MHz, TA = +25°C6470

= 15MHz, TA = +25°C -69 -62

= 15MHz, TA = +25°C 60 63.5

= 15MHz, TA = +25°C 60 10.3

= 11.569MHz, f

= 13.445MHz

IN2

±0.5

±2 LSB

-4

-1.5 ±0.5 1.5

-6

-80 dBc

LSB

%/°C

%FSR

%/°C

dBc

Bits

Page 3

MAX1421

12-Bit, 40Msps, +3.3V, Low-Power ADC

with Internal Reference

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

AVDD

= V

DVDD

= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dB FS, internal reference,

CLK

= 40MHz (50% duty cycle), digital output load CL≈ 10pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Differential Gain DG ±1% Differential Phase DP ±0.25 degrees

ANALOG INPUTS (INP, INN, CML)

Input Resistance R

Input Capacitance C

Common-Mode Input Level, (Note 5)

Common-Mode Input Voltage Range, (Note 5)

CMVR

CML

Differential Input Range V

Small-Signal Bandwidth BW

Large-Signal Bandwidth FPBW

Over-Voltage Recovery OVR 1.5 ✕ FS input 1

Either input to ground 32.5 kΩ

Either input to ground 4 pF

AVDD

× 0.5

CML

±5%

- V

-3dB

INP

(Note 7) 400 MHz

(Note 7) 150 MHz

-3dB

(Note 6) ±V

INN

DIFF

Clock Cycle

INTERNAL REFERENCE (REFIN bypassed with 0.22µF in parallel with 1nF)

Common-Mode Reference Input Voltage

CML

At CML

AVDD

0.5

Positive Reference Voltage Range

Negative Reference Voltage Range

Differential Reference Voltage Range

Differential Reference Temperature Coefficient

REFTC ±100 ppm/°C

EXTER N AL R EF ER EN C E

REFIN Input Resistance R

REFIN Input Capacitance C

REFIN Reference Input Voltage V

Differential Reference Voltage V

EXTERNAL REFERENCE (V

= AGND, reference voltage applied to REFP, REFN and CML)

REFIN

REFP, REFN, CML Input Current I

REFP, REFN, CML Input Capacitance

REFP

REFN

DIFF

REFIN

DIFF

At REFP

At REFN

= V

DIFF

REFP

- V

REFN

CML

+ 0.512

CML

- 0.512

1.024

±5%

(Note 8) 5 kΩ

10 pF

2.048 ±10%

DIFF

= (V

REFP

- V

REFN

)

0.95

REFIN/2

1.05

REFIN/2

-200 200 µA

15 pF

Page 4

MAX1421

12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

AVDD

= V

DVDD

= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dB FS, internal reference,

CLK

= 40MHz (50% duty cycle), digital output load CL≈ 10pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Differential Reference Voltage Range

CML Input Voltage Range V

REFP Input Voltage Range V

REFN Input Voltage Range V

DIFF

CML

REFP

REFN

DIFF

= V

REFP

- V

REFN

1.024 ±10%

1.65

±10%

CML

DIFF

CML

DIFF

+ /2

DIGITAL INPUTS (CLK, CLK, OE, PD)

Input Logic High V

Input Logic Low V

0.7

DVDD

0.3

DVDD

CLK, CLK ±330

Input Current

PD -20 20

µA

OE -20 20

Input Capacitance 10 pF

DIGITAL OUTPUTS (D0–D11)

Output Logic High V

Output Logic Low V

IOH = 200µA

DVDD

- 0.5

IOL = -200µA 0 0.5 V

DVDD

Three-State Leakage -10 10 µA

Three-State Capacitance 2pF

POWER REQUIREMENTS

Analog Supply Voltage V

Digital Supply Voltage V

Analog Supply Current I

Analog Supply Current with Internal Reference in Shutdown

AVDD

DVDD

AVDD

REFIN = AGND 50 63 mA

Analog Shutdown Current PD = DV

Digital Supply Current I

DVDD

Digital Shutdown Current PD = DV

Power Dissipation P

DISS

Analog power 188 214 mW

3.135 3.3 3.465 V

2.7 3.3 3.6 V

52 65 mA

20 µA

5.5 mA

20 µA

Power-Supply Rejection Ratio PSRR (Note 9) ±1 mV/V

TIMING CHARACTERISTICS

Clock Frequency f

Clock High t

Clock Low t

CLK

Figure 5 0.1 40 MHz

Figure 5, clock period 25ns 12.5 ns

Page 5

MAX1421

12-Bit, 40Msps, +3.3V, Low-Power ADC

with Internal Reference

_______________________________________________________________________________________ 5

Note 1: Internal reference, REFIN bypassed to AGND with a combination of 0.22µF in parallel with 1nF capacitor. Note 2: External +2.048V reference applied to REFIN. Note 3: Internal reference disabled. V

REFIN

= 0, V

REFP

= +2.162V, V

CML

= +1.65V, and V

REFN

= +1.138V.

Note 4: IMD is measured with respect to either of the fundamental tones. Note 5: Specifies the common-mode range of the differential input signal supplied to the MAX1421. Note 6: V

DIFF

= V

REFP

- V

REFN

Note 7: Input bandwidth is measured at a 3dB level. Note 8: V

REFIN

is internally biased to +2.048V through a 10kΩ resistor.

Note 9: Measured as the ratio of the change in mid-scale offset voltage for a ± 5% change in V

AVDD

using the internal reference.

ELECTRICAL CHARACTERISTICS (continued)

AVDD

= V

DVDD

= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dB FS, internal reference,

CLK

= 40MHz (50% duty cycle), digital output load CL≈ 10pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

= +25°C.)

Typical Operating Characteristics

AVDD

= V

DVDD

= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage, f

CLK

= 40MHz (50% duty cycle), digital output

load CL= 10pF, TA= T

MIN

to T

MAX,

unless otherwise noted. Typical values are at TA= +25°C.)

-120

-80

-100

-40

-60

-20

01051520

FFT PLOT, 4096-POINT RECORD,

DIFFERENTIAL INPUT

MAX1421 toc01

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

fIN = 7.5439934MHz A

= -0.45dB FS

HD3

HD2

-120

-80

-100

-40

-60

-20

01051520

FFT PLOT, 4096-POINT RECORD,

DIFFERENTIAL INPUT

MAX1421 toc02

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

fIN = 19.9047628MHz A

= -0.50dB FS

HD2

HD3

-120

-80

-100

-40

-60

-20

01051520

FFT PLOT, 4096-POINT RECORD,

DIFFERENTIAL INPUT

MAX1421 toc03

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

fIN = 38.5440183MHz A

= -0.49dB FS

HD3

HD2

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Pipeline Delay (Latency) Figure 5 7

Aperture Delay t

Aperture Jitter t

Data Output Delay t

Bus Enable Time t

Bus Disable Time t

Figure 9 2 ns

Figure 9 2 ps

Figure 5 5 10 14 ns

Figure 4 5 ns

CLK

cycles

Page 6

MAX1421

12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference

6 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

AVDD

= V

DVDD

= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage, f

CLK

= 40MHz (50% duty cycle), digital output

load C

= 10pF, TA= T

MIN

to T

MAX,

unless otherwise noted. Typical values are at TA= +25°C.)

-120

-80

-100

-40

-60

-20

024 101214166 8 18 20

TWO-TONE IMD, 8192-POINT RECORD,

DIFFERENTIAL INPUT

MAX1421 toc04

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

IN1

= 11.5104229MHz

IN2

= 13.5126603MHz

TWO-TONE ENVELOPE:

-0.49dB FS A

IN1

= A

IN2

= -6.5dB FS

IMD2

IMD3

IN1

IN2

110100

SIGNAL-TO-NOISE PLUS DISTORTION

vs. ANALOG INPUT FREQUENCY

MAX1421 toc08

ANALOG INPUT FREQUENCY (MHz)

SINAD (dB)

-60 -40 -30-50 -20 -10 0

SPURIOUS-FREE DYNAMIC RANGE

vs. INPUT POWER (f

= 15MHz)

MAX1421 toc09

INPUT POWER (dB FS)

SFDR (dBc)

-80

-70

-50

-60

-40

-30

-60 -40-50 -30 -20 -10 0

TOTAL HARMONIC DISTORTION

vs. INPUT POWER (f

= 15MHz)

MAX1421 toc11

INPUT POWER (dB FS)

THD (dBc)

-20

-60 -40-50 -30 -20 -10 0

SIGNAL-TO-NOISE PLUS DISTORTION

vs. INPUT POWER (f

= 15MHz)

MAX1421 toc12

INPUT POWER (dB FS)

SINAD (dB)

-50

-80 110100

TOTAL HARMONIC DISTORTION vs.

ANALOG INPUT FREQUENCY

-74

MAX1421 toc07

ANALOG INPUT FREQUENCY (MHz)

THD (dBc)

-68

-62

-56

-60 -40-50 -30 -20 -10 0

SIGNAL-TO-NOISE RATIO

vs. INPUT POWER (f

= 15MHZ)

MAX1421 toc10

INPUT POWER (dB FS)

SNR (dB)

1 10 100

SPURIOUS-FREE DYNAMIC RANGE vs.

ANALOG INPUT FREQUENCY

MAX1421 toc05

ANALOG INPUT FREQUENCY (MHz)

SFDR (dBc)

1 10 100

SIGNAL-TO-NOISE RATIO vs.

ANALOG INPUT FREQUENCY

MAX1421 toc06

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

Page 7

MAX1421

12-Bit, 40Msps, +3.3V, Low-Power ADC

with Internal Reference

Typical Operating Characteristics (continued)

AVDD

= V

DVDD

= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage, f

CLK

= 40MHz (50% duty cycle), digital output

load CL= 10pF, TA= T

MIN

to T

MAX,

unless otherwise noted. Typical values are at TA= +25°C.)

-40 10-15 35 60 85

SPURIOUS-FREE DYNAMIC RANGE

vs. TEMPERATURE

MAX1421 toc13

TEMPERATURE (°C)

SFDR (dBc)

fIN = 5.51502MHz

-1

-2 0 20481024 3072 4096

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1421 toc17

DIGITAL OUTPUT CODE

INL (LSB)

0.50

0.25

-0.25

-0.50 0 20481024 3072 4096

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1421 toc18

DIGITAL OUTPUT CODE

DNL (LSB)

-40 10-15 356085

ANALOG SUPPLY CURRENT

vs. TEMPERATURE

MAX1421 toc20

TEMPERATURE (°C)

AVDD

(mA)

-40 10-15 356085

DIGITAL SUPPLY CURRENT

vs. TEMPERATURE

MAX1421 toc21

TEMPERATURE (°C)

AVDD

(mA)

CL ≈ 10pF

-40 10-15 35 60 85

SIGNAL-TO-NOISE PLUS DISTORTION

vs. TEMPERATURE

MAX1421 toc16

TEMPERATURE (°C)

SINAD (dB)

fIN = 5.51502MHz

0.50

0.25

-0.25

-0.50

-40 10-15 35 60 85

GAIN ERROR vs. TEMPERATURE, EXTERNAL

REFERENCE (V

REFIN

= +2.048V)

MAX1421 toc19

TEMPERATURE (°C)

GAIN ERROR (%FSR)

-40 10-15 35 60 85

SIGNAL-TO-NOISE RATIO

vs. TEMPERATURE

TEMPERATURE (°C)

SNR (dB)

fIN = 5.51502MHz

MAX1421 toc14

-80

-78

-74

-76

-72

-70

-40 10-15 35 60 85

TOTAL HARMONIC DISTORTION

vs. TEMPERATURE

MAX1421 toc15

TEMPERATURE (°C)

THD (dB)

fIN = 5.51502MHz

________________________________________________________________________________________ 7

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1421 toc17

INL (LSB)

-1

-2 020481024 3072 4096

DIGITAL OUTPUT CODE

Page 8

MAX1421

12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

AVDD

= V

DVDD

= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage, f

CLK

= 40MHz (50% duty cycle), digital output

load C

= 10pF, TA= T

MIN

to T

MAX,

unless otherwise noted. Typical values are at TA= +25°C.)

10 2618 34

SFDR, SNR, THD, SINAD vs. CLOCK FREQUENCY

MAX1421 toc22

CLOCK FREQUENCY (MHz)

SFDR, SNR, THD, SINAD (dB)

fIN = 5MHz

SINAD

SNR

SFDR

THD

10,000

5000

20,000

15,000

25,000

30,000

N-1

N+2

OUTPUT NOISE HISTOGRAM (DC-INPUT)

MAX1421 toc25

DIGITAL OUTPUT NOISE

COUNTS

N-3

N+1

N+3

43707

10709

116

10824

179

N-2

40,000

35,000

45,000

50,000

2.00

2.02

2.06

2.04

2.08

2.10

-40 10-15 35 60 85

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

MAX1421 toc24

TEMPERATURE (°C)

REF

(V)

2.0750

2.0625

2.0500

2.0375

2.0250

3.1 3.33.2 3.4

INTERNAL REFERENCE VOLTAGE

vs. ANALOG SUPPLY VOLTAGE

MAX1421 toc23

VDD (V)

REF

(V)

3.5

Page 9

MAX1421

12-Bit, 40Msps, +3.3V, Low-Power ADC

with Internal Reference

_______________________________________________________________________________________ 9

Pin Description

PIN NAME FUNCTION

1, 4, 5, 8,

9, 12, 13,

16, 19, 41,

2, 3, 10,

11, 14, 15,

20, 42, 47

AGND Analog Ground. Connect all return paths for analog signals to AGND.

Analog Supply Voltage. For optimum performance bypass to the closest AGND with a parallel

combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination between AV

and AGND.

6 INP Positive Analog Signal Input

7 INN Negative Analog Signal Input

17 CLK Clock Frequency Input. Clock frequency input ranges from 100kHz to 40MHz.

18 CLK

Complementary Clock Frequency Input. This input is used for differential clock inputs. If the ADC is

driven with a single-ended clock, bypass CLK with a 0.1µF capacitor to AGND.

Digital Supply Voltage. For optimum performance bypass, to the closest DGND with a parallel

21, 31, 32, DV

combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination between DV

and DGND.

22, 29, 30 DGND Digital Ground

23–28 D0–D5 Digital Data Outputs. Data bits D0 through D5, where D0 represents the LSB.

33–38 D6–D11 Digital Data Outputs. D6 through D11, where D11 represents the MSB.

39 OE

Output Enable Input. A logic “1” on OE places the outputs D0–D11 into a high-impedance state. A

logic “0” allows for the data bits to be read from the outputs.

40 PD Shutdown Input. A logic “1” on PD places the ADC into shutdown mode.

External Reference Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel with

43 REFIN

1nF. REFIN can be biased externally to adjust reference levels and calibrate full-scale errors. To disable the internal reference, connect REFIN to AGND.

44 REFP

45 REFN

46 CML

P osi ti ve Refer ence I/O . Byp ass to AG N D w i th a cap aci tor com b i nati on of 0.22µF i n p ar al l el w i th 1nF.

W i th the i nter nal r efer ence d i sab l ed ( RE FIN = AG N D ) , RE FP shoul d b e b i ased to V

C M L

+ V

D IF F

/ 2.

N eg ati ve Refer ence I/O . Byp ass to AG N D w i th a cap aci tor com b i nati on of 0.22µF i n p ar al l el w i th 1nF.

W i th the i nter nal r efer ence d i sab l ed ( RE FIN = AG N D ) , RE FN shoul d b e b i ased to V

C M L

- V

D IF F

/ 2.

Common-Mode Level Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel

with 1nF. With the internal reference disabled (REFIN = AGND).

Page 10

MAX1421

12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference

10 ______________________________________________________________________________________

Detailed Description

The MAX1421 uses a 12-stage, fully-differential, pipelined architecture (Figure 1) that allows for high-speed conversion while minimizing power consumption. Each sample moves through a pipeline stage every halfclock-cycle. Including the delay through the output latch, the latency is seven clock cycles.

A 2-bit (2-comparator) flash ADC converts the heldinput voltage into a digital code. The following digital-toanalog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held-input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage. This process is repeated until the signal has been processed by all 12 stages. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes.

Input Track-and-Hold Circuit

Figure 2 displays a simplified functional diagram of the input T/H circuit in both track-and-hold modes. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuit passes the input signal to the two capacitors (C2a and C2b) throughswitches (S4a and S4b). Switches S2a and S2b set the common mode for the transconductance amplifier

(OTA) input, and open simultaneously with S1, sampling the input waveform. The resulting differential voltage is held on capacitors C2a and C2b. Switches S4a and S4b are then opened before switches S3a and S3b, connecting capacitors C1a and C1b to the output of the amplifier, and switch S4c is closed. The OTA is used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. This value is then presented to the first-stage quantizer and isolates the pipeline from the fast-changing input. The wide-input bandwidth, T/H amplifier allows the MAX1421 to track and sample/hold analog inputs of high frequencies beyond Nyquist. The analog inputs INP and INN can be driven either differentially or single-ended. Match the impedance of INP and INN and set the common-mode voltage to midsupply (AV

/ 2) for optimum perfor-

mance.

Analog Input and Reference Configuration

The full-scale range of the MAX1421 is determined by the internally generated voltage difference between REFP (AVDD/ 2 + V

REFIN

/ 4) and REFN (AVDD/ 2 -

REFIN

/ 4). The MAX1421’s full-scale range is adjustable through REFIN, which provides a high input impedance for this purpose. REFP, CML (AVDD/ 2), and REFN are internally buffered low impedance outputs.

Figure 1. Pipelined Architecture

Figure 2. Internal Track-and-Hold Circuit

MDAC

T/H

FLASH

ADC

2 BITS

STAGE 1 STAGE 2

DAC

DIGITAL CORRECTION LOGIC

D11–D0

OUT

TO NEXT

STAGE

S4a

S4c

STAGE 12

S4b

C2a

C2b

INTERNAL

BIAS

S2a

INTERNAL

BIAS

OTA

C1a

C1b

CML

S5a

S3a

OUT

S3b

S5bS2b

CML

Page 11

MAX1421

12-Bit, 40Msps, +3.3V, Low-Power ADC

with Internal Reference

______________________________________________________________________________________ 11

The MAX1421 provides three modes of reference operation:

• Internal reference mode

• Buffered external reference mode

• Unbuffered external reference mode

In internal reference mode, the on-chip +2.048V bandgap reference is active and REFIN, REFP, CML, and REFN are left floating. For stability purposes, bypass REFIN, REFP, REFN, and CML with a capacitor network of 0.22µF, in parallel with a 1nF capacitor to AGND.

In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a stable and accurate voltage at REFIN.

In unbuffered external reference mode, REFIN is connected to AGND, which deactivates the on-chip buffers of REFP, CML, and REFN. With their buffers shut down, these nodes become high impedance and can be driven by external reference sources, as shown in Figure 3.

Clock Inputs (CLK,

CCLLKK

)

The MAX1421’s CLK and CLK inputs accept both single-ended and differential input operation, and accept CMOS-compatible clock signals. If CLK is driven with a

single-ended clock signal, bypass CLK with a 0.1µF capacitor to AGND. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to have the lowest possible jitter. Any significant aperture jitter limits the SNR performance of the ADC according to the following relationship:

where f

represents the analog input frequency and

tAJis the aperture jitter.

Clock jitter is especially critical for high input frequency applications. The clock input should always be considered as an analog input and routed away from any analog or digital signal lines.

The MAX1421 clock input operates with a voltage threshold set to AVDD/ 2. Clock inputs must meet the specifications for high and low periods, as stated in the

Electrical Characteristics.

Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled

50Ω

MAX4284

0.22µF

50Ω

+1V

AGND

1nF

1nF0.22µF

CML

REFP

REFN

REFIN

( )

+ 1V

( )

MAX1421

+ 1V

( )

log

 



NR =×

××

πƒ

IN AJ

 



Page 12

MAX1421

12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference

12 ______________________________________________________________________________________

Figure 4 shows a simplified model of the clock input circuit. This circuit consists of two 10kΩ resistors to bias the common-mode level of each input. This circuit may be used to AC-couple the system clock signal to the MAX1421 clock input.

Output Enable (

OOEE

), Power-Down (PD), and

Output Data (D0–D11)

With OE high, the digital outputs enter a high-impedance state. If OE is held low with PD high, the outputs are latched at the last value prior to the power-down. All data outputs, D0 (LSB) through D11 (MSB), are TTL/CMOS-logic compatible. There is a seven clock-

cycle latency between any particular sample and its valid output data. The output coding is in offset binary format (Table 1).

The capacitive load on the digital outputs D0 through D11 should be kept as low as possible (≤10pF), to avoid large digital currents that could feed back into the analog portion of the MAX1421, thereby degrading its dynamic performance. The use of digital buffers (e.g., 74LVCH16244) on the digital outputs of the ADC can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1421, add small-series resistors of 100Ω to the digital output paths, close to the ADC. Figure 5 displays the timing relationship between output enable and data output.

System Timing Requirements

Figure 6 depicts the relationship between the clock input, analog input, and data output. The MAX1421 samples at the rising edge of CLK (falling edge of CLK) and output data is valid seven clock cycles (latency) later. Figure 6 also displays the relationship between the input clock parameters and the valid output data.

Applications Information

Figure 7 depicts a typical application circuit containing a single-ended to differential converter. The internal reference provides an AVDD/ 2 output voltage for levelshifting purposes. The input is buffered and then split to a voltage follower and inverter. A lowpass filter at the input suppresses some of the wideband noise associated with high-speed op amps. Select the R

ISO

and C

values to optimize the filter performance and to suit a particular application. For the application in Figure 7, a R

ISO

of 50Ω is placed before the capacitive load to pre-

vent ringing and oscillation. The 22pF CINcapacitor acts as a small bypassing capacitor.

Connecting CINfrom INN to INP may further improve dynamic performance.

Figure 4. Simplified Clock Input Circuit

Figure 5. Output Enable Timing

Table 1. MAX1421 Output Code for Differential Inputs

* V

REF

= V

REFP

- V

REFN

INP

INN

VDD

CLK

AGND

ADC

10kΩ

D11–D0

10kΩ

MAX1421

DIFFERENTIAL

INPUT VOLTAGE*

× 2047/2048

REF

× 2046/2048

REF

× 1/2048 + 1 LSB 1000 0000 0001

REF

0 Bipolar Zero 1000 0000 0000

-V

× 1/2048 - 1 LSB 0111 1111 1111

REF

-V

× 2046/2048

REF

-V

× 2047/2048 -FULL SCALE 0000 0000 0000

REF

DIFFERENTIAL

+FULL SCALE -

-FULL SCALE +

INPUT

1LSB

2LSB

1 LSB

OFFSET BINARY

1111 1111 1111

1111 1111 1110

0000 0000 0001

OUTPUT

DATA D11–D0

VALID DATA

HIGH-ZHIGH-Z

Page 13

MAX1421

12-Bit, 40Msps, +3.3V, Low-Power ADC

with Internal Reference

______________________________________________________________________________________ 13

Using Transformer Coupling

An RF transformer (Figure 8) provides an excellent solution to convert a single-ended signal to a fully differential signal, required by the MAX1421 for optimum performance. Connecting the center tap of the transformer to CML provides an AVDD/ 2 DC level shift to the input. Although a 1:1 transformer is shown, a 1:2 or 1:4 step-up transformer may be selected to reduce the drive requirements.

In general, the MAX1421 provides better SFDR and THD with fully differential input signals over singleended input signals, especially for very high input frequencies. In differential input mode, even-order harmonics are suppressed and each of the inputs requires only half the signal swing compared to singleended mode.

Single-Ended AC-Coupled Input Signal

Figure 9 shows an AC-coupled, single-ended application, using a MAX4108 op amp. This configuration provides high-speed, high-bandwidth, low noise, and low distortion to maintain the integrity of the input signal.

Grounding, Bypassing, and

Board Layout

The MAX1421 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the ADC, using surface-mount devices for minimum inductance. Bypass REFP, REFN, REFIN, and CML with a parallel network of 0.22µF capacitors and 1nF to AGND. AVDDshould be bypassed with a similar

network of a 10µF bipolar capacitor in parallel with two ceramic capacitors of 1nF and 0.1µF. Follow the same rules to bypass the digital supply DV

to DGND. Multilayer boards with separate ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arrangement to match the physical location of the analog ground (AGND) and the digital output driver ground (DGND) on the ADCs package. The two ground planes should be joined at a single point so that the noisy digital ground currents do not interfere with the analog ground plane. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer, DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces and remove digital ground and power planes from underneath digital outputs. Keep all signal lines short and free of 90 degree turns.

Static Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straightline can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1421 are measured using the best straight-line fit method.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an actual step-width and the ideal value of 1LSB. A DNL

Figure 6. System and Output Timing Diagram

7 CLOCK-CYCLE LATENCY

ANALOG INPUT

CLK

DATA OUTPUT

N + 1

N - 7

N - 6

N + 2

N - 5

N + 3

N - 4

N + 4

N - 3

N + 5

N - 2

N + 6

N - 1 N

Page 14

MAX1421

error specification of less than 1LSB guarantees no missing codes.

Dynamic Parameter Definitions

Aperture Jitter

Figure 10 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.

Aperture Delay

Aperture delay (t

) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 10).

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of

the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADCs resolution (N-bits):

SNR

(MAX)

= (6.02 ✕N + 1.76)dB

In reality, there are other noise sources besides quantization noise e.g., thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset.

12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference

14 ______________________________________________________________________________________

Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion

+5V

INPUT

MAX4108

-5V

300Ω

0.1µF

300Ω

600Ω

0.1µF

MAX4108

-5V

+5V

MAX4108

-5V

600Ω

0.1µF

300Ω

LOWPASS FILTER

ISO

50Ω

0.1µF

LOWPASS FILTER

ISO

50Ω

*TWO C

(22pF) CAPS MAY BE REPLACED BY

ONE 44pF CAP, TO IMPROVE PERFORMANCE.

44pF*

22pF

1nF0.22µF

22pF

INP

MAX1421

CML

INN

Page 15

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset.

Effective Number of Bits (ENOB)

ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB is computed from:

MAX1421

12-Bit, 40Msps, +3.3V, Low-Power ADC

with Internal Reference

______________________________________________________________________________________ 15

Figure 8. Using a Transformer for AC-Coupling

Figure 9. Single-Ended AC-Coupled Input Signal

Figure 10. Track-and-Hold Aperture Timing

0.1µF

N.C.

MAX4108

100Ω

25Ω

22pF

ISO

1nF

44pF

22pF

1nF

ISO

50Ω

22pF

0.22µF

MINICIRCUITS

T1–1T–KK81

*REPLACE BOTH 22pF CAPS WITH 44pF BETWEEN INP AND INN TO IMPROVE DYNAMIC PERFORMANCE.

0.1µF

25Ω

1kΩ100Ω

0.22µF

50Ω

INP

MAX1421

CML

INN

INP

MAX1421

CML

INN

CLK

ANALOG

INPUT

SAMPLED

DATA (T/H)

T/H

TRACK TRACK

HOLD

ENOB

SINADdB dB

602..

176

Page 16

MAX1421

Total Harmonic Distortion (THD)

THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as:

where V

is the fundamental amplitude, and V2through V5are the amplitudes of the 2nd- through 5th-order harmonics.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset.

Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale and their envelope is at -0.5dB full scale.

12-Bit, 40Msps, +3.3V, Low-Power ADC with Internal Reference

16 ______________________________________________________________________________________

Functional Diagram



   

THD

=×

log



VVVV

+++

2232425

()

 





CLK

INP

INN

MAX1421

INTERFACE

T/H

BANDGAP

REFERENCE

PIPELINE ADC

REF SYSTEM +

BIAS

REFIN REFP CML REFN OE

OUTPUT DRIVERS

AGND

D11–D0

DGND

Page 17

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

17 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Package Information

12-Bit, 40Msps, +3.3V, Low-Power ADC

with Internal Reference

MAX1421

32L/48L,TQFP.EPS