Rainbow Electronics MAX1420 User Manual

Page 1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

General Description

The MAX1420, +3.3V, 12-bit analog-to-digital converter (ADC) features a fully-differential input, pipelined, 12stage ADC architecture with wideband track-and-hold (T/H) and digital error correction, incorporating a fullydifferential signal path. The MAX1420 is optimized for low-power, high dynamic performance applications in imaging and digital communications. The converter operates from a single +3.3V supply, and consumes only 221mW. The fully-differential input stage has a small signal -3dB bandwidth of 400MHz and may be operated with single-ended inputs.

An internal +2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure accommodates an internal reference, or externally applied buffered or unbuffered reference for applications that require increased accuracy and a different input voltage range.

In addition to low operating power, the MAX1420 features two power-down modes: reference power-down and shutdown mode. In reference power-down, the internal bandgap reference is deactivated, which results in a typical 2mA supply current reduction. A full shutdown mode is available to maximize power savings during idle periods.

The MAX1420 provides parallel, offset binary, CMOScompatible three-state outputs.

The MAX1420 is available in a 7mm ✕7mm, 48-pin TQFP package, and is specified over the commercial (0°C to +70°C) and the extended industrial (-40°C to +85°C) temperature range.

Pin-compatible lower speed versions of the MAX1420 are also available. Please refer to the MAX1421 data sheet for 40Msps and the MAX1422 data sheet for 20Msps.

________________________Applications

Medical Ultrasound Imaging CCD Pixel Processing IR Focal Plane Arrays Radar IF & Baseband Digitization

Features

♦ +3.3V Single Power Supply

♦ 67dB SNR at f

= 5MHz

♦ 66dB SNR at f

= 15MHz

♦ Internal +2.048V Precision Bandgap Reference

♦ Differential, Wideband Input T/H Amplifier

♦ Power-Down Modes:

218mW (Reference Shutdown Mode) 10µW (Shutdown Mode)

♦ Space-Saving 48-Pin TQFP Package

MAX1420

12-Bit, 60Msps, +3.3V, Low-Power ADC

with Internal Reference

________________________________________________________________ Maxim Integrated Products 1

Pin Configuration

19-1981; Rev 0; 5/01

Ordering Information

Functional diagram appears at end of data sheet.

PART TEMP. RANGE PIN-PACKAGE

MAX1420CCM 0°C to +70°C 48 TQFP MAX1420ECM -40°C to +85°C 48 TQFP

AGND

AVDDCML

REFN

REFP

REFIN

AGND

AV AGND AGND

INP

INN AGND AGND

AV AV

AGND

AVDDAGNDPDOE

4847464544434241403938

MAX1420

D11

D10

D9 D8

DGND

1314151617181920212223

AGND

DDAVDD

CLK

AGND

48-TQFP

CLK

AGND

DGND

Page 2

MAX1420

12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

AVDD

= V

DVDD

= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dB FS, internal reference, f

CLK

62.5MHz (50% duty cycle), digital output load C

≈ 10pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AVDD, DVDDto AGND..............................................-0.3V to +4V

, AVDDto DGND..............................................-0.3V to +4V

DGND to AGND.....................................................-0.3V to +0.3V

INP, INN, REFP, REFN, REFIN,

CML, CLK, CLK ....................(AGND - 0.3V) to (AV

+ 0.3V)

D0–D11, OE, PD .....................(DGND - 0.3V) to (DV

+ 0.3V)

Continuous Power Dissipation (T

= +70°C)

48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW

Operating Temperature Ranges

MAX1420CCM ....................................................0°C to +70°C

MAX1420ECM .................................................-40°C to +85°C

Maximum Junction Temperature .....................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

DC ACCURACY

Resolution RES 12 Bits

Differential Nonlinearity DNL

Integral Nonlinearity INL TA = T

Mid-scale Offset MSO -3 .75 3 %FSR

Mid-scale Offset Temperature Coefficient

Gain Error GE

Gain Error Temperature Coefficient

DYNAMIC PERFORMANCE (f

Signal-to-Noise Ratio SNR

Spurious-Free Dynamic Range SFDR

Total Harmonic Distortion THD

Signal-to-Noise and Distortion SINAD

Effective Number of Bits ENOB

Two-Tone Intermodulation Distortion

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

MSOTC

GETC

= 60MHz, 4096-point FFT)

CLK

IMD

TA = +25°C, no missing codes -1 1

= T

Internal reference (Note 1) -5 ±0.1 5

E xter nal r efer ence ap p l i ed to RE FIN ( N ote 2)

E xter nal r efer ence ap p li ed to RE FP , CML, and REFN (Note 3)

External reference applied to REFP, CML, and REFN (Note 3)

fIN = 5MHz 67

fIN = 5MHz 72

fIN = 5MHz -70

fIN = 5MHz 64.5

fIN = 5MHz 10.4

IN1

IN2

to T

MIN

to T

MIN

= 15MHz, TA =+25°C6266

= 15MHz, TA =+25°C6472

= 15MHz, TA =+25°C -69 -62

= 15MHz, TA =+25°C 58.5 63

= 15MHz 10.2

= 11.566036MHz, = 13.4119138MHz (Note 4)

MAX

±0.5

±2 LSB

-4

3 x 10

-5 ±0.2 5

-1.5 1.5

100 x 106 %/°C

-74 dBc

LSB

%/°C

%FSR

Bits

Page 3

MAX1420

12-Bit, 60Msps, +3.3V, Low-Power ADC

with Internal Reference

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

AVDD

= V

DVDD

= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dB FS, internal reference, f

CLK

62.5MHz (50% duty cycle), digital output load C

≈ 10pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Differential Gain DG ±1% Differential Phase DP ±0.25 degrees

ANALOG INPUTS (INP, INN, CML)

Input Resistance R

Input Capacitance C

Common-Mode Input Level (Note 5)

Common-Mode Input Voltage Range (Note 5)

Differential Input Range V

Small-Signal Bandwidth BW

Large-Signal Bandwidth FPBW

CMVR

CML

-3dB

Overvoltage Recovery OVR 1.5 ✕ FS input 1

Either input to ground 22 kΩ

Either input to ground 4 pF

AVDD

0.5

CML

± 5%

- V

INP

(Note 6) ±V

INN

DIFF

(Note 7) 400 MHz

(Note 7) 150 MHz

Clock Cycle

INTERNAL REFERENCE (REFIN bypassed with 0.22µF in parallel with 1nF)

Common-Mode Reference Voltage

Positive Reference Voltage V

Negative Reference Voltage V

Differential Reference Voltage V

Differential Reference Temperature Coefficient

REFTC ±100 ppm/°C

CML

REFP

REFN

DIFF

At CML

At REFP

At REFN

= V

DIFF

REFP

- V

REFN

AVDD

0.5

CML

+ 0.512

CML

- 0.512

1.024 ±5% V

EXTERNAL REFERENCE (REFIN = +2.048V)

REFIN Input Resistance R

REFIN Input Capacitance C

REFIN Reference Input Voltage V

Differential Reference Voltage V

EXTERNAL REFERENCE (V

= AGND, reference voltage applied to REFP, REFN, and CML)

REFIN

REFP, REFN, CML Input Current I

REFP, REFN, CML Input Capacitance

REFIN

DIFF

(Note 8) 5 kΩ

10 pF

2.048 ±10%

DIFF

= (V

REFP

- V

REFN

)

0.95

RE F IN

1.05

REFIN

-200 200 µA

15 pF

Page 4

MAX1420

12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

AVDD

= V

DVDD

= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dB FS, internal reference, f

CLK

62.5MHz (50% duty cycle), digital output load C

≈ 10pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Differential Reference Voltage Range

CML Input Voltage Range V

REFP Input Voltage Range V

REFN Input Voltage Range V

DIFF

CML

REFP

REFN

DIFF

= V

REFP

- V

REFN

1.024 ±10%

1.65

±10%

CML

DIFF

CML

DIFF

+ /2

DIGITAL INPUTS (CLK, CLK, PD, OE)

Input Logic High V

Input Logic Low V

0.7

DVDD

0.3

DVDD

CLK, CLK ±330

Input Current

PD -20 20

µA

OE -20 20

Input Capacitance 10 pF

DIGITAL OUTPUTS (D0–D11)

Output Logic High V

Output Logic Low V

IOH = 200µA

DVDD

- 0.5

IOL = -200µA 0 0.5 V

DVDD

Three-State Leakage -10 10 µA

Three-State Capacitance 2pF

POWER REQUIREMENTS

Analog Supply Voltage V

Digital Supply Voltage V

Analog Supply Current I

Analog Supply Current with Internal Reference in Shutdown

AVDD

DVDD

AVDD

REFIN

Analog Shutdown Current PD = D

Digital Supply Current I

DVDD

Digital Shutdown Current PD = V

Power Dissipation P

Power Dissipation with Internal Reference in Shutdown (Note 8)

DISS

Analog power dissipation 221 258 mW

REFIN = AGND 218 251 mW

= AGND 66 76 mA

VDD

DVDD

3.135 3.3 3.465 V

2.7 3.3 3.63 V

67 78 mA

10 20 µA

8mA

20 µA

Page 5

MAX1420

12-Bit, 60Msps, +3.3V, Low-Power ADC

with Internal Reference

_______________________________________________________________________________________ 5

Note 1: Internal reference, REFIN bypassed to AGND with a combination of 0.22µF in parallel with 1nF capacitor. Note 2: External +2.048V reference applied to REFIN. Note 3: Internal reference disabled. V

REFIN

= 0, V

REFP

= +2.162V, V

CML

= +1.65V, and V

REFN

= +1.138V.

Note 4: IMD is measured with respect to either of the fundamental tones. Note 5: Specifies the common-mode range of the differential input signal supplied to the MAX1420. Note 6: V

DIFF

= V

REFP

- V

REFN

Note 7: Input bandwidth is measured at a 3dB level. Note 8: V

REFIN

is internally biased to +2.048V through a 10kΩ resistor.

Note 9: Measured as the ratio of the change in mid-scale offset voltage for a ±5% change in V

AVDD

, using the internal reference.

ELECTRICAL CHARACTERISTICS (continued)

AVDD

= V

DVDD

= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dB FS, internal reference, f

CLK

62.5MHz (50% duty cycle), digital output load C

≈ 10pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at

= +25°C.)

Typical Operating Characteristics

AVDD

= V

DVDD

= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dB FS, f

CLK

= 60.006MHz (50% duty

cycle), digital output load CL= 10pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

-120

-80

-100

-40

-60

-20

030

FFT PLOT (8192-POINT DATA RECORD)

DIFFERENTIAL INPUT

MAX1420 toc01

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

10 1552025

HD2

HD3

fIN = 5.5449583MHz

-120

-80

-100

-40

-60

-20

030

FFT PLOT (8192-POINT DATA RECORD)

DIFFERENTIAL INPUT

MAX1420 toc02

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

10 1552025

HD2

HD3

fIN = 13.4119138MHz

-120

-80

-100

-40

-60

-20

030

FFT PLOT (8192-POINT DATA RECORD)

DIFFERENTIAL INPUT

MAX1420 toc03

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

10 1552025

HD2

HD3

fIN = 37.701219MHz

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Power Dissipation In Shutdown P

DISS

PD = V

DVDD

10 µW

Power-Supply Rejection Ratio PSRR (Note 9) ±1 mV/V

TIMING CHARACTERISTICS

Maximum Clock Frequency f

Clock High t

Clock Low t

CLK

Figure 6, clock period 16.667ns 8.33 ns

60 MHz

Pipeline Delay (Latency) Figure 6 7

Aperture Delay t

Aperture Jitter t

Data Output Delay t

Bus Enable Time t

Bus Disable Time t

Figure 10 2 ns

Figure 10 2 ps

Figure 6 5 10 14 ns

Figure 5 5 ns

CLK

cycles

Page 6

MAX1420

12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference

6 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

AVDD

= V

DVDD

= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dB FS, f

CLK

= 60.006MHz (50% duty

cycle), digital output load C

= 10pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

-120

-80

-100

-40

-60

-20

030

TWO-TONE IMD PLOT

(8192-POINT DATA RECORD)

DIFFERENTIAL INPUT

MAX1420 toc04

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dB)

10 1552025

IN1

= 11.566036MHz

IN2

= 13.4119138MHz

IN1

= A

IN2

= -6.5dB FS TWO TONE ENVELOPE: -0.5dB FS

IN2

IMD3

IMD2

IMD3

110100

SPURIOUS-FREE DYNAMIC RANGE

vs. ANALOG INPUT FREQUENCY

MAX1420 toc08

ANALOG INPUT FREQUENCY (MHz)

SFDR (dB)

MAX1420 toc09

-10

SNR (dB)

-70 -50 -40-60

-30

-20 -10 0

INPUT POWER (dB FS)

SIGNAL-TO-NOISE RATIO

vs. INPUT POWER (f

= 15MHz)

-80

-60

-70

-40

-50

-30

-20

MAX1420 toc11

THD (dB)

TOTAL HARMONIC DISTORTION

vs. INPUT POWER (f

= 15MHz)

-70 -50 -40-60

-30

-20 -10 0

INPUT POWER (dB FS)

MAX1420 toc12

SFDR (dB)

SPURIOUS-FREE DYNAMIC RANGE

vs. INPUT POWER (f

= 15MHz)

-70 -50 -40-60

-30

-20 -10 0

INPUT POWER (dB FS)

-50

-80 110100

TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY

-74

MAX1420 toc07

ANALOG INPUT FREQUENCY (MHz)

THD (dB)

-68

-62

-56

MAX1420 toc10

-10

SINAD (dB)

-70 -50 -40-60

-30

-20 -10 0

INPUT POWER (dB FS)

SIGNAL-TO-NOISE + DISTORTION vs. INPUT POWER (f

= 15MHz)

110100

SIGNAL-TO-NOISE RATIO

vs. ANALOG INPUT FREQUENCY

MAX1420 toc05

ANALOG INPUT FREQUENCY (MHz)

SNR (dB)

1 10 100

SIGNAL-TO-NOISE + DISTORTION

vs. ANALOG INPUT FREQUENCY

MAX1420 toc06

ANALOG INPUT FREQUENCY (MHz)

SINAD (dB)

Page 7

MAX1420

12-Bit, 60Msps, +3.3V, Low-Power ADC

with Internal Reference

Typical Operating Characteristics (continued)

AVDD

= V

DVDD

= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dB FS, f

CLK

= 60.006MHz (50% duty

cycle), digital output load CL= 10pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

-40 10-15 35 60 85

MAX1420 toc13

TEMPERATURE (°C)

SNR (dB)

SIGNAL-TO-NOISE RATIO

vs. TEMPERATURE

fIN = 15MHz

-1

-2 020481024 3072 4096

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1421 toc17

INL (LSB)

0.50

0.25

-0.25

-0.50 0 20481024 3072 4096

MAX1420 toc18

DIGITAL OUTPUT CODE

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

INL (LSB)

-1.25

-1.00

-0.50

-0.75

-0.25

-40 10-15 35 60 85

OFFSET ERROR vs. TEMPERATURE

MAX1420 toc20

TEMPERATURE (°C)

OFFSET ERROR (%FSR)

3.1 3.5

MAX1420 toc21

AVDD (V)

AVDD

(mA)

ANALOG SUPPLY CURRENT

vs. ANALOG SUPPLY VOLTAGE

3.33.2 3.4

-40 10-15 35 60 85

MAX1420 toc16

TEMPERATURE (°C)

SFDR (dB)

SPURIOUS-FREE DYNAMIC RANGE

vs. TEMPERATURE

fIN = 15MHz

-0.500

0.250

-40 10-15 35 60 85

MAX1420 toc19

TEMPERATURE (°C)

GAIN ERROR (%FSR)

GAIN ERROR vs. TEMPERATURE,

EXTERNAL REFERENCE V

REFIN

= +2.048V

-0.250

-0.375

-0.125

0.125

-40 10-15 35 60 85

MAX1420 toc14

TEMPERATURE (°C)

SINAD (dB)

SIGNAL-TO-NOISE + DISTORTION

vs. TEMPERATURE

fIN = 15MHz

-75

-73

-69

-71

-67

-65

-40 10-15 35 60 85

MAX1420 toc15

TEMPERATURE (°C)

THD (dB)

TOTAL HARMONIC DISTORTION

vs. TEMPERATURE

fIN = 15MHz

________________________________________________________________________________________ 7

Page 8

MAX1420

12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference

8 _______________________________________________________________________________________

Typical Operating Characteristics (continued)

AVDD

= V

DVDD

= +3.3V, AGND = DGND = 0, VIN= ±1.024V, differential input voltage at -0.5dB FS, f

CLK

= 60.006MHz (50% duty

cycle), digital output load C

= 10pF, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical values are at TA= +25°C.)

-40 10-15 356085

MAX1420 toc22

TEMPERATURE (°C)

AVDD

(mA)

ANALOG SUPPLY CURRENT

vs. TEMPERATURE

0.03

0.09

0.06

0.12

0.15

2.7 3.02.9 3.2 3.3 3.5 3.6

MAX1420 toc26

DVDD (V)

DVDD

(µA)

DIGITAL POWER-DOWN CURRENT

vs. DIGITAL SUPPLY VOLTAGE

-80

-60

-40

-20

20 4030 50 60 70 80

MAX1420 toc27

CLOCK FREQUENCY (MHz)

SFDR, SNR, THD, SINAD (dB)

SNR, SINAD, THD, SFDR

vs. CLOCK FREQUENCY

SFDR

SINAD

SNR

THD

fIN = 15MHz

2.00

2.02

2.06

2.04

2.08

2.10

-40 10-15 35 60 85

MAX1420 toc29

TEMPERATURE (°C)

REF

(dB)

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

N-6 N-4 N-3N-5 N-2 N-1 N N+1 N+2N+3 N+4 N+5 N+6

MAX1420 toc30

DIGITAL OUTPUT NOISE

COUNTS

300,000

200,000

100,000

400,000

500,000

600,000

OUTPUT NOISE HISTOGRAM

(DC INPUT)

0342

14538

6113

242 0

115171

153704

53499

339785

387312

502186

0.04

0.12

0.08

0.16

0.20

3.10 3.50

MAX1420 toc25

AVDD (V)

AVDD

(µA)

ANALOG POWER-DOWN CURRENT

vs. ANALOG SUPPLY VOLTAGE

3.303.20 3.40

2.075

2.063

2.050

2.038

2.025

3.1 3.33.2 3.4 3.5

MAX1420 toc28

AVDD (V)

REF

(V)

INTERNAL REFERENCE VOLTAGE

vs. ANALOG SUPPLY VOLTAGE

2.7 3.22.9 3.0 3.3 3.5 3.6

MAX1420 toc23

(V)

DVDD

(mA)

DIGITAL SUPPLY CURRENT

vs. DIGITAL SUPPLY VOLTAGE

-40 10-15 35 60 85

MAX1420 toc24

TEMPERATURE (°C)

DVDD

(mA)

DIGITAL SUPPLY CURRENT

vs. TEMPERATURE

Page 9

MAX1420

12-Bit, 60Msps, +3.3V, Low-Power ADC

with Internal Reference

_______________________________________________________________________________________ 9

Pin Description

PIN NAME FUNCTION

1, 4, 5, 8,

9, 12, 13,

16, 19, 41,

2, 3, 10,

11, 14, 15,

20, 42, 47

AGND Analog Ground. Connect all return paths for analog signals to AGND.

Analog Supply Voltage. For optimum performance, bypass to the closest AGND with a parallel

combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination between A

VDD

and A

GND

6 INP Positive Analog Signal Input

7 INN Negative Analog Signal Input

17 CLK Clock Frequency Input. Clock frequency input ranges from 100kHz to 60MHz.

18 CLK

Complementary Clock Frequency Input. This input is used for differential clock inputs. If the ADC is

driven with a single-ended clock, bypass CLK with a 0.1µF capacitor to AGND.

Digital Supply Voltage. For optimum performance, bypass to the closest DGND with a parallel

21, 31, 32 DV

combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination between D

VDD

and D

GND

22, 29, 30 DGND Digital Ground

23–28 D0–D5 Digital Data Outputs. Data bits D0 through D5, where D0 represents the LSB.

33–38 D6–D11 Digital Data Outputs. D6 through D11, where D11 represents the MSB.

39 OE

Output Enable Input. A logic “1” on OE places the outputs D0–D11 into a high-impedance state. A

logic “0” allows for the data bits to be read from the outputs.

40 PD Shutdown Input. A logic “1” on PD places the ADC into shutdown mode.

External Reference Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel with

43 REFIN

1nF. REFIN can be biased externally to adjust reference levels and calibrate full-scale errors. To disable the internal reference, connect REFIN to AGND.

44 REFP

45 REFN

46 CML

P osi ti ve Refer ence I/O . Byp ass to AG N D w i th a cap aci tor com b i nati on of 0.22µF i n p ar al l el w i th 1nF.

W i th the i nter nal r efer ence d i sab l ed ( RE FIN = AG N D ) , RE FP shoul d b e b i ased to V

C M L

+ V

D IF F

/ 2.

N eg ati ve Refer ence I/O . Byp ass to AG N D w i th a cap aci tor com b i nati on of 0.22µF i n p ar al l el w i th 1nF.

W i th the i nter nal r efer ence d i sab l ed ( RE FIN = AG N D ) , RE FN shoul d b e b i ased to V

C M L

- V

D IF F

/ 2.

Common-Mode Level Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel

with 1nF.

Page 10

MAX1420

12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference

10 ______________________________________________________________________________________

Detailed Description

The MAX1420 uses a 12-stage, fully-differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half-clock cycle, including the delay through the output latch. The latency is seven clock cycles.

A 2-bit (2-comparator) flash ADC converts the heldinput voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held-input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage. This process is repeated until the signal has been processed by all 12 stages. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes.

Input Track-and-Hold Circuit

Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuit in both track-and-hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully-differential circuit passes the input signal to the two capacitors C2a and C2b through switches S4a and S4b. Switches S2a and S2b set the common mode for the operational transcon-

ductance amplifier (OTA) input, and open simultaneously with S1, sampling the input waveform. The resulting differential voltage is held on capacitors C2a and C2b. Switches S4a and S4b are then opened before S3a, S3b, S4C are closed. The OTA is used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. This value is then presented to the first stage quantizer and isolates the pipeline from the fast-changing input. The wide input bandwidth T/H amplifier allows the MAX1420 to track and sample/hold analog inputs of high frequencies beyond Nyquist. The analog inputs INP to INN can be driven either differentially or single-ended. Match the impedance of INP and INN and set the common-mode voltage to midsupply (AV

/2) for optimum performance.

Analog Input and Reference Configuration

The full-scale range of the MAX1420 is determined by the internally generated voltage difference between REFP (AVDD/2 + V

REFIN

/4) and REFN (AVDD/2 -

REFIN

/4). The MAX1420’s full-scale range is adjustable through REFIN, which provides high input impedance for this purpose. REFP, CML (AVDD/2), and REFN are internally buffered low impedance outputs.

Figure 1. Pipelined Architecture—Stage Blocks

Figure 2. Internal Track-and-Hold Circuit

C2a

C2b

INTERNAL

BIAS

S2a

INTERNAL

BIAS

C1a

OTA

C1b

MDAC

MAX1420

T/H

FLASH

ADC

2 BITS

STAGE 1 STAGE 2

DAC

DIGITAL CORRECTION LOGIC

D11–D0

OUT

TO NEXT

STAGE

S4a

S4c

STAGE 12

S4b

MAX1420

CML

S5a

S3a

OUT

S3b

S5bS2b

CML

Page 11

MAX1420

12-Bit, 60Msps, +3.3V, Low-Power ADC

with Internal Reference

______________________________________________________________________________________ 11

cations that require increased accuracy and a different input voltage range.

The MAX1420 provides three modes of reference operation:

• Internal reference mode

• Buffered external reference mode

• Unbuffered external reference mode

In internal reference mode, the on-chip +2.048V bandgap reference is active and REFIN, REFP, CML, and REFN are left floating. For stability purposes, bypass REFIN, REFP, REFN and CML with a capacitor network of 0.22µF in parallel with a 1nF capacitor to AGND.

In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a stable and accurate voltage at REFIN.

In unbuffered external reference mode, REFIN is connected to AGND, thereby deactivating the on-chip buffers of REFP, CML, and REFN. With their buffers shut down, these nodes become high impedance and can be driven by external reference sources, as shown in Figure 3.

Clock Inputs (CLK,

CLK

)

The MAX1420’s CLK and CLK inputs accept both differential and single-ended input operation and accept CMOS-compatible clock signals. If CLK is driven with a single-ended clock signal, bypass CLK with a 0.1µF capacitor to AGND. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). Sampling occurs on the rising edge of the clock signal, requiring this edge to have the lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the ADC according to the following relationship:

where fINrepresents the analog input frequency and tAJis the aperture jitter. Clock jitter is especially critical for high input frequency applications. The clock input should always be considered as an analog signal and routed away from any analog or digital signal lines.

The MAX1420 clock input operates with a voltage threshold set to AVDD/2. Clock inputs must meet the specifications for high and low periods as stated in the

Electrical Characteristics.

Figure 3. Unbuffered External Reference Drive—Internal Reference Disabled

50Ω

MAX4284

0.22µF

0.5V

50Ω

AGND

SNR

CML

( )

REFP

REFN

REFIN

0.5V

( )

MAX1420

DD-

0.5V

( )

1nF

1nF0.22µF

=×

log

××

IN AJ

Page 12

12 ______________________________________________________________________________________

MAX1420

12-Bit, 60Msps, +3.3V, Low-Power ADC

Figure 4 shows a simplified model of the clock input circuit. This circuit consists of two 10kΩ resistors to bias the common-mode level of each input. This circuit may be used to AC-couple the system clock signal to the MAX1420 clock input.

Output Enable (OE), Power-Down (PD)

and Output Data (D0–D11)

In addition to low operating power, the MAX1420 features two power-down modes: reference power-down and shutdown mode. In reference power-down, the in-

ternal bandgap reference is deactivated, which results in a typical 2mA supply current reduction. A full shutdown mode is available to maximize power savings during idle periods.

The MAX1420 provides parallel, offset binary, CMOScompatible three-state outputs.

With OE high, the digital outputs enter a high-impedance state. If OE is held low with PD high, the outputs are latched at the last digital output code prior to the power-down. All data outputs, D0 (LSB) through D11 (MSB), are TTL/CMOS logic-compatible. There is a seven clock-cycle latency between any particular sample and its valid output data. The output coding is in offset binary format (Table 1).

The capacitive load on the digital outputs D0 through D11 should be kept as low as possible (≤10pF), to avoid large digital currents that could feed back into the analog portion of the MAX1420, thereby degrading its performance. The use of buffers (e.g., 74LVCH16244) on the digital outputs of the ADC can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1420, add small-series resistors of 100Ω to the digital output paths, close to the ADC.

Figure 5 displays the timing relationship between output enable and data output.

System Timing Requirements

Figure 6 depicts the relationship between the clock input, analog input, and valid data output. The MAX1420 samples the analog input signal on the rising edge of CLK (falling edge of CLK) and output data is valid seven clock cycles (latency) later.

Applications Information

Figure 7 depicts a typical application circuit containing a single-ended to differential converter. The internal reference provides an AVDD/2 output voltage for level shifting purposes. The input is buffered and then split to a voltage follower and inverter. A lowpass filter at the input suppresses some of the wideband noise associated

Figure 4. Simplified Clock Input Circuit

Figure 5. Output Enable Timing

Table 1. MAX1420 Output Code for Differential Inputs

* V

REF

= V

REFP

- V

REFN

INP

INN

VDD

CLK

AGND

ADC

10kΩ

D11–D0

10kΩ

MAX1420

DIFFERENTIAL

INPUT VOLTAGE*

× 2047/2048

REF

× 2046/2048

REF

× 1/2048 + 1 LSB 1000 0000 0001

REF

0 Bipolar Zero 1000 0000 0000

-V

× 1/2048 - 1 LSB 0111 1111 1111

REF

-V

× 2046/2048

REF

-V

× 2047/2048 -FULL SCALE 0000 0000 0000

REF

DIFFERENTIAL

+FULL SCALE -

-FULL SCALE +

INPUT

1LSB

2LSB

1 LSB

OFFSET BINARY

1111 1111 1111

1111 1111 1110

0000 0000 0001

OUTPUT

DATA D11–D0

VALID DATA

HIGH-ZHIGH-Z

Page 13

MAX1420

12-Bit, 60Msps, +3.3V, Low-Power ADC

with Internal Reference

______________________________________________________________________________________ 13

Figure 6. System and Output Timing Diagram

Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion

ANALOG INPUT

DATA OUTPUT

CLK

N + 1

N - 7

300Ω

N - 6

0.1µF

N + 2

7 CLOCK-CYCLE LATENCY

N + 3

N - 5

+5V

MAX4108

N - 4

0.1µF

N + 4

N - 3

N + 5

N - 2

LOWPASS FILTER

ISO

50Ω

*C 22pF

N + 6

N - 1 N

INP

0.1µF

600Ω

0.1µF

600Ω

INPUT

MAX4108

300Ω

+5V

-5V

300Ω

0.1µF

300Ω

-5V

600Ω

0.1µF

+5V

600Ω

MAX4108

-5V

0.1µF

LOWPASS FILTER

ISO

50Ω

*TWO C ONE 44pF CAP, TO IMPROVE PERFORMANCE.

44pF*

1nF0.22µF

22pF

(22pF) CAPS MAY BE REPLACED BY

MAX1420

CML

INN

Page 14

MAX1420

with high-speed op amps. Select the R

ISO

and CINvalues to optimize the filter performance, to suit a particular application. For the application in Figure 7, an isolation resistor (R

ISO

) of 50Ω is placed before the

capacitive load to prevent ringing and oscillation. The 22pF CINcapacitor acts as a small bypassing capacitor. Connecting CINfrom INN to INP may further improve dynamic performance.

Using Transformer Coupling

An RF transformer (Figure 8) provides an excellent solution to convert a single-ended signal to a fully differential signal, required by the MAX1420 for optimum performance. Connecting the center tap of the transformer to CML provides an AVDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a 1:2 or 1:4 step-up transformer may be selected to reduce the drive requirements.

In general, the MAX1420 provides better SFDR and THD with fully differential input signals over single-ended input signals, especially for very high input frequencies. In differential input mode, even-order harmonics are suppressed and each input requires only half the signal swing compared to single-ended mode.

Single-Ended AC-Coupled Input Signal

Figure 9 shows an AC-coupled, single-ended application, using a MAX4108 op amp. This configuration provides high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal.

Grounding, Bypassing and

Board Layout

The MAX1420 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the ADC, using surface-mount devices for minimum inductance. Bypass REFP, REFN, REFIN, and CML with a parallel network of 0.22µF capacitors and 1nF to AGND. AVDDshould be bypassed with a similar network of a 10µF bipolar capacitor in parallel with two ceramic capacitors of 1nF and 0.1µF. Follow the same rules to bypass the digital supply DVDDto DGND. Multilayer boards with separate ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arrangement to match the physical location of the analog ground (AGND) and the digital ground (DGND) on the ADCs package. Join the two ground planes at a single point, such that the noisy digital ground currents do not interfere with the analog ground plane. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces and remove digital ground and power planes from underneath digital outputs. Keep all signal lines short and free of 90 degree turns.

12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference

Figure 8. Using a Transformer for AC-Coupling

14 _____________________________________________________________________________________

25Ω

INP

MAX1420

CML

INN

22pF

0.1µF

N.C.

*REPLACE BOTH 22pF CAPS WITH 44pF BETWEEN

0.22µF

MINICIRCUITS

T1–1T–KK81

INP AND INN TO IMPROVE DYNAMIC PERFORMANCE.

25Ω

22pF

44pF

1nF

Page 15

Static Parameter Definitions

Integral Nonlinearity (INL)

Integral nonlinearity is the deviation of the values on an actual transfer function from a straight-line. This straightline can be either a best straight-line fit or a line drawn between the endpoints of the transfer function once offset and gain errors have been nullified. The static linearity parameters for the MAX1420 are measured using the best straight-line fit method.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between an actual step-width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes.

Dynamic Parameter Definitions

Aperture Jitter

Figure 10 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.

Aperture Delay

Aperture delay (t

) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 10).

Signal-to-Noise Ratio (SNR)

For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADCs resolution (N-bits):

SNR

MAX

= (6.02 x N + 1.76)

In reality, there are other noise sources besides quantization noise, e.g., thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four harmonics, and the DC offset.

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset.

Effective Number of Bits (ENOB)

ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB is computed from:

MAX1420

12-Bit, 60Msps, +3.3V, Low-Power ADC

with Internal Reference

______________________________________________________________________________________ 15

Figure 9. Single-Ended AC-Coupled Input Signal

Figure 10. T/H Aperture Timing

MAX4108

100Ω

0.1µF

ISO

1kΩ

0.22µF

50Ω

C 22pF

1nF

22pF

50Ω

ISO

INP

MAX1420

CML

INN

CLK

ANALOG

INPUT

SAMPLED

DATA (T/H)

TRACK TRACK

T/H

HOLD

ENOB

SINADdB dB

602..

−176 dB

Page 16

MAX1420

Total Harmonic Distortion (THD)

THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as:

where V1is the fundamental amplitude, and V2through V

are the amplitudes of the 2nd- through 5th-order

harmonics.

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset.

Intermodulation Distortion (IMD)

The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale and their envelope is at -0.5dB full scale.





  



12-Bit, 60Msps, +3.3V, Low-Power ADC with Internal Reference

Functional Diagram

______________________________________________________________________________________ 16



2222



VVVV

+++

2345



THDdB

=×

20 10

log

  

 

CLK

 

INP

T/H

INN

BANDGAP

REFERENCE

INTERFACE

PIPELINE ADC

REF SYSTEM +

BIAS

REFIN REFP CML REFN OE

MAX1420

OUTPUT

DRIVERS

AGND

D11–D0

DGND

Page 17

MAX1420

12-Bit, 60Msps, +3.3V, Low-Power ADC

with Internal Reference

Package Information

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

17 ____________________ Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

32L/48L,TQFP.EPS