Rainbow Electronics MAX1419 User Manual
General Description
The MAX1419 is a 5V, high-speed, high-performance
analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) and a 15-bit converter core. The MAX1419 is optimized for multichannel,
multimode receivers, which require the ADC to meet very
stringent dynamic performance requirements. With a
noise floor of -79.3dBFS, the MAX1427 allows for the
design of receivers with superior sensitivity.
The MAX1419 achieves two-tone, spurious-free dynamic
range (SFDR) of -91dBc for input tones of 10MHz and
15MHz. Its excellent signal-to-noise ratio (SNR) of 76.2dB
and single-tone SFDR performance (SFDR1/SFDR2) of
93.1dBc/95.5dBc at f
IN
= 15MHz and a sampling rate of
65Msps make this part ideal for high-performance digital
receivers.
The MAX1419 operates from an analog 5V and a digital
3V supply, features a 2.56V
P-P
full-scale input range,
and allows for a sampling speed of up to 65Msps. The
input T/H operates with a -1dB full-power bandwidth of
200MHz.
The MAX1419 features parallel, CMOS-compatible outputs in two’s-complement format. To enable the interface
with a wide range of logic devices, this ADC provides a
separate output driver power-supply range of 2.3V to
3.5V. The MAX1419 is manufactured in an 8mm x 8mm,
56-pin thin QFN package with exposed paddle (EP) for
low thermal resistance, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Note that IF parts MAX1418, MAX1428, and MAX1430
(see the Pin-Compatible Higher/Lower Speed Versions
Selection table) are recommended for applications that
require high dynamic performance for input frequencies greater than f
CLK
/3. The MAX1419 is optimized for
input frequencies of less than f
CLK
/3.
Applications
Cellular Base-Station Transceiver Systems (BTS)
Wireless Local Loop (WLL)
Single- and Multicarrier Receivers
Multistandard Receivers
E911 Location Receivers
Power Amplifier Linearity Correction
Antenna Array Processing
Features
♦ 65Msps Minimum Sampling Rate
♦ -79.3dBFS Noise Floor
♦ Excellent Dynamic Performance
76.2dB SNR at f
IN
=15MHz and A
IN
= -1dBFS
93.1dBc/95.5dBc Single-Tone SFDR1/SFDR2 at
f
IN
= 15MHz and A
IN
= -1dBFS
-91dBc Multitone SFDR at f
IN1
= 10MHz
and f
IN2
= 15MHz
♦ Less than 0.25ps Sampling Jitter
♦ Fully Differential Analog Input Voltage Range of
2.56V
P-P
♦ CMOS-Compatible Two’s-Complement Data Output
♦ Separate Data Valid Clock and Overrange Outputs
♦ Flexible-Input Clock Buffer
♦ EV Kit Available for the MAX1419
(Order MAX1427EVKIT)
MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3011; Rev 1; 2/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Pin Configuration appears at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX1419ETN -40°C to +85°C 56 Thin QFN-EP*
Pin-Compatible Higher/Lower
Speed Versions Selection
PART
SPEED GRADE
(Msps)
TARGET
APPLICATION
MAX1418 65 IF
MAX1419 65 Baseband
MAX1427 80 Baseband
MAX1428* 80 IF
MAX1429* 100 Baseband
MAX1430* 100 IF
*
Future product—contact factory for availability.
*
EP = Exposed paddle.
MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVCC= 5V, DVCC= DRVCC= 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, CL= 5pF at digital outputs, f
CLK
= 65MHz, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCC, DVCC, DRVCCto GND.................................. -0.3V to +6V
INP, INN, CLKP, CLKN, CM to GND........-0.3V to (AV
CC
+ 0.3V)
D0–D14, DAV, DOR to GND..................-0.3V to (DRV
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
56-Pin Thin QFN (derate 47.6mW/°C above +70°C)................
3809.5mW
Operating Temperature Range ...........................-40°C to +85°C
Thermal Resistance
θ
J
A
...................................................21°C/W
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution 15 Bits
Integral Nonlinearity INL f
IN
= 15MHz
LSB
Differential Nonlinearity DNL f
IN
= 15MHz, no missing codes guaranteed
LSB
Offset Error -12
mV
Gain Error -4 +4
%FS
ANALOG INPUT (INP, INN)
D i ffer enti al Inp ut V ol tag e Rang e
V
DIFF
V
P-P
Common-Mode Input Voltage
V
CM
Self-biased
V
Differential Input Resistance R
IN
1
kΩ
Differential Input Capacitance
C
IN
1pF
Full-Power Analog Bandwidth
-1dB rolloff for a full-scale input
MHz
CONVERSION RATE
Maximum Clock Frequency f
CLK
65
MHz
Minimum Clock Frequency f
CLK
20
MHz
Aperture Jitter t
AJ
ps
RMS
CLOCK INPUT (CLKP, CLKN)
Full-Scale Differential Input
Voltage
Fully differential input drive, V
CLKP
- V
CLKN
0.5 to
3.0
V
Common-Mode Input Voltage
V
CM
Self-biased 2.4 V
Differential Input Resistance R
INCLK
2
kΩ
Differential Input Capacitance
C
INCLK
1pF
DYNAMIC CHARACTERISTICS
Thermal + Quantization
Noise Floor
NF Analog input <-35dBFS
dBFS
fIN = 5MHz at -1dBFS
fIN = 15MHz at -1dBFS
Signal-to-Noise Ratio (Note 1)
SNR
f
IN
= 25MHz at -1dBFS 76
dB
Fully differential inputs drive, V
FPBW
-1dB
V
DIFFCLK
DIFF
= V
INP
±1.5
±0.4
- V
INN
73.5 76.1
2.56
3.38
±15%
200
0.21
±15%
-79.3
76.5
+12
MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVCC= 5V, DVCC= DRVCC= 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, CL= 5pF at digital outputs, f
CLK
= 65MHz, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
fIN = 5MHz at -1dBFS
fIN = 15MHz at -1dBFS 73
(Note 1)
f
IN
= 25MHz at -1dBFS
dB
fIN = 5MHz at -1dBFS
fIN = 15MHz at -1dBFS 84
(HD2 and HD3)
(Note 1)
SFDR1
f
IN
= 25MHz at -1dBFS
dBc
fIN = 5MHz at -1dBFS
fIN = 15MHz at -1dBFS
(HD4 and Higher)
(Note 1)
SFDR2
f
IN
= 25MHz at -1dBFS
dBc
Two-Tone Intermodulation
Distortion
TTIMD
f
IN1
= 10MHz at -7dBFS;
f
IN2
= 15MHz at -7dBFS
dBc
Two-Tone Spurious-Free
Dynamic Range
f
IN1
= 10MHz at -10dBFS < f
IN1
< -100dBFS;
f
IN2
= 15MHz at -10dBFS < f
IN2
< -100dBFS
dBFS
DIGITAL OUTPUTS (D0–D14, DAV, DOR)
Digital Output Voltage Low V
OL
0.5 V
Digital Output Voltage High V
OH
DVCC -
0.5
V
TIMING CHARACTERISTICS (DV
CC
= DRV
CC
= 2.5V) Figure 4
CLKP/CLKN Duty Cycle
50
±5
%
Effective Aperture Delay t
AD
ps
Output Data Delay t
DAT
(Note 3) 3 4.5 7.5 ns
Data Valid Delay t
DAV
(Note 3) 5.3 6.5 8.7 ns
Pipeline Latency
3
Clock
cycles
CLKP Rising Edge to DATA
Not Valid
t
DNV
(Note 3) 2.6 3.8 5.7 ns
CLKP Rising Edge to DATA
Valid (Guaranteed)
t
DGV
(Note 3) 3.4 5.2 8.6 ns
DATA Setup Time
(Before DAV Rising Edge)
t
SETUP
(Note 3)
t
CLKP
-
0.5
t
CLKP
t
CLKP
ns
DATA Hold Time
(After DAV Rising Edge)
t
HOLD
(Note 3)
t
CLKN
-
3.6
t
CLKN
-
2.8
t
CLKN
-
2.0
ns
Signal-to-Noise and Distortion
Spurious-Free Dynamic Range
Spurious-Free Dynamic Range
76.3
75.9
74.3
96.5
93.5
80.5
94.5
85.5 94.5
93.2
-91
SFDR
TT
-105
Duty cycle
t
LATENCY
230
+ 1.3
+ 2.4
MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
4 _______________________________________________________________________________________
Note 1: Dynamic performance is based on a 32,768-point data record with a sampling frequency of f
SAMPLE
= 65.0117120MHz, an
input frequency of f
IN
= f
SAMPLE
x (7561/32768) = 15.001024MHz, and a frequency bin size of 1984Hz. Close-in (f
IN
±23.8kHz) and low-frequency (DC to 47.6kHz) bins are excluded from the spectrum analysis.
Note 2: Apply the same voltage levels to DV
CC
and DRVCC.
Note 3: Guaranteed by design and characterization.
ELECTRICAL CHARACTERISTICS (continued)
(AVCC= 5V, DVCC= DRVCC= 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, CL= 5pF at digital outputs, f
CLK
= 65MHz, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
CONDITIONS
UNITS
TIMING CHARACTERISTICS (DV
CC
= DRV
CC
= 3.3V) Figure 4
CLKP/CLKN Duty Cycle
50
±5
%
Effective Aperture Delay t
AD
ps
Output Data Delay t
DAT
(Note 3) 2.8 4.1 6.5 ns
Data Valid Delay t
DAV
(Note 3) 5.3 6.3 8.6 ns
Pipeline Latency
3
Clock
cycles
CLKP Rising Edge to
DATA Not Valid
t
DNV
(Note 3) 2.5 3.4 5.2 ns
CLKP Rising Edge to
DATA Valid (Guaranteed)
t
DGV
(Note 3) 3.2 4.4 7.4 ns
DATA Setup Time
(Before DAV Rising Edge)
t
SETUP
(Note 3)
t
CLKP
t
CLKP
t
CLKP
ns
DATA Hold Time
(After DAV Rising Edge)
t
HOLD
(Note 3)
t
CLKN
-
3.5
t
CLKN
-
2.7
t
CLKN
-
2.0
ns
POWER REQUIREMENTS
AV
CC
5
V
DV
CC
(Note 2)
V
DRV
CC
(Note 2)
V
Analog Supply Current I
AVCC
mA
I
DVCC
+
f
CLK
= 65MHz, C
LOAD
= 5pF
42 mA
Analog Power Dissipation PDISS
mW
SYMBOL
MIN TYP MAX
Analog Supply Voltage Range
Digital Supply Voltage Range
Output Supply Voltage Range
D i g i tal + Outp ut S up p l y C ur r ent
Duty cycle
t
LATENCY
+ 0.2
230
+ 1.7
+ 2.8
±3%
2.3 to 3.5
2.3 to 3.5
377 440
35.5
1974
MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
_______________________________________________________________________________________ 5
FFT PLOT (32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1419 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
252015105
-100
-80
-60
-40
-20
0
-120
030
f
CLK
= 65.0117MHz
f
IN
= 10.0013MHz
A
IN
= -1.02dBFS
SNR = 76.8dB
SFDR1 = 87.7dBc
SFDR2 = 98.3dBc
HD2 = 87.7dBc
HD3 = 91.5dBc
FFT PLOT (32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1419 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
252015105
-100
-80
-60
-40
-20
0
-120
030
f
CLK
= 65.0117MHz
f
IN
= 15.0010MHz
A
IN
= -0.98dBFS
SNR = 76.5dB
SFDR1 = 89.1dBc
SFDR2 = 98.1dBc
HD2 = 94.8dBc
HD3 = 89dBc
FFT PLOT (32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1419 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
252015105
-100
-80
-60
-40
-20
0
-120
030
f
CLK
= 65.0117MHz
f
IN
= 25.0004MHz
A
IN
= -06dBFS
SNR = 76.3dB
SFDR1 = 77.9dBc
SFDR2 = 92.3dBc
HD2 = 85.6dBc
HD3 = 77.9dBc
SNR vs. ANALOG INPUT FREQUENCY
(f
CLK
= 65.0117MHz, AIN = -1dBFS)
MAX1419 toc04
fIN (MHz)
SNR (dBc)
554515 25 35
71
72
73
74
75
76
77
78
70
565
SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY
(f
CLK
= 65.0117MHz, AIN = -1dBFS)
MAX1419 toc05
fIN (MHz)
SFDR1/SFDR2 (dBc)
5545352515
75
80
85
90
95
100
70
565
SFDR1
SFDR2
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(f
CLK
= 65.0117MHz, AIN = -1dBFS)
MAX1419 toc06
fIN (MHz)
HD2/HD3 (dBc)
5545352515
-95
-90
-85
-80
-75
-70
-100
565
HD2
HD3
FULL-SCALE-TO-NOISE RATIO vs.
ANALOG INPUT AMPLITUDE
(f
CLK
= 65.011712MHz, fIN = 15.0010MHz)
MAX1419 toc07
ANALOG INPUT AMPLITUDE (dBFS)
FULL-SCALE-TO-NOISE RATIO (dBFS)
-10-20-40 -30-50-60
71
72
73
74
75
76
77
78
79
80
70
-70 0
SFDR1/SFDR2 vs. ANALOG INPUT AMPLITUDE
(f
CLK
= 65.0117MHz, fIN = 15.0010MHz)
MAX1419 toc08
ANALOG INPUT AMPLITUDE (dBFS)
SFDR1/SFDR2 (dBFS)
-10-20-40 -30-50-60
80
90
100
110
120
130
70
-70 0
SFDR1
SFDR2
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
(f
CLK
= 65.0117MHz, fIN = 15.0010MHz)
MAX1419 toc09
ANALOG INPUT AMPLITUDE (dBFS)
HD2/HD3 (dBFS)
-10-20-40 -30-50-60
-120
-110
-100
-90
-80
-70
-150
-140
-130
-70 0
HD3
HD2
Typical Operating Characteristics
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, CL= 5pF at digital outputs, f
CLK
= 65MHz, TA= +25°C. All AC data based on a 32k-point FFT
record and under coherent sampling conditions.)
MAX1419
15-Bit, 65Msps ADC with -79.3dBFS
Noise Floor for Baseband Applications
6 _______________________________________________________________________________________
SNR vs. SAMPLING FREQUENCY
(f
IN
= 15.2MHz, AIN = -1dBFS)
MAX1419 toc10
f
CLK
(MHz)
SNR (dBc)
605525 30 35 4540 50
71
72
73
74
75
76
77
78
70
20 65
SFDR1/SFDR2 vs. SAMPLING FREQUENCY
(f
IN
= 15.2MHz, AIN = -1dBFS)
MAX1419 toc11
f
CLK
(MHz)
SFDR1/SFDR2 (dBc)
6055503540353025
75
80
85
90
95
100
70
20 65
SFDR1
SFDR2
HD2/HD3 vs. SAMPLING FREQUENCY
(f
IN
= 15.2MHz, AIN = -1dBFS)
MAX1419 toc12
f
CLK
(MHz)
HD2/HD3 (dBc)
605545 5030 35 4025
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
-120
20 65
HD2
HD3
SNR vs. TEMPERATURE
(f
CLK
= 65.0117MHz,
f
IN
= 15.0010MHz, AIN = -1dBFS)
MAX1419 toc13
TEMPERATURE (°C)
SNR (dB)
603510-15
74
75
76
77
78
73
-40 85
SINAD vs. TEMPERATURE
(f
CLK
= 65.0117MHz,
f
IN
= 15.0010MHz, AIN = -1dBFS)
MAX1419 toc14
TEMPERATURE (°C)
SINAD (dB)
603510-15
74
75
76
77
78
73
-40 85
Typical Operating Characteristics (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, INP and INN driven differentially with a -1dBFS amplitude, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, CL= 5pF at digital outputs, f
CLK
= 65MHz, TA= +25°C. All AC data based on a 32k-point FFT
record and under coherent sampling conditions.)
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