Rainbow Electronics MAX1418 User Manual

General Description

The MAX1418 is a 5V, high-speed, high-performance analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) and a 15-bit converter core. The MAX1418 is optimized for multichannel, multimode receivers, which require the ADC to meet very stringent dynamic performance requirements. With a noise floor of -78.2dBFS, the MAX1418 allows for the design of receivers with superior sensitivity.

The MAX1418 achieves two-tone, spurious-free dynamic range (SFDR) of -85dBc for input tones of 69MHz and 71MHz. Its excellent signal-to-noise ratio (SNR) of 73.6dB and single-tone SFDR performance (SFDR1/SFDR2) of 88dBc/92dBc at f

= 70MHz and a sampling rate of 65Msps make this part ideal for high-performance digital receivers.

The MAX1418 operates from an analog 5V and a digital 3V supply, features a 2.56V

P-P

full-scale input range, and allows for a sampling speed of up to 65Msps. The input T/H operates with a -1dB full-power bandwidth of 260MHz.

The MAX1418 features parallel, CMOS-compatible outputs in two’s-complement format. To enable the interface with a wide range of logic devices, this ADC provides a separate output driver power-supply range of 2.3V to

3.5V. The MAX1418 is manufactured in an 8mm x 8mm, 56-pin thin QFN package with exposed paddle (EP) for low thermal resistance, and is specified for the extended industrial (-40°C to +85°C) temperature range.

Note that IF parts MAX1418, MAX1428, and MAX1430 (see Pin-Compatible Higher/Lower Speed Versions Selection table) are recommended for applications that require high dynamic performance for input frequencies greater than f

CLK

/3. Unlike its baseband counterpart MAX1419, the MAX1418 is optimized for input frequencies greater than f

CLK

/3.

Applications

Cellular Base-Station Transceiver Systems (BTS) Wireless Local Loop (WLL) Single- and Multicarrier Receivers Multistandard Receivers E911 Location Receivers Power Amplifier Linearity Correction Antenna Array Processing

Features

♦ 65Msps Minimum Sampling Rate

♦ -78.2dBFS Noise Floor

♦ Excellent Dynamic Performance

73.6dB SNR at f

= 70MHz and A

= -2dBFS 88dBc/92dBc Single-Tone SFDR1/SFDR2 at f

= 70MHz and AIN= -2dBFS

-85dB Multitone SFDR at f

IN1

= 69MHz

and f

IN2

= 71MHz

♦ Less than 0.25ps Sampling Jitter

♦ Fully Differential Analog Input Voltage Range of

2.56V

P-P

♦ CMOS-Compatible Two’s-Complement Data Output

♦ Separate Data Valid Clock and Overrange Outputs

♦ Flexible-Input Clock Buffer

♦ EV Kit Available for MAX1418

(Order MAX1427EVKIT)

MAX1418

15-Bit, 65Msps ADC with -78.2dBFS

Noise Floor for IF Applications

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

19-3022; Rev 1; 2/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

EVALUATION KIT

AVAILABLE

Pin Configuration appears at end of data sheet.

PART TEMP RANGE PIN-PACKAGE

MAX1418ETN -40°C to +85°C 56 Thin QFN-EP*

Pin-Compatible Higher/Lower

Speed Versions Selection

PART

SPEED GRADE

(Msps)

TARGET

APPLICATION

MAX1418 65 IF MAX1419 65 Baseband MAX1427 80 Baseband MAX1428* 80 IF MAX1429* 100 Baseband MAX1430* 100 IF

*Future product—contact factory for availability.

*EP = Exposed paddle.

MAX1418

15-Bit, 65Msps ADC with -78.2dBFS Noise Floor for IF Applications

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(AVCC= 5V, DVCC= DRVCC= 2.5V, GND = 0, INP and INN driven differentially with -2dBFS, CLKP and CLKN driven differentially with a 2V

P-P

sinusoidal input signal, CL= 5pF at digital outputs, f

CLK

= 65MHz, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical

values are at T

= +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and char-

acterization.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AVCC, DVCC, DRVCCto GND.................................. -0.3V to +6V

INP, INN, CLKP, CLKN, CM to GND........-0.3V to (AV

+ 0.3V)

D0–D14, DAV, DOR to GND..................-0.3V to (DRV

+ 0.3V)

Continuous Power Dissipation (T

= +70°C)

56-Pin Thin QFN (derate 47.6mW/°C above +70°C)................

3809.5mW

Operating Temperature Range ...........................-40°C to +85°C

Thermal Resistance

...................................................21°C/W

Junction Temperature......................................................+150°C

Storage Temperature Range .............................-60°C to +150°C

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DC ACCURACY

Resolution 15 Bits Integral Nonlinearity INL f

= 15MHz

LSB

Differential Nonlinearity DNL f

= 70MHz, no missing codes guaranteed

LSB

Offset Error -12

Gain Error -4 +4

%FS

ANALOG INPUT (INP, INN)

D i ffer enti al Inp ut V ol tag e Rang e

DIFF

P-P

Common-Mode Input Voltage

Self-biased

Differential Input Resistance R

kΩ

Differential Input Capacitance

1pF

Full-Power Analog Bandwidth

-1dB rolloff for a full-scale input

MHz

CONVERSION RATE

Maximum Clock Frequency f

CLK

MHz

Minimum Clock Frequency f

CLK

MHz

Aperture Jitter t

RMS

CLOCK INPUT (CLKP, CLKN)

Full-Scale Differential Input Voltage

Fully differential input drive, V

CLKP

- V

CLKN

0.5 to

3.0

Common-Mode Input Voltage

Self-biased 2.4 V

Differential Input Resistance R

INCLK

kΩ

Differential Input Capacitance

INCLK

1pF

DYNAMIC CHARACTERISTICS

Thermal + Quantization Noise Floor

NF Analog input <-35dBFS

dBFS

±1.5 ±0.4

+12

FPBW

DIFFCLK

Fully differential inputs drive, V

-1dB

DIFF

= V

INP

- V

INN

2.56

4.17

±15%

260

0.21

±15%

-78.2

MAX1418

15-Bit, 65Msps ADC with -78.2dBFS

Noise Floor for IF Applications

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(AVCC= 5V, DVCC= DRVCC= 2.5V, GND = 0, INP and INN driven differentially with -2dBFS, CLKP and CLKN driven differentially with a 2V

P-P

sinusoidal input signal, CL= 5pF at digital outputs, f

CLK

= 65MHz, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical

values are at T

= +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and char-

acterization.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

fIN = 5MHz at -2dBFS 75 fIN = 15MHz at -2dBFS 75 fIN = 35MHz at -2dBFS fIN = 70MHz at -2dBFS 72

SNR

= 170MHz at -6dBFS

fIN = 5MHz at -2dBFS fIN = 15MHz at -2dBFS fIN = 35MHz at -2dBFS fIN = 70MHz at -2dBFS 71

(Note 2)

SINAD

= 170MHz at -6dBFS

fIN = 5MHz at -2dBFS 90 fIN = 15MHz at -2dBFS 90 fIN = 35MHz at -2dBFS 88 fIN = 70MHz at -2dBFS 78 88

(HD2 and HD3) (Note 2)

SFDR1

= 170MHz at -6dBFS

dBc

fIN = 5MHz at -2dBFS 95 fIN = 15MHz at -2dBFS 95 fIN = 35MHz at -2dBFS 93 fIN = 70MHz at -2dBFS

(HD4 and Higher) (Note 2)

SFDR2

= 170MHz at -6dBFS 82

dBc

Two-Tone Intermodulation Distortion

TTIMD

IN1

= 69MHz at -8dBFS;

IN2

= 71MHz at -8dBFS

dBc

Two-Tone Spurious-Free Dynamic Range

IN1

= 69MHz at -12dBFS < f

IN1

< -100dBFS;

IN2

= 71MHz at -12dBFS < f

IN2

< -100dBFS

(Note 2)

dBFS

DIGITAL OUTPUTS (D0–D14, DAV, DOR)

Digital Output-Voltage Low V

0.5 V

Digital Output-Voltage High V

DVCC -

0.5

TIMING CHARACTERISTICS (DV

= DRV

= 2.5V) Figure 4

CLKP/CLKN Duty Cycle

±5

Effective Aperture Delay t

Output Data Delay t

DAT

(Note 3) 3.0 4.5 7.5 ns

Data Valid Delay t

DAV

(Note 3) 5.3 6.5 8.7 ns

Signal-to-Noise Ratio (Note 1)

Signal-to-Noise and Distortion

Spurious-Free Dynamic Range

SFDR

Duty cycle

74.8

73.6

68.5

74.8

74.4

73.3

64.4

67.5

84.5

-85

-100

230

MAX1418

15-Bit, 65Msps ADC with -78.2dBFS Noise Floor for IF Applications

4 _______________________________________________________________________________________

Note 1: Dynamic performance is based on a 32,768-point data record with a sampling frequency of f

SAMPLE

= 65.0117120MHz, an

input frequency of f

= f

SAMPLE

x (35283/32768) = 70.001472MHz, and a frequency bin size of 1984Hz. Close-in (f

±23.8kHz) and low-frequency (DC to 47.6kHz) bins are excluded from the spectrum analysis.

Note 2: Apply the same voltage levels to DV

and DRV

Note 3: Guaranteed by design and characterization.

ELECTRICAL CHARACTERISTICS (continued)

(AVCC= 5V, DVCC= DRVCC= 2.5V, GND = 0, INP and INN driven differentially with -2dBFS, CLKP and CLKN driven differentially with a 2V

P-P

sinusoidal input signal, CL= 5pF at digital outputs, f

CLK

= 65MHz, TA= T

MIN

to T

MAX

, unless otherwise noted. Typical

values are at T

= +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and char-

acterization.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Pipeline Latency

Clock

cycles

CLKP Rising Edge to DATA Not Valid

DNV

(Note 3) 2.6 3.8 5.7 ns

CLKP Rising Edge to DATA Valid (Guaranteed)

DGV

(Note 3) 3.4 5.2 8.6 ns

DATA Setup Time (Before DAV Rising Edge)

SETUP

(Note 3)

CLKP

0.5

CLKP

DATA Hold Time (After DAV Rising Edge)

HOLD

(Note 3)

CLKN

3.6

CLKN

2.8

CLKN

2.0

TIMING CHARACTERISTICS (DV

= DRV

= 3.3V) Figure 4

CLKP/CLKN Duty Cycle

±5

Effective Aperture Delay t

Output Data Delay t

DAT

(Note 3) 2.8 4.1 6.5 ns

Data Valid Delay t

DAV

(Note 3) 5.3 6.3 8.6 ns

Pipeline Latency

Clock

cycles

CLKP Rising Edge to DATA Not Valid

DNV

(Note 3) 2.5 3.4 5.2 ns

CLKP Rising Edge to DATA Valid (Guaranteed)

DGV

(Note 3) 3.2 4.4 7.4 ns

DATA Setup Time (Before DAV Rising Edge)

SETUP

(Note 3)

CLKP

DATA Hold Time (After DAV Rising Edge)

HOLD

(Note 3)

CLKN

3.5

CLKN

2.7

CLKN

2.0

POWER REQUIREMENTS

(Note 2)

DRV

(Note 2)

Analog Supply Current I

AVCC

DVCC

DRV

CLK

= 65MHz, C

LOAD

= 5pF

42 mA

Analog Power Dissipation PDISS

LATENCY

Analog Supply Voltage Range Digital Supply Voltage Range Output Supply Voltage Range

D i g i tal + Outp ut S up p l y C ur r ent

Duty cycle

LATENCY

+ 0.2

+ 1.3

+ 2.4

230

+ 1.7

+ 2.8

5 ±3%

2.5 to 3.5

2.5 to 3.5 382 447

35.5

2000

MAX1418

15-Bit, 65Msps ADC with -78.2dBFS

Noise Floor for IF Applications

_______________________________________________________________________________________ 5

FFT PLOT

(32,768-POINT DATA RECORD,

COHERENT SAMPLING)

MAX1418 toc01

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dBFS)

30252015105

-100

-80

-60

-40

-20

-120 0

CLK

= 65.0117MHz

= 15.0010MHz

= -1.97dBFS

SNR = 75dB

SFDR1 = 87.8dBc SFDR2 = 94.7dBc HD2 = -96.9dBc HD3 = -87.8dBc

FFT PLOT

(32,768-POINT DATA RECORD,

COHERENT SAMPLING)

MAX1418 toc02

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dBFS)

30252015105

-100

-80

-60

-40

-20

-120 0

CLK

= 65.0117MHz

= 34.9997MHz

= -1.98dBFS

SNR = 74.8dB

SFDR1 = 86.55dBc SFDR2 = 93.5dBc HD2 = -92.6dBc HD3 = -86.4dBc

FFT PLOT

(32,768-POINT DATA RECORD,

COHERENT SAMPLING)

MAX1418 toc03

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dBFS)

30252015105

-100

-80

-60

-40

-20

-120 0

CLK

= 65.0117MHz

= 70.0015MHz

= -2.02dBFS SNR = 73.7dB SFDR1 = 85.6dBc SFDR2 = 91.2dBc HD2 = -85.6dBc HD3 = -96.9dBc

FFT PLOT

(32,768-POINT DATA RECORD,

COHERENT SAMPLING)

MAX1418 toc04

ANALOG INPUT FREQUENCY (MHz)

AMPLITUDE (dBFS)

30252015105

-100

-80

-60

-40

-20

-120 0

CLK

= 65.0117MHz

= 169.9992MHz

= -6.01dBFS SNR = 68.5dBc SFDR1 = 67.5dBc SFDR2 = 82.1dBc HD2 = -67.5dBc HD3 = -73.6dBc

5658525 45 105 125 145 165 185

SNR vs. ANALOG INPUT FREQUENCY

CLK

= 65.0117MHz, AIN = -2dBFS)

MAX1418toc05

fIN (MHz)

SNR (dB)

105

5658525 45 105 125 145 165 185

SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY

CLK

= 65.0117MHz, AIN = -2dBFS)

MAX1418toc06

fIN (MHz)

SFDR1/SFDR2 (dBc)

SFDR2

SFDR1

Typical Operating Characteristics

(AV

= 5V, DV

= DRV

= 2.5V, INP and INN driven differentially with a -2dBFS amplitude, CLKP and CLKN driven differentially

with a 2V

P-P

sinusoidal input signal, CL= 5pF at digital outputs, f

CLK

= 65MHz, TA= 25°C. All AC data based on a 32k-point FFT

record and under coherent sampling conditions.)

MAX1418

15-Bit, 65Msps ADC with -78.2dBFS Noise Floor for IF Applications

6 _______________________________________________________________________________________

-105

-95

-75

-85

-65

-55

5658525 45 105 125 145 165 185

HD2/HD3 vs. ANALOG INPUT FREQUENCY

CLK

= 65.0117MHz, AIN = -2dBFS)

MAX1418toc07

fIN (MHz)

HD2/HD3 (dBc)

HD2

HD3

79 78 77 76 75

-70 -50 -40-60 -30 -20 -10 0

FULL-SCALE-TO-NOISE RATIO

vs. ANALOG INPUT AMPLITUDE

CLK

= 65.0117MHz, fIN = 15.0010MHz)

MAX1418toc08

ANALOG INPUT AMPLITUDE (dBFS)

FULL-SCALE-TO-NOISE RATIO (dBFS)

110

105

100

115

120

-70 -60 -50 -40 -30 -20 -10 0

SFDR1/SFDR2 vs. ANALOG INPUT AMPLITUDE

CLK

= 65.0117MHz, fIN = 15.0010MHz)

MAX1418toc09

ANALOG INPUT AMPLITUDE (dBFS)

SFDR1/SFDR2 (dBFS)

SFDR2

SFDR1

-125

-120

-105

-115

-90

-95

-100

-110

-85

-70 -50 -40-60 -30 -20 -10 0

HD2/HD3 vs. ANALOG INPUT AMPLITUDE

CLK

= 65.0117MHz, fIN = 15.0010MHz)

MAX1418toc10

ANALOG INPUT AMPLITUDE (dBFS)

HD2/HD3 (dBFS)

HD2

HD3

79 78 77 76 75

-70 -50 -40-60 -30 -20 -10 0

FULL-SCALE-TO-NOISE RATIO

vs. ANALOG INPUT AMPLITUDE

CLK

= 65.0117MHz, fIN = 70.0015MHz)

MAX1418toc11

ANALOG INPUT AMPLITUDE (dBFS)

FULL-SCALE-TO-NOISE RATIO (dBFS)

100

120 115 110 105

125

130

-70 -60 -50 -40 -30 -20 -10 0

SFDR1/SFDR2 vs. ANALOG INPUT AMPLITUDE

CLK

= 65.0117MHz, fIN = 70.0015MHz)

MAX1418toc12

ANALOG INPUT AMPLITUDE (dBFS)

SFDR1/SFDR2 (dBFS)

SFDR2

SFDR1

Typical Operating Characteristics (continued)

(AV

= 5V, DV

= DRV

= 2.5V, INP and INN driven differentially with a -2dBFS amplitude, CLKP and CLKN driven differentially

with a 2V

P-P

sinusoidal input signal, CL= 5pF at digital outputs, f

CLK

= 65MHz, TA= 25°C. All AC data based on a 32k-point FFT

record and under coherent sampling conditions.)

+ 14 hidden pages