General Description
The MAX1418 is a 5V, high-speed, high-performance
analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) and a 15-bit converter core. The MAX1418 is optimized for multichannel,
multimode receivers, which require the ADC to meet very
stringent dynamic performance requirements. With a
noise floor of -78.2dBFS, the MAX1418 allows for the
design of receivers with superior sensitivity.
The MAX1418 achieves two-tone, spurious-free dynamic
range (SFDR) of -85dBc for input tones of 69MHz and
71MHz. Its excellent signal-to-noise ratio (SNR) of 73.6dB
and single-tone SFDR performance (SFDR1/SFDR2) of
88dBc/92dBc at f
IN
= 70MHz and a sampling rate of
65Msps make this part ideal for high-performance digital
receivers.
The MAX1418 operates from an analog 5V and a digital
3V supply, features a 2.56V
P-P
full-scale input range,
and allows for a sampling speed of up to 65Msps. The
input T/H operates with a -1dB full-power bandwidth of
260MHz.
The MAX1418 features parallel, CMOS-compatible outputs in two’s-complement format. To enable the interface
with a wide range of logic devices, this ADC provides a
separate output driver power-supply range of 2.3V to
3.5V. The MAX1418 is manufactured in an 8mm x 8mm,
56-pin thin QFN package with exposed paddle (EP) for
low thermal resistance, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Note that IF parts MAX1418, MAX1428, and MAX1430
(see Pin-Compatible Higher/Lower Speed Versions
Selection table) are recommended for applications that
require high dynamic performance for input frequencies greater than f
CLK
/3. Unlike its baseband counterpart MAX1419, the MAX1418 is optimized for input
frequencies greater than f
CLK
/3.
Applications
Cellular Base-Station Transceiver Systems (BTS)
Wireless Local Loop (WLL)
Single- and Multicarrier Receivers
Multistandard Receivers
E911 Location Receivers
Power Amplifier Linearity Correction
Antenna Array Processing
Features
♦ 65Msps Minimum Sampling Rate
♦ -78.2dBFS Noise Floor
♦ Excellent Dynamic Performance
73.6dB SNR at f
IN
= 70MHz and A
IN
= -2dBFS
88dBc/92dBc Single-Tone SFDR1/SFDR2 at
f
IN
= 70MHz and AIN= -2dBFS
-85dB Multitone SFDR at f
IN1
= 69MHz
and f
IN2
= 71MHz
♦ Less than 0.25ps Sampling Jitter
♦ Fully Differential Analog Input Voltage Range of
2.56V
P-P
♦ CMOS-Compatible Two’s-Complement Data Output
♦ Separate Data Valid Clock and Overrange Outputs
♦ Flexible-Input Clock Buffer
♦ EV Kit Available for MAX1418
(Order MAX1427EVKIT)
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3022; Rev 1; 2/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Pin Configuration appears at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX1418ETN -40°C to +85°C 56 Thin QFN-EP*
Pin-Compatible Higher/Lower
Speed Versions Selection
PART
SPEED GRADE
(Msps)
TARGET
APPLICATION
MAX1418 65 IF
MAX1419 65 Baseband
MAX1427 80 Baseband
MAX1428* 80 IF
MAX1429* 100 Baseband
MAX1430* 100 IF
*Future product—contact factory for availability.
*EP = Exposed paddle.
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AVCC= 5V, DVCC= DRVCC= 2.5V, GND = 0, INP and INN driven differentially with -2dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, CL= 5pF at digital outputs, f
CLK
= 65MHz, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVCC, DVCC, DRVCCto GND.................................. -0.3V to +6V
INP, INN, CLKP, CLKN, CM to GND........-0.3V to (AV
CC
+ 0.3V)
D0–D14, DAV, DOR to GND..................-0.3V to (DRV
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
56-Pin Thin QFN (derate 47.6mW/°C above +70°C)................
3809.5mW
Operating Temperature Range ...........................-40°C to +85°C
Thermal Resistance
θ
J
A
...................................................21°C/W
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution 15 Bits
Integral Nonlinearity INL f
IN
= 15MHz
LSB
Differential Nonlinearity DNL f
IN
= 70MHz, no missing codes guaranteed
LSB
Offset Error -12
mV
Gain Error -4 +4
%FS
ANALOG INPUT (INP, INN)
D i ffer enti al Inp ut V ol tag e Rang e
V
DIFF
V
P-P
Common-Mode Input Voltage
V
CM
Self-biased
V
Differential Input Resistance R
IN
1
kΩ
Differential Input Capacitance
C
IN
1pF
Full-Power Analog Bandwidth
-1dB rolloff for a full-scale input
MHz
CONVERSION RATE
Maximum Clock Frequency f
CLK
65
MHz
Minimum Clock Frequency f
CLK
20
MHz
Aperture Jitter t
AJ
ps
RMS
CLOCK INPUT (CLKP, CLKN)
Full-Scale Differential Input
Voltage
Fully differential input drive, V
CLKP
- V
CLKN
0.5 to
3.0
V
Common-Mode Input Voltage
V
CM
Self-biased 2.4 V
Differential Input Resistance R
INCLK
2
kΩ
Differential Input Capacitance
C
INCLK
1pF
DYNAMIC CHARACTERISTICS
Thermal + Quantization
Noise Floor
NF Analog input <-35dBFS
dBFS
±1.5
±0.4
+12
FPBW
V
DIFFCLK
Fully differential inputs drive, V
-1dB
DIFF
= V
INP
- V
INN
2.56
4.17
±15%
260
0.21
±15%
-78.2
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AVCC= 5V, DVCC= DRVCC= 2.5V, GND = 0, INP and INN driven differentially with -2dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, CL= 5pF at digital outputs, f
CLK
= 65MHz, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
fIN = 5MHz at -2dBFS 75
fIN = 15MHz at -2dBFS 75
fIN = 35MHz at -2dBFS
fIN = 70MHz at -2dBFS 72
SNR
f
IN
= 170MHz at -6dBFS
dB
fIN = 5MHz at -2dBFS
fIN = 15MHz at -2dBFS
fIN = 35MHz at -2dBFS
fIN = 70MHz at -2dBFS 71
(Note 2)
SINAD
f
IN
= 170MHz at -6dBFS
dB
fIN = 5MHz at -2dBFS 90
fIN = 15MHz at -2dBFS 90
fIN = 35MHz at -2dBFS 88
fIN = 70MHz at -2dBFS 78 88
(HD2 and HD3)
(Note 2)
SFDR1
f
IN
= 170MHz at -6dBFS
dBc
fIN = 5MHz at -2dBFS 95
fIN = 15MHz at -2dBFS 95
fIN = 35MHz at -2dBFS 93
fIN = 70MHz at -2dBFS
92
(HD4 and Higher)
(Note 2)
SFDR2
f
IN
= 170MHz at -6dBFS 82
dBc
Two-Tone Intermodulation
Distortion
TTIMD
f
IN1
= 69MHz at -8dBFS;
f
IN2
= 71MHz at -8dBFS
dBc
Two-Tone Spurious-Free
Dynamic Range
f
IN1
= 69MHz at -12dBFS < f
IN1
< -100dBFS;
f
IN2
= 71MHz at -12dBFS < f
IN2
< -100dBFS
(Note 2)
dBFS
DIGITAL OUTPUTS (D0–D14, DAV, DOR)
Digital Output-Voltage Low V
OL
0.5 V
Digital Output-Voltage High V
OH
DVCC -
0.5
V
TIMING CHARACTERISTICS (DV
CC
= DRV
CC
= 2.5V) Figure 4
CLKP/CLKN Duty Cycle
50
±5
%
Effective Aperture Delay t
AD
ps
Output Data Delay t
DAT
(Note 3) 3.0 4.5 7.5 ns
Data Valid Delay t
DAV
(Note 3) 5.3 6.5 8.7 ns
Signal-to-Noise Ratio (Note 1)
Signal-to-Noise and Distortion
Spurious-Free Dynamic Range
Spurious-Free Dynamic Range
SFDR
TT
Duty cycle
74.8
73.6
68.5
74.8
74.8
74.4
73.3
64.4
67.5
84.5
-85
-100
230
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
4 _______________________________________________________________________________________
Note 1: Dynamic performance is based on a 32,768-point data record with a sampling frequency of f
SAMPLE
= 65.0117120MHz, an
input frequency of f
IN
= f
SAMPLE
x (35283/32768) = 70.001472MHz, and a frequency bin size of 1984Hz. Close-in (f
IN
±23.8kHz) and low-frequency (DC to 47.6kHz) bins are excluded from the spectrum analysis.
Note 2: Apply the same voltage levels to DV
CC
and DRV
CC
Note 3: Guaranteed by design and characterization.
ELECTRICAL CHARACTERISTICS (continued)
(AVCC= 5V, DVCC= DRVCC= 2.5V, GND = 0, INP and INN driven differentially with -2dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, CL= 5pF at digital outputs, f
CLK
= 65MHz, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted. ≥+25°C guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Pipeline Latency
3
Clock
cycles
CLKP Rising Edge to DATA
Not Valid
t
DNV
(Note 3) 2.6 3.8 5.7 ns
CLKP Rising Edge to DATA
Valid (Guaranteed)
t
DGV
(Note 3) 3.4 5.2 8.6 ns
DATA Setup Time
(Before DAV Rising Edge)
t
SETUP
(Note 3)
t
CLKP
-
0.5
t
CLKP
t
CLKP
ns
DATA Hold Time
(After DAV Rising Edge)
t
HOLD
(Note 3)
t
CLKN
-
3.6
t
CLKN
-
2.8
t
CLKN
-
2.0
ns
TIMING CHARACTERISTICS (DV
CC
= DRV
CC
= 3.3V) Figure 4
CLKP/CLKN Duty Cycle
50
±5
%
Effective Aperture Delay t
AD
ps
Output Data Delay t
DAT
(Note 3) 2.8 4.1 6.5 ns
Data Valid Delay t
DAV
(Note 3) 5.3 6.3 8.6 ns
Pipeline Latency
3
Clock
cycles
CLKP Rising Edge to
DATA Not Valid
t
DNV
(Note 3) 2.5 3.4 5.2 ns
CLKP Rising Edge to
DATA Valid (Guaranteed)
t
DGV
(Note 3) 3.2 4.4 7.4 ns
DATA Setup Time
(Before DAV Rising Edge)
t
SETUP
(Note 3)
t
CLKP
t
CLKP
t
CLKP
ns
DATA Hold Time
(After DAV Rising Edge)
t
HOLD
(Note 3)
t
CLKN
-
3.5
t
CLKN
-
2.7
t
CLKN
-
2.0
ns
POWER REQUIREMENTS
AV
CC
V
DV
CC
(Note 2)
V
DRV
CC
(Note 2)
V
Analog Supply Current I
AVCC
mA
I
DVCC
+
DRV
CC
f
CLK
= 65MHz, C
LOAD
= 5pF
42 mA
Analog Power Dissipation PDISS
mW
t
LATENCY
Analog Supply Voltage Range
Digital Supply Voltage Range
Output Supply Voltage Range
D i g i tal + Outp ut S up p l y C ur r ent
Duty cycle
t
LATENCY
+ 0.2
+ 1.3
+ 2.4
230
+ 1.7
+ 2.8
5 ±3%
2.5 to 3.5
2.5 to 3.5
382 447
35.5
2000
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
_______________________________________________________________________________________ 5
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1418 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
30252015105
-100
-80
-60
-40
-20
0
-120
0
f
CLK
= 65.0117MHz
f
IN
= 15.0010MHz
A
IN
= -1.97dBFS
SNR = 75dB
SFDR1 = 87.8dBc
SFDR2 = 94.7dBc
HD2 = -96.9dBc
HD3 = -87.8dBc
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1418 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
30252015105
-100
-80
-60
-40
-20
0
-120
0
f
CLK
= 65.0117MHz
f
IN
= 34.9997MHz
A
IN
= -1.98dBFS
SNR = 74.8dB
SFDR1 = 86.55dBc
SFDR2 = 93.5dBc
HD2 = -92.6dBc
HD3 = -86.4dBc
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1418 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
30252015105
-100
-80
-60
-40
-20
0
-120
0
f
CLK
= 65.0117MHz
f
IN
= 70.0015MHz
A
IN
= -2.02dBFS
SNR = 73.7dB
SFDR1 = 85.6dBc
SFDR2 = 91.2dBc
HD2 = -85.6dBc
HD3 = -96.9dBc
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1418 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
30252015105
-100
-80
-60
-40
-20
0
-120
0
f
CLK
= 65.0117MHz
f
IN
= 169.9992MHz
A
IN
= -6.01dBFS
SNR = 68.5dBc
SFDR1 = 67.5dBc
SFDR2 = 82.1dBc
HD2 = -67.5dBc
HD3 = -73.6dBc
68
70
69
73
72
71
75
76
74
77
5658525 45 105 125 145 165 185
SNR vs. ANALOG INPUT FREQUENCY
(f
CLK
= 65.0117MHz, AIN = -2dBFS)
MAX1418toc05
fIN (MHz)
SNR (dB)
55
65
85
75
95
105
5658525 45 105 125 145 165 185
SFDR1/SFDR2 vs. ANALOG INPUT FREQUENCY
(f
CLK
= 65.0117MHz, AIN = -2dBFS)
MAX1418toc06
fIN (MHz)
SFDR1/SFDR2 (dBc)
SFDR2
SFDR1
Typical Operating Characteristics
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, INP and INN driven differentially with a -2dBFS amplitude, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, CL= 5pF at digital outputs, f
CLK
= 65MHz, TA= 25°C. All AC data based on a 32k-point FFT
record and under coherent sampling conditions.)
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
6 _______________________________________________________________________________________
-105
-95
-75
-85
-65
-55
5658525 45 105 125 145 165 185
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(f
CLK
= 65.0117MHz, AIN = -2dBFS)
MAX1418toc07
fIN (MHz)
HD2/HD3 (dBc)
HD2
HD3
70
71
74
72
79
78
77
76
75
73
80
-70 -50 -40-60 -30 -20 -10 0
FULL-SCALE-TO-NOISE RATIO
vs. ANALOG INPUT AMPLITUDE
(f
CLK
= 65.0117MHz, fIN = 15.0010MHz)
MAX1418toc08
ANALOG INPUT AMPLITUDE (dBFS)
FULL-SCALE-TO-NOISE RATIO (dBFS)
85
90
110
105
100
95
115
120
-70 -60 -50 -40 -30 -20 -10 0
SFDR1/SFDR2 vs. ANALOG INPUT AMPLITUDE
(f
CLK
= 65.0117MHz, fIN = 15.0010MHz)
MAX1418toc09
ANALOG INPUT AMPLITUDE (dBFS)
SFDR1/SFDR2 (dBFS)
SFDR2
SFDR1
-125
-120
-105
-115
-90
-95
-100
-110
-85
-70 -50 -40-60 -30 -20 -10 0
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
(f
CLK
= 65.0117MHz, fIN = 15.0010MHz)
MAX1418toc10
ANALOG INPUT AMPLITUDE (dBFS)
HD2/HD3 (dBFS)
HD2
HD3
70
71
74
72
79
78
77
76
75
73
80
-70 -50 -40-60 -30 -20 -10 0
FULL-SCALE-TO-NOISE RATIO
vs. ANALOG INPUT AMPLITUDE
(f
CLK
= 65.0117MHz, fIN = 70.0015MHz)
MAX1418toc11
ANALOG INPUT AMPLITUDE (dBFS)
FULL-SCALE-TO-NOISE RATIO (dBFS)
80
100
95
85
90
120
115
110
105
125
130
-70 -60 -50 -40 -30 -20 -10 0
SFDR1/SFDR2 vs. ANALOG INPUT AMPLITUDE
(f
CLK
= 65.0117MHz, fIN = 70.0015MHz)
MAX1418toc12
ANALOG INPUT AMPLITUDE (dBFS)
SFDR1/SFDR2 (dBFS)
SFDR2
SFDR1
Typical Operating Characteristics (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, INP and INN driven differentially with a -2dBFS amplitude, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, CL= 5pF at digital outputs, f
CLK
= 65MHz, TA= 25°C. All AC data based on a 32k-point FFT
record and under coherent sampling conditions.)
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
_______________________________________________________________________________________ 7
-140
-130
-100
-120
-90
-110
-80
-70 -50 -40-60 -30 -20 -10 0
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
(f
CLK
= 65.0117MHz, fIN = 70.0015MHz)
MAX1418toc13
ANALOG INPUT AMPLITUDE (dBFS)
HD2/HD3 (dBFS)
HD2
HD3
70
71
74
72
73
76
77
75
78
20 4030 50 60 70 80
SNR vs. SAMPLING FREQUENCY
(f
IN
= 15.2MHz, AIN = -2dBFS)
MAX1418toc14
f
CLK
(MHz)
SNR (dB)
75
85
80
95
90
100
105
20 30 40 50 60 70 80
SFDR1/SFDR2 vs. SAMPLING FREQUENCY
(f
IN
= 15.2MHz, AIN = -2dBFS)
MAX1418toc15
f
CLK
(MHz)
SFDR1/SFDR2 (dBc)
SFDR2
SFDR1
-110
-105
-85
-95
-75
-90
-100
-80
-70
20 30 40 50 60 70 80
HD2/HD3 vs. SAMPLING FREQUENCY
(f
IN
= 15.2MHz, AIN = -2dBFS)
MAX1418toc16
f
CLK
(MHz)
HD2/HD3 (dBc)
HD2
HD3
Typical Operating Characteristics (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, INP and INN driven differentially with a -2dBFS amplitude, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, CL= 5pF at digital outputs, f
CLK
= 65MHz, TA= 25°C. All AC data based on a 32k-point FFT
record and under coherent sampling conditions.)
70
71
73
72
75
76
74
77
-40 10 35-15 60 85
SNR vs. TEMPERATURE
(f
CLK
= 65.0117MHz, fIN = 15.0010MHz,
A
IN
= -2dBFS)
MAX1418toc17
TEMPERATURE (°C)
SNR (dB)
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
8 _______________________________________________________________________________________
70
72
74
71
73
75
-40 10 35-15 60 85
SNR vs. TEMPERATURE
(f
CLK
= 65.0117MHz, fIN = 70.0015MHz,
A
IN
= -2dBFS)
MAX1418toc21
TEMPERATURE (°C)
SNR (dB)
70
72
74
71
73
75
-40 10 35-15 60 85
SINAD vs. TEMPERATURE
(f
CLK
= 65.0117MHz, fIN = 70.0015MHz,
A
IN
= -2dBFS)
MAX1418toc22
TEMPERATURE (°C)
SINAD (dB)
Typical Operating Characteristics (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, INP and INN driven differentially with a -2dBFS amplitude, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, CL= 5pF at digital outputs, f
CLK
= 65MHz, TA= 25°C. All AC data based on a 32k-point FFT
record and under coherent sampling conditions.)
70
71
73
72
75
76
74
77
-40 10 35-15 60 85
SINAD vs. TEMPERATURE
(f
CLK
= 65.0117MHz, fIN = 15.0010MHz,
A
IN
= -2dBFS)
MAX1418toc18
TEMPERATURE (°C)
SINAD (dB)
75
85
80
95
100
90
105
-40 10 35-15 60 85
SFDR1/SFDR2 vs. TEMPERATURE
(f
CLK
= 65.0117MHz, fIN = 15.0010MHz,
A
IN
= -2dBFS)
MAX1418toc19
TEMPERATURE (°C)
SFDR1/SFDR2 (dBc)
SFDR2
SFDR1
-115
-105
-110
-85
-75
-95
-90
-80
-100
-70
-40 10 35-15 60 85
HD2/HD3 vs. TEMPERATURE
(f
CLK
= 65.0117MHz, fIN = 15.0010MHz,
A
IN
= -2dBFS)
MAX1418toc20
TEMPERATURE (°C)
HD2/HD3 (dBc)
HD2
HD3
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
_______________________________________________________________________________________ 9
70
80
95
90
75
85
100
-40 10 35-15 60 85
SFDR1/SFDR2 vs. TEMPERATURE
(f
CLK
= 65.0117MHz, fIN = 70.0015MHz,
A
IN
= -2dBFS)
MAX1418toc23
TEMPERATURE (°C)
SFDR1/SFDR2 (dBc)
SFDR2
SFDR1
1900
2100
2000
2050
1950
2150
2200
4.85 5.00 5.104.90 5.05 5.154.95 5.20 5.25
POWER DISSIPATION vs. SUPPLY VOLTAGE
(f
CLK
= 65.0117MHz, fIN = 15.0010MHz,
A
IN
= -2dBFS)
MAX1418toc26
SUPPLY VOLTAGE (V)
POWER DISSIPATION (mW)
TWO-TONE IMD PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1418 toc27
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
30252015105
-100
-80
-60
-40
-20
0
-120
0
f
CLK
= 65.0117MHz
f
IN
= 69.0017MHz
f
IN2
= 71.0014MHz
A
IN1
= A
IN2
= -8dBFS
f
IN1
2f
IN1
- f
IN2
2f
IN2
- f
IN1
f
IN2
-110
-90
-75
-80
-100
-95
-105
-85
-70
-40 10 35-15 60 85
HD2/HD3 vs. TEMPERATURE
(f
CLK
= 65.0117MHz, fIN = 70.0015MHz,
A
IN
= -2dBFS)
MAX1418toc24
TEMPERATURE (°C)
HD2/HD3 (dBc)
HD2
HD3
1980
2000
2015
2010
1990
1995
1985
2005
2020
-40 10 35-15 60 85
POWER DISSIPATION vs. TEMPERATURE
(f
CLK
= 65.0117MHz, fIN = 15.0010MHz,
A
IN
= -2dBFS)
MAX1418toc25
TEMPERATURE (°C)
POWER DISSIPATION (mW)
Typical Operating Characteristics (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, INP and INN driven differentially with a -2dBFS amplitude, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, CL= 5pF at digital outputs, f
CLK
= 65MHz, TA= 25°C. All AC data based on a 32k-point FFT
record and under coherent sampling conditions.)
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1, 2, 3, 6, 9, 12, 14–17,
GND
Converter Ground. Analog, digital, and output driver grounds are internally
connected to the same potential. Connect the converter’s EP to GND.
4 CLKP Differential Clock, Positive Input Terminal
5 CLKN Differential Clock, Negative Input Terminal
AV
CC
Analog Supply Voltage. Provide local bypassing to ground with 0.1µF to 0.22µF
capacitors.
10 INP Differential Analog Input, Positive Terminal
11 INN Differential Analog Input, Negative/Complementary Terminal
13 CM Common-Mode Reference Terminal
29 DV
CC
Digital Supply Voltage. Provide local bypassing to ground with 0.1µF to 0.22µF
capacitors.
31, 41, 42, 51 DRV
CC
Digital Output Driver Supply Voltage. Provide local bypassing to ground with
0.1µF to 0.22µF capacitors.
32 DOR
Data Overrange Bit. This control line flags an overrange condition in the ADC.
If DOR transitions high, an overrange condition was detected. If DOR remains low,
the ADC operates within the allowable full-scale range.
33 D0 Digital CMOS Output Bit 0 (LSB)
34 D1 Digital CMOS Output Bit 1
35 D2 Digital CMOS Output Bit 2
36 D3 Digital CMOS Output Bit 3
37 D4 Digital CMOS Output Bit 4
38 D5 Digital CMOS Output Bit 5
39 D6 Digital CMOS Output Bit 6
40 D7 Digital CMOS Output Bit 7
43 D8 Digital CMOS Output Bit 8
44 D9 Digital CMOS Output Bit 9
45 D10 Digital CMOS Output Bit 10
46 D11 Digital CMOS Output Bit 11
47 D12 Digital CMOS Output Bit 12
48 D13 Digital CMOS Output Bit 13
49 D14 Digital CMOS Output Bit 14 (MSB)
50 DAV
Data Valid Output. This output can be used as a clock control line to drive an
external buffer or data-acquisition system. The typical delay time between the
falling edge of the converter clock and the rising edge of DAV is 6.5ns.
20, 23, 26, 27, 30, 52–56, EP
7, 8, 18, 19, 21, 22, 24, 25, 28
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
______________________________________________________________________________________ 11
Detailed Description
Figure 1 provides an overview of the MAX1418 architecture. The MAX1418 employs an input T/H amplifier,
which has been optimized for low thermal noise and
low distortion. The high-impedance differential inputs to
the T/H amplifier (INP and INN) are self-biased at
4.17V, and support a full-scale differential input voltage
of 2.56V
P-P
. The output of the T/H amplifier is fed to a
multistage pipelined ADC core, which has also been
optimized to achieve a very low thermal noise floor and
low distortion.
A clock buffer receives a differential input clock waveform and generates a low-jitter clock signal for the input
T/H. The signal at the analog inputs is sampled at the
rising edge of the differential clock waveform. The differential clock inputs (CLKP and CLKN) are highimpedance inputs, are self-biased at 2.4V, and support
differential clock waveforms from 0.5V
P-P
to 3.0V
P-P
.
The outputs from the multistage pipelined ADC core
are delivered to error correction and formatting logic,
which in turn, deliver the 15-bit output code in two’scomplement format to digital output drivers. The output
drivers provide CMOS-compatible outputs with levels
programmable over a 2.3V to 3.5V range.
Analog Inputs and
Common Mode (INP, INN, CM)
The signal inputs to the MAX1418 (INP and INN) are
balanced differential inputs. This differential configuration provides immunity to common-mode noise coupling and rejection of even-order harmonic terms. The
differential signal inputs to the MAX1418 should be ACcoupled and carefully balanced to achieve the best
dynamic performance (see the Applications Information
section for more detail). AC-coupling of the input signal
is easily accomplished because the MAX1418 inputs
are self-biasing as illustrated in Figure 2. Although the
T/H inputs are high impedance, the actual differential
input impedance is nominally 1kΩ because of the two
500Ω bias resistors connected from each input to the
common-mode reference.
The CM pin provides a monitor of the input commonmode self-bias potential. In most applications, in which
the input signal is AC-coupled, this pin is not connected. If DC-coupling of the input signal is required, this
pin may be used to construct a DC servo loop to control the input common-mode potential. See the
Applications Information section for more details.
T/H
CORRECTION
LOGIC + OUTPUT
BUFFERS
INTERNAL
TIMING
INTERNAL
REFERENCE
INP
INN
CM
CLKP
CLKN
DAV
15
DATA BITS D0 THROUGH D14
AV
CC
DRV
CC
DV
CC
GND
MULTISTAGE
PIPELINE ADC CORE
CLOCK
BUFFER
MAX1418
Figure 1. Simplified MAX1418 Diagram
BUFFER
INTERNAL REFERENCE
AND BIASING CIRCUIT
T/H AMPLIFIER
T/H AMPLIFIER
500Ω
500Ω
CM
INP
INN
TO 1. QUANTIZER STAGE
TO 1. QUANTIZER STAGE
1kΩ
Figure 2. Simplified Analog and Common-Mode Input Architecture
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
12 ______________________________________________________________________________________
On-Chip Reference Circuit
The MAX1418 incorporates an on-chip 2.5V, low-drift
bandgap reference. This reference potential establishes the full-scale range for the converter, which is nominally 2.56V
P-P
differential. The internal reference
potential is not accessible to the user, so the full-scale
range for the MAX1418 cannot be externally adjusted.
Figure 3 shows how the reference is used to generate
the common-mode bias potential for the analog inputs.
The common-mode input bias is set to two diode potentials above the bandgap reference potential, and so
varies over temperature.
Clock Inputs (CLKP, CLKN)
The differential clock buffer for the MAX1418 has been
designed to accept an AC-coupled clock waveform. Like
the signal inputs, the clock inputs are self-biasing. In this
case, the common-mode bias potential is 2.4V and each
input is connected to the reference potential through a
1kΩ resistor. Consequently, the differential input resistance associated with the clock inputs is 2kΩ. While differential clock signals as low as 0.5V
P-P
may be used to
drive the clock inputs, best dynamic performance is
achieved with clock input voltage levels of 2V
P-P
to 3V
P-P
.
Jitter on the clock signal translates directly to jitter (noise)
on the sampled signal. Therefore, the clock source
should be a low-jitter (low phase noise) source. See the
Applications Information section for additional details on
driving the clock inputs.
System Timing Requirements
Figure 4 depicts the timing relationships for the signal
input, clock input, data output, and DAV output. The
variables shown in the figure correspond to the various
timing specifications in the Electrical Characteristics
section. These include:
• t
DAT
: Delay from the rising edge of the clock until the
50% point of the output data transition
• t
DAV
: Delay from the falling edge of the clock until the
50% point of the DAV rising edge
• t
DNV
: Time from the rising edge of the clock until data
is no longer valid
• t
DGV
: Time from the rising edge of the clock until data
is guaranteed to be valid
1mA
2mA
INP/INN
COMMON-MODE
REFERENCE
500Ω 500Ω
1kΩ
2.5V
Figure 3. Simplified Reference Architecture
INP
INN
D0–D14
DOR
DAV
N + 1NN + 2N + 3
CLKP
CLKN
t
AD
t
CLKP
t
CLKN
N - 3 N - 2 N - 1 N
t
S
t
H
t
DAT
t
DAV
t
DNV
t
DGV
Figure 4. System and Output Timing Diagram
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
______________________________________________________________________________________ 13
• t
SETUP
: Time from data guaranteed valid until the ris-
ing edge of DAV
• t
HOLD
: Time from the rising edge of DAV until data is
no longer valid
• t
CLKP
: Time from the 50% point of the rising edge to
the 50% point of the falling edge of the clock signal
• t
CLKN
: Time from the 50% point of the falling edge to
the 50% point of the rising edge of the clock signal
The MAX1418 samples the input signal on the rising
edge of the input clock. Output data is valid on the rising edge of the DAV signal, with a data latency of three
clock cycles. Note that the clock duty cycle must be
50% ±5% for proper operation.
Digital Outputs (D0–D14, DAV, DOR)
The logic-high level of the CMOS-compatible digital
outputs (D0–D14, DAV, and DOR) can be set in the
2.3V to 3.5V range. This is accomplished by setting the
voltage at the DVCCand DRVCCpins to the desired
logic-high level. Note that the DVCCand DRVCCvoltages must be the same value.
For best performance, the capacitive loading on the digital
outputs of the MAX1418 should be kept as low as possible
(<10pF). Large capacitive loads result in large charging
currents during data transitions, which may feed back into
the analog section of the ADC and create distortion terms.
The loading capacitance is kept low by keeping the output
traces short and by driving a single CMOS buffer or latch
input (as opposed to multiple CMOS inputs).
Inserting small series resistors (220Ω or less) between
the MAX1418 outputs and the digital load, placed as
closely as possible to the output pins, is helpful in controlling the size of the charging currents during data
transitions and can improve dynamic performance.
Keep the trace length from the resistor to the load as
short as possible to minimize trace capacitance.
The output data is in two’s complement format, as illustrated in Table 1.
Data is valid at the rising edge of DAV (Figure 4), and
DAV can be used as a clock signal to latch the output
data. The DAV output provides twice the drive strength
of the data outputs, and may therefore be used to drive
multiple data latches.
The DOR output is used to identify an overrange condition. If the input signal exceeds the positive or negative
full-scale range for the MAX1418, then DOR is asserted
high. The timing for DOR is identical to the timing for
the data outputs, and DOR therefore provides an overrange indication on a sample-by-sample basis.
Table 1. MAX1418 Digital Output Coding
INP
ANALOG VOLTAGE LEVEL
INN
ANALOG VOLTAGE LEVEL
D14–D0
TWO’S COMPLEMENT CODE
V
REF
+ 0.64V V
REF
- 0.64V
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(positive full scale)
V
REF
V
REF
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(midscale + δ)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(midscale - δ)
V
REF
- 0.64V V
REF
+ 0.64V
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(negative full scale)
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
14 ______________________________________________________________________________________
Applications Information
Differential, AC-Coupled Clock Input
The clock inputs to the MAX1418 are designed to be
driven with an AC-coupled differential signal, and best
performance is achieved under these conditions.
However, it is often the case that the available clock
source is single ended. Figure 5 demonstrates one
method for converting a single-ended clock signal into
a differential signal through a transformer. In this example, the transformer turns ratio from the primary to secondary side is 1:1.414. The impedance ratio from
primary to secondary is the square of the turns ratio, or
1:2, so that terminating the secondary side with a 100Ω
differential resistance results in a 50Ω load looking into
the primary side of the transformer. The termination
resistor in this example comprises the series combination of two 50Ω resistors with their common node ACcoupled to ground. Alternatively, a single 100Ω resistor
across the two inputs with no common-mode connection could be employed.
In the example of Figure 5, the secondary side of the
transformer is coupled directly to the clock inputs.
Since the clock inputs are self-biasing, the center tap of
the transformer must be AC-coupled to ground or left
floating. If the center tap of the secondary were DCcoupled to ground, then it would be necessary to add
blocking capacitors in series with the clock inputs.
Clock jitter is generally improved if the clock signal has
a high slew rate at the time of its zero crossing.
Therefore, if a sinusoidal source is used to drive the
clock inputs, it is desirable that the clock amplitude be
as large as possible to maximize the zero-crossing
slew rate. The back-to-back Schottky diodes shown in
Figure 5 are not required as long as the input signal is
held to 3V
P-P
differential or less. If a larger amplitude
signal is provided (to maximize the zero-crossing slew
rate), then the diodes serve to limit the differential signal swing at the clock inputs.
Any differential-mode noise coupled to the clock inputs
translates to clock jitter and degrades the SNR performance of the MAX1418. Any differential-mode coupling
of the analog input signal into the clock inputs results in
harmonic distortion. Consequently, it is important that
the clock lines be well isolated from the analog signal
input and from the digital outputs. See the PC Board
Layout Considerations section for more discussion on
noise coupling.
Differential, AC-Coupled Analog Input
The analog inputs (INP and INN) are designed to be driven with a differential AC-coupled signal. It is extremely
important that these inputs be accurately balanced. Any
common-mode signal applied to these inputs degrades
even-order distortion terms. Therefore, any attempt at
driving these inputs in a single-ended fashion results in
significant even-order distortion terms.
Figure 6 presents one method for converting a singleended signal to a balanced differential signal using a
transformer. The primary-to-secondary turns ratio in this
example is 1:1.414. The impedance ratio is the square
of the turns ratio, so in this example, the impedance
ratio is 1:2. To achieve a 50Ω input impedance at the
primary side of the transformer, the secondary side is
terminated with a 112Ω differential load. This load, in
shunt with the differential input resistance of the
MAX1418, results in a 100Ω differential load on the secondary side. It is reasonable to use a larger transformer
turns ratio to achieve a larger signal step-up, and this
may be desirable to relax the drive requirements for the
circuitry driving the MAX1418. However, the larger the
MAX1418
50Ω
50Ω
0.1µF
0.1µF 0.01µF 0.1µF 0.01µF
BACK-TO-BACK DIODE
T2-1T-KK81
15
D0–D14
AV
CC
DVCC DRV
CC
GND
CLKP
CLKN
INP
INN
Figure 5. Transformer-Coupled Clock Input Configuration
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
______________________________________________________________________________________ 15
turns ratio, the larger the effect of the differential input
resistance of the MAX1418 on the primary referred
input resistance. At a turns ratio of 1:4.47, the 1kΩ dif-
ferential input resistance of the MAX1418 by itself
results in a primary referred input resistance of 50Ω.
Although the center tap of the transformer in Figure 6 is
shown floating, it may be AC-coupled to ground.
However, experience has shown that better balance is
achieved if the center tap is left floating.
As stated previously, the signal inputs to the MAX1418
must be accurately balanced to achieve the best evenorder distortion performance. Figure 7 provides
improved balance over the circuit of Figure 6 by adding
a balun on the primary side of the transformer, and can
yield substantial improvement in even-order distortion
terms over the circuit of Figure 6.
One note of caution in relation to transformers is important. Any DC current passed through the primary or
secondary windings of a transformer may magnetically
bias the transformer core. When this happens, the
transformer is no longer accurately balanced and a
degradation in the distortion of the MAX1418 may be
observed. The core must be demagnetized to return to
balanced operation.
MAX1418
56Ω
56Ω
0.1µF
0.1µF 0.1µF
T2-1T-KK81
15
D0–D14
AV
CC
DVCC DRV
CC
GND
CLKP CLKN
INP
INN
SINGLE-ENDED
INPUT TERMINAL
Figure 6. Transformer-Coupled Analog Input Configuration
MAX1418
56Ω
56Ω
0.1µF
0.1µF 0.1µF
T2-1T-KK81
T2-1T-KK81
15
D0–D14
AV
CC
DVCC DRV
CC
GND
CLKP CLKN
INP
INN
POSITIVE
TERMINAL
Figure 7. Transformer-Coupled Analog Input Configuration with Primary-Side Transformer
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
16 ______________________________________________________________________________________
DC-Coupled Analog Input
While AC-coupling of the input signal is the proper
means for achieving the best dynamic performance, it
is possible to DC-couple the inputs by making use of
the CM potential. Figure 8 shows one method for
accomplishing DC-coupling. The common-mode
potentials at the outputs of amplifiers OA1 and OA2 are
“servoed” by the action of amplifier OA3 to be equal to
the CM potential of the MAX1418. Care must be taken
to ensure that the common-mode loop is stable, and
the R
F/RG
ratios of both half circuits must be well
matched to ensure balance.
PC Board Layout Considerations
The performance of any high-dynamic-range, highsample-rate converter can be compromised by poor
PC board layout practices. The MAX1418 is no exception to the rule, and careful layout techniques must be
observed to achieve the specified performance. Layout
issues are addressed in the following four categories:
1) Layer assignments
2) Signal routing
3) Grounding
4) Supply routing and bypassing
The MAX1427 evaluation board (MAX1427 EV kit) pro-
vides an excellent frame of reference for board layout,
and the discussion that follows is consistent with the
practices incorporated on the evaluation board.
Layer Assignments
The MAX1427 EV kit is a six-layer board, and the
assignment of layers is discussed in this context. It is
recommended that the ground plane be on a layer
between the signal routing layer and the supply routing
layer(s). This practice prevents coupling from the supply lines into the signal lines. The MAX1427 EV kit PC
board places the signal lines on the top (component)
layer and the ground plane on layer 2. Any region on
the top layer not devoted to signal routing is filled with
ground plane with vias to layer 2. Layers 3 and 4 are
devoted to supply routing, layer 5 is another ground
plane, and layer 6 is used for the placement of additional components and for additional signal routing.
A four-layer implementation is also feasible using layer
1 for signal lines, layer 2 as a ground plane, layer 3 for
supply routing, and layer 4 for additional signal routing.
However, care must be taken to ensure the clock and
signal lines are isolated from each other and from the
supply lines.
Signal Routing
To preserve good even-order distortion, the signal lines
(those traces feeding the INP and INN inputs) must be
carefully balanced. To accomplish this, the signal traces
should be made as symmetric as possible, meaning that
each of the two signal traces should be the same length
and should see the same parasitic environment. As mentioned previously, the signal lines must be isolated from
the supply lines to prevent coupling from the supplies to
the inputs. This is accomplished by making the necessary layer assignments as described in the previous section. Additionally, it is crucial that the clock lines be
isolated from the signal lines. On the MAX1427 EV kit,
this is done by routing the clock lines on the bottom layer
(layer 6). The clock lines then connect to the ADC
through vias placed in close proximity to the device. The
clock lines are isolated from the supply lines by virtue of
the ground plane on layer 5.
The digital output traces should be kept as short as
possible to minimize capacitive loading. The ground
plane on layer 2 beneath these traces should not be
removed so the digital ground return currents have an
uninterrupted path back to the bypass capacitors.
FROM CM
TO INN
TO INP
OA1
OA2
OA3
R
C2
R
C1
R
G1
R
G2
POSITIVE
INPUT
NEGATIVE
INPUT
R
F1
R
F2
Figure 8. DC-Coupled Analog Input Configuration
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
______________________________________________________________________________________ 17
Grounding
The practice of providing a split ground plane in an
attempt to confine digital ground return currents has
often been recommended in ADC application literature.
However, for converters such as the MAX1418, it is
strongly recommended to employ a single, uninterrupted ground plane. The MAX1427 EV kit achieves excellent dynamic performance with such a ground plane.
The EP of the MAX1418 should be soldered directly to
a ground pad on layer 1 with vias to the ground plane
on layer 2. This provides excellent electrical and thermal connections to the printed circuit.
Supply Bypassing
The MAX1427 EV kit uses 220µF capacitors on each
supply line (AVCC, DVCC, and DRVCC) to provide lowfrequency bypassing. The loss (series resistance)
associated with these capacitors is actually of some
benefit in eliminating high-Q supply resonances. Ferrite
beads are also used on each of the supply lines to
enhance supply bypassing (Figure 9).
Small value (0.01µF to 0.1µF) surface-mount capacitors
should be placed at each supply pin or each grouping
of supply pins to attenuate high-frequency supply noise
(Figure 9). It is recommended to place these capacitors
on the topside of the board and as close to the device
as possible with short connections to the ground plane.
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. However, the
static linearity parameters for the MAX1418 are measured using the histogram method with an input frequency of 15MHz.
MAX1418
15
D0–D14
AV
CC
DV
CC
BYPASSING—ADC LEVEL BYPASSING—BOARD LEVEL
0.1µF
DRV
CC
GND
0.1µF
GND
0.1µF
GND
10µF47µF 220µF
AV
CC
FERRITE BEAD
10µF47µF 220µF
DV
CC
FERRITE BEAD
10µF47µF 220µF
DRV
CC
FERRITE BEAD
ANALOG
POWER-SUPPLY SOURCE
DIGITAL
POWER-SUPPLY SOURCE
OUTPUT-DRIVER
POWER-SUPPLY SOURCE
Figure 9. Grounding, Bypassing, and Decoupling Recommendations for MAX1418
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
18 ______________________________________________________________________________________
Differential Nonlinearly (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. The
MAX1418’s DNL specification is measured with the histogram method based on a 70MHz input tone.
Dynamic Parameter Definitions
Aperture Delay
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 4).
Aperture Jitter
The aperture jitter (tAJ) is the sample-to-sample variation in the aperture delay.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
SNR
dB[max]
= 6.02dBx N + 1.76
dB
In reality, other noise sources such as thermal noise,
clock jitter, signal phase noise, and transfer function
nonlinearities are also contributing to the SNR calculation and should be considered when determining the
SNR in ADC. For a near-full-scale analog input signal
(-0.5dBFS to -1dBFS), thermal and quantization noise
are uniformly distributed across the frequency bins.
Error energy caused by transfer function nonlinearities
on the other hand is not distributed uniformly, but confined to the first few hundred odd-order harmonics.
BTS applications, which are the main target application
for the MAX1418 usually do not care about excess
noise and error energy in close proximity to the carrier
frequency or to DC. These low-frequency and sideband
errors are test system artifacts and are of no consequence to the BTS channel sensitivity. They are therefore excluded from the SNR calculation.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to all spectral components excluding the fundamental and the DC offset.
Single-Tone Spurious-Free
Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier frequency (maximum signal component) to the RMS value
of the next-largest noise or harmonic distortion component. SFDR is usually measured in dBc with respect to
the carrier frequency amplitude or in dBFS with respect
to the ADC’s full-scale range.
Two-Tone Spurious-Free
Dynamic Range (SFDR
TT
)
SFDRTTrepresents the ratio of the RMS value of either
input tone to the RMS value of the peak spurious component in the power spectrum. This peak spur can be
an intermodulation product of the two input test tones.
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels
are at -7dB full scale.
GNDEP1
GND 2
GND 3
CLKP 4
CLKN 5
GND 6
AVCC7
AVCC8
GND 9
INP 10
INN 11
GND 12
CM 13
GND 14
DRVCC42
DRVCC41
D740
D639
D538
D437
D336
D235
D134
D033
DOR32
DRVCC31
GND30
DVCC29
GND15GND16GND
17 18 19
GND
20
AV
CC
21
AVCCAVCCAVCCAVCCAV
CC
AV
CC
22
GND
23 24 25
GND
GND
26 27 28
GND56GND55GND
54 53 52
DRV
CC
51
GND50GND
DAV
D14
D12
D11
D8
49
D13
48 47 46
D9
D10
45 44 43
MAX1418
TOP VIEW
THIN QFN
Pin Configuration
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
______________________________________________________________________________________ 19
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
56L THIN QFN.EPS
MAX1418
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
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