Rainbow Electronics MAX1386 User Manual
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX1385/MAX1386 set and control bias conditions
for dual RF LDMOS power devices found in cellular
base stations. Each device includes a high-side current-sense amplifier with programmable gains of 2, 10,
and 25 to monitor LDMOS drain current over the 20mA
to 5A range. Two external diode-connected transistors
monitor LDMOS temperatures while an internal temperature sensor measures the local die temperature of the
MAX1385/MAX1386. A 12-bit ADC converts the programmable-gain amplifier (PGA) outputs, external/internal temperature readings, and two auxiliary inputs.
The two gate-drive channels, each consisting of 8-bit
coarse and 10-bit fine DACs and a gate-drive amplifier,
generate a positive gate voltage to bias the LDMOS
devices. The MAX1385 includes a gate-drive amplifier
with a gain of 2 and the MAX1386 gate-drive amplifier
provides a gain of 4. The 8-bit coarse and 10-bit fine
DACs allow up to 18 bits of resolution. The MAX1385/
MAX1386 include autocalibration features to minimize
error over time, temperature, and supply voltage.
The MAX1385/MAX1386 feature an I2C/SPI™-compatible
serial interface. Both devices operate from a 4.75V to
5.25V analog supply (3.2mA supply current), a 2.7V to
5.25V digital supply (3.1mA supply current), and a 4.75V
to 11.0V gate-drive supply (4.5mA supply current). The
MAX1385/MAX1386 are available in a 48-pin thin QFN
package.
Applications
RF LDMOS Bias Control in Cellular Base Stations
Industrial Process Control
Features
♦ Integrated High-Side Drain Current-Sense PGA
with Gain of 2, 10, or 25
♦ ±0.5% Accuracy for Sense Voltage Between 75mV
and 250mV
♦ Full-Scale Sense Voltage of 100mV with Gain of 25
♦ Full-Scale Sense Voltage of 250mV with Gain of 10
♦ Common-Mode Range of 5V to 30V Drain Voltage
for LDMOS
♦ Adjustable Low Noise 0 to 5V, 0 to 10V Output
Gate-Bias Voltage Ranges with ±10mA Gate Drive
♦ Fast Clamp to 0V for LDMOS Protection
♦ 8-Bit DAC Control of Gate-Bias Voltage
♦ 10-Bit DAC Control of Gate-Bias Offset with
Temperature
♦ Internal Die Temperature Measurement
♦ External Temperature Measurement by Diode-
Connected Transistor (2N3904)
♦ Internal 12-Bit ADC Measurement of Temperature,
Current, and Voltages
♦ Selectable I
2
C-/SPI-Compatible Serial Interface
400kHz/1.7MHz/3.4MHz I
2
C-Compatible Control
for Settings and Data Measurement
16MHz SPI-Compatible Control for Settings
and Data Measurement
♦ Internal 2.5V Reference
♦ Three Address Inputs to Control Eight Devices in
I
2
C Mode
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
________________________________________________________________
Maxim Integrated Products
1
19-4456; Rev 0; 2/09
EVALUATION KIT
AVAILABLE
Ordering Information/Selector Guide
SPI is a trademark of Motorola, Inc.
*
EP = Exposed pad.
**
Future product—contact factory for availability.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration and Typical Operating Circuit (I
2
C Mode)
appear at end of data sheet.
PART TEMP RANGE PIN-PACKAGE TEMP ERROR (°C) V
MAX1385AETM+** -40°C to +85°C 48 Thin QFN-EP* ±1 5
MAX1385BETM+ -40°C to +85°C 48 Thin QFN-EP* ±2 5
MAX1386AETM+** -40°C to +85°C 48 Thin QFN-EP* ±1 10
MAX1386BETM+** -40°C to +85°C 48 Thin QFN-EP* ±2 10
GATE
(V)
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDDto AGND .........................................................-0.3V to +6V
DV
DD
to DGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
CS1+, CS1-, CS2+, CS2- to GATEGND.................-0.3V to +32V
CS1- to CS1+, CS2- to CS2+ ...................................-6V to +0.3V
GATEV
DD
to GATEGND .........................................-0.3V to +12V
GATE1, GATE2 to GATEGND...........-0.3V to (GATEV
DD
+ 0.3V)
SAFE1, SAFE2 to GATEGND....................................-0.3V to +6V
GATEGND to AGND..............................................-0.3V to +0.3V
All Other Analog Inputs
to AGND ............-0.3V to the lower of +6V and (AV
DD
+ 0.3V)
Digital Inputs
to DGND ............-0.3V to the lower of +6V and (DV
DD
+ 0.3V)
SDA/DIN, SCL to DGND...........................................-0.3V to +6V
Digital Outputs to DGND .........................-0.3V to (DV
DD
+ 0.3V)
Maximum Continuous Current into Any Pin ........................50mA
Continuous Power Dissipation (T
A
= +70°C)
48-Pin, 7mm x 7mm, Thin QFN (derate 27.8 mW/°C
above +70°C).............................................................2222mW
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(GATEVDD= +5.5V for the MAX1385, GATEVDD= +11V for the MAX1386, AVDD= DVDD= +5V, external V
REFADC
= +2.5V, external V
REF-
DAC
= +2.5V, C
REF
= 0.1µF, unless otherwise noted. TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
HIGH-SIDE CURRENT SENSE WITH PGA
Common-Mode Input Voltage
Range
Common-Mode Rejection Ratio CMRR 11V < V
Input-Bias Current
Sense Voltage Range for
Accuracy of ±0.5% V
Sense Voltage Range for
Accuracy of ±2% V
Total PGAOUT Voltage Error V
PGAOUT Capacitive Load C
PGAOUT Settling Time t
Saturation Recovery Time
Sense-Amplifier Slew Rate
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
, V
V
CS+
CS-
V
SENSE
range
PGA gain = 25 0 100
=
PGA gain = 10 0 250Full-Scale Sense Voltage Range
PGA gain = 2 0 1250
PGA gain = 25 75 100
PGA gain = 10 75 250
PGA gain = 2 75 1250
PGA gain = 25 20 100
PGA gain = 10 20 250
PGA gain = 2 20 1250
SENSE
Settles to within ±0.5% of final value, RS =
50Ω, C
Settles to within ±0.5% accuracy; from
V
SENSE
Av
Av
Av
SENSE
SENSE
I
CS+
I
CS-
V
SENSE
VCS_+ -
VCS_-
PGAOUT
HSCS
CS+
< 100mV over the common-mode
= 75mV ±0.1 ±0.5 %
GATE
= 3 x full scale
= 2 0.5
PGA
= 10 2
PGA
= 25 2
PGA
< 30V 90 dB
= 15pF
530V
120 195
0.002 ±2
< 25 µs
< 45 µs
100 pF
µA
mV
mV
mV
V/µs
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(GATEVDD= +5.5V for the MAX1385, GATEVDD= +11V for the MAX1386, AVDD= DVDD= +5V, external V
REFADC
= +2.5V, external V
REF-
DAC
= +2.5V, C
REF
= 0.1µF, unless otherwise noted. TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
Sense-Amplifier Bandwidth
LDMOS GATE DRIVER (GAIN = 2 and 4)
Output Gate-Drive Voltage Range V
Output Impedance R
V
Settling Time t
GATE
Output Capacitive Load (Note 1) C
Noise RMS noise; 1kHz - 1MHz 250 nV/√Hz
V
GATE
Maximum Power-On Transient ±100 mV
Output Short-Circuit Current Limit I
Total Unadjusted Error
No Autocalibration and Offset
Removal (Note 2)
Total Adjusted Error
With Autocalibration and Offset
Removal
Drift
Clamp to Zero Delay 1µs
Output Safe Switch OnResistance
Amplifier Bandwidth
Amplifier Slew Rate 0.375 V/µs
MONITOR ADC DC ACCURACY
Resolution N
Differential Nonlinearity DNL
Integral Nonlinearity INL
Offset Error ±2 ±4 LSB
Gain Error (Note 5) ±2 ±4 LSB
Gain Temperature Coefficient ±0.4 ppm/°C
Offset Temperature Coefficient ±0.4 ppm/°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Av
= 2 900
PGA
Av
= 10 720
PGA
= 25 290
Av
PGA
I
= ±1mA 0.75
GATE
GATE
I
= ±10mA 1
GATE
GATE
GATE
GATE
TUE
TUE
R
OPSW
SC
ADC
Measured at DC 0.1 Ω
Settles to within ±0.5% of final value;
R
= 50Ω, C
SERIES
No series resistance, R
R
= 50Ω 0 25,000
SERIES
1s, sinking or sourcing ±25 mA
MAX1385, LOCODE = 128, HICODE = 180 ±6 ±20
MAX1386, LOCODE = 128, HICODE = 180 ±12 ±40
MAX1385, LOCODE = 128, HICODE = 180 ±1 ±8
MAX1386, LOCODE = 128, HICODE = 180 ±2 ±16
MAX1385, V
MAX1386, V
GATE_ clamped to AGND (Note 3) 500 Ω
MAX1385 300
MAX1386 150
ADC
(Note 4) ±0.6 ±2 LSB
ADC
GATE
GATE
= 15µF
GATE
= 0Ω 010
SERIES
> 1V ±15
> 1V ±30
12 Bits
GATEV
- 0.75
GATEV
- 1
10 ms
±0.5 ±2 LSB
kHz
DD
V
DD
nF
mV
mV
µV/°C
kHz
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(GATEVDD= +5.5V for the MAX1385, GATEVDD= +11V for the MAX1386, AVDD= DVDD= +5V, external V
REFADC
= +2.5V, external V
REF-
DAC
= +2.5V, C
REF
= 0.1µF, unless otherwise noted. TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
Channel-to-Channel Offset
Matching
Channel-to-Channel Gain
Matching
MONITOR ADC DYNAMIC ACCURACY (1kHz sine-wave input, 2.5V
Signal-to-Noise Plus Distortion SINAD 70 dB
Total Harmonic Distortion THD Up to the 5th harmonic -82 dB
Spurious-Free Dynamic Range SFDR 86 dB
Intermodulation Distortion IMD f
Full-Power Bandwidth -3dB point 10 MHz
Full-Linear Bandwidth S/(N + D) > 68dB 100 kHz
MONITOR ADC CONVERSION RATE
Power-Up Time t
Conversion Time t
MONITOR ADC ANALOG INPUT (ADCIN1, ADCIN2)
Input Range V
Input Leakage Current VIN = 0V and VIN = AV
Input Capacitance C
TEMPERATURE MEASUREMENTS
Internal Sensor Measurement
Error (Note 1)
External Sensor Measurement
Error (Notes 1, 7)
Temperature Resolution 1/8 °C/LSB
External Diode Drive 2.8 85 µA
Drive Current Ratio (Note 8) 16.5
INTERNAL REFERENCE
REFADC/REFDAC Output Voltage
REFADC/REFDAC Output
Temperature Coefficient
REFADC/REFDAC Output
Impedance
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
, up to 94.4ksps)
P-P
PU
CONV
ADCIN
ADCIN
V
REFADCTA
V
REFDACTA
TC
REFADC
TC
REFDAC
= 0.99kHz, f
IN1
External reference 0.8
Internal reference 70
Internally clocked 7.5 10 µs
Relative to AGND (Note 6) 0 V
MAX1385A/MAX1386A, TA = +25°C ±0.25
MAX1385A/MAX1386A, TA = T
MAX1385B/MAX1386B, TA = +25°C ±0.25
MAX1385B/MAX1386B, T
TA = +25°C ±0.4
T
= T
A
,
to T
MIN
= +25°C 2.494 2.500 2.506
= +25°C 2.494 2.500 2.506
= 1.02kHz 76 dB
IN2
DD
MAX
A
= T
MIN
MIN
to T
to T
MAX
MAX
-1.0 ±0.25 +1.0
-2.0 ±0.35 +2.0
-3 ±0.75 +3
±0.1 LSB
±0.1 LSB
REF
±0.01 ±1 µA
34 pF
±14 ppm/°C
6.5 kΩ
µs
V
°C
°C
V
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(GATEVDD= +5.5V for the MAX1385, GATEVDD= +11V for the MAX1386, AVDD= DVDD= +5V, external V
REFADC
= +2.5V, external V
REF-
DAC
= +2.5V, C
REF
= 0.1µF, unless otherwise noted. TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
Capacitive Bypass at REF 270 nF
Power-Supply Rejection Ratio PSRR AVDD = +5V ±5% 70 dB
EXTERNAL REFERENCE
REFADC Input Voltage Range V
REFADC Input Current I
REFDAC Input Voltage Range V
REFDAC Input Current Static current when no DAC calibration 0.1 µA
GATE-DRIVER COARSE-DAC DC ACCURACY
Resolution N
Integral Nonlinearity INL
Differential Nonlinearity DNL
GATE-DRIVER FINE-DAC DC ACCURACY
Resolution N
Integral Nonlinearity INL
Differential Nonlinearity DNL
POWER SUPPLIES (Note 10)
Analog Supply Voltage AV
Digital Supply Voltage DV
Gate-Drive Supply Voltage V
Analog Supply Current I
Digital Supply Current I
GATEVDD Supply Current I
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REFADC
REFADC
REFDAC
CDAC
CDAC
FDAC
GATEVDD
AVDD
DVDD
GATEVDD
Limited code test 1.0 AV
V
= 2.5V, f
REF
Acquisition/between conversions ±0.01 ±1
(Note 9) 0.5 2.5 V
Measured at GATE; fine DAC set at full scale ±0.15 ±1 LSB
Guaranteed monotonic ±0.05 ±0.5 LSB
CDAC
Measured at GATE; coarse DAC set at full
FDAC
scale
Guaranteed monotonic ±0.1 ±1 LSB
FDAC
DD
DD
AVDD = 5V 3.2 4 mA
DVDD = 2.7V to 5.25V 3.1 4.3 mA
I
AVDD
I
PD
DVDD
I
VDDGATE
= 174ksps 60 80
SAMPLE
8 Bits
10 Bits
4.75 5.25 V
2.7
4.75 11.00 V
3 4.5 7 mA
DD
±0.25 ±4 LSB
AV
DD
+ 0.3
0.1 2
0.1 2Shutdown Current (Note 11) I
0.1 2
V
µA
V
µA
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(GATEVDD= +5.5V for the MAX1385, GATEVDD= +11V for the MAX1386, AVDD= DVDD= +5V, external V
REFADC
= +2.5V, external V
REF-
DAC
= +2.5V, C
REF
= 0.1µF, unless otherwise noted. TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
VIH AND VIL FOR SDA/DIN AND SCL IN I2C OPERATION ONLY
Input High Voltage V
Input Low Voltage V
Input Hysteresis V
VIH AND VIL FOR OPSAFE1 AND OPSAFE2
Input High Voltage V
Input Low Voltage V
VIH AND VIL FOR ALL OTHER DIGITAL INPUTS
Input High Voltage V
Input Low Voltage V
VOH AND VOL FOR A1/DOUT (SPI), SDA/DIN, ALARM
Output Low Voltage V
Output High Voltage V
VOH AND VOL FOR SAFE1, SAFE2, BUSY
Output Low Voltage V
Output High Voltage V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IH
IL
HYS
IH
IL
IH
IL
I
OL
OH
OL
OH
= 3mA 0.4 V
SINK
I
SOURCE
I
SINK
I
SOURCE
= 2mA
= 0.5mA 0.4 V
= 0.5mA
0.7 x
DV
DD
0.3 x
DV
DD
0.1 x
DV
DD
2.4 V
0.4 V
2.2 V
0.7 V
DV
DD
- 0.5
DV
DD
- 0.5
V
V
V
V
V
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
_______________________________________________________________________________________ 7
I2C SLOW-/FAST-MODE TIMING CHARACTERISTICS (Note 12, see Figure 1)
(GATEVDD= +5.5V for MAX1385, GATEVDD= +11V for MAX1386, AVDD= +5V, DVDD= 2.7V to 5.25V, external V
REFADC
= +2.5V,
external V
REFDAC
= +2.5V, C
REF
= 0.1µF, TA= -40°C to +85°C, unless otherwise noted).
Serial-Clock Frequency f
Bus Free Time Between STOP
and START Condition
Hold Time Repeated START
Condition
SCL Pulse-Width Low t
SCL Pulse-Width High t
Setup Time Repeated START
Condition
Data Hold Time t
Data Setup Time t
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Signal,
Transmitting
Setup Time for STOP Condition t
Capacitive Load for Each Bus
Line
Pulse Width of Spikes
Suppressed by the Input Filter
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL
t
BUF
t
HD;STA
LOW
HIGH
t
SU;STA
HD;DAT
SU;DAT
t
t
t
SU;STO
C
t
SP
After this period, the first clock pulse is
generated
(Note 13) 0 0.9 µs
(Note 14) 0 300 ns
R
(Note 14) 0 300 ns
F
(Notes 14, 15)
F
b
(Note 16) 0 50 ns
0 400 kHz
1.3 µs
0.6 µs
1.3 µs
0.6 µs
0.6 µs
100 ns
20 +
0.1C
b
0.6 µs
250 ns
400 pF
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
8 _______________________________________________________________________________________
I2C HIGH-SPEED-MODE TIMING CHARACTERISTICS (Note 12, see Figure 2)
(GATEVDD= +5.5V for MAX1385, GATEVDD= +11V for MAX1386, AVDD= +5V, DVDD= 2.7V to 5.25V, external V
REFADC
= +2.5V,
external V
REFDAC
= +2.5V, C
REF
= 0.1µF, TA= -40°C to +85°C, unless otherwise noted).
Serial-Clock Frequency f
Setup Time Repeated START
Condition
Hold Time Repeated START
Condition
SCL Pulse-Width Low t
SCL Pulse-Width High t
Data Setup Time t
Data Hold Time t
Rise Time of SCL Signal,
Receiving
Rise Time of SCL Signal After a
Repeated START Condition and
After an Acknowledge Bit,
Receiving
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL
t
SU;STA
t
HD;STA
LOW
HIGH
SU;DAT
HD;DAT
t
RCL
t
RCL1
(Note 17) 0 70 ns
0 3.4 MHz
160 ns
160 ns
160 ns
60 ns
10 ns
10 40 ns
10 80 ns
Fall Time of SCL Signal,
Receiving
Rise Time of SDA Signal,
Receiving
Fall Time of SDA Signal,
Transmitting
Setup Time for STOP Condition t
Capacitive Load for Each Bus
Line
Pulse Width of Spikes That are
Suppressed by the Input Filter
t
FCL
t
RDA
t
FDA
SU;STO
C
b
t
SP
10 40 ns
10 80 ns
10 80 ns
160 ns
(Note 18) 100 pF
010ns
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
_______________________________________________________________________________________ 9
Note 1: Guaranteed by design.
Note 2: Total unadjusted errors are for the entire gain drive channel including the 8- and 10-bit DACs and the gate driver. They are
all measured at the GATE1 and GATE2 outputs. Offset removal refers to presetting the drain current after a room temperature calibration by the user. This effectively removes the channel offset.
Note 3: During power-on reset, the output safe switch is closed. The output safe switch opens once both AV
DD
and DVDDsupply
voltages are established.
Note 4: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after the gain and offset errors
have been removed.
Note 5: Offset nulled.
Note 6: Absolute range for analog inputs is from 0 to AV
DD
.
Note 7: The MAX1385/MAX1386 and external sensor are at the same temperature. External sensor measurement error is tested with
a diode-connected 2N3904.
Note 8: The drive current ratio is defined as the large drive current divided by the small drive current in a temperature measure-
ment. See the
Temperature Measurements
section for further details.
Note 9: Guaranteed monotonicity. Accuracy might be degraded at lower V
REFDAC
.
Note 10: Supply current limits are valid only when digital inputs are at DV
DD
or DGND. Timing specifications are only guaranteed
when inputs are driven rail-to-rail.
Note 11: Shutdown supply currents are typically 0.1µA. Maximum specification is limited by automated test equipment.
Note 12: All timing specifications referred to V
IH
or VILlevels.
Note 13: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V
IL
of SCL) to bridge the unde-
fined region of SCL’s falling edge.
Note 14: C
b
= total capacitance of one bus line in pF; tRand tFare measured between 0.3 x DVDDand 0.7 x DVDD.
Note 15: For a device operating in an I
2
C-compatible system.
Note 16: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 17: A device must provide a data hold time to bridge the undefined part between V
IH
and VILof the falling edge of the SCL signal.
An input circuit with a threshold as low as possible for the falling edge of the SCL signal minimizes this hold time.
Note 18: Cb = total capacitance of one bus line in pF. For bus loads between 100pF and 400pF, the timing parameters should be
linearly interpolated.
SPI TIMING CHARACTERISTICS (Note 12, See Figure 3)
(GATEVDD= +5.5V for the MAX1385, GATEVDD= +11V for the MAX1386, AVDD= +5V, DVDD= 2.7V to 5.25V, external V
REFADC
=
+2.5V, external V
REFDAC
= +2.5V, C
REF
= 0.1µF, TA= -40°C to +85°C, unless otherwise noted.)
SCL Clock Period t
SCL High Time t
SCL Low Time t
DIN Setup Time t
DIN Hold Time t
SCL Fall to DOUT Transition t
CSB Fall to DOUT Enable t
CSB Rise to DOUT Disable t
CSB Rise or Fall to SCL Rise t
CSB Pulse-Width High t
Last Clock Rise to CSB Rise t
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CP
CH
CL
DS
DH
DO
DV
TR
CSS
CSW
CSH
62.5 ns
25 ns
25 ns
10 ns
0ns
C
= 30pF 20 ns
LOAD
C
= 30pF 40 ns
LOAD
C
= 30pF (Note 12) 100 ns
LOAD
25 ns
100 ns
50 ns
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
10 ______________________________________________________________________________________
Figure 1. I2C Slow-/Fast-Mode Timing Diagram
Figure 2. I2C High-Speed-Mode Timing Diagram
Figure 3. SPI Timing Diagram
SDA
t
t
R
t
HD;DAT
SU;DAT
t
HIGH
t
F
t
SU;STA
t
HD;STA
S
r
SCL
t
F
S
t
LOW
t
HD;STA
t
SP
t
SU;STO
t
r
t
BUF
P
S
Sr
t
t
FDA
RDA
SDA
t
SU;STA
t
HD;STA
t
HD;DAT
SCL
t
HIGH
t
FCL
t
LOW
t
RCL1
CSB
SCL
t
CSS
t
DH
t
CL
t
CH
t
DS
t
SU;DAT
t
LOW
t
RCL
t
HIGH
Sr
P
t
SU;STO
t
RCL1
t
CSW
t
t
CP
t
CSH
CSS
DIN
DOUT
D23
t
DV
D22
D1
D0
t
DO
D0D1
t
TR
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 11
Typical Operating Characteristics
(GATEVDD= +5.5V for the MAX1385, GATEVDD= +11V for the MAX1386, AVDD= DVDD= +5V, external V
REFADC
= +2.5V, external
V
REFDAC
= +2.5V, C
REF
= 0.1µF, TA= +25°C, unless otherwise noted.)
3.0
3.3
3.2
3.1
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.7 4.94.8 5.0 5.1 5.2 5.3
AVDD SUPPLY CURRENT
vs. AV
DD
VOLTAGE
MAX1385/86 toc01
AVDD (V)
I
AVDD
(mA)
Av
PGA
= 2
CMV = 12V
V
SENSE
= 100mV
TA = +85°C
TA = +25°C
TA = -40°C
DVDD SUPPLY CURRENT vs. DVDD VOLTAGE
MAX1385/86 toc02
DVDD (V)
I
DVDD
(mA)
5.24.74.23.73.2
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
1.00
2.7
Av
PGA
= 2
CMV = 12V
V
SENSE
= 100mV
TA = +25°C
TA = +85°C
TA = -40°C
GATEVDD SUPPLY CURRENT
vs. GATEV
DD
VOLTAGE
MAX1385/86 toc03
GATEVDD (V)
I
GATEVDD
(mA)
11108 96 75
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
4.0
412
Av
PGA
= 2
CMV = 12V
V
SENSE
= 100mV
TA = +85°C
TA = +25°C
TA = -40°C
TOTAL PGAOUT_ ERROR
vs. TEMPERATURE
MAX1385/86 toc04
TEMPERATURE (°C)
PGAOUT_ ERROR (%)
806535 50-10 5 20-25
-0.125
-0.100
-0.075
-0.050
-0.025
0
0.025
0.050
0.075
0.100
0.125
0.150
-0.150
-40
Av
PGA
= 2
CMV = 12V
V
SENSE
= 100mV
ACQUISITION
TRACKING
TOTAL PGAOUT_ ERROR vs. V
SENSE
MAX1385/86 toc05
V
SENSE
(mV)
PGAOUT_ ERROR (%)
1000750500250
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0
0 1250
Av
PGA
= 2
CMV = 12V
TOTAL PGAOUT_ ERROR vs. V
SENSE
MAX1385/86 toc06
V
SENSE
(mV)
PGAOUT_ ERROR (%)
80604020
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0
0.5
-4.0
0 100
Av
PGA
= 25
CMV = 12V
TOTAL PGAOUT_ ERROR
vs. COMMON-MODE VOLTAGE
MAX1385/86 toc07
COMMON-MODE VOLTAGE (V)
PGAOUT_ ERROR (%)
3025201510
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
0
5
Av
PGA
= 2
V
SENSE
= 100mV
PGAOUT_ OFFSET VOLTAGE
vs. TEMPERATURE
MAX1385/86 toc08
TEMPERATURE (°C)
OFFSET VOLTAGE (μV)
806535 50-10 5 20-25
-350
-300
-250
-200
-150
-100
-50
0
50
100
150
200
-400
-40
Av
PGA
= 2
CMV = 12V
V
SENSE
= 100mV
ACQUISITION
TRACKING
V
SENSE
TRANSIENT RESPONSE
MAX1385/86 toc09
100mV/div
1V/div
PGAOUT_
V
SENSE
10μs/div
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
12 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(GATEVDD= +5.5V for the MAX1385, GATEVDD= +11V for the MAX1386, AVDD= DVDD= +5V, external V
REFADC
= +2.5V, external
V
REFDAC
= +2.5V, C
REF
= 0.1µF, TA= +25°C, unless otherwise noted.)
PGAOUT_ 0mV TO 250mV
V
SENSE
TRANSIENT RESPONSE
MAX1385/86 toc10
V
SENSE
PGAOUT_
10µs/div
100mV/div
1V/div
PGAOUT_ PEDESTAL ERROR
DURING CALIBRATION
MAX1385/86 toc11
BUSY
PGAOUT_
20µs/div
2V/div
10mV/div
GATE_ OFFSET COMPENSATED
ERROR vs. TEMPERATURE
MAX1385/86 toc12
TEMPERATURE (°C)
ERROR VOLTAGE (mV)
8065-25 -10 5 3520 50
-7
-6
-5
-4
-3
-2
-1
0
-8
-40
L_ERROR, AUTOCALIBRATION
H_ERROR, AUTOCALIBRATION
L_ERROR, NO AUTOCALIBRATION
H_ERROR, NO AUTOCALIBRATION
V
GATE
vs. POWER-ON TIME
MAX1385/86 toc13
V
GATE_
400µs/div
50mV/div
CHARGE CURRENT vs. V
GATE
MAX1385/86 toc15
V
GATE_
1ms/div
I
GATE_
2V/div
20mA/div
GATE_ SETTLING TIME
vs. LOAD CAPACITANCE
MAX1385/86 toc14
LOAD CAPACITANCE (µF)
SETTLING TIME (ms)
101
2
4
6
8
10
12
14
16
0
0.1 100
R
SERIES
= 50
Ω
GATE_ VOLTAGE SWING
vs. LOAD RESISTANCE
MAX1385/86 toc16
LOAD RESISTANCE (Ω)
GATE_ VOLTAGE SWING (V)
10,0001000100
1
2
3
4
5
6
7
8
9
10
0
10 100,000
GLITCH ENERGY
MAX1385/86 toc17
1µs/div
10mV/div
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 13
Typical Operating Characteristics (continued)
(GATEVDD= +5.5V for the MAX1385, GATEVDD= +11V for the MAX1386, AVDD= DVDD= +5V, external V
REFADC
= +2.5V, external
V
REFDAC
= +2.5V, C
REF
= 0.1µF, TA= +25°C, unless otherwise noted.)
-1.0
-0.4
-0.6
-0.8
-0.2
0
0.2
0.4
0.6
0.8
1.0
0 10050 150 200 250
INTEGRAL NONLINEARITY vs. DIGITAL
INPUT CODE (8-BIT COARSE DAC)
MAX1385/86 toc18
DIGITAL INPUT CODE
INL (LSB)
INTEGRAL NONLINEARITY vs. DIGITAL
INPUT CODE (10-BIT FINE DAC)
1.0
0.8
0.6
0.4
0.2
0
INL (LSB)
-0.2
-0.4
-0.6
-0.8
-1.0
0400200 600 800 1000
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT FINE DAC)
1.0
0.8
0.6
0.4
0.2
0
DNL (LSB)
-0.2
-0.4
-0.6
-0.8
-1.0
0 400200 600 800 1000
DIGITAL INPUT CODE
DIGITAL INPUT CODE
MAX1385/86 toc21
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT DAC)
1.0
0.8
MAX1385/86 toc19
0.6
0.4
0.2
0
DNL (LSB)
-0.2
-0.4
-0.6
-0.8
-1.0
0 10050 150 200 250
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (ADC)
1.0
0.8
0.6
0.4
0.2
0
INL (LSB)
-0.2
-0.4
-0.6
-0.8
-1.0
0 20001000 3000 4000
DIGITAL OUTPUT CODE
DIGITAL INPUT CODE
MAX1385/86 toc22
MAX1385/86 toc20
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (ADC)
1.0
0.8
0.6
0.4
0.2
0
DNL (LSB)
-0.2
-0.4
-0.6
-0.8
-1.0
0 20001000 3000 4000
DIGITAL OUTPUT CODE
MAX1385/86 toc23
0
-20
-40
-60
-80
-100
AMPLITUDE (dB)
-120
-140
-160
0 5 10 15 20 25
FFT PLOT
fIN = 303Hz
f
SAMPLE
FREQUENCY (kHz)
= 49.15kHz
MAX1385/86 toc24
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
14 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(GATEVDD= +5.5V for the MAX1385, GATEVDD= +11V for the MAX1386, AVDD= DVDD= +5V, external V
REFADC
= +2.5V, external
V
REFDAC
= +2.5V, C
REF
= 0.1µF, TA= +25°C, unless otherwise noted.)
2.484
2.489
2.494
2.499
2.504
2.509
-40 -10-25 5 20 35 50 65 80
INTERNAL REFERENCE
vs. TEMPERATURE
MAX1385/86 toc25
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
AVDD = 5V
-0.100
-0.050
-0.075
0.025
0
-0.025
0.075
0.050
0.100
-40 5 20-25 -10 35 50 65 80
ADC OFFSET ERROR vs. TEMPERATURE
MAX1385/86 toc26
TEMPERATURE (°C)
OFFSET ERROR (%)
AVDD = 5V
ADC OFFSET ERROR vs. AVDD VOLTAGE
0.100
0.075
0.050
0.025
0
-0.025
OFFSET ERROR (%)
-0.050
-0.075
-0.100
4.75 4.85 4.95 5.05 5.15 5.25
AVDD (V)
INTERNAL TEMPERATURE SENSOR
ERROR vs. TEMPERATURE
0
-0.2
-0.4
-0.6
-0.8
ERROR (°C)
-1.0
-1.2
-1.4
-40 0 20-20 40 60 80
TEMPERATURE (°C)
MAX1385/86 toc27
MAX1385/86 toc29
ADC GAIN ERROR vs. TEMPERATURE
0.05
0.04
0.03
0.02
0.01
0
-0.01
GAIN ERROR (%)
-0.02
-0.03
-0.04
-0.05
-40 -10 5 20-25 35 50 65 80
TEMPERATURE (°C)
EXTERNAL TEMPERATURE SENSOR
ERROR vs. TEMPERATURE
1.0
0.8
0.6
0.4
0.2
0
ERROR (°C)
-0.2
-0.4
-0.6
-0.8
-1.0
-40 0 20-20 40 60 80
TEMPERATURE (°C)
AVDD = 5V
MAX1385/86 toc28
MAX1385/86 toc30
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 15
Pin Description
PIN NAME FUNCTION
1 DGND Digital Ground
2 SAFE1
3 A0/CSB
4 CNVST
5 SEL Mode Select. Connect SEL to DGND to select I2C mode. Connect SEL to DVDD to select SPI mode.
6 ALARM
7 SAFE2
8, 19, 25, 28,
35–39, 42, 46
9 REFDAC DAC Reference Input/Output
10 REFADC ADC Reference Input/Output
11 DXP1
12 DXN1 Diode Negative Input 1. Connect to cathode of temperature diode or the emitter of an npn transistor.
13 DXP2
14 DXN2 Diode Negative Input 2. Connect to cathode of temperature diode or the emitter of an npn transistor.
15 ADCIN1 ADC Input 1
16 ADCIN2 ADC Input 2
17 PGAOUT2 Programmable-Gain Amplifier Output 2
18 AV
20, 21, 22 AGND Analog Ground
N.C. No Connection. Not internally connected.
Safe Status Channel 1 Output. Programmable active-high or active-low. SAFE1 asserts when
programmed channel 1 temperature threshold or current threshold has been reached.
2
I
C-Compatible Address 0/ SPI-Compatible Chip Select. See the Digital Serial Interface section. In
SPI mode, drive A0/CSB low to select the device.
Active-Low Conversion-Start Input. Drive CNVST low to start a conversion (clock modes 01 and 11).
Connect CNVST to DV
Alarm Output. Program ALARM for comparator or interrupt output modes (see the Alarm Modes
section). Program ALARM to assert on any combination of channel temperature or current
thresholds.
Safe Status Channel 2 Output. Programmable active-high or active-low. SAFE2 asserts when
programmed channel 2 temperature threshold or current threshold has been reached.
Diode Positive Input 1. Connect to anode of temperature diode or the base and collector of an npn
transistor.
Diode Positive Input 2. Connect to anode of temperature diode or the base and collector of an npn
transistor.
Analog Power-Supply Input
DD
when initiating conversions through the serial interface (clock mode 00).
DD
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
16 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
23 GATEGND Gate-Drive Amplifier Ground
24 GATEV
26 OPSAFE2 Operating Safe Channel 2 Input. Drive OPSAFE2 high to clamp GATE2 to AGND.
27 CS2+
29 CS2-
30 GATE2 Channel 2 Gate-Drive Amplifier Output
31 GATE1 Channel 1 Gate-Drive Amplifier Output
32 CS1-
33 CS1+
34 OPSAFE1 Operating Safe Channel 1 Input. Drive OPSAFE1 high to clamp GATE1 to AGND.
40 PGAOUT1 Programmable-Gain Amplifier Output 1
41 A2/N.C.
43 SCL Digital Serial Clock Input
44 SDA/DIN
45 A1/DOUT
47 BUSY Device Busy Output. See the BUSY Output section
48 DV
— EP Exposed Pad. Connect to AGND. Internally connected to analog ground.
DD
Gate-Drive Amplifier Supply Input
DD
Current-Sense Positive Input 2. CS2+ is the external sense resistor connection to the LDMOS 2
supply.
Current-Sense Negative Input 2. CS2- is the external sense resistor connection to the LDMOS 2
drain.
Current-Sense Negative Input 1. CS1- is the external sense resistor connection to the LDMOS 1
drain.
Current-Sense Positive Input 1. CS1+ is the external sense resistor connection to the LDMOS 1
supply.
I2C-Compatible Address 2. See the Digital Serial Interface section.
No Connection. Leave unconnected in SPI mode.
I2C-Compatible Serial Data Input/Output
SPI-Compatible Serial Data Input
I2C-Compatible Address 1. See the Digital Serial Interface section.
SPI-Compatible Serial Data Output
Digital Supply Input
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