Rainbow Electronics MAX1362 User Manual

General Description
The MAX1361/MAX1362 low-power, 10-bit, 4-channel, analog-to-digital converters (ADCs) feature a digitally programmable window comparator with an interrupt out­put for automatic system-monitoring applications. Once configured, monitor mode automatically asserts an inter­rupt when any analog input exceeds the programmed upper or lower thresholds, without interaction to the host. The MAX1361/MAX1362 respond to the SMBus™ alert, allowing quick identification of the alarming device on a shared interrupt. A programmable delay between monitoring intervals lowers power consumption at reduced monitoring rates.
In addition, the MAX1361/MAX1362 integrate an inter­nal voltage reference, a clock, and a 1.7MHz, high­speed, I2C™-compatible, 2-wire, serial interface. The optimized interface allows a maximum conversion rate of 94.4ksps in normal mode while reading back the conversion results. Each of the four analog inputs is configurable for single-ended or fully differential opera­tion and unipolar or bipolar operation. Two scan modes utilize on-chip random access memory (RAM) to allow eight conversions of a selected channel or scanning of a group of channels to reduce interface overhead.
These devices operate from a single 2.7V to 3.6V (MAX1361) or 4.5V to 5.5V (MAX1362) supply and require only 436µA at the maximum sampling rate of 150ksps in monitor mode and 670µA at the maximum sampling rate of 94.4ksps. AutoShutdown™ powers down the devices between conversions, reducing sup­ply current to less than 0.5µA when idle.
The full-scale analog-input range is determined by the internal reference or by an externally applied reference voltage ranging from 1V to VDD. The MAX1361 features a 2.048V internal reference, and the MAX1362 features a 4.096V internal reference.
The MAX1361/MAX1362 are available in a 10-pin µMAX®package and are specified over the extended (-40°C to +85°C) temperature range. For 12-bit applica­tions, refer to the pin-compatible MAX1363/MAX1364 data sheet.
Applications
System Monitoring/Supervision Servers/Workstations High Reliability Power Supplies Medical Instrumentation
Features
Monitor Mode
Programmable Lower/Upper Trip Threshold Alarm-Status Register Records Fault Events SMBus Alert Response Programmable Sampling Intervals
10-Bit I2C-Compatible ADC
±1 LSB INL, ±1 LSB DNL
4-Channel Single-Ended or 2-Channel Fully
Differential Inputs
Software Programmable Bipolar/Unipolar
Conversions
Fast Sampling Rate
94.4ksps While Continuously Reading Conversions 150ksps in Monitor Mode
High-Speed I2C-Compatible Serial Interface
100kHz/400kHz Standard/Fast Mode Up to 1.7MHz High-Speed Mode 6 Available I2C Slave Addresses
Single Supply
2.7V to 3.6V (MAX1361)
4.5V to 5.5V (MAX1362)
Internal Reference
2.048V (MAX1361)
4.096V (MAX1362)
External Reference: 1V to V
DD
Low Power
436µA in Monitor Mode (150ksps) 670µA at 94.4ksps 6µA at 1ksps
0.5µA in Power-Down Mode
Small Package
10-Pin µMAX
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitors with Programmable
Trip Window and SMBus Alert Response
________________________________________________________________ Maxim Integrated Products 1
Ordering Information/Selector Guide
19-3268; Rev 1; 7/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE I2C SLAVE ADDRESS
SUPPLY VOLTAGE (V)
MAX1361EUB -40°C to +85°C 10 µMAX 0110100/0110101 2.7 to 3.6
MAX1361LEUB* -40°C to +85°C 10 µMAX 0110010/0110011 2.7 to 3.6 MAX1361MEUB* -40°C to +85°C 10 µMAX 0110110/0110111 2.7 to 3.6
SMBus is a trademark of Intel Corporation. I2C is a trademark of Philips Corporation. Purchase of I2C compo­nents from Maxim Integrated Products, Inc. or one of its subli­censed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C sys­tem, provided that the system conforms to the I
2
C Standard Specification as defined by Philips. AutoShutdown is a trademark of Maxim Integrated Products, Inc. µMAX is a registered trademark of Maxim Integrated Products, Inc.
Typical Operating Circuit and Pin Configuration appear at end of data sheet.
Ordering Information/Selector Guide continued at end of data sheet.
*Future product—contact factory for availability.
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable Trip Window and SMBus Alert Response
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= 2.7V to 3.6V (MAX1361), VDD= 4.5V to 5.5V (MAX1362), V
REF
= 2.048V (MAX1361), V
REF
= 4.096V (MAX1362), C
REF
=
0.1µF, f
SCL
= 1.7MHz, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
AIN0–AIN3, A0, REF to GND......................-0.3V to (V
DD
+ 0.3V)
SDA, SCL,
INT to GND.............................................-0.3V to +6V
Maximum Current Into Any Pin.........................................±50mA
Continuous Power Dissipation (T
A
= +70°C)
10-Pin µMAX (derate 5.6mW/°C above +70°C)........444.4mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
PARAMETER
CONDITIONS
UNITS
DC ACCURACY (f
SAMPLE
= 94.4ksps) (Note 1)
Resolution 10 Bits Relative Accuracy INL (Note 2) ±1 LSB Differential Nonlinearity DNL No missing codes ±1 LSB Offset Error ±1 LSB
Offset-Error Temperature Coefficient
Relative to FSR 0.3
ppm/°C
Gain Error (Note 3) ±1 LSB Gain Temperature Coefficient Relative to FSR 0.3
ppm/°C
Channel-to-Channel Offset Matching
LSB
Channel-to-Channel Gain Matching
LSB
DYNAMIC PERFORMANCE (f
IN(SINE-WAVE)
= 10kHz, V
IN(P-P)
= V
REF
, f
SAMPLE
= 94.4ksps)
Signal-to-Noise Plus Distortion SINAD 60 dB Total Harmonic Distortion THD Up to the 5th harmonic -70 dB Spurious-Free Dynamic Range SFDR 70 dB Full-Power Bandwidth SINAD > 57dB 3.0
MHz
Full-Linear Bandwidth -3dB point 5.0
MHz
CONVERSION RATE
Internal clock 6.8
Conversion Time (Note 4) t
CONV
External clock
µs
Internal clock, SCAN[1:0] = 01 53 External clock
Throughput Rate (Note 5)
Monitor mode, SCAN[1:0] = 10 150
ksps
SYMBOL
MIN TYP MAX
f
SAMPLE
10.6
±0.1
±0.1
94.4
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 2.7V to 3.6V (MAX1361), VDD= 4.5V to 5.5V (MAX1362), V
REF
= 2.048V (MAX1361), V
REF
= 4.096V (MAX1362), C
REF
=
0.1µF, f
SCL
= 1.7MHz, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Track/Hold Acquisition Time
ns
Internal Clock Frequency 2.8
MHz
External clock, fast mode 60
Aperture Delay (Note 6) t
AD
External clock, high-speed mode 30
ns
ANALOG INPUT (AIN0–AIN3)
Unipolar 0
Input Voltage Range, Single­Ended and Differential (Note 7)
Bipolar
V
Input Multiplexer Leakage Current
±1 µA
Input Capacitance C
IN
22 pF
INTERNAL REFERENCE (Note 8)
MAX1361
Reference Voltage V
REF
TA = +25°C
MAX1362
V
Reference-Voltage Temperature Coefficient
25
ppm/°C
REF Short-Circuit Current 2mA REF Source Impedance 1.5 k
EXTERNAL REFERENCE
REF Input Voltage Range V
REF
(Note 9) 1
V
REF Input Current I
REF
f
SAMPLE
= 94.4ksps 40 µA
DIGITAL INPUTS/OUTPUTS (SCL, SDA, A0)
Input High Voltage V
IH
0.7 x V
DD
V
Input Low Voltage V
IL
V
Input Hysteresis V
HYST
0.1 x V
DD
V
Input Current I
IN
±10 µA
Input Capacitance C
IN
15 pF
Output Low Voltage V
OL
I
SINK
= 3mA 0.4 V
INT OUTPUT
Output Low Voltage I
SINK
= 3mA 0.4 V
INT Leakage Current No faults detected
µA
Output Capacitance 15 pF
POWER REQUIREMENTS
MAX1361 2.7 3.6
Supply Voltage V
DD
MAX1362 4.5 5.5
V
ON/OFF leakage current, V
TCV
REF
= 0 or V
AIN_
800
-V
/ 2 +V
REF
DD
2.027 2.048 2.068
4.055 4.096 4.137
±0.01
0.3 x V
V
REF
REF
V
±10
/ 2
DD
DD
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable Trip Window and SMBus Alert Response
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 2.7V to 3.6V (MAX1361), VDD= 4.5V to 5.5V (MAX1362), V
REF
= 2.048V (MAX1361), V
REF
= 4.096V (MAX1362), C
REF
=
0.1µF, f
SCL
= 1.7MHz, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
CONDITIONS
UNITS
Internal
f
SAMPLE
= 150ksps, monitor mode (Note 10)
External
Internal
f
SAMPLE
=
94.4ksps, external clock
External
900
Internal
f
SAMPLE
= 40ksps, internal clock
External
Internal
internal clock
External
60
Internal
f
SAMPLE
= 1ksps, internal clock
External
6
Internal
f
SAMPLE
= 150ksps, monitor mode (Note10)
External
Internal
f
SAMPLE
=
94.4ksps, external clock
External
900
Internal
internal clock
External
Internal
f
SAMPLE
= 10ksps, internal clock
External
60
Internal
Supply Current I
DD
f
SAMPLE
= 1ksps, internal clock
External
6
µA
Internal reference on
Shutdown Current
Internal reference off 0.5 10
µA
Power-Supply Rejection Ratio PSRR Full-scale input (Note 11)
LSB/V
TIMING CHARACTERISTICS FOR FAST MODE (Figures 1a, 2)
Serial Clock Frequency f
SCL
400 kHz
Bus Free Time Between a STOP (P) and a START (S) Condition
t
BUF
1.3 µs
SYMBOL
MIN TYP MAX
660 1600
MAX1361
MAX1362
f
SAMPLE
f
SAMPLE
= 10ksps,
= 40ksps,
reference
reference
reference
reference
reference
reference
reference
reference
reference
reference
436 1350
900 1150 670 530 230 380
330
666 1600
436 1350
900 1150 670 530 230 380
330
330
±0.01 ±0.5
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 2.7V to 3.6V (MAX1361), VDD= 4.5V to 5.5V (MAX1362), V
REF
= 2.048V (MAX1361), V
REF
= 4.096V (MAX1362), C
REF
=
0.1µF, f
SCL
= 1.7MHz, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Hold Time for START (S) Condition
0.6 µs
Low Period of the SCL Clock t
LOW
1.3 µs
High Period of the SCL Clock t
HIGH
0.6 µs
Setup Time for a Repeated START Condition (Sr)
0.6 µs
Data Hold Time
0 900 ns
Data Setup Time
ns
Rise Time of Both SDA and SCL Signals, Receiving
t
R
Measured from 0.3VDD to 0.7V
DD
0 300 ns
Fall Time of SDA Transmitting
t
F
Measured from 0.3VDD to 0.7V
DD 0
300 ns
Setup Time for STOP (P) Condition
0.6 µs
Capacitive Load for Each Bus Line
C
B
400 pF
Pulse Width of Spike Suppressed
50 ns
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Figures 1a, 2) (Note 12)
Serial Clock Frequency f
SCLH
(Note 13) 1.7
MHz
Hold Time, Repeated START Condition (Sr)
ns
Low Period of the SCL Clock t
LOW
(Note 13)
ns
High Period of the SCL Clock t
HIGH
ns
Setup Time for a Repeated START Condition (Sr)
ns
Data Hold Time
(Note 14) 0 150 ns
Data Setup Time
10 ns
Rise Time of SCL Signal t
RCL
Measured from 0.3VDD to 0.7V
DD
20 80 ns
Rise Time of SCL Signal After Acknowledge Bit
t
RCL1
Measured from 0.3VDD to 0.7V
DD
20 160 ns
Fall Time of SCL Signal t
FCL
Measured from 0.3VDD to 0.7V
DD
20 80 ns
Rise Time of SDA Signal t
RDA
Measured from 0.3VDD to 0.7V
DD
20 160 ns
Fall Time of SDA Signal t
FDA
Measured from 0.3VDD to 0.7V
DD
20 160 ns
Setup Time for STOP (P) Condition
ns
Capacitive Load for Each Bus
C
B
400 pF
Pulse Width of Spike Suppressed
010ns
t
HD, STA
t
SU, STA
t
HD, DAT
t
SU, DAT
t
SU, STO
t
HD, STA
t
SU, STA
t
HD, DAT
t
SU, DAT
t
SU, STO
100
160 320
120 160
160
Typical Operating Characteristics
(VDD= 3.3V (MAX1361), VDD= 5V (MAX1362), f
SCL
= 1.7MHz, external clock, f
SAMPLE
= 94.4ksps, single-ended, unipolar,
TA= +25°C, unless otherwise noted.)
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable Trip Window and SMBus Alert Response
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 2.7V to 3.6V (MAX1361), VDD= 4.5V to 5.5V (MAX1362), V
REF
= 2.048V (MAX1361), V
REF
= 4.096V (MAX1362), C
REF
=
0.1µF, f
SCL
= 1.7MHz, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Note 1: Devices configured for unipolar single-ended inputs. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain and offset have
been calibrated.
Note 3: Offset nulled. Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period.
Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 5: The throughput rate of the I
2
C bus is limited to 94.4ksps. The MAX1361/MAX1362 can perform conversions up to 150ksps
in monitor mode when not reading back results on the I
2
C bus.
Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant. Note 7: The absolute input voltage range for the analog inputs (AIN0–AIN3) is from GND to V
DD
.
Note 8: When the internal reference is configured to be available at AIN3/REF (SEL[2:1] = 11), decouple AIN3/REF to GND with a
0.01µF capacitor.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µV
P-P
.
Note 10: Maximum conversion throughput in internal clock mode when the data is not clocked out. Note 11: For the MAX1361, PSRR is measured as
and for the MAX1362, PSRR is measured as
Note 12: C
B
= total capacitance of one bus line in pF.
Note 13: f
SCLH
must meet the minimum clock low time plus the rise/fall times.
Note 14: A master device must provide a data hold time for SDA (referred to V
IL
of SCL) to bridge the undefined region of SCL’s
falling edge.
VVVV
V
VV
FS FS
N
REF
(. ) (. )
(. . )
55 45
21
55 45
[]
×
⎢ ⎢
⎥ ⎥
VVVV
V
VV
FS FS
N
REF
(. ) (. )
(. . )
36 27
21
36 27
[]
×
⎢ ⎢
⎥ ⎥
-160
-140
-120
-100
-80
-60
-40
-20
0
0 1020304050
FFT PLOT
MAX1361 toc03
FREQUENCY (kHz)
AMPLITUDE (dBc)
f
SAMPLE
= 94.4ksps
f
IN
= 10kHz
-0.3
-0.1
-0.2
0.1
0
0.2
0.3
0 1000
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
MAX1361 toc01
DIGITAL OUTPUT CODE
DNL (LSB)
400200 600 800
-0.5
-0.2
-0.3
-0.4
-0.1
0
0.1
0.2
0.3
0.4
0.5
0 400200 600 800 1000
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
MAX1361 toc02
DIGITAL OUTPUT CODE
INL (LSB)
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
_______________________________________________________________________________________ 7
300
400 350
500 450
600 550
650
750 700
800
-40 -10 5-25 20 35 50 65 80
SUPPLY CURRENT vs. TEMPERATURE
MAX1361 toc04
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
INTERNAL REFERENCE
MAX1362
MAX1361
MAX1362
MAX1361
INTERNAL REFERENCE
EXTERNAL REFERENCE
EXTERNAL REFERENCE
SETUP BYTE EXT REF: 10111010 INT REF: 11011010
0
0.2
0.1
0.4
0.3
0.5
0.6
2.7 5.2
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1361 toc05
INPUT VOLTAGE (V)
I
DD
(µA)
3.73.2 4.2 4.7
SDA = SCL = V
DD
0
0.10
0.05
0.20
0.15
0.30
0.25
0.35
0.45
0.40
0.50
-40 -10 5-25 20 35 50 65 80
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX1361 toc06
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
MAX1362
MAX1361
200
300 250
350
400
450
500
550
600
650
700
750
800
0 20 30 40 60 80 100
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE (EXTERNAL CLOCK)
MAX1361 toc07
CONVERSION RATE (ksps)
AVERAGE I
DD
(µA)
010 50 70 90
A
B
A) INTERNAL REFERENCE ALWAYS ON B) EXTERNAL REFERENCE
0.9990
0.9994
0.9992
0.9998
0.9996
1.0002
1.0000
1.0004
1.0008
1.0006
1.0010
-40 -10 5-25 20 35 50 65 80
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1361 toc08
TEMPERATURE (°C)
V
REF
NORMALIZED
MAX1362
MAX1361
NORMALIZED TO REFERENCE VALUE AT +25°C
0.99990
0.99994
0.99992
0.99998
0.99996
1.00002
1.00000
1.00004
1.00008
1.00006
1.00010
2.7 3.3 3.6 3.93.0 4.2 4.5 4.8 5.1 5.4
NORMALIZED REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
MAX1361 toc09
VDD (V)
V
REF
NORMALIZED
MAX1362 NORMALIZED TO REFERENCE VALUE AT V
DD
= 5V
MAX1361 NORMALIZED TO REFERENCE VALUE AT V
DD
= 3.3V
-1.0
-0.8
-0.9
-0.6
-0.7
-0.4
-0.5
-0.3
-0.1
-0.2
0
-40 -10 5-25 2035506580
OFFSET ERROR vs. TEMPERATURE
MAX1361 toc10
TEMPERATURE (°C)
OFFSET ERROR (LSB)
-1.0
-0.8
-0.9
-0.6
-0.7
-0.4
-0.5
-0.3
-0.1
-0.2
0
2.7 3.3 3.6 3.93.0 4.2 4.5 4.8 5.1 5.4
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1361 toc11
VDD (V)
OFFSET ERROR (LSB)
Typical Operating Characteristics (continued)
(VDD= 3.3V (MAX1361), VDD= 5V (MAX1362), f
SCL
= 1.7MHz, external clock, f
SAMPLE
= 94.4ksps, single-ended, unipolar,
TA= +25°C, unless otherwise noted.)
0
0.2
0.1
0.4
0.3
0.6
0.5
0.7
0.9
0.8
1.0
-40 -10 5-25 2035506580
GAIN ERROR vs. TEMPERATURE
MAX1361 toc12
TEMPERATURE (°C)
GAIN ERROR (LSB)
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable Trip Window and SMBus Alert Response
8 _______________________________________________________________________________________
PIN NAME FUNCTION
1 AIN0 Analog Input 2 AIN1 Analog Input 3 AIN2 Analog Input 4 AIN3/V
REF
Analog Input or Reference Input or Output. See Table 3.
5A0I
2
C Address Select Input. Connect to VDD or GND. See Table 1. 6 INT Active-Low, Open-Drain Interrupt Output 7 SCL I2C Clock Input 8 SDA I2C Data Input/Output 9 GND Ground
10 V
DD
Positive Supply Voltage. Bypass V
DD
to GND with a 0.1µF capacitor.
Pin Description
MAX1361/MAX1362
10-BIT
ADC
4:1
MUX
CONTROL
TRIP
THRESHOLDS
I2C
INTERFACE
SDA SCL A0
INT
CLK
INT REF
GND
V
DD
AIN0
AIN1
AIN2
AIN3/
REF
Functional Diagram
0
0.3
0.2
0.1
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2.7 3.73.2 4.2 4.7 5.2
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1361 toc13
VDD (V)
GAIN ERROR (LSB)
MONITOR-MODE SUPPLY CURRENT
vs. SPEED
MAX1361 toc14
SPEED (ksps)
SUPPLY CURRENT (µA)
125100755025
100
200
300
400
500
600
700
0
0 150
INTERNAL REF
EXTERNAL REF
Typical Operating Characteristics (continued)
(VDD= 3.3V (MAX1361), VDD= 5V (MAX1362), f
SCL
= 1.7MHz, external clock, f
SAMPLE
= 94.4ksps, single-ended, unipolar,
TA= +25°C, unless otherwise noted.)
Detailed Description
The MAX1361/MAX1362 4-channel ADCs use succes­sive-approximation conversion techniques and fully dif­ferential input track/hold (T/H) circuitry to capture and convert analog signals to a serial 10-bit digital output. The MAX1361/MAX1362 feature a monitor mode with programmable trip thresholds and window comparator. The monitor function asserts an interrupt when any channel violates the programmed upper or lower thresholds. SMBus alert response allows the host microcontroller (µC) to quickly identify which device caused the interrupt. A programmable delay between monitoring intervals lowers power consumption at lower monitor rates.
The MAX1361/MAX1362 integrate an internal voltage reference and clock. The software configures the ana­log inputs for unipolar/bipolar and single-ended/fully differential operation. Integrated first-in/first-out (FIFO) allows conversion of all channels, or eight conversions
on a selected channel to reduce interface overhead. An I
2
C-compatible serial interface complies with standard,
fast, and high-speed (1.7MHz) modes.
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
_______________________________________________________________________________________ 9
t
SU.STA
t
SU.DAT
t
HIGH
t
R
t
F
t
HD.DAT
t
HD.STA
S
Sr
ACK
9
SCL
SDA
t
SU.STA
t
LOW
t
BUF
t
SU.STO
PS
t
R
t
F
Figure 1a. F/S-Mode 2-Wire Serial-Interface Timing
V
DD
I
OL
I
OH
V
OUT
400pF
SDA
Figure 2. Load Circuits
t
HD.STA
t
SU.DAT
t
HIGH
t
FCL
t
HD.DAT
t
HD.STA
Sr Sr
ACK
SCL
SDA
t
SU.STA
t
LOW
t
SU.STO
S
t
RCL
t
RCL1
HS-MODE
1 9
F/S-MODE
t
FDA
t
RDA
P
Figure 1b. HS-Mode 2-Wire Serial-Interface Timing
MAX1361/MAX1362
Power Supply
The MAX1361 (2.7V to 3.6V) and MAX1362 (4.5V to
5.5V) operate from a single supply and consume 670µA (typ) at sampling rates up to 94.4ksps and 436µA in monitor mode at 150ksps. The MAX1361 fea­tures a 2.048V internal reference and the MAX1362 fea­tures a 4.096V internal reference. All devices can be configured for use with an external reference from 1V to VDD. Bypass VDDto GND using a 0.1µF or greater ceramic capacitor for best performance.
Analog Input and Track/Hold
The MAX1361/MAX1362 analog-input architecture con­tains an analog-input multiplexer (MUX), fully differen­tial T/H, comparator, and a fully differential switched capacitive digital-to-analog converter (DAC). Figure 3 shows the equivalent input circuit for the MAX1361/ MAX1362.
In single-ended mode, the analog-input MUX connects C
T/H
between the analog input selected by CS[3:0] and GND (see the Configuration/Setup Bytes (Write Cycle) section). In differential mode, the analog-input MUX connects C
T/H
to the plus and minus analog inputs
selected by CS[3:0]. During the acquisition interval, the T/H switches are in
the track position, and C
T/H
charges to the analog-input signal. At the end of the acquisition interval, the T/H switches move to the hold position, retaining the charge on C
T/H
as a stable sample of the input signal.
During the conversion, a switched capacitive DAC adjusts to restore the comparator input voltage to 0V within the limits of 10-bit resolution. This action requires
10 conversion clock cycles and is equivalent to trans­ferring a charge of 11pF x (VIN+ - VIN-) from C
T/H
to the binary-weighted capacitive DAC, forming a digital rep­resentation of the analog-input signal.
Use a low source impedance to ensure an accurate sample. A source impedance of up to 1.5kdoes not significantly degrade sampling accuracy. For larger source impedances, connect a 100pF capacitor from the analog-input to GND or buffer the input.
In internal clock mode, the T/H circuitry enters track mode on the eighth rising clock edge of the address byte (see the Slave Address section). The T/H circuitry enters hold mode on the falling clock edge of the acknowledge bit of the address byte (the ninth clock pulse). The conversions are then internally clocked, dur­ing which time the MAX1361/MAX1362 hold SCL low.
In external clock mode, the T/H circuitry enters track mode after a valid address on the rising edge of the clock during the read bit (R/W = 1, bit 8). Hold mode is entered on the rising edge of the second clock pulse during the shifting out of the 1st byte of the result. The next 10 clock cycles perform the conversions (see Figure 13).
The time required for the T/H circuitry to acquire an input signal is a function of the input sample capaci­tance. If the analog-input source impedance is high, the acquisition-time constant lengthens and more time must be allowed between conversions. The acquisition time (t
ACQ
) is the minimum time needed for the signal
to be acquired. It is calculated by:
t
ACQ
7 x (R
SOURCE
+ RIN) x C
IN
4-Channel, 10-Bit, System Monitor with Programmable Trip Window and SMBus Alert Response
10 ______________________________________________________________________________________
TRACK
TRACK
HOLD
C
T/H
C
T/H
TRACK
TRACK
HOLD
AIN0
AIN1
AIN2
AIN3/REF
ANALOG INPUT MUX
CAPACITIVE DAC
REF
CAPACITIVE DAC
REF
MAX1361 MAX1362
HOLD
HOLD
TRACK
HOLD
VDD/2
Figure 3. Equivalent Input Circuit
where R
SOURCE
is the analog-input source impedance, RIN= 2.5k, and CIN= 22pF. For internal clock mode, t
ACQ
= 1.5 / f
SCL
, and for external clock mode t
ACQ
=
2 / f
SCL
.
Analog-Input Bandwidth
The MAX1361/MAX1362 feature input-tracking circuitry with a 5MHz small-signal bandwidth. The 5MHz input bandwidth makes it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high-fre­quency signals from aliasing into the frequency band of interest, use anti-aliasing filtering.
Analog-Input Range and Protection
Internal protection diodes clamp the analog inputs to V
DD
and GND. These diodes allow the analog inputs to swing from (GND - 0.3V) to (VDD+ 0.3V) without causing dam­age to the device. For accurate conversions the inputs must remain within 50mV below GND or above VDD.
Single-Ended/Differential Input
The SE/DIF of the configuration byte configures the MAX1361/MAX1362 analog-input circuitry for single­ended or differential input. In single-ended mode (SE/DIF = 1), the digital conversion results are the difference between the analog input selected by CS[3:0] and GND. In differential mode (SE/DIF = 0), the digital conversion results are the difference between the plus and the minus analog inputs selected by CS[3:0] (see Tables 5 and 6).
Unipolar/Bipolar
Unipolar mode sets the differential input range from 0 to V
REF
. A negative differential analog input in unipolar mode causes the digital output code to be zero. Selecting bipolar mode sets the differential input range to ±V
REF
/ 2. The digital output code is binary in unipo­lar mode and two’s complement in bipolar mode. (See the Transfer Functions section.)
In single-ended mode the MAX1361/MAX1362 always operate in unipolar mode. The analog inputs are inter­nally referenced to GND with a full-scale input range from 0 to V
REF
(Table 7).
Reference
SEL[1:0] of the setup byte controls the reference and the AIN3/REF configuration. When AIN3/REF is config­ured as a reference input or reference output (SEL0 =
1), differential conversions on AIN3/REF appear as if AIN3/REF is connected to GND. A single-ended conver­sion in scan mode on AIN3/REF is ignored by an internal limiter that sets the highest available channel at AIN2 (Table 2).
Internal Reference
The internal reference is 2.048V for the MAX1361 and
4.096V for the MAX1362. SEL0 of the setup byte con­trols whether AIN3/REF is used for an analog input or a reference (SEL0 = 0 selects AIN3/REF as AIN3, and SEL0 = 1 selects AIN3/REF as REF). Decouple AIN3/REF to GND with a 0.1µF capacitor and a 2k resistor in series when AIN3/REF is configured as an internal reference output (SEL[1:0] = 11). See the Typical Operating Circuit. Once powered up, the refer­ence remains on until reconfigured. Do not use the ref­erence to supply current for external circuitry.
External Reference
The external reference ranges from 1V to VDD. For max­imum conversion accuracy, the reference must deliver 40µA and have an impedance of 500or less. For noisy or high-output-impedance references, insert a
0.1µF bypass capacitor to GND as close to AIN3/REF as possible.
Clock Modes
The clock mode determines the conversion clock and the data acquisition and conversion time. The clock mode also affects the scan mode. The state of the setup byte’s INT/EXT clock bit determines the clock mode. At power-up, the MAX1361/MAX1362 default to internal clock mode (INT/EXT clock = 0).
Internal Clock
See the Configuration/Setup Bytes (Write Cycle) section. In internal clock mode (INT/EXT clock = 0), the MAX1361/ MAX1362 use an internal oscillator for the conversion clock. The MAX1361/MAX1362 begin tracking the analog input after a valid address on the eighth rising edge of the clock. On the falling edge of the ninth clock, the analog signal is acquired and the conversion begins. While con­verting, the MAX1361/MAX1362 hold SCL low (clock stretching). After completing the conversion, the results are stored in internal memory. For scan-mode configura­tions with multiple conversions (see the Scan Modes sec­tion), all conversions happen in succession with each additional result stored in memory. Once all conversions are complete, the MAX1361/MAX1362 release SCL, allowing it to go high. The master can now clock the results out in the same order as the scan conversion.
The converted results are read back in a FIFO sequence. If AIN3/REF is configured as a reference input or output, AIN3/REF is excluded from multichan­nel scan. If reading continues past the final result stored in memory, the pointer wraps around and points to the first result. Only the current conversion results are read from memory. The MAX1361/MAX1362 must
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
______________________________________________________________________________________ 11
MAX1361/MAX1362
be addressed with a read command to obtain new con­version results.
External Clock
See the Configuration/Setup Bytes (Write Cycle) section. When configured for external clock mode (INT/EXT = 1), the MAX1361/MAX1362 use SCL as the conversion clock. In external clock mode, the MAX1361/MAX1362 begin tracking the analog input on the eighth rising clock edge of a valid slave address byte. Two SCL clock cycles later, the analog signal is acquired and the conversion begins. Unlike internal clock mode, converted data is clocked out immediately in the format described in the Reading a Conversion (Read Cycle) section.
The device continuously converts input channels dictat­ed by the scan mode until given a not acknowledge (NACK). There is no need to readdress the device with a read command to obtain new conversion results.
The conversion must complete in 1ms or droop on the T/H capacitor degrades conversion results. Use inter­nal clock mode if the SCL clock period exceeds 60µs.
Use external clock mode for conversion rates from 40ksps to 94.4ksps. Use internal clock mode for con­versions under 40ksps. Internal clock mode consumes less power. Monitor mode always uses internal clock mode regardless of conversion rate.
Applications Section
Power-On Reset
The configuration and setup registers default to a sin­gle-ended, unipolar, single-channel conversion on AIN0 using the internal clock with VDDas the reference and AIN3/REF configured as an analog input. The memory contents are unknown at power-up (see the Software Description section).
I2C-Compatible 2-Wire Serial Interface
The MAX1361/MAX1362 use an I2C-compatible 2-wire interface consisting of a serial data line (SDA) and serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX1361/MAX1362 and the master at rates up to 1.7MHz. The master (typically a microcontroller) initiates data transfer on the bus and generates the SCL signal to permit data transfer. The MAX1361/MAX1362 behave as I2C slave devices that transfer and receive data.
SDA and SCL must be pulled high for proper I
2
C oper­ation. This is typically done with pullup resistors (750 or greater). Series resistors (RS) are optional (see the Typical Operating Circuit section). The resistors protect the input architecture of the MAX1361/MAX1362 from
high voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals.
One bit transfers during each SCL clock cycle. A mini­mum of nine clock cycles is required to transfer a byte in or out of the MAX1361/MAX1362 (8 bits and an ACK/NACK). The data on SDA must remain stable dur­ing the high period of the SCL clock pulse. Changes in SDA while SCL is high and stable are considered con­trol signals (see the START and STOP Conditions sec­tion). Both SDA and SCL remain high when the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condi­tion (S), which is a high-to-low transition on SDA while SCL is high. The master terminates a transmission with a STOP condition (P), which is a low-to-high transition on SDA while SCL is high (Figure 4). A repeated START condition (Sr) can be used in place of a STOP condition to leave the bus active and the mode unchanged (see the HS I
2
C Mode section).
Acknowledge and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the mas­ter and the MAX1361/MAX1362 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (Figure 5).
4-Channel, 10-Bit, System Monitor with Programmable Trip Window and SMBus Alert Response
12 ______________________________________________________________________________________
SCL
SDA
SP
Sr
Figure 4. START and STOP Conditions
SCL
SDA
S
NOT ACKNOWLEDGE
ACKNOWLEDGE
12 89
Figure 5. Acknowledge Bits
To generate a not-acknowledge condition, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves SDA high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuc­cessful data transfer, the bus master reattempts com­munication at a later time.
Slave Address
The MAX1361/MAX1362 have a 7-bit I2C slave address. The slave address is selected using A0. The MAX1361/MAX1362 (EUB, MEUB, and LEUB) have 3
base address options, allowing up to 6 devices concur­rently per I2C bus (see Table 1).
The MAX1361/MAX1362 continuously wait for a START condition followed by its slave address. When the device recognizes its slave address, it is ready to accept or send data depending on the R/W bit (Figure 6).
HS I2C Mode
At power-up, the MAX1361/MAX1362 bus timing is set for fast mode (F/S mode, up to 400kHz I2C clock), which limits the conversion rate to approximately 22ksps. Switch to high-speed mode (HS mode, up to 1.7MHz I2C clock) to achieve conversion rates up to 94.4ksps. The MAX1361/MAX1362 convert up to 150ksps in moni­tor mode, regardless of I2C mode. If conversion results are unread, I2C bandwidth limitations do not apply in monitor mode.
Select HS mode by addressing all devices on the bus with the HS-mode master code 0000 1XXX (X = don’t care). After successfully receiving the HS-mode master code, the MAX1361/MAX1362 issue a NACK, allowing SDA to be pulled high for one clock cycle (Figure 7).
After the NACK, the MAX1361/MAX1362 operate in HS mode. Send a repeated START (Sr) followed by a slave address to initiate HS-mode communication. If the mas­ter generates a STOP condition the MAX1361/MAX1362
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
______________________________________________________________________________________ 13
011 1000R/WACK
SLAVE ADDRESS
S
SCL
SDA
123456789
Figure 6. MAX1361/MAX1362 Slave Address Byte
A0 STATE SUFFIX ADDRESS
Low EUB 0110100
High EUB 0110101
Low MEUB 0110110
High MEUB 0110111
Low LEUB 0110010
High LEUB 0110011
Table 1. I2C Slave Selection Table
000 10XXXNACK
HS-MODE MASTER CODE
SCL
SDA
S Sr
F/S MODE HS MODE
Figure 7. F/S-Mode to HS-Mode Transfer
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable Trip Window and SMBus Alert Response
14 ______________________________________________________________________________________
START
CONDITION
START
ADDRESS
FROM THE MASTER
CONFIGURATION
BYTE FROM THE MASTER
SETUP
BYTE FROM THE MASTER
0 A A A STOP
R/W BIT FROM
THE MASTER
Figure 8. Example of Writing Setup and Control Bytes
START
CONDITION
START
ADDRESS
FROM THE MASTER
SETUP BYTE
FROM THE MASTER
MONITOR
SETUP BIT
ALARM RESET, SCAN
SPEED, INT_EN
0A 1A A
CH 0 LT [11:4] CH 0 LT [3:0]; UT [11:8] CH 1 LT [11:4]CH 0 UT [7:0]AAAASTOP
R/W BIT FROM
THE MASTER
Figure 9. Example of Extended Setup-Byte Writing
BIT
NAME
DESCRIPTION
The configuration byte always starts with 0.
6
5
SCAN1, SCAN0 = [0,0], scans from channel 0 to the upper channel chosen by CS1, CS0. SCAN1, SCAN0 = [0,1], converts a single channel chosen by CS1, CS0 eight times. SCAN1, SCAN0 = [1,0] monitor mode monitors from channel 0 to the upper channel chosen by CS1, CS0. SCAN1, SCAN0 = [1,1], single channel conversion for the channel is chosen by CS0, CS1.
4 CS3 3 CS2
CS3, CS2 = [1,1] enables readback of monitor-mode setup data.
2 CS1
1 CS0
Selects the upper limit of the channel range used for the conversion sequence in scan modes SCAN = [0,0] and monitor modes SCAN = [1,0]. Selects the conversion channel when SCAN = [0,1] or when SCAN = [1,1]. (Tables 5 and 6)
0
1 = single-ended inputs. 0 = differential inputs. AIN0 and AIN1 form the first differential pair and AIN2 and AIN3 form the second differential pair. (See Tables 4 and 5.) Selects single-ended or differential conversions. In single-ended mode, input signal voltages are referenced to GND. In differential mode, the voltage difference between two channels is measured. When single-ended mode is used, the MAX1361/MAX1362 perform unipolar conversions regardless of the UNI/BIP bit in the setup byte. (Table 7)
Table 2. Configuration Byte Format*
*Power-on defaults: 0x01
7(MSB) CONFIG
SCAN1
SCAN0
SE/DIF
return to F/S mode. Use a repeated START condition (Sr) in place of a STOP condition to leave the bus active and the mode unchanged.
Software Description
Configuration/Setup Bytes (Write Cycle)
A write cycle begins with the bus master issuing a START condition followed by 7 address bits and a write bit (R/W = 0). If the address byte is successfully received, the MAX1361/MAX1362 (slave) issue an ACK. The master then writes to the slave. If the most significant bit (MSB) is 1, the slave recognizes the received byte as the setup byte (Table 4). If the MSB is 0, the slave recognizes that byte as the configuration byte (Table 2). Write to the configuration byte before writing to the setup byte (Figure 8). If enabling RESET in the setup byte, rewrite the configuration byte after writing the setup byte, since RESET clears the contents of the configuration byte back to the power-up state.
When the monitor-setup bit of the setup byte is set to 1, writing extends up to 13 bytes to clock in monitor-setup data. Terminate writing monitor-setup data at any time by issuing a STOP or repeated START condition. If the slave receives a byte successfully, it issues an ACK (Figure 9).
Note: When operating in HS mode, a STOP condition returns the bus into F/S mode (see the HS I2C Mode section).
Automatic Shutdown
AutoShutdown occurs between conversions when the MAX1361/MAX1362 are idle. When operating in exter­nal clock mode, issue a STOP, NACK, or repeated START condition to place the devices in idle mode and benefit from automatic shutdown. A STOP condition is not necessary in internal clock mode for automatic shutdown because power-down occurs once all con­versions are complete. Shutdown reduces supply cur­rent to less than 0.5µA (external reference mode, typ) and 300µA (internal reference mode, typ).
When idle, the MAX1361/MAX1362 continuously wait for a START condition followed by their slave address. Upon reading a valid address byte, the MAX1361/ MAX1362 power up. The internal reference requires 10ms to wake up. Therefore, power up the internal ref­erence 10ms prior to conversion or leave the reference continuously powered. Wake-up is transparent when using an external reference or V
DD
as the reference.
Automatic shutdown results in dramatic power savings, particularly at slow conversion rates with internal clock. For example, using an external reference at a conver­sion rate of 10ksps, the average supply current for the MAX1361 is 60µA (typ) and drops to 6µA (typ) at 1ksps. At 0.1ksps, the average supply current is just 1µA. Table 3 shows AIN3/REF configuration and refer­ence power-down state.
Scan Modes
SCAN1 and SCAN0 of the configuration byte set the scan-mode configuration. When configuring AIN3/REF for reference input or output (SEL0 = 1), AIN3/REF is excluded from a multichannel scan. The scanned results write to memory in the same order as the con­version. Start a conversion sequence by initiating a read with the desired scan mode. Read the results from memory in the order they were converted (see the Reading a Conversion (Read Cycle) section).
Selecting channel scan mode [0,0] starts converting from channel 0 up to the channel chosen by CS1, CS0.
Selecting channel scan mode [0,1] converts the chan­nel selected by CS1, CS0 eight times and returns eight consecutive results.
Selecting monitor mode [1,0] initiates a continuous con­version scan sequence from channel 0 to the channel selected by CS1, CS0. See the Monitor Mode section for more details.
Selecting channel scan mode [1,1] performs a single conversion on the channel selected by CS1, CS0 and returns the result.
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
______________________________________________________________________________________ 15
SEL1 SEL0
INT REF
POWERDOWN
REFERENCE VOLTAGE AIN3/REF
INTERNAL
REFERENCE STATE
00 X V
DD
Analog input Always off 0 1 X External reference Reference input Always off 1 0 0 Internal reference Analog input Always off 1 0 1 Internal reference Analog input Always on 1 1 0 Internal reference Reference output Always off 1 1 1 Internal reference Reference output Always on
Table 3. Reference Voltage and AIN3/REF Format
MAX1361/MAX1362
Reading a Conversion (Read Cycle)
Initiate a read cycle to start a conversion sequence and to obtain conversion results. See the Scan Modes section for details on the channel-scan sequence. Read cycles begin with the bus master issuing a START condition followed by 7 address bits and a read bit (R/W = 1). After successfully receiving the address byte, the MAX1361/MAX1362 (slave) issue an ACK. The master then reads from the slave. (See Figures 10–13.)
The result is transmitted in 2 bytes. The 1st byte con­sists of a leading 1 followed by a 2-bit binary channel address tag, a 12/10 bit flag (0 for the MAX1361/ MAX1362), 2 bits of 1s, the first 2 bits of the data result, and the expected ACK from the master. The 2nd byte
4-Channel, 10-Bit, System Monitor with Programmable Trip Window and SMBus Alert Response
16 ______________________________________________________________________________________
BIT NAME DESCRIPTION
7 (MSB)
Setup Setup byte always starts with 1.
6 REF/AIN SEL1
5 REF/AIN SEL0
When [0,0], REF/AIN3 = AIN3, REF = V
DD.
When [0,1], REF/AIN3 = REF, REF = external reference. When [1,0], REF/AIN3 = AIN3, REF = internal reference. When [1,1], REF/AIN3 = REF, REF = internal reference. (Table 3)
4
INT REF Power
Down
1 = internal reference always powered up. 0 = internal reference always powered down. (Table 3)
3 INT/EXT Clock
0 = internal clock. 1 = external clock (MAX1361/MAX1362 use the SCL clock for conversions).
2 UNI/BIP
0 = unipolar. 1 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, analog signal in 0 to V
REF
range can
be converted. In differential bipolar mode, input signal can range from -V
REF
/ 2 to +V
REF
/ 2. When single-ended mode is chosen, the SE/DIF bit of configuration byte overrides UNI/BIP, and conversions are performed in unipolar mode.
1 Reset
1 = no action.
0 Monitor Setup
0 = no action. 1 = extends writing up to 13 bytes (104 bits) of alarm reset mask. Scans speed selection and alarm thresholds. See the Configuring Monitor Mode section.
Table 4. Setup-Byte Format*
*Power-on defaults: 0x82
CS1 CS0 CH0 CH1 CH2 CH3
00+ 01 + 10 + 11 +
Table 5. Channel Selection in Single­Ended Mode (SE/DIF = 1)
CS1 CS0 CH0 CH1 CH2 CH3
00+­01-+ 10 +­11 -+
Table 6. Channel Selection in Differential Mode (SE/DIF = 0)
SE/DIF UNI/BIP MODE
0 0 Differential inputs, unipolar 0 1 Differential inputs, bipolar 10
Single-ended inputs, unipolar
11
Single-ended inputs, unipolar
Table 7. SE/DIF and UNI/BIP Table
0 = resets INT and configuration register. Setup register and channel trip thresholds are unaffected.
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable
______________________________________________________________________________________ 17
HIGH
CH1
CH0
12/111100
00
HIGH
HIGH
DATA
D8D7D6D5D4D3D2D1D0
1
1 1 0/1
ACK/
NACK
Table 8. Data Format
START
CONDITION
START
ADDRESS
FROM THE MASTER
1, CH ADD, 10b/12b FLAG,
1,1 RESULT (2 MSBs)
RESULT (8 LSBs)
1 ACK ACK ACK STOP
R/W
t
ACQ
t
CONV
Figure 10. Example of Reading the Conversion Result—External Clock Mode
START
ADDRESS
FROM THE MASTER
MAX1361/MAX1362
KEEPS SCL LOW
RESULT (8 LSBs)
1, CH ADD, 10b/12b, 1,1
RESULT (2 MSBs)
1 ACK
ACK
ACK STOP
t
ACQ
t
CONV
6.8µs MAX
R/W
Figure 11. Example of a Single Conversion Using the Internal Clock, SCAN = 1,1
START
MAX1361/MAX1362
KEEPS SCL LOW
ADDRESS
FROM THE MASTER
1 ACK
ACKACK
t
ACQ
t
CONV
t
ACQ
t
CONV
CONVERSION 1
6.8µs MAX
CONVERSION 2
MAX1361/MAX1362
KEEPS SCL LOW
1, CH ADD, 10b/12b, 1,1
RESULT (2 MSBs)
RESULT 1
(8 LSBs)
STOPACK
ACK
1, CH ADD, 10b/12b, 1,1
RESULT (2 MSBs)
RESULT N
(8 LSBs)
t
ACQ
t
CONV
CONVERSION N
R/W
Figure 12. Example of Scan-Mode Conversions Using the Internal Clock, SCAN = 0,0 and 0,1
(MSB)
0/1 0/1
0 = 10b 1 = 12b
0/1 ACK 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
MAX1361/MAX1362
contains D7–D0. To read the next conversion result, issue an ACK. To stop reading, issue a NACK.
When the MAX1361/MAX1362 receive a NACK, they release SDA allowing the master to generate a STOP or a repeated START condition.
Monitor Mode
Monitor-Mode Overview
The MAX1361/MAX1362 automatically monitor up to four input channels. For systems with limited I2C bandwidth, monitor mode allows the µC to set a window by programming lower and upper thresholds during initial­ization, and only intervening if the MAX1361/MAX1362 detect an alarm condition. This allows an interrupt-driven approach as an alternative to continuously polling the ADC with the µC. Monitor mode reduces processor over­head and conserves I2C bandwidth.
The following shows an example of events in monitor mode:
1) Fault condition(s) detected, INT asserted.
2) Host µC services interrupt and send SMBus alert to identify the alarming device. The MAX1361/ MAX1362 respond with the I2C slave address, pending arbitration rules. (See the SMBus Alert sec­tion.)
3) The MAX1361/MAX1362 release the INT.
4) Host-µC reads the alarm-status register, latched­fault register, and current-conversion results to determine the alarming channel(s) and course of action.
5) Host µC services alarm(s); adjusts system parame­ters as needed and/or adjust lower and upper thresholds.
6) Clears the alarm register. See the Configuring Monitor Mode section.
7) Monitor mode resumes.
8) If there is still an active fault, the device asserts INT again. See step 1.
Writing SCAN1 and SCAN0 bits = [1,0] in the configura­tion byte activates monitor mode. The MAX1361/ MAX1362 scan from channels 0 up to the channel selected by [CS1:CS0] at a rate determined by the scan delay bits. The MAX1361/MAX1362 compare the conversion results with the lower and upper thresholds for each channel. When any conversion exceeds the threshold, the MAX1361/MAX1362 assert an interrupt by pulling INT low (if enabled). The MAX1361/ MAX1362 set the corresponding flag bit in the alarm­status register and write conversion results to the latched-fault register to record the event causing the alarm condition.
INT active state is randomly delayed with respect to the conversion. Depending on the number of channels scanned and the position in the channel scan sequence, the maximum possible delay for asserting INT is five conversion periods (34µs typ, delay = 0,0,0).
Configuring Monitor Mode
To write monitoring setup data, set the monitor-setup bit (bit 0 in setup byte) to 1 to extend writing up to 104 bits (13 bytes) of monitoring setup data. The number of bits written to the MAX1361/MAX1362 depends on whether the part is in single-ended or differential mode and whether the upper channel limit is set by [CS1:CS0] (Table 9).
Terminate writing at any time by using a STOP or repeated START condition. Previous monitoring setup data not overwritten remains valid.
4-Channel, 10-Bit, System Monitor with Programmable Trip Window and SMBus Alert Response
18 ______________________________________________________________________________________
ACK ACK
1, CH ADD, 10b/12b, 1,1
RESULT (2 MSBs)
RESULT N (8 LSBs)
t
ACQ
t
ACQ
CONVERSION 1
t
ACQ
t
ACQ
CONVERSION N
START
ADDRESS
FROM THE MASTER
1, CH ADD, 10b/12b
1,1 RESULT (2 MSBs)
RESULT (8 LSBs)
1 ACK ACK ACK
R/W
Figure 13. Example of Scan-Mode Conversions Using the External Clock, SCAN = 0,0 and 0,1
A 1 written to the reset alarm CH_ clears the alarm, oth­erwise no action occurs (Table 10). Deassert INT by clearing all alarms or by initiating an SMBus alert dur­ing an alarm condition (see the SMBus Alert section)
The Delay 2, Delay 1, Delay 0 bits set the speed of monitoring by changing the delay between conver­sions. Delay 2, 1, 0 = 000 sets the maximum possible speed; 001 divides the maximum speed by ~2. Increasing delay values further divides the previous speed by two (Table 11).
INT_EN controls the open-drain INT output. Set INT_EN to 1 to enable the hardware interrupt. Set INT_EN to 0 to disable the hardware interrupt output. The INT output is high impedance when disabled or when there are no alarms. The master can also poll the alarm status regis­ter at any time to check the alarm status.
Repeat clocking channel threshold data up to the chan­nel programmed by CS1 and CS0 (Table 12). For differ­ential input mode, omit odd channels; the lower and upper threshold data applies to channel pairs. There is no need to clock in dummy data for odd (or even) channels (Table 6).
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
______________________________________________________________________________________ 19
Alarm reset, scan
speed, INT_EN ,
(8 bits)
AIN0 thresholds
(24 bits)
AIN1 thresholds
(skip if differential mode, or
CS1, CS0 < 1) (24 bits)
AIN2 thresholds (skip if
CS1, CS0 < 2)
(24 bits)
AIN3 thresholds (skip if differential
mode, or CS1, CS0 < 3)
(24 bits)
Table 9. Monitor-Mode Setup Data Format
RESET
ALARM CH 0
RESET
RESET
RESET
DELAY 2 DELAY 1 DELAY 0 INT_EN
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Table 10. Alarm Reset, Scan Speed Register, and INT_EN Data Format
DELAY 2
DELAY 1
DELAY 0
MONITOR-MODE
CONVERSION RATE
(ksps)
0 0 0 150.0* 0 0 1 75.0 0 1 0 37.5 0 1 1 18.8 100 9.4 101 4.7 110 2.3 111 1.2
Table 11. Delay Settings
*When using delay = [0,0,0] in internal reference mode and AIN3/REF configured as a REF output, the MAX1361/MAX1362 may exhibit a code-dependant gain error due to insufficient internal reference drive. Gain error caused by this phenomenon is typically less than 1%FSR (0.1µF C
REF
in series with a 2k
resistor) and increases with a larger C
REF
. Avoid this gain error
by using an external reference, V
DD
, as a reference or use an
internal reference with AIN3/REF as an analog input (see Table
4). Alternatively, choose delay bits other than [0,0,0] to lower the conversion rate.
BYTE B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE
1XX
LT9
(MSB)
LT8 LT7 LT6 LT5 LT4 ACK
2 LT3 LT2 LT1
XX
UT9
(MSB)
UT8 ACK
3 UT7 UT6 UT5 UT4 UT3 UT2 UT1
ACK
Table 12. Lower and Upper Threshold Data Format
X = Don’t care. ACK = Acknowledge.
ALARM CH 1
ALARM CH 2
ALARM CH 3
LT0 (LSB)
UT0 (LSB)
MAX1361/MAX1362
To disable alarming on a specific channel, set the lower threshold to 0x800 and the upper threshold to 0x7FF for bipolar mode, or set the lower threshold to 0x000 and the upper threshold to 0xFFF for unipolar mode.
Readback Mode
Select readback mode by setting CS3, CS2 to [1,1] in the configuration byte. Begin a read operation to start reading back monitor-setup data. Clock out delay bit settings, INT_EN bit, and the lower and upper thresh­olds programmed for each channel. Readback mode follows exactly the same format as writing to the moni­tor-setup data, with the exception of the first 4 alarm­reset bits, which are always 1 (Table 13).
Reading in Monitor Mode
Reading in monitor mode reads back the alarm-status register, latched-fault register, and current-conversion results as shown in Table 14.
The MAX1361/MAX1362 register pointer loops back to the beginning of the current-conversion result after reading the last conversion result. Stop reading at any time by asserting a STOP condition or NACK.
Note: The MAX1361/MAX1362 do not update the cur­rent-conversion results register while reading in monitor
mode. Monitor mode resumes after a STOP condition or NACK.
Alarm-Status Register
The latched-fault register records a snapshot of the alarming channel at the instance that a fault condition is asserted. An alarm-status bit of 1 (Table 15) indicates a fault, and the data in the latched-fault register of the corresponding channel contains the conversion result that caused the alarm to trip. Resetting alarms does not clear the latched-fault register, thus the latched-fault register contains valid data only if an alarm status bit is high for the given channel.
The current-conversion register contains the most recent conversion results. If the user attempts to read past the last result of the current-conversion register, the MAX1361/MAX1362 wraps back to the beginning of the current-conversion result.
The latched-fault register and current-conversion regis­ter follow the data format detailed in Tables 8 and 16. Register length depends on the number of conversions in one monitoring sequence. For example, when chan­nel pairs 0/1 and channels 2/3 are monitored differen­tially, there are only two conversion results to report. The latched-fault register is 2 x 16 bits long, after which two current-conversion results follow. Likewise, if CS0 and CS1 limit the upper bound of the channel scan range from CH0 to CH2 in single-ended mode, the latched­fault register clocks out 3 x 16 bits of data followed by the current-conversion results, also 3 x 16 bits.
4-Channel, 10-Bit, System Monitor with Programmable Trip Window and SMBus Alert Response
20 ______________________________________________________________________________________
SCAN SPEED AND INT_EN
AIN0
AIN1 THRESHOLDS
(SKIP IF DIFFERENTIAL
AIN2 THRESHOLDS
AIN3 THRESHOLDS
(SKIP IF DIFFERENTIAL
MODE OR CS1, CS0 < 3)
1
24 bits 24 bits 24 bits 24 bits
Table 13. Readback-Mode Format
ALARM-STATUS REGISTER
LATCHED-FAULT REGISTER CURRENT-CONVERSION RESULTS
8 bits
16, 32, 48, or 64 bits (depends on CSO, CS1,
and SE/DIF)
16, 32, 48, or 64 bits (depends on CSO, CS1,
and SE/DIF)
Table 14. Reading in Monitor-Mode Data Format
CH0 UP CH0 LOW CH1 UP CH1 LOW CH2 UP CH2 LOW CH3 UP CH3 LOW
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Table 15. Alarm-Status Register
0 = Not-alarm condition. 1 = Alarm condition.
AIN0 AIN1 AIN2 AIN3
16-bit read
16-bit read
Table 16. Latched-Fault and Current­Conversion Register
THRESHOLDS
1 1 1 D2 D1 D0 INT_EN
MODE OR CS1, CS0 < 1)
16-bit read 16-bit read
(SKIP IF CS1, CS0 < 2)
Resetting Alarm
Reset alarms by writing to monitor-setup data. See the Configuring Monitor Mode section and Table 10.
SMBus Alert
The SMBus-alert feature provides a quick method to identify alarming devices on a shared interrupt. Upon receiving an interrupt signal, the host µC can broadcast a receive byte request to the alert-response slave address (0001100). Any slave device that generated an interrupt attempts to identify itself by putting its own address on the bus. The alert response can activate several different slave devices simultaneously. If more than one slave attempts to respond, bus arbitration rules apply, and the device with the lower address wins as a consequence of the open-collector bus. The losing device does not generate an acknowledgement and continues to hold the alert line low until serviced. Successful reading of the alert response address de­asserts INT.
The MAX1361/MAX1362 resume monitoring after clean­ing an alarm-status register. INT may immediately re­assert if a fault is still present, or if the alarm register has not been thoroughly cleared.
Transfer Functions
Output data coding for the MAX1361/MAX1362 is bina­ry in unipolar mode and two’s complement in bipolar mode with 1 LSB = V
REF
/ 2N, where N is the number of
bits. Code transitions occur halfway between succes-
sive-integer LSB values. Figures 14 and 15 show the transfer functions for unipolar and bipolar operations, respectively.
Layout, Grounding, and Bypassing
Only use PC boards. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run ana­log and digital lines parallel to each other, and do not layout digital signal paths underneath the ADC pack­age. Use separate analog and digital PC board ground sections with only one star point (Figure 16).
High-frequency noise in the power supply (VDD) could influence the proper operation of the ADC’s fast com­parator. Bypass VDDto the star ground with a network of two parallel capacitors, 0.1µF and 4.7µF, located as close as possible to the MAX1361/MAX1362 power sup­ply. Minimize capacitor lead length for best supply noise rejection. For extremely noisy supplies, add an attenua­tion resistor (5) in series with the power supply.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
______________________________________________________________________________________ 21
111...111
OUTPUT CODE
FS = REF + GND ZS = GND
FULL-SCALE
TRANSITION
111...110
100...010
100...001
100...000
011...111
011...110
011...101
000...001
000...000
0
1
512
INPUT VOLTAGE (LSB)(GND)
1 LSB =
V
REF
1024
FS - 0.5 LSB
Figure 14. Unipolar Transfer Function
011...111
OUTPUT CODE
ZS = AIN-
011...110
000...010
000...001
000...000
111...111
111...110
111...101
100...001
100...000
AIN-
INPUT VOLTAGE (LSB)
+FS - 1 LSB
1 LSB =
V
REF
1024
AIN-
V
REF
2
FS =
V
REF
+ AIN-
2
-FS =
-V
REF
+ AIN-
2
-FS + 0.5 LSB
Figure 15. Bipolar Transfer Function
MAX1361/MAX1362
MAX1361/MAX1362’s INL is measured using the end­point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples.
Aperture Delay
Aperture delay (tAD) is the time between the falling edge of the sampling clock and the instant when an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza­tion error only and results directly from the ADC’s reso­lution (N bits):
SNR (MAX)[dB] = 6.02dB x N + 1.76dB
In reality, there are other noise sources besides quanti­zation noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five har­monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to RMS equivalent of all other ADC output signals.
SINAD(dB) = 20 x log (SignalRMS / NoiseRMS)
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quanti­zation noise only. With an input range equal to the ADC’s full-scale range, calculate the ENOB as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal’s first five harmonics to the fun­damental itself. This is expressed as:
where V1is the fundamental amplitude, and V2through V5are the amplitudes of the 2nd- through 5th-order harmonics.
THD
VVVV
V
+++
⎜ ⎜ ⎜
⎟ ⎟ ⎟
20
2
2
3
2
4
2
5
2
1
log
SINAD dB
Signal
Noise THD
RMS
RMS RMS
( ) log
+
⎢ ⎢
⎥ ⎥
20
4-Channel, 10-Bit, System Monitor with Programmable Trip Window and SMBus Alert Response
22 ______________________________________________________________________________________
GND
V
LOGIC
= 3V / 5V3V OR 5V
SUPPLIES
DGND3V/5VGND
*OPTIONAL
4.7µF
R* = 5
0.1µF
V
DD
DIGITAL
CIRCUITRY
MAX1361 MAX1362
Figure 16. Power-Supply Grounding Connection
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
______________________________________________________________________________________ 23
Ordering Information/Selector Guide (continued)
PART TEMP RANGE PIN-PACKAGE I2C SLAVE ADDRESS
SUPPLY VOLTAGE (V)
MAX1362EUB -40°C to +85°C 10 µMAX 0110100/0110101 4.5 to 5.5
MAX1362LEUB* -40°C to +85°C 10 µMAX 0110010/0110011 4.5 to 5.5 MAX1362MEUB* -40°C to +85°C 10 µMAX 0110110/0110111 4.5 to 5.5
Pin Configuration
*OPTIONAL
*R
S
*R
S
ANALOG
INPUTS
µ
C
SDA
SCL
GND
V
DD
SDA
SCL
AIN0 AIN1
AIN3/REF
0.1µF
0.1µF
2k
R
P
R
P
C
REF
R
P
3V/5V
3V/5V
3V/5V
MAX1361 MAX1362
INT
INT
4.7µF
Typical Operating Circuit
*Future product—contact factory for availability.
TOP VIEW
AIN0
1
AIN1
2
AIN2
REF
A0 INT
MAX1361
3
MAX1362
4 5
µMAX
10
9 8 7 6
V GND SDA SCLAIN3/V
DD
MAX1361/MAX1362
4-Channel, 10-Bit, System Monitor with Programmable Trip Window and SMBus Alert Response
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages
.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
10LUMAX.EPS
PACKAGE OUTLINE, 10L uMAX/uSOP
1
1
21-0061
I
REV.DOCUMENT CONTROL NO.APPROVAL
PROPRIETARY INFORMATION
TITLE:
TOP VIEW
FRONT VIEW
1
0.498 REF
0.0196 REF
S
SIDE VIEW
α
BOTTOM VIEW
0.037 REF
0.0078
MAX
0.006
0.043
0.118
0.120
0.199
0.0275
0.118
0.0106
0.120
0.0197 BSC
INCHES
1
10
L1
0.0035
0.007
e
c
b
0.187
0.0157
0.114 H L
E2
DIM
0.116
0.114
0.116
0.002
D2 E1
A1
D1
MIN
-A
0.940 REF
0.500 BSC
0.090
0.177
4.75
2.89
0.40
0.200
0.270
5.05
0.70
3.00
MILLIMETERS
0.05
2.89
2.95
2.95
-
MIN
3.00
3.05
0.15
3.05
MAX
1.10
10
0.6±0.1
0.6±0.1
0 0.50±0.1
H
4X S
e
D2
D1
b
A2
A
E2
E1
L
L1
c
α
GAGE PLANE
A2 0.030 0.037 0.75 0.95
A1
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