General Description
The MAX1302/MAX1303 multirange, low-power, 16-bit,
successive-approximation, analog-to-digital converters
(ADCs) operate from a single +5V supply and achieve
throughput rates up to 115ksps. A separate digital supply allows digital interfacing with 2.7V to 5.25V systems
using the SPI™-/QSPI™-/MICROWIRE™-compatible
serial interface. Partial power-down mode reduces the
supply current to 1.3mA (typ). Full power-down mode
reduces the power-supply current to 1µA (typ).
The MAX1302 provides eight (single-ended) or four
(true differential) analog input channels. The MAX1303
provides four (single-ended) or two (true differential)
analog input channels. Each analog input channel is
independently software programmable for seven
single-ended input ranges (0 to +V
REF
/2, -V
REF
/2 to 0,
0 to +V
REF
, -V
REF
to 0, ±V
REF
/4, ±V
REF
/2, and ±V
REF
),
and three differential input ranges (±V
REF
/2, ±V
REF
,
±2 x V
REF
).
An on-chip +4.096V reference offers a small convenient
ADC solution. The MAX1302/MAX1303 also accept an
external reference voltage between 3.800V and 4.136V.
The MAX1302 is available in a 24-pin TSSOP package
and the MAX1303 is available in a 20-pin TSSOP package. Each device is specified for operation from -40°C
to +85°C.
Applications
Industrial Control Systems
Data-Acquisition Systems
Avionics
Robotics
Features
♦ Software-Programmable Input Range for Each
Channel
♦ Single-Ended Input Ranges
0 to +V
REF
/2, -V
REF
/2 to 0, 0 to +V
REF
, -V
REF
to 0, ±V
REF
/4, ±V
REF
/2, and ±V
REF
♦ Differential Input Ranges
±V
REF
/2, ±V
REF
, and ±2 x V
REF
♦ Eight Single-Ended or Four Differential Analog
Inputs (MAX1302)
♦ Four Single-Ended or Two Differential Analog
Inputs (MAX1303)
♦ ±6V Overvoltage Tolerant Inputs
♦ Internal or External Reference
♦ 115ksps Maximum Sample Rate
♦ Single +5V Power Supply
♦ 20-/24-Pin TSSOP Package
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
________________________________________________________________ Maxim Integrated Products 1
Pin Configurations
Ordering Information
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
AGND1
AGND2
AV
DD2
AGND3CH2
CH1
CH0
AV
DD1
TOP VIEW
REF
REFCAP
DV
DD
DV
DDO
CH6
CH5
CH4
CH3
16
15
14
13
9
10
11
12
DGND
DGNDO
DOUT
SCLKSSTRB
DIN
CS
CH7
TSSOP
MAX1302
19-3576; Rev 1; 12/06
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART
PIN-
C H A N N EL S
PKG CODE
MAX1302AEUG*
24 TSSOP 8 U24-1
MAX1302BEUG*
24 TSSOP 8 U24-1
MAX1303AEUP* 20 TSSOP 4 U20-2
MAX1303BEUP 20 TSSOP 4 U20-2
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Pin Configurations continued at end of data sheet.
*Future product—contact factory for availability.
Note: All devices are specified over the -40°C to +85°C operating temperature range.
PACKAGE
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(AV
DD1
= AV
DD2
= DVDD= DV
DDO
= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f
CLK
= 3.5MHz (50% duty cycle),
external clock mode, V
REF
= 4.096V (external reference operation), REFCAP = AV
DD1
, maximum single-ended bipolar input range
(±V
REF
), C
DOUT
= 50pF, C
SSTRB
= 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AV
DD1
to AGND1 ....................................................-0.3V to +6V
AV
DD2
to AGND2 ....................................................-0.3V to +6V
DVDDto DGND ........................................................-0.3V to +6V
DV
DDO
to DGNDO ..................................................-0.3V to +6V
DVDDto DV
DDO
......................................................-0.3V to +6V
DVDD, DV
DDO
to AV
DD1
........................................-0.3V to +6V
AV
DD1
, DVDD, DV
DDO
to AV
DD2
..........................-0.3V to +6V
DGND, DGNDO, AGND3, AGND2 to AGND1 ......-0.3V to +0.3V
CS, SCLK, DIN, DOUT, SSTRB to
DGNDO ............................................-0.3V to (DV
DDO
+ 0.3V)
CH0–CH7 to AGND1 ...................................................-6V to +6V
REF, REFCAP to AGND1.......................-0.3V to (AV
DD1
+ 0.3V)
Continuous Current (any pin) ...........................................±50mA
Continuous Power Dissipation (T
A
= +70°C)
20-Pin TSSOP (derate 11mW/°C above +70°C) ..........879mW
24-Pin TSSOP (derate 12.2mW/°C above +70°C) .......976mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER
CONDITIONS
UNITS
DC ACCURACY (Notes 1, 2)
Resolution 16 Bits
MAX130_A
±2
Integral Nonlinearity INL
MAX130_B
±4
LSB
Differential Nonlinearity DNL No missing codes -1 +2 LSB
Transition Noise External or internal reference 1
LSB
RMS
Unipolar 0
Bipolar
Unipolar 0
Offset Error
Differential inputs
(Note 3)
Bipolar
mV
Channel-to-Channel Gain
Matching
Unipolar or bipolar
%FSR
Channel-to-Channel Offset Error
Matching
Unipolar or bipolar 1.0 mV
Unipolar 10
Offset Temperature Coefficient
Bipolar 5
ppm/°C
Unipolar
Gain Error
Bipolar
%FSR
Unipolar 1.5
Gain Temperature Coefficient
Bipolar 1.0
ppm/°C
Unipolar Endpoint Overlap
Negative unipolar full scale to positive
unipolar zero-scale
020 LSB
DYNAMIC SPECIFICATIONS f
IN(SINE-WAVE)
= 5kHz, VIN = FSR - 0.05dB, f
SAMPLE
= 130ksps (Notes 1, 2)
Differential inputs, FSR = 2 x V
REF
90
Single-ended inputs, FSR = V
REF
88
Single-ended inputs, FSR = V
REF
/ 2 85
Signal-to-Noise Plus Distortion SINAD
Single-ended inputs, FSR = V
REF
/ 4 80 82
dB
SYMBOL
MIN TYP MAX
±1.0
±1.0
Single-ended inputs
-1.0 ±10
-2.0 ±20
0.025
±10
±20
±0.5
±0.3
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD1
= AV
DD2
= DVDD= DV
DDO
= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f
CLK
= 3.5MHz (50% duty cycle),
external clock mode, V
REF
= 4.096V (external reference operation), REFCAP = AV
DD1
, maximum single-ended bipolar input range
(±V
REF
), C
DOUT
= 50pF, C
SSTRB
= 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
CONDITIONS
UNITS
Differential inputs, FSR = 2 x V
REF
90
Single-ended inputs, FSR = V
REF
88
Single-ended inputs, FSR = V
REF
/ 2 85
Signal-to-Noise Ratio SNR
Single-ended inputs, FSR = V
REF
/ 4 82
dB
Total Harmonic Distortion
(Up to the 5th Harmonic)
THD -98 dB
Spurious-Free Dynamic Range SFDR 92 99 dB
Aperture Delay t
AD
Figure 21 15 ns
Aperture Jitter t
AJ
Figure 21
ps
Channel-to-Channel Isolation
dB
CONVERSION RATE
External clock mode, Figure 2
External acquisition mode, Figure 3 84Byte-Wide Throughput Rate
Internal clock mode, Figure 4
ksps
ANALOG INPUTS (CH0–CH3 MAX1303, CH0–CH7 MAX1302, AGND1)
Small-Signal Bandwidth All input ranges, VIN = 100mV
P-P
(Note 2) 1.5
MHz
Full-Power Bandwidth All input ranges, VIN = 4V
P-P
(Note 2)
kHz
R[2:1] = 001
R[2:1] = 010
0
R[2:1] = 011 0
R[2:1] = 100
R[2:1] = 101
0
R[2:1] = 110 0
Input Voltage Range (Table 6) V
CH_
R[2:1] = 111
V
Tr ue- D i ffer enti al Anal og C om m onM od e V ol tag e Rang e
V
CMDR
DIF/SGL = 1 (Note 4)
V
Common-Mode Rejection Ratio CMRR
75 dB
Input Current I
CH_
-V
REF
< V
CH_
< +V
REF
µA
Input Capacitance C
CH_
5pF
Input Resistance R
CH_
6kΩ
SYMBOL
f
SAMPLE
D IF/S G L = 1, i np ut vol tag e r ang e = ± V
/ 4
R E F
MIN TYP MAX
100
105
-V
REF
-V
REF
-V
REF
-V
REF
-V
REF
-4.75 +5.50
-1500 +650
700
/ 4 +V
/ 2
+V
/ 2 +V
114
106
/ 4
REF
/ 2
REF
/ 2
REF
+V
REF
+V
REF
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD1
= AV
DD2
= DVDD= DV
DDO
= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f
CLK
= 3.5MHz (50% duty cycle),
external clock mode, V
REF
= 4.096V (external reference operation), REFCAP = AV
DD1
, maximum single-ended bipolar input range
(±V
REF
), C
DOUT
= 50pF, C
SSTRB
= 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
CONDITIONS
UNITS
INTERNAL REFERENCE (Bypass REFCAP with 0.1µF to AGND1 and REF with 1.0µF to AGND1)
Reference Output Voltage V
REF
V
Reference Temperature
Coefficient
TC
REF
ppm/°C
REF shorted to AGND1 10
Reference Short-Circuit Current I
REFSC
REF shorted to AV
DD
-1
mA
Reference Load Regulation I
REF
= 0 to 0.5mA 0.1 10 mV
EXTERNAL REFERENCE (REFCAP = AVDD)
Reference Input Voltage Range V
REF
V
REFCAP Buffer Disable
Threshold
V
RCTH
(Note 5)
V
V
REF
= +4.096V, external clock mode,
external acquisition mode, internal clock
mode, or partial power-down mode
90
Reference Input Current I
REF
V
REF
= +4.096V, full power-down mode
µA
External clock mode, external acquisition
mode, internal clock mode, or partial
power-down mode
20 45 kΩ
Reference Input Resistance R
REF
Full power-down mode 40 MΩ
DIGITAL INPUTS (DIN, SCLK, CS)
Input High Voltage V
IH
0.7 x
V
Input Low Voltage V
IL
0.3 x
V
Input Hysteresis V
HYST
0.2 V
Input Leakage Current I
IN
VIN = 0 to DV
DDO
-10
µA
Input Capacitance C
IN
10 pF
DIGITAL OUTPUTS (DOUT, SSTRB)
DV
DDO
= 4.75V, I
SINK
= 10mA 0.4
Output Low Voltage V
OL
DV
DDO
= 2.7V, I
SINK
= 5mA 0.4
V
Output High Voltage V
OH
I
SOURCE
= 0.5mA
V
DOUT Tri-State Leakage Current
I
DDO
CS = DV
DDO
-10
µA
POWER REQUIREMENTS (AV
DD1
and AGND1, AV
DD2
and AGND2, DVDD and DGND, DV
DDO
and DGNDO)
Analog Supply Voltage AV
DD1
V
Digital Supply Voltage DV
DD
V
SYMBOL
MIN TYP MAX
4.056 4.096 4.136
±30
3.800 4.136
AV
DD1
- 0.4
DV
DDO
DV
DDO
- 0.4
4.75 5.25
4.75 5.25
±0.1 ±10
AV
DD1
- 0.1
200
DV
DDO
+10
+10
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD1
= AV
DD2
= DVDD= DV
DDO
= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f
CLK
= 3.5MHz (50% duty cycle),
external clock mode, V
REF
= 4.096V (external reference operation), REFCAP = AV
DD1
, maximum single-ended bipolar input range
(±V
REF
), C
DOUT
= 50pF, C
SSTRB
= 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
CONDITIONS
UNITS
Preamplifier Supply Voltage AV
DD2
V
Digital I/O Supply Voltage DV
DDO
V
Internal reference 3 3.5
AV
DD1
Supply Current I
AVDD1
External clock mode,
external acquisition
mode, or internal
clock mode
External reference 2.5 3
mA
DVDD Supply Current I
DVDD
External clock mode, external acquisition
mode, or internal clock mode
0.9 2 mA
AV
DD2
Supply Current I
AVDD2
External clock mode, external acquisition
mode, or internal clock mode
25 mA
DV
DDO
Supply Current
External clock mode, external acquisition
mode, or internal clock mode
0.2 1 mA
Partial power-down mode 1.3 mA
Total Supply Current
Full power-down mode 2 µA
Power-Supply Rejection Ratio PSRR All analog input ranges
LSB
TIMING CHARACTERISTICS (Figures 15 and 16)
External clock mode
62
External acquisition mode
62SCLK Period t
CP
Internal clock mode
83
µs
External clock mode
External acquisition mode 92
SCLK High Pulse Width (Note 6)
t
CH
Internal clock mode 40
ns
External clock mode
External acquisition mode 92
SCLK Low Pulse Width (Note 6) t
CL
Internal clock mode 40
ns
DIN to SCLK Setup t
DS
40 ns
DIN to SCLK Hold t
DH
0ns
SCLK Fall to DOUT Valid t
DO
40 ns
CS Fall to DOUT Enable t
DV
40 ns
SYMBOL
I
DVDDO
MIN TYP MAX
4.75 5.25
2.70 5.25
17.5
±0.5
272
228
100
109
109
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD1
= AV
DD2
= DVDD= DV
DDO
= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f
CLK
= 3.5MHz (50% duty cycle),
external clock mode, V
REF
= 4.096V (external reference operation), REFCAP = AV
DD1
, maximum single-ended bipolar input range
(±V
REF
), C
DOUT
= 50pF, C
SSTRB
= 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CS Rise to DOUT Disable t
TR
40 ns
CS Fall to SCLK Rise Setup t
CSS
40 ns
CS High Minimum Pulse Width t
CSPW
40 ns
SCLK Fall to CS Rise Hold t
CSH
0ns
SSTRB Rise to CS Fall Setup (Note 4) 40 ns
DOUT Rise/Fall Time CL = 50pF 10 ns
SSTRB Rise/Fall Time CL = 50pF 10 ns
Note 1: Parameter tested at AV
DD1
= AV
DD2
= DVDD= DV
DDO
= 5V.
Note 2: See definitions in the Parameter Definitions section at the end of the data sheet.
Note 3: Guaranteed by correlation with single-ended measurements.
Note 4: Not production tested. Guaranteed by design.
Note 5: To ensure external reference operation, V
REFCAP
must exceed (AV
DD1
- 0.1V). To ensure internal reference operation, V
REFCAP
must be below (AV
DD1
- 0.4V). Bypassing REFCAP with a 0.1µF or larger capacitor to AGND1 sets V
REFCAP
≈ 4.096V. The tran-
sition point between internal reference mode and external reference mode lies between the REFCAP buffer disable threshold
minimum and maximum values (Figures 17 and 18).
Note 6: The SCLK duty cycle can vary between 40% and 60%, as long as the t
CL
and tCHtiming requirements are met.
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1302/03 toc01
AV
DD1
(V)
I
AVDD1
(mA)
5.155.054.954.85
2.35
2.40
2.45
2.50
2.55
2.60
2.30
4.75 5.25
TA = +85°C
TA = +25°C
TA = -40°C
EXTERNAL CLOCK MODE
PREAMPLIFIER SUPPLY CURRENT
vs. PREAMPLIFIER SUPPLY VOLTAGE
MAX1302/03 toc02
AV
DD2
(V)
I
AVDD2
(mA)
5.155.054.85 4.95
16
17
18
19
20
21
22
23
24
15
4.75 5.25
TA = +85°C
TA = +25°C
TA = -40°C
EXTERNAL CLOCK MODE
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
MAX1302/03 toc03
DVDD (V)
I
DVDD
(mA)
5.155.054.954.85
0.70
0.75
0.80
0.85
0.90
0.65
4.75 5.25
TA = +85°C
TA = +25°C
TA = -40°C
EXTERNAL CLOCK MODE
Typical Operating Characteristics
(AV
DD1
= AV
DD2
= DVDD= DV
DDO
= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f
CLK
= 3.5MHz (50% duty cycle),
external clock mode, V
REF
= 4.096V (external reference operation), REFCAP = AV
DD1
, maximum single-ended bipolar input range
(±V
REF
), C
DOUT
= 50pF, C
SSTRB
= 50pF; unless otherwise noted.)
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
_______________________________________________________________________________________ 7
DIGITAL I/O SUPPLY CURRENT
vs. DIGITAL I/O SUPPLY VOLTAGE
MAX1302/03 toc04
DV
DDO
(V)
I
DVDDO
(mA)
5.155.054.85 4.95
0.12
0.14
0.16
0.18
0.20
0.22
0.24
0.26
0.28
0.10
4.75 5.25
TA = +85°C
TA = +25°C
TA = -40°C
EXTERNAL CLOCK MODE
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1302/03 toc05
AV
DD1
(V)
I
AVDD1
(mA)
5.155.054.954.85
0.47
0.49
0.51
0.53
0.55
0.45
4.75 5.25
TA = +85°C
TA = +25°C
TA = -40°C
PARTIAL POWER-DOWN MODE
Typical Operating Characteristics (continued)
(AV
DD1
= AV
DD2
= DVDD= DV
DDO
= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f
CLK
= 3.5MHz (50% duty cycle),
external clock mode, V
REF
= 4.096V (external reference operation), REFCAP = AV
DD1
, maximum single-ended bipolar input range
(±V
REF
), C
DOUT
= 50pF, C
SSTRB
= 50pF; unless otherwise noted.)
PREAMPLIFIER SUPPLY CURRENT
vs. PREAMPLIFIER SUPPLY VOLTAGE
MAX1302/03 toc06
AV
DD2
(V)
I
AVDD2
(mA)
5.155.054.954.85
0.12
0.14
0.16
0.18
0.20
0.10
4.75 5.25
TA = +85°C
TA = +25°C
TA = -40°C
PARTIAL POWER-DOWN MODE
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
MAX1302/03 toc07
DVDD (V)
I
DVDD
(mA)
5.154.85 5.054.95
0.122
0.124
0.126
0.128
0.130
0.132
0.134
0.136
0.120
4.75 5.25
PARTIAL POWER-DOWN MODE
TA = +85°C
TA = +25°C
TA = -40°C
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
8 _______________________________________________________________________________________
ANALOG SUPPLY CURRENT
vs. CONVERSION RATE
MAX1302/03 toc08
CONVERSION RATE (ksps)
I
AVDD1
(mA)
20015010050
0.5
1.0
1.5
2.0
2.5
3.0
0
0
EXTERNAL CLOCK MODE
PARTIAL
POWER-DOWN MODE
FULL
POWER-DOWN MODE
PREAMPLIFIER SUPPLY CURRENT
vs. CONVERSION RATE
MAX1302/03 toc09
I
AVDD2
(mA)
5
10
15
20
25
0
CONVERSION RATE (ksps)
200
150100500
f
CLK
= 7.5MHz (NOTE 6)
EXTERNAL CLOCK MODE
FULL POWER-DOWN MODE,
PARTIAL POWER-DOWN MODE
Typical Operating Characteristics (continued)
(AV
DD1
= AV
DD2
= DVDD= DV
DDO
= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f
CLK
= 3.5MHz (50% duty cycle),
external clock mode, V
REF
= 4.096V (external reference operation), REFCAP = AV
DD1
, maximum single-ended bipolar input range
(±V
REF
), C
DOUT
= 50pF, C
SSTRB
= 50pF; unless otherwise noted.)
DIGITAL SUPPLY CURRENT
vs. CONVERSION RATE
MAX1302/03 toc10
I
DVDD
(mA)
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
0
CONVERSION RATE (ksps)
200
15010050
f
CLK
= 7.5MHz (NOTE 6)
FULL POWER-DOWN MODE
EXTERNAL CLOCK MODE,
PARTIAL POWER-DOWN MODE
DIGITAL I/O SUPPLY CURRENT
vs. CONVERSION RATE
MAX1302/03 toc11
CONVERSION RATE (ksps)
I
DVDDO
(mA)
20015010050
0.1
0.2
0.3
0.4
0.5
0.6
0
0
f
CLK
= 7.5MHz (NOTE 6)
EXTERNAL CLOCK MODE
FULL POWER-DOWN MODE,
PARTIAL POWER-DOWN MODE
Note 6: For partial power-down and full power-down modes, external clock mode was used for a burst of continuous samples.
Partial power-down or full power-down modes were entered thereafter. By using this method, the conversion rate was found
by averaging the number of conversions over the time starting from the first conversion to the end of the partial power-down
or full power-down modes.
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
_______________________________________________________________________________________ 9
EXTERNAL REFERENCE INPUT CURRENT
vs. EXTERNAL REFERENCE INPUT VOLTAGE
MAX1302/03 toc12
EXTERNAL REFERENCE VOLTAGE (V)
EXTERNAL REFERENCE CURRENT (mA)
4.104.054.003.953.903.85
0.13
0.14
0.15
0.16
0.12
3.80 4.15
ALL MODES
-0.10
-0.04
-0.06
-0.08
-0.02
0
0.02
0.04
0.06
0.08
0.10
-40 10-15 35 60 85
GAIN DRIFT
vs. TEMPERATURE
MAX1302toc13
TEMPERATURE (°C)
GAIN DRIFT (%)
+V
REF
/2 BIPOLAR
±
V
REF
BIPOLAR RANGE
±
V
REF
/4 BIPOLAR
-1.0
-0.4
-0.6
-0.8
-0.2
0
0.2
0.4
0.6
0.8
1.0
-40 10-15 35 60 85
OFFSET DRIFT
vs. TEMPERATURE
MAX1302toc14
TEMPERATURE (°C)
OFFSET ERROR (mV)
+V
REF
/4 BIPOLAR RANGE
±
V
REF
BIPOLAR
CHANNEL-TO-CHANNEL ISOLATION
vs. INPUT FREQUENCY
MAX1302/03 toc15
FREQUENCY (kHz)
ISOLATION (dB)
100010010
-100
-80
-60
-40
-20
0
-120
1 10,000
f
SAMPLE
= 115ksps
±
V
REF
BIPOLAR RANGE
CH0 TO CH2
COMMON-MODE REJECTION RATIO
vs. FREQUENCY
MAX1302/03 toc16
FREQUENCY (kHz)
CMRR (dB)
100010010
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
110,000
f
SAMPLE
= 115ksps
±
V
REF
BIPOLAR RANGE
-2.0
-1.0
-1.5
0
-0.5
0.5
1.0
1.5
2.0
0 16,384 32,768 49,152 65,535
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1302toc17
DIGITAL OUTPUT CODE
INL (LSB)
f
SAMPLE
= 115ksps
±
V
REF
BIPOLAR RANGE
-2.0
-1.0
-1.5
0
-0.5
0.5
1.0
1.5
2.0
0 16,384 32,768 49,152 65,535
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1302toc18
DIGITAL OUTPUT CODE
DNL (LSB)
f
SAMPLE
= 115ksps
±V
REF
BIPOLAR RANGE
-140
-60
-100
-120
-40
-80
-20
0
02010 30 40 50
FFT AT 5kHz
MAX1302toc19
TEMPERATURE (°C)
MAGNITUDE (dB)
f
SAMPLE
= 115ksps
f
IN(SINE WAVE)
= 5kHz
±
V
REF
BIPOLAR RANGE
100
0
1 100 1000
SNR, SINAD, ENOB
vs. ANALOG INPUT FREQUENCY
30
70
40
80
50
90
20
10
60
MAX1302/03 toc20
FREQUENCY (kHz)
SNR, SINAD (dB)
10
f
SAMPLE
= 115ksps
±V
REF
BIPOLAR RANGE
ENOB
SNR
SINAD
Typical Operating Characteristics (continued)
(AV
DD1
= AV
DD2
= DVDD= DV
DDO
= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f
CLK
= 3.5MHz (50% duty cycle),
external clock mode, V
REF
= 4.096V (external reference operation), REFCAP = AV
DD1
, maximum single-ended bipolar input range
(±V
REF
), C
DOUT
= 50pF, C
SSTRB
= 50pF; unless otherwise noted.)
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
10 ______________________________________________________________________________________
SNR, SINAD, ENOB
vs. SAMPLE RATE
MAX1302/03 toc21
SAMPLE RATE (ksps)
SNR, SINAD (dB)
ENOB (BITS)
100101
20
40
60
80
100
0
8
10
12
14
16
6
0.1 1000
f
IN(SINE WAVE)
= 5kHz
±
V
REF
BIPOLAR RANGE
ENOB
SNR, SINAD
-SFDR, THD
vs. SAMPLE RATE
MAX1302/03 toc22
SAMPLE RATE (ksps)
-SFDR, THD (dB)
100101
-100
-80
-60
-40
-20
0
-120
0.1 1000
f
IN(SINE WAVE)
= 5kHz
±
V
REF
BIPOLAR RANGE
THD
-SFDR
0
-120
1 100 1000
-SFDR, THD
vs. ANALOG INPUT FREQUENCY
-80
-60
-40
-100
-20
MAX1302/03 toc23
FREQUENCY (kHz)
-SFDR, THD (dB)
10
f
SAMPLE
= 115ksps
±
V
REF
BIPOLAR RANGE
THD
-SFDR
-1.5
-0.5
-1.0
0.5
0
1.0
1.5
ANALOG INPUT CURRENT
vs. ANALOG INPUT VOLTAGE
MAX1302/03 toc24
ANALOG INPUT VOLTAGE (V)
ANALOG INPUT CURRENT (mA)
-6 -2 0-4 2 4 6
SMALL-SIGNAL BANDWIDTH
MAX1302/03 toc25
FREQUENCY (kHz)
ATTENUATION (dB)
100010010
-25
-20
-15
-10
-5
0
-30
110,000
Typical Operating Characteristics (continued)
(AV
DD1
= AV
DD2
= DVDD= DV
DDO
= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f
CLK
= 3.5MHz (50% duty cycle),
external clock mode, V
REF
= 4.096V (external reference operation), REFCAP = AV
DD1
, maximum single-ended bipolar input range
(±V
REF
), C
DOUT
= 50pF, C
SSTRB
= 50pF; unless otherwise noted.)
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
______________________________________________________________________________________ 11
NOISE HISTOGRAM
(CODE EDGE)
MAX1302/03toc27
CODE
NUMBER OF HITS
32,771
5000
10,000
15,000
20,000
25,000
30,000
35,000
0
32,769 32,772 32,774
32,770 32,773
65,534 SAMPLES
NOISE HISTOGRAM
(CODE CENTER)
MAX11302/03 toc28
CODE
NUMBER OF HITS
32,769
5000
10,000
15,000
20,000
25,000
30,000
35,000
40,000
0
32,770
32,768
32,772
32,771 32,77332,767
65,534 SAMPLES
REFERENCE VOLTAGE vs. TIME
MAX1302/03 toc29
1V/div
0V
4ms/div
FULL-POWER BANDWIDTH
MAX1302/03 toc26
FREQUENCY (kHz)
ATTENUATION (dB)
100010010
-50
-40
-30
-20
-10
0
-60
110,000
Typical Operating Characteristics (continued)
(AV
DD1
= AV
DD2
= DVDD= DV
DDO
= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f
CLK
= 3.5MHz (50% duty cycle),
external clock mode, V
REF
= 4.096V (external reference operation), REFCAP = AV
DD1
, maximum single-ended bipolar input range
(±V
REF
), C
DOUT
= 50pF, C
SSTRB
= 50pF; unless otherwise noted.)
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
12 ______________________________________________________________________________________
Pin Description
PIN
MAX1302
FUNCTION
12
Analog Supply Voltage 1. Connect AV
DD1
to a +4.75V to +5.25V power-supply voltage. Bypass
AV
DD1
to AGND1 with a 0.1µF capacitor.
23CH0 Analog Input Channel 0
34CH1 Analog Input Channel 1
45CH2 Analog Input Channel 2
56CH3 Analog Input Channel 3
6—CH4 Analog Input Channel 4
7—CH5 Analog Input Channel 5
8—CH6 Analog Input Channel 6
9—CH7 Analog Input Channel 7
10 7 CS
Active-Low Chip-Select Input. When CS is low, data is clocked into the device from DIN on the
rising edge of SCLK. With CS low, data is clocked out of DOUT on the falling edge of SCLK.
When CS is high, activity on SCLK and DIN is ignored and DOUT is high impedance.
11 8 DIN
Serial Data Input. When CS is low, data is clocked in on the rising edge of SCLK. When CS is
high, transitions on DIN are ignored.
12 9
Serial-Strobe Output. When using the internal clock, SSTRB rising edge transitions indicate that
data is ready to be read from the device. When operating in external clock mode, SSTRB is
always low. SSTRB does not tri-state, regardless of the state of CS, and therefore requires
a dedicated I/O line.
13 10
Serial Clock Input. When CS is low, transitions on SCLK clock data into DIN and out of DOUT.
When CS is high, transitions on SCLK are ignored.
14 11
Serial Data Output. When CS is low, data is clocked out of DOUT with each falling SCLK
transition. When CS is high, DOUT is high impedance.
15 12
Digital I/O Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
16 13
Digital Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
17 14
Digital I/O Supply Voltage Input. Connect DV
DDO
to a +2.7V to +5.25V power-supply voltage.
Bypass DV
DDO
to DGNDO with a 0.1µF capacitor.
18 15
Digital-Supply Voltage Input. Connect DVDD to a +4.75V to +5.25V power-supply voltage.
Bypass DV
DD
to DGND with a 0.1µF capacitor.
19 16
Bandgap-Voltage Bypass Node. For external reference operation, connect REFCAP to AVDD. For
internal reference operation, bypass REFCAP with a 0.01µF capacitor to AGND1 (V
REFCAP
≈
4.096V).
20 17 REF
Reference-Buffer Output/ADC Reference Input. For external reference operation, apply an
external reference voltage from 3.800V to 4.136V to REF. For internal reference operation,
bypassing REF with a 1µF capacitor to AGND1 sets V
REF
= 4.096V ±1%.
MAX1303
NAME
AV
DD1
SSTRB
SCLK
DOUT
DGNDO
DGND
DV
DDO
DV
DD
REFCAP
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
______________________________________________________________________________________ 13
Detailed Description
The MAX1302/MAX1303 multirange, low-power, 16-bit
successive-approximation ADCs operate from a single
+5V supply and have a separate digital supply allowing
digital interface with 2.7V to 5.25V systems. These 16-bit
ADCs have internal track-and-hold (T/H) circuitry that
supports single-ended and fully differential inputs. For
single-ended conversions, the valid analog input voltage
range spans from -V
REF
below ground to +V
REF
above
ground. The maximum allowable differential input voltage
spans from -2 x V
REF
to +2 x V
REF
. Data can be converted in a variety of software-programmable channel and
data-acquisition configurations. Microprocessor (µP) con-
trol is made easy through an SPI-/QSPI-/MICROWIREcompatible serial interface.
The MAX1302 has eight single-ended analog input
channels or four differential channels (see the Block
Diagram at the end of the data sheet). The MAX1303 has
four single-ended analog input channels or two differential
channels. Each analog input channel is independently
software programmable for seven single-ended input
ranges (0 to +V
REF
/2, -V
REF
/2 to 0, 0 to +V
REF
, -V
REF
to 0,
±V
REF
/4, ±V
REF
/2, and ±V
REF
) and three differential input
ranges (±V
REF
/2, ±V
REF
, and ±2 x V
REF
). Additionally, all
analog input channels are fault tolerant to ±6V. A fault
condition on an idle channel does not affect the conversion result of other channels.
Pin Description (continued)
PIN
MAX1300
NAME
FUNCTION
21 18
Analog Signal Ground 3. AGND3 is the ADC negative reference potential. Connect AGND3 to
AGND1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
22 19
Analog Supply Voltage 2. Connect AV
DD2
to a +4.75V to +5.25V power-supply voltage. Bypass
AV
DD2
to AGND2 with a 0.1µF capacitor.
23 20
Analog Ground 2. This ground carries approximately five times more current than AGND1.
DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
24 1
Analog Ground 1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.
Figure 1. Typical Application Circuit
MAX1301
AGND3
AV
DD2
AGND2
AGND1
ACCELERATION
WHEATESTONE
WHEATESTONE
1µF
4–20mA
PLC
PRESSURE
TEMPERATURE
0.1µF
5.0V 5.0V 5.0V
0.1µF 0.1µF 0.1µF
AV
CHO
CH1
CH2
CH3
CH4
CH5
CH6
CH7
REF
AGND1
REFCAP
AGND2
DD2
AV
DD1
MAX1302
DV
DV
SSTRB
DGNDOAGND3 DGND
DD
DDO
SCLK
CS
DIN
DOUT
3.3V
0.1µF
V
DD
MC68HCXX
µC
SCK
I/O
MOSI
I/O
MISO
V
SS
MAX1302/MAX1303
Power Supplies
To maintain a low-noise environment, the MAX1302 and
MAX1303 provide separate power supplies for each
section of circuitry. Table 1 shows the four separate
power supplies. Achieve optimal performance using
separate AV
DD1
, AV
DD2
, DVDD, and DV
DDO
supplies.
Alternatively, connect AV
DD1
, AV
DD2
, and DV
DD
together as close to the device as possible for a convenient power connection. Connect AGND1, AGND2,
AGND3, DGND, and DGNDO together as close to the
device as possible. Bypass each supply to the corresponding ground using a 0.1µF capacitor (Table 1). If
significant low-frequency noise is present, add a 10µF
capacitor in parallel with the 0.1µF bypass capacitor.
Converter Operation
The MAX1302/MAX1303 ADCs feature a fully differential, successive-approximation register (SAR) conversion technique and an on-chip T/H block to convert
voltage signals into a 16-bit digital result. Both singleended and differential configurations are supported
with programmable unipolar and bipolar signal ranges.
Track-and-Hold Circuitry
The MAX1302/MAX1303 feature a switched-capacitor
T/H architecture that allows the analog input signal to be
stored as charge on sampling capacitors. See Figures 2,
3, and 4 for T/H timing and the sampling instants for
each operating mode. The MAX1302/MAX1303 analog
input circuitry buffers the input signal from the sampling
capacitors, resulting in a constant analog input impedance with varying input voltage (Figure 5).
Analog Input Circuitry
Select differential or single-ended conversions using the
associated analog input configuration byte (Table 2).
The analog input signal source must be capable of driving the ADC’s 6kΩ input resistance (Figure 6).
Figure 6 shows the simplified analog input circuit. The
analog inputs are ±6V fault tolerant and are protected
by back-to-back diodes. The summing junction voltage,
VSJ, is a function of the channel’s input common-mode
voltage:
V
R
RR
V
R
RR
V
SJ CM
.
=
+
×++
+
×
1
12
2 375 1
1
12
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
14 ______________________________________________________________________________________
Table 1. MAX1302/MAX1303 Power Supplies and Bypassing
POWER
SUPPLY/GROUND
SUPPLY VOLTAGE
RANGE (V)
TYPICAL SUPPLY
CIRCUIT SECTION BYPASSING
DV
DDO
/DGNDO 2.7 to 5.25 0.2 Digital I/O 0.1µF to DGNDO
AV
DD2
/AGND2 4.75 to 5.25 17.5 Analog Circuitry 0.1µF to AGND2
AV
DD1
/AGND1 4.75 to 5.25 3.0 Analog Circuitry 0.1µF to AGND1
DVDD/DGND 4.75 to 5.25 0.9
Digital Control Logic and
Memory
0.1µF to DGND
Table 2. Analog Input Configuration Byte
BIT
NUMBER
NAME DESCRIPTION
7 START Start Bit. The first logic 1 after CS goes low defines the beginning of the analog input configuration byte.
6C2
5C1
4C0
Channel-Select Bits. SEL[2:0] select the analog input channel to be configured (Tables 4 and 5).
3
Differential or Single-Ended Configuration Bit. DIF/SGL = 0 configures the selected analog input channel
for single-ended operation. DIF/SGL = 1 configures the channel for differential operation. In single-ended
mode, input voltages are measured between the selected input channel and AGND1, as shown in
Table 4. In differential mode, the input voltages are measured between two input channels, as shown in
Table 5. Be aware that changing DIF/SGL adjusts the FSR, as shown in Table 6.
2R2
1R1
0R0
Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 7.
CURRENT (mA)
DIF/SGL
As a result, the analog input impedance is relatively
constant over the input voltage as shown in Figure 5.
Single-ended conversions are internally referenced to
AGND1 (Tables 3 and 4). In differential mode, IN+ and
IN- are selected according to Tables 3 and 5. When configuring differential channels, the differential pair follows
the analog configuration byte for the positive channel.
For example, to configure CH2 and CH3 for a ±V
REF
differential conversion, set the CH2 analog configuration
byte for a differential conversion with the ±V
REF
range
(1010 1100). To initiate a conversion for the CH2 and
CH3 differential pair, issue the command 1010 0000.
Analog Input Bandwidth
The MAX1302/MAX1303 input-tracking circuitry has a
1.5MHz small-signal bandwidth. The 1.5MHz input bandwidth makes it possible to digitize high-speed transient
events. Harmonic distortion increases when digitizing
signal frequencies above 15kHz as shown in the THD, SFDR vs. Analog Input Frequency plot in the Typical
Operating Characteristics.
Analog Input Range and Fault Tolerance
Figure 7 illustrates the software-selectable singleended analog input voltage range that produces a valid
digital output. Each analog input channel can be independently programmed to one of seven single-ended
input ranges by setting the R[2:0] control bits with
DIF/SGL = 0.
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
______________________________________________________________________________________ 15
CS
SCLK
1
2
3
4
5
6
7
8
9
10
111213
141516
17
181920
212223
242526
27
28
29
30
31
32
DIN S C2 C1 C0 0 0 0 0
ANALOG INPUT
TRACK AND HOLD*
DOUT
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
BYTE 1 BYTE 2 BYTE 3 BYTE 4
SSTRB
HOLD TRACK HOLD
HIGH
IMPEDANCE
t
ACQ
HIGH
IMPEDANCE
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
f
SAMPLE
≈ f
SCLK
/ 32
SAMPLING INSTANT
Figure 2. External Clock-Mode Conversion (Mode 0)
MAX1302/MAX1303
Figure 8 illustrates the software-selectable differential
analog input voltage range that produces a valid digital
output. Each analog input differential pair can be independently programmed to one of three differential input
ranges by setting the R[2:0] control bits with DIF/SGL = 1.
Regardless of the specified input voltage range and
whether the channel is selected, each analog input is
±6V fault tolerant. The analog input fault protection is
active whether the device is unpowered or powered.
Any voltage beyond FSR, but within the ±6V fault-tolerant range, applied to an analog input results in a fullscale output voltage for that channel.
Clamping diodes with breakdown thresholds in excess
of 6V protect the MAX1302/MAX1303 analog inputs
during ESD and other transient events (Figure 6). The
clamping diodes do not conduct during normal device
operation, nor do they limit the current during such
transients. When operating in an environment with the
potential for high-energy voltage and/or current transients, protect the MAX1302/MAX1303 externally.
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
16 ______________________________________________________________________________________
CS
SCLK
123456789
10111213141516
171819202122232425262728293031
32
DIN SC2C1C00000
ANALOG INPUT
TRACK AND HOLD*
HOLD
DOUT
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
BYTE 1 BYTE 2 BYTE 3 BYTE 4
SSTRB
INTCLK**
123
141516
17
TRACK HOLD
HIGH IMPEDANCE
t
ACQ
100ns to 400ns
f
INTCLK
≈ 4.5MHz
f
SAMPLE
≈ f
SCLK
/ 32 + f
INTCLK
/ 17
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.
SAMPLING INSTANT
Figure 3. External Acquisition-Mode Conversion (Mode 1)
Figure 6. Simplified Analog Input Circuit
MAX1302
MAX1303
R2
R1
V
SJ
*R
SOURCE
ANALOG
SIGNAL
SOURCE
R2
R1
V
SJ
*R
SOURCE
ANALOG
SIGNAL
SOURCE
IN_+
IN_+
*MINIMIZE R
SOURCE
TO AVOID GAIN ERROR AND DISTORTION.
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
______________________________________________________________________________________ 17
CS
SCLK
1234567
8
17181920212223
24
DIN S C2 C1 C0 0 0 0 0
ANALOG INPUT
TRACK AND HOLD*
TRACK
DOUT
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
BYTE 1 BYTE 2 BYTE 3
SSTRB
INTCLK**
123
252627
28
9
10111213141516
1011121314
HOLD HOLD
HIGH IMPEDANCE
t
ACQ
100ns to 400ns
f
INTCLK
≈ 4.5MHz
f
SAMPLE
≈ f
SCLK
/ 24 + f
INTCLK
/ 28
*TRACK AND HOLD TIMING IS CONTROLLED BY INTCLK, AND IS NOT ACCESSIBLE TO THE USER.
**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.
SAMPLING INSTANT
Figure 4. Internal Clock-Mode Conversion (Mode 2)
-1.5
-0.5
-1.0
0.5
0
1.0
1.5
ANALOG INPUT VOLTAGE (V)
ANALOG INPUT CURRENT (mA)
-6 -2 0-4 2 4 6
Figure 5. Analog Input Current vs. Input Voltage
MAX1302/MAX1303
Differential Common-Mode Range
The MAX1302/MAX1303 differential common-mode
range (V
CMDR
) must remain within -4.75V to +5.5V to
obtain valid conversion results. The differential common-mode range is defined as:
In addition to the common-mode input voltage limitations, each individual analog input must be limited to
±6V with respect to AGND1.
The range-select bits R[2:0] in the analog input configuration bytes determine the full-scale range for the corresponding channel (Tables 2 and 6). Figures 9, 10,
and 11 show the valid analog input voltage ranges for
the MAX1302/MAX1303 when operating with FSR =
V
REF
/2, FSR = V
REF
, and FSR = 2 x V
REF
, respectively.
V
CH CH
CMDR
_ _
=
+
()
+
()
−
2
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
18 ______________________________________________________________________________________
Table 3. Input Data Word Formats
DATA BIT
OPERATION
D7
D6 D5 D4 D3 D2 D1 D0
Conversion-Start Byte
(Tables 4 and 5)
1C2C1C00 0 0 0
Analog-Input Configuration Byte
(Table 2)
1C2C1C0
R2 R1 R0
Mode-Control Byte
(Table 7)
1M2M1M01 0 0 0
Table 4. Channel Selection in Single-Ended Mode (DIF/SGL = 0)
CHANNEL-SELECT BIT CHANNEL
C2 C1 C0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
AGND1
000+ -
001 + -
010 + -
011 + -
100 + -
101 + -
110 +-
111 +-
Table 5. Channel Selection in True-Differential Mode (DIF/SGL = 1)
CHANNEL-SELECT BIT CHANNEL
C2 C1 C0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
AGND1
000+-
001 RESERVED
010 +-
011 RESERVED
100 +-
101 RESERVED
110 +-
111 RESERVED
(START)
DIF/SGL
The shaded area contains the valid common-mode
voltage ranges that support the entire FSR.
Digital Interface
The MAX1302/MAX1303 feature a serial interface that is
compatible with SPI/QSPI and MICROWIRE devices.
DIN, DOUT, SCLK, CS, and SSTRB facilitate bidirectional communication between the MAX1302/MAX1303
and the master at SCLK rates up to 10MHz (internal
clock mode, mode 2), 3.67MHz (external clock mode,
mode 0), or 4.39MHz (external acquisition mode, mode
1). The master, typically a microcontroller, should use
the CPOL = 0, CPHA = 0, SPI transfer format, as shown
in the timing diagrams of Figures 2, 3, and 4.
The digital interface is used to:
• Select single-ended or true-differential input channel
configurations
• Select the unipolar or bipolar input range
• Select the mode of operation:
External clock (mode 0)
External acquisition (mode 1)
Internal clock (mode 2)
Reset (mode 4)
Partial power-down (mode 6)
Full power-down (mode 7)
• Initiate conversions and read results
Chip Select (CS)
CS enables communication with the MAX1302/MAX1303.
When CS is low, data is clocked into the device from DIN
on the rising edge of SCLK and data is clocked out of
DOUT on the falling edge of SCLK. When CS is high,
activity on SCLK and DIN is ignored and DOUT is high
impedance allowing DOUT to be shared with other
peripherals. SSTRB is never high impedance and therefore cannot be shared with other peripherals.
Serial Strobe Output (SSTRB)
As shown in Figures 3 and 4, the SSTRB transitions high
to indicate that the ADC has completed a conversion
and results are ready to be read by the master. SSTRB
remains low in the external clock mode (Figure 2) and
consequently may be left unconnected. SSTRB is driven high or low regardless of the state of CS, therefore
SSTRB cannot be shared with other peripherals.
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
______________________________________________________________________________________ 19
001
010
011
100
101
110
111
0
-V
REF
/2
-V
REF
+V
REF
+V
REF
/2
+V
REF
/4
-V
REF
/4
EACH INPUT IS FAULT TOLERANT TO ±6V.
(CH_) - AGND1 (V)
INPUT RANGE SELECTION BITS, R[2:0]
FSR = V
REF
/ 2
FSR = V
REF
/ 2
FSR = V
REF
/ 2
FSR = V
REF
FSR = V
REF
FSR = V
REF
FSR = 2 x V
REF
+
3
/
4
V
REF
-
3
/
4
V
REF
Figure 7. Single-Ended Input Voltage Ranges
001
010
011
100
101
110
111
-V
REF
-2 x V
REF
+2 x V
REF
+V
REF
+V
REF
/2
-V
REF
/2
EACH INPUT IS FAULT TOLERANT TO ±6V.
(CH_+) - (CH_-) (V)
INPUT RANGE SELECTION BITS, R[2:0]
0
FSR = V
REF
FSR = 2 x V
REF
FSR = 4 x V
REF
-
3
/
2
V
REF
+
3
/
2
V
REF
Figure 8. Differential Input Voltage Ranges
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
20 ______________________________________________________________________________________
Table 6. Range-Select Bits
DIF/SGL R2 R1 R0 MODE TRANSFER FUNCTION
0 000No Range Change* —
0 001
Single-Ended
Bipolar -V
REF
/4 to +V
REF
/4
Full-Scale Range (FSR) = V
REF
/ 2
Figure 12
0 010
Single-Ended
Unipolar -V
REF
/2 to 0
FSR = V
REF
/ 2
Figure 13
0 011
Single-Ended
Unipolar 0 to +V
REF
/2
FSR = V
REF
/ 2
Figure 14
0 100
Single-Ended
Bipolar -V
REF
/2 to +V
REF
/2
FSR = V
REF
Figure 12
0 101
Single-Ended
Unipolar -V
REF
to 0
FSR = V
REF
Figure 13
0 110
Single-Ended
Unipolar 0 to +V
REF
FSR = V
REF
Figure 14
0 111
DEFAULT SETTING
Single-Ended
Bipolar -V
REF
to +V
REF
FSR = 2 x V
REF
Figure 12
1 000No Range Change** —
1 001
Differential
Bipolar -V
REF
/2 to +V
REF
/2
FSR = V
REF
Figure 12
1 010Reserved —
1 011Reserved —
1 100
Differential
Bipolar -V
REF
to +V
REF
FSR = 2 x V
REF
Figure 12
1 101Reserved —
1 110Reserved —
1 111
Differential
Bipolar -2 x V
REF
to +2 x V
REF
FSR = 4 x V
REF
Figure 12
*Conversion-Start Byte (see Table 3).
**Mode-Control Byte (see Table 3).
Start Bit
Communication with the MAX1302/MAX1303 is accomplished using the three input data word formats shown
in Table 3. Each input data word begins with a start bit.
The start bit is defined as the first high bit clocked into
DIN with CS low when any of the following are true:
• Data conversion is not in process and all data from
the previous conversion has clocked out of DOUT.
• The device is configured for operation in external
clock mode (mode 0) and previous conversion-result
bits B15–B3 have clocked out of DOUT.
• The device is configured for operation in external
acquisition mode (mode 1) and previous conversionresult bits B15–B7 have clocked out of DOUT.
• The device is configured for operation in internal
clock mode, (mode 2) and previous conversionresult bits B15–B4 have clocked out of DOUT.
Output Data Format
Output data is clocked out of DOUT in offset binary format on the falling edge of SCLK, MSB first (B15). For
output binary codes, see the Transfer Function section
and Figures 12, 13, and 14.
Configuring Analog Inputs
Each analog input has two configurable parameters:
• Single-ended or true-differential input
• Input voltage range
These parameters are configured using the analog input
configuration byte as shown in Table 2. Each analog
input has a dedicated register to store its input configuration information. The timing diagram of Figure 15 shows
how to write to the analog input configuration registers.
Figure 16 shows DOUT and SSTRB timing.
Transfer Function
An ADC’s transfer function defines the relationship
between the analog input voltage and the digital output
code. Figures 12, 13, and 14 show the MAX1302/
MAX1303 transfer functions. The transfer function is
determined by the following characteristics:
• Analog input voltage range
• Single-ended or differential configuration
• Reference voltage
The axes of an ADC transfer function are typically in least
significant bits (LSBs). For the MAX1302/MAX1303, an
LSB is calculated using the following equation:
where N is the number of bits (N = 16) and FSR is the
full-scale range (see Figures 7 and 8).
1
24096
.
LSB
FSR V
V
REF
N
=
×
×
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
______________________________________________________________________________________ 21
INPUT VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
6420-2-4-6
-4
-2
0
2
4
6
-6
-8 8
V
REF
= 4.096V
Figure 9. Common-Mode Voltage vs. Input Voltage (FSR = V
REF
)
INPUT VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
6420-2-4-6
-4
-2
0
2
4
6
-6
-8 8
V
REF
= 4.096V
Figure 10. Common-Mode Voltage vs. Input Voltage (FSR = 2 x
V
REF
)
INPUT VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
6420-2-4-6
-4
-2
0
2
4
6
-6
-8 8
V
REF
= 4.096V
Figure 11. Common-Mode Voltage vs. Input Voltage (FSR = 4 x
V
REF
)
MAX1302/MAX1303
Mode Control
The MAX1302/MAX1303 contain one byte-wide modecontrol register. The timing diagram of Figure 15 shows
how to use the mode-control byte, and the mode-control byte format is shown in Table 7. The mode-control
byte is used to select the conversion method and to
control the power modes of the MAX1302/MAX1303.
Selecting the Conversion Method
The conversion method is selected using the mode-control byte (see the Mode Control section), and the conversion is initiated using a conversion start command (Table
3, and Figures 2, 3, and 4).The MAX1302/MAX1303 convert analog signals to digital data using one of three
methods:
• External Clock Mode, Mode 0 (Figure 2)
• Highest maximum throughput (see the Electrical
Characteristics table)
• User controls the sample instant
• CS remains low during the conversion
• User supplies SCLK throughout the ADC conversion and reads data at DOUT
• External Acquisition Mode, Mode 1 (Figure 3)
• Lowest maximum throughput (see the Electrical
Characteristics table)
• User controls the sample instant
• User supplies two bytes of SCLK, then drives
CS high to relieve processor load while the
ADC converts
• After SSTRB transitions high, the user supplies
two bytes of SCLK and reads data at DOUT
• Internal Clock Mode, Mode 2 (Figure 4)
• High maximum throughput (see the Electrical
Characteristics table)
• The internal clock controls the sampling instant
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
22 ______________________________________________________________________________________
1 LSB =
FSR x V
REF
65,536 x 4.096V
BINARY OUTPUT CODE (LSB [hex])
FFFF
FFFE
FFFD
8001
8000
7FFF
0003
0002
0001
0000
FSR
0123 32,768 65,533 65,535
INPUT VOLTAGE (LSB [DECIMAL])
(AGND1)
FSR
Figure 13. Ideal Unipolar Transfer Function, Single-Ended
Input, -FSR to 0
1 LSB =
FSR x V
REF
65,536 x 4.096V
BINARY OUTPUT CODE (LSB [hex])
FFFF
FFFE
FFFD
8001
8000
7FFF
0003
0002
0001
0000
FSR
0123 32,768 65,533 65,535
INPUT VOLTAGE (LSB [DECIMAL])
(AGND1)
FSR
Figure 14. Ideal Unipolar Transfer Function, Single-Ended
Input, 0 to +FSR
1 LSB =
FSR x V
REF
65,536 x 4.096V
BINARY OUTPUT CODE (LSB [hex])
FFFF
FFFE
FFFD
8001
8000
7FFF
0003
0002
0001
0000
FSR
-32,768 -32,766 0 +32,765 +32,767
INPUT VOLTAGE (LSB [DECIMAL])
AGND1 (DIF/SGL = 0)
0V (DIF/SGL = 1)
FSR
-1 +1
Figure 12. Ideal Bipolar Transfer Function, Single-Ended or
Differential Input
• User supplies one byte of SCLK, then drives CS
high to relieve processor load while the ADC
converts
• After SSTRB transitions high, the user supplies
two bytes of SCLK and reads data at DOUT
External Clock Mode (Mode 0)
The MAX1302/MAX1303’s fastest maximum throughput
rate is achieved operating in external clock mode.
SCLK controls both the acquisition and conversion of
the analog signal, facilitating precise control over when
the analog signal is captured. The analog input sampling instant is at the falling edge of the 14th SCLK
(Figure 2).
Since SCLK drives the conversion in external clock
mode, the SCLK frequency should remain constant
while the conversion is clocked. The minimum SCLK
frequency prevents droop in the internal sampling
capacitor voltages during conversion.
SSTRB remains low in the external clock mode, and as a
result may be left unconnected if the MAX1302/
MAX1303 will always be used in the external clock mode.
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
______________________________________________________________________________________ 23
CS
SCLK
DIN
DOUT
18
START
SEL2
SEL1 SEL0 R2 R1
R0
DIF/SGL
t
CL
t
CP
t
CH
t
DV
t
CSS
t
DS
t
DH
t
CSH
t
CSPW
t
TR
HIGH
IMPEDANCE
18
START
M2
M1 M0 1 0 0
0
ANALOG INPUT CONFIGURATION BYTE
MODE CONTROL BYTE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 15. Analog Input Configuration Byte and Mode-Control Byte Timing
CS
SCLK
DOUT
t
CSS
HIGH IMPEDANCE
SSTRB
t
SSCS
MSB
t
DO
NOTE: SSTRB AND CS REMAIN LOW IN EXTERNAL CLOCK MODE (MODE 0).
Figure 16. DOUT and SSTRB Timing
Table 7. Mode-Control Byte
BIT NUMBER
BIT NAME DESCRIPTION
7 START Start Bit. The first logic 1 after CS goes low defines the beginning of the mode-control byte.
6M2
5M1
4M0
Mode-Control Bits. M[2:0] select the mode of operation as shown in Table 8.
31Bit 3 must be a logic 1 for the mode-control byte.
20Bit 2 must be a logic 0 for the mode-control byte.
10Bit 1 must be a logic 0 for the mode-control byte.
00Bit 0 must be a logic 0 for the mode-control byte.
MAX1302/MAX1303
External Acquisition Mode (Mode 1)
The slowest maximum throughput rate is achieved with
the external acquisition method. SCLK controls the
acquisition of the analog signal in external acquisition
mode, facilitating precise control over when the analog
signal is captured. The internal clock controls the conversion of the analog input voltage. The analog input
sampling instant is at the falling edge of the 16th SCLK
(Figure 3).
For the external acquisition mode, CS must remain low
for the first 15 clock cycles and then rise on or after the
falling edge of the 16th SCLK cycle as shown in Figure
3. For optimal performance, idle DIN and SCLK during
the conversion. With careful board layout, transitions at
DIN and SCLK during the conversion have a minimal
impact on the conversion result.
After the conversion is complete, SSTRB asserts high
and CS can be brought low to read the conversion
result. SSTRB returns low on the rising SCLK edge of
the subsequent start bit.
Internal Clock Mode (Mode 2)
In internal clock mode, the internal clock controls both
acquisition and conversion of the analog signal. The internal clock starts approximately 100ns to 400ns after the
falling edge of the eighth SCLK and has a rate of about
4.5MHz. The analog input sampling instant occurs at the
falling edge of the 11th internal clock signal (Figure 4).
For the internal clock mode, CS must remain low for the
first seven SCLK cycles and then rise on or after the
falling edge of the eighth SCLK cycle. After the conversion is complete, SSTRB asserts high and CS can be
brought low to read the conversion result. SSTRB returns
low on the rising SCLK edge of the subsequent start bit.
Reset (Mode 4)
As shown in Table 8, set M[2:0] = 100 to reset the
MAX1302/MAX1303 to its default conditions. The
default conditions are full power operation with each
channel configured for ±V
REF
, bipolar, single-ended
conversions using external clock mode (mode 0).
Partial Power-Down Mode (Mode 6)
As shown in Table 8, when M[2:0] = 110, the device
enters partial power-down mode. In partial powerdown, all analog portions of the device are powered
down except for the reference voltage generator and
bias supplies.
To exit partial power-down, change the mode by issuing one of the following mode-control bytes (see the
Mode Control section):
• External-clock-mode control byte
• External-acquisition-mode control byte
• Internal-clock-mode control byte
• Reset byte
• Full power-down-mode control byte
This prevents the MAX1302/MAX1303 from inadvertently exiting partial power-down mode because of a CS
glitch in a noisy digital environment.
Full Power-Down Mode (Mode 7)
When M[2:0] = 111, the device enters full power-down
mode and the total supply current falls to 1µA (typ). In
full power-down, all analog portions of the device are
powered down. When using the internal reference,
upon exiting full power-down mode, allow 10ms for the
internal reference voltage to stabilize prior to initiating a
conversion.
To exit full power-down, change the mode by issuing
one of the following mode-control bytes (see the Mode
Control section):
• External-clock-mode control byte
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
24 ______________________________________________________________________________________
M2 M1 M0 MODE
000External Clock (DEFAULT)
001External Acquisition
010Internal Clock
011Reserved
100Reset
101Reserved
110Partial Power-Down
111Full Power-Down
Table 8. Mode-Control Bits M[2:0]
• External-acquisition-mode control byte
• Internal-clock-mode control byte
• Reset byte
• Partial power-down-mode control byte
This prevents the MAX1302/MAX1303 from inadvertently exiting full power-down mode because of a CS glitch
in a noisy digital environment.
Power-On Reset
The MAX1302/MAX1303 power up in normal operation
configured for external clock mode with all circuitry
active (Tables 7 and 8). Each analog input channel
(CH0–CH7) is set for single-ended conversions with a
±V
REF
bipolar input range (Table 6).
Allow the power supplies to stabilize after power-up. Do
not initiate any conversions until the power supplies
have stabilized. Additionally, allow 10ms for the internal
reference to stabilize when C
REF
= 1.0µF and C
RECAP
= 0.1µF. Larger reference capacitors require longer
stabilization times.
Internal or External Reference
The MAX1302/MAX1303 operate with either an internal or
external reference. The reference voltage impacts the
ADC’s FSR (Figures 12, 13, and 14). An external reference is recommended if more accuracy is required than
the internal reference provides, and/or multiple converters
require the same reference voltage.
Internal Reference
The MAX1302/MAX1303 contain an internal 4.096V
bandgap reference. This bandgap reference is connected to REFCAP through a nominal 5kΩ resistor (Figure 17).
The voltage at REFCAP is buffered creating 4.096V at
REF. When using the internal reference, bypass
REFCAP with a 0.1µF or greater capacitor to AGND1 and
bypass REF with a 1.0µF or greater capacitor to AGND1.
External Reference
For external reference operation, disable the internal
reference and reference buffer by connecting REFCAP
to AV
DD1
. With AV
DD1
connected to REFCAP, REF
becomes a high-impedance input and accepts an
external reference voltage. The MAX1302/MAX1303
external reference current varies depending on the
applied reference voltage and the operating mode (see
the External Reference Input Current vs. External
Reference Input Voltage in the Typical Operating
Characteristics).
Applications Information
Noise Reduction
Additional samples can be taken and averaged (oversampling) to remove the effect of transition noise on
conversion results. The square root of the number of
samples determines the improvement in performance.
For example, with 2/3 LSB
RMS
(4 LSB
P-P
) transition
noise, 16 (42= 16) samples must be taken to reduce
the noise to 1 LSB
P-P
.
Interface with 4–20mA Signals
Figure 19 illustrates a simple interface between the
MAX1302/MAX1303 and a 4–20mA signal. 4–20mA signaling can be used as a binary switch (4mA represents
a logic-low signal, 20mA represents a logic-high signal), or for precision communication where currents
between 4mA and 20mA represent intermediate analog
data. For binary switch applications, connect the
4–20mA signal to the MAX1302/MAX1303 with a resistor to ground. For example, a 200Ω resistor converts
the 4–20mA signal to a 0.8V to 4V signal. Adjust the
resistor value so the parallel combination of the resistor
and the MAX1302/MAX1303 source impedance is
200Ω. In this application, select the single-ended 0 to
V
REF
range (R[2:0] = 011, Table 6). For applications
that require precision measurements of continuous
analog currents between 4mA and 20mA, use a buffer
to prevent the MAX1302/MAX1303 input from diverting
current from the 4–20mA signal.
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
______________________________________________________________________________________ 25
REF
REFCAP
AGND1
4.096V
BANDGAP
REFERENCE
5kΩ
1x
SAR
ADC
REF
4.096V
1.0µF
0.1µF
V
RCTH
MAX1302
MAX1303
Figure 17. Internal Reference Operation
MAX1302/MAX1303
Bridge Application
The MAX1302/MAX1303 convert 1kHz signals more
accurately than a similar sigma-delta converter that
might be considered in bridge applications. The input
impedance of the MAX1302, in combination with the current-limiting resistors, can affect the gain of the
MAX1302. In many applications this error is acceptable,
but for applications that cannot tolerate this error, the
MAX1302 inputs can be buffered (Figure 20). Connect
the bridge to a low-offset differential amplifier and then
the true differential inputs of the MAX1302/MAX1303.
Larger excitation voltages take advantage of more of the
±V
REF
/2 differential input voltage range. Select an input
voltage range that matches the amplifier output. Be
aware of the amplifier offset and offset-drift errors when
selecting an appropriate amplifier.
Dynamically Adjusting the Input Range
Software control of each channel’s analog input range
and the unipolar endpoint overlap specification make it
possible for the user to change the input range for a
channel dynamically and improve performance in some
applications. Changing the input range results in a
small LSB step-size over a wider output voltage range.
For example, by switching between a -V
REF
/2 to 0V
range and a 0 to V
REF
/2 range, an LSB is:
but the input voltage range effectively spans from
-V
REF
/2 to +V
REF
/2 (FSR = +V
REF
).
Layout, Grounding, and Bypassing
Careful PC board layout is essential for best system
performance. Boards should have separate analog and
digital ground planes and ensure that digital and analog
signals are separated from each other. Do not run analog and digital (especially clock) lines parallel to one
another, or digital lines underneath the device package.
Figure 1 shows the recommended system ground connections. Establish an analog ground point at AGND1
and a digital ground point at DGND. Connect all analog
grounds to the star analog ground. Connect the digital
grounds to the star digital ground. Connect the digital
ground plane to the analog ground plane at one point.
For lowest noise operation, make the ground return to
the star ground’s power-supply low impedance and as
short as possible.
High-frequency noise in the AV
DD1
power supply
degrades the ADC’s high-speed comparator performance. Bypass AV
DD1
to AGND1 with a 0.1µF ceramic
surface-mount capacitor. Make bypass capacitor connections as short as possible.
Parameter Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. This straight line is either a
best straight-line fit or a line drawn between the endpoints of the transfer function once offset and gain
errors have been nullified. The MAX1302/MAX1303 INL
is measured using the endpoint method.
(/)
, .
VV
REF REF
2
65 536 4 096
×
×
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
26 ______________________________________________________________________________________
REF
REFCAP
AGND1
4.096V
BANDGAP
REFERENCE
5kΩ
1x
SAR
ADC
REF
4.096V
1.0µF
V
RCTH
MAX1302
MAX1303
AV
DD1
MAX6341
V+
1.0µF
OUT
GND
IN
Figure 18. External Reference Operation
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. A DNL error specification of
greater than -1 LSB guarantees no missing codes and
a monotonic transfer function.
Transition Noise
Transition noise is the amount of noise that appears at a
code transition on the ADC transfer function. Conversions
performed with the analog input right at the code transition can result in code flickering in the LSBs.
Channel-to-Channel Isolation
Channel-to-channel isolation indicates how well each
analog input is isolated from the others. The channel-tochannel isolation for these devices is measured by
applying a near full-scale magnitude 5kHz sine wave to
the selected analog input channel while applying an
equal magnitude sine wave of a different frequency to
all unselected channels. An FFT of the selected channel output is used to determine the ratio of the magnitudes of the signal applied to the unselected channels
and the 5kHz signal applied to the selected analog
input channel. This ratio is reported, in dB, as channelto-channel isolation.
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
______________________________________________________________________________________ 27
MAX1302
200Ω
4–20mA INPUT
200Ω
4–20mA INPUT
CH0
CH8
µC
Figure 19. 4–20mA Application
MAX1302
MAX1303
CH0
REF
µP
CH1
LOW-OFFSET
DIFFERENTIAL
AMPLIFIER
BRIDGE
Figure 20. Bridge Application
MAX1302/MAX1303
Unipolar Offset Error
-FSR to 0V
When a zero-scale analog input voltage is applied to
the converter inputs, the digital output is all ones
(0xFFFF). Ideally, the transition from 0xFFFF to 0xFFFE
occurs at AGND1 - 0.5 LSB. Unipolar offset error is the
amount of deviation between the measured zero-scale
transition point and the ideal zero-scale transition point,
with all untested channels grounded.
0V to +FSR
When a zero-scale analog input voltage is applied to
the converter inputs, the digital output is all zeros
(0x0000). Ideally, the transition from 0x0000 to 0x0001
occurs at AGND1 + 0.5 LSB. Unipolar offset error is the
amount of deviation between the measured zero-scale
transition point and the ideal zero-scale transition point,
with all untested channels grounded.
Bipolar Offset Error
When a zero-scale analog input voltage is applied to
the converter inputs, the digital output is a one followed
by all zeros (0x8000). Ideally, the transition from
0x7FFF to 0x8000 occurs at (2
N-1
- 0.5) LSB. Bipolar offset error is the amount of deviation between the measured midscale transition point and the ideal midscale
transition point, with untested channels grounded.
Gain Error
When a positive full-scale voltage is applied to the converter inputs, the digital output is all ones (0xFFFF). The
transition from 0xFFFE to 0xFFFF occurs at 1.5 LSB
below full scale. Gain error is the amount of deviation
between the measured full-scale transition point and
the ideal full-scale transition point with the offset error
removed and all untested channels grounded.
Unipolar Endpoint Overlap
Unipolar endpoint overlap is the change in offset when
switching between complementary input voltage
ranges. For example, the difference between the voltage that results in a 0xFFFF output in the -V
REF
/2 to 0V
input voltage range and the voltage that results in a
0x0000 output in the 0 to +V
REF
/2 input voltage range
is the unipolar endpoint overlap. The unipolar endpoint
overlap is positive for the MAX1302/MAX1303, preventing loss of signal or a dead zone when switching
between adjacent analog input voltage ranges.
Small-Signal Bandwidth
A 100mV
P-P
sine wave is applied to the ADC, and the
input frequency is then swept up to the point where the
amplitude of the digitized conversion result has
decreased by -3dB.
Full-Power Bandwidth
A 95% of full-scale sine wave is applied to the ADC,
and the input frequency is then swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB.
Common-Mode Rejection Ratio (CMRR)
CMRR is the ability of a device to reject a signal that is
“common” to or applied to both input terminals. The
common-mode signal can be either an AC or a DC signal or a combination of the two. CMR is expressed in
decibels. Common-mode rejection ratio is the ratio of
the differential signal gain to the common-mode signal
gain. CMRR applies only to differential operation.
Power-Supply Rejection Ratio (PSRR)
PSRR is the ratio of the output-voltage shift to the
power-supply-voltage shift for a fixed input voltage. For
the MAX1302/MAX1303, AV
DD1
can vary from 4.75V to
5.25V. PSRR is expressed in decibels and is calculated
using the following equation:
For the MAX1302/MAX1303, PSRR is tested in bipolar
operation with the analog inputs grounded.
Aperture Jitter
Aperture jitter, tAJ, is the statistical distribution of the
variation in the sampling instant (Figure 21).
Aperture Delay
Aperture delay, tAD, is the time from the falling edge of
SCLK to the sampling instant (Figure 21).
Signal-to-Noise Ratio (SNR)
SNR is computed by taking the ratio of the RMS signal
to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus
distortion includes all spectral components to the
Nyquist frequency excluding the fundamental and the
DC offset.
SINAD dB
Signal
Noise
RMS
RMS
() log=×
20
PSRR dB
VV
VVVV
OUT OUT
[] log
. .
(. ) (. )
=×
−
−
20
525 475
525 475
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
28 ______________________________________________________________________________________
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. With an
input range equal to the ADC’s full-scale range, calculate the ENOB as follows:
Total Harmonic Distortion (THD)
For the MAX1302/MAX1303, THD is the ratio of the
RMS sum of the input signal’s first four harmonic components to the fundamental itself. This is expressed as:
where V1is the fundamental amplitude, and V2through
V5are the amplitudes of the 2nd- through 5th-order
harmonic components.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the fundamental
(maximum signal component) to the RMS value of the
next-largest spectral component.
THD
VVVV
V
log
=×
+++
20
2
2
3
2
4
2
5
2
1
ENOB
SINAD
.
.
=
− 176
602
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
______________________________________________________________________________________ 29
t
AD
t
AJ
INTCLK
(MODE 2)
ANALOG INPUT
TRACK AND HOLD
TRACK HOLD
SAMPLE INSTANT
SCLK
(MODE 0)
13
14
15
SCLK
(MODE 1)
15
16
10
11
12
Figure 21. Aperture Diagram
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
30 ______________________________________________________________________________________
Chip Information
TRANSISTOR COUNT: 28,210
PROCESS: BiCMOS
Revision History
Pages changed at Rev 1: 1, 3–6, 30, 31
Block Diagram
MAX1302
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
AGND1
ANALOG
INPUT MUX
AND
MULTIRANGE
CIRCUITRY
PGA
AGND2
AV
DD2
4.096V
BANDGAP
REFERENCE
1x
5kΩ
IN
REF
REFCAP
REF
CONTROL LOGIC AND REGISTERS
FIFO
CLOCK
OUT
SAR
ADC
SERIAL I/O
AGND2
AV
DD2
AGND3
AV
DD1
DGND
DV
DD
DGNDO
SCLK
DOUT
SSTRB
DIN
CS
DV
DDO
Pin Configurations (continued)
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
AGND2
AV
DD2
AGND3
REFCH1
CH0
AV
DD1
AGND1
REFCAP
DV
DD
DV
DDO
DGNDDIN
CS
CH3
CH2
12
11
9
10
DGNDO
DOUTSCLK
SSTRB
MAX1303
TSSOP
TOP VIEW
MAX1302/MAX1303
8-/4-Channel, ±V
REF
Multirange Inputs,
Serial 16-Bit ADCs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31
© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages
.)
TSSOP4.40mm.EPS
PACKAGE OUTLINE, TSSOP 4.40mm BODY
21-0066
1
1
G
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