General Description
The MAX1272/MAX1273 multirange 12-bit data-acquisition systems (DAS) operate with a single 5V supply. The
software-programmable analog input accepts a variety
of voltage ranges: ±10V, ±5V, 0 to 10V, 0 to 5V for the
MAX1272; ±V
REF
, ±V
REF
/ 2, 0 to V
REF
, 0 to V
REF
/ 2 for
the MAX1273. The software-selectable extended analog
input range increases the effective dynamic range to 14
bits and provides the flexibility to interface 4–20mA powered sensors directly to a single 5V system. In addition,
the MAX1272 provides fault protection to ±12V. Other
features include a 5MHz track/hold (T/H) bandwidth,
87ksps throughput rate, and internal (4.096V) or external
(2.40V to 4.18V) reference.
The MAX1272/MAX1273 serial interfaces connect
directly to SPI™/QSPI™/MICROWIRE™-compatible
devices without any external logic.
Four software-programmable power-down modes
(delayed standby, immediate standby, delayed full powerdown, and immediate full power-down) provide low-current shutdown between conversions. In standby mode, the
internal reference buffer remains active, thus eliminating
startup delay.
The MAX1272/MAX1273 are available in 8-pin PDIP
and µMAX packages. Both devices are available in the
commercial (0°C to +70°C) or extended (-40°C to
+85°C) temperature range.
Applications
Industrial Control Systems
Data-Acquisition Systems
Robotics
Automatic Testing
Battery-Powered Instruments
Medical Instruments
Features
♦ Four Software-Selectable Input Ranges
MAX1272: 0 to 10V, 0 to 5V, ±10V, ±5V
MAX1273: 0 to V
REF
, 0 to V
REF
/ 2, ±V
REF
,
±V
REF
/ 2
♦ 12-Bit Resolution, No Missing Codes
♦ 5V Single-Supply Operation
♦ SPI/QSPI/MICROWIRE-Compatible 3-Wire
Interface
♦ 87ksps Sampling Rate
♦ ±12V Fault-Protected Analog Input (MAX1272)
♦ Internal (4.096V) or External (2.4V to 4.18V)
Reference
♦ Low Power
1.5mA at 87ksps
0.4mA at 10ksps
0.2mA at 1ksps
♦ Four Power-Down Modes
♦ 8-Pin µMAX and PDIP Packages
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
________________________________________________________________ Maxim Integrated Products 1
Pin Configuration
Ordering Information
19-2921; Rev 0; 7/03
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
PART
TEMP
RANGE
PINPACKAGE
INL
(LSB)
MAX1272CPA
±1
MAX1272CUA
8 µMAX ±1
MAX1272EPA
±1
MAX1272EUA
8 µMAX ±1
MAX1273CPA
±1
MAX1273CUA
8 µMAX ±1
MAX1273EPA
±1
MAX1273EUA
8 µMAX ±1
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Typical Application Circuit appears at end of data sheet.
0°C to +70°C 8 Plastic DIP
0°C to +70°C
-40°C to +85°C 8 Plastic DIP
-40°C to +85°C
0°C to +70°C 8 Plastic DIP
0°C to +70°C
-40°C to +85°C 8 Plastic DIP
-40°C to +85°C
TOP VIEW
1
SCLK
2
MAX1272
MAX1273
3
V
DD
4
PDIP/µMAX
87DOUT
CSDIN
REF
6
AINGND
5
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto GND..............................................................-0.3V to +6V
AIN to GND (MAX1272) ...................................................... ±12V
AIN to GND (MAX1273) ........................................................ ±6V
DOUT, CS, DIN, SCLK, REF to GND..........-0.3V to (V
DD
+ 0.3V)
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T
A
= +70°C)
8-Pin Plastic DIP (derate 9.1mW/°C above +70°C) ......727mW
8-Pin µMAX (derate 4.5mW/°C above +70°C) ..............362mW
Operating Temperature Ranges
MAX127_ C_ _ .....................................................0°C to +70°C
MAX127_ E_ _...................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Junction Temperature .....................................................+150°C
ELECTRICAL CHARACTERISTICS
(VDD= 4.75V to 5.25V, unipolar/bipolar input range, external reference mode, V
REF
= 4.096V, C
REF
= 1.0µF, f
SCLK
= 1.4MHz,
50% duty cycle, C
LOAD
= 50pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
ACCURACY (Note 1)
Resolution 12 Bits
Integral Nonlinearity INL ±0.3 ±1.0 LSB
Differential Nonlinearity DNL No missing codes over temperature ±0.35 ±1.00 LSB
Offset Error
Gain Error (Note 2)
Gain Error Temperature
Coefficient (Note 2)
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±10V
Signal-to-Noise + Distortion Ratio SINAD 69 72 dB
Total Harmonic Distortion THD Up to the 5th harmonic -87 -78 dB
Spurious-Free Dynamic Range SFDR 80 88 dB
Aperture Delay t
Aperture Jitter t
ANALOG INPUT
T/H Acquisition Time t
PARAMETERS SYMBOL CONDITIONS MIN TYP MAX UNITS
AD
AJ
ACQ
Unipolar ±5
Bipolar ±10
Unipolar ±10
Bipolar ±10
Unipolar ±3
Bipolar ±5
(MAX1272), or ±4.096V
P-P
P-P
(MAX1273), f
SAMPLE
15 ns
<50 ps
= 87ksps)
2.85 µs
LSB
LSB
ppm/°C
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 4.75V to 5.25V, unipolar/bipolar input range, external reference mode, V
REF
= 4.096V, C
REF
= 1.0µF, f
SCLK
= 1.4MHz,
50% duty cycle, C
LOAD
= 50pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Small-Signal Bandwidth BW
Input Voltage Range
(Tables 2, 3)
Input Current I
Input Capacitance 40 pF
INTERNAL REFERENCE
REF Output Voltage V
REF Output Tempco TC V
Output Short-Circuit Current REF shorted to GND 40 mA
Load Regulation 0 to 0.5mA output current 0.7 10 mV
Capacitive Bypass at REF 1µF
REFERENCE INPUT (Reference buffer disabled, reference input applied to REF)
Input Voltage Range 2.40 4.18 V
PARAMETERS SYMBOL CONDITIONS MIN TYP MAX UNITS
V
REF
-3dB
IN
IN
REF
±10V (MAX1272) or ±V
range
±5V (MAX1272) or ±V
range
0 to 10V (MAX1272) or 0 to V
range
0 to 5V (MAX1272) or 0 to V
(MAX1273) range
MAX1272
Unipolar
MAX1273
MAX1272
Bipolar
MAX1273
MAX1272
Unipolar
MAX1273
MAX1272
Bipolar
MAX1273
MAX127_ C ±15
MAX127_ E ±30
(MAX1273)
REF
/ 2 (MAX1273)
REF
REF
REF
RNG = 1 0 10
RNG = 0 0 5
RNG = 1 0 V
RNG = 0 0 V
RNG = 1 -10 +10
RNG = 0 -5 +5
RNG = 1 -V
RNG = 0 -V
0 to 10V range -10 +860
0 to 5V range -10 +430
0 to V
0 to V
±10V range -1400 +860
±5V range -720 +430
±V
REF
±V
REF
(MAX1273)
/ 2
range -10 +10
REF
/ 2 range -10 +10
REF
range -1400 +10
/ 2 range -720 +10
4.036 4.096 4.156 V
REF
/ 2 +V
REF
5
2.5
2.5
1.25
REF
+V
REF
REF
/ 2
REF
/ 2
MHz
V
µA
ppm/°C
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD= 4.75V to 5.25V, unipolar/bipolar input range, external reference mode, V
REF
= 4.096V, C
REF
= 1.0µF, f
SCLK
= 1.4MHz,
50% duty cycle, C
LOAD
= 50pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.)
Input Current V
POWER REQUIREMENTS
Supply Voltage V
Supply Current
(Internal Reference Mode)
Supply Current
(External Reference Mode)
Power-Supply Rejection
Ratio (Note 3)
TIMING
Clock Frequency Range f
T/H Acquisition Time t
Conversion Time t
Throughput Rate 87.5 ksps
Internal Reference Settling Time REF bypass capacitor initially discharged 2 ms
Device Power-Up Time External reference mode 10 µs
DIGITAL INPUTS (DIN, SCLK, and CS)
Input High-Threshold Voltage V
Input Low-Threshold Voltage V
Input Hysteresis V
Input Leakage Current I
Input Capacitance C
DIGITAL OUTPUT (DOUT)
Output Voltage Low V
Output Voltage High V
Three-State Leakage Current I
Three-State Output Capacitance C
PARAMETERS SYMBOL CONDITIONS MIN TYP MAX UNITS
DD
I
DD
I
DD
PSRR
SCLK
ACQ
CONV
IH
IL
HYS
IN
IN
OL
OH
L
OUT
Converting 400 850
= 4.096V
REF
Converting
Standby power-down mode 400 700
Full power-down mode 1
Converting
Standby power-down mode 200 450
Full power-down mode 1
External reference = 4.096V ±0.3 ±1.0
Internal reference ±0.5
(Note 4) 2.85 µs
(Note 4) 8.57 µs
VIN = 0 to V
I
= 10mA 0.4
SINK
I
= 16mA 0.6
SINK
I
CS = V
CS = V
SOURCE
= 0.5mA
DD
DD
Standby power-down
mode
Full power-down mode 1
Bipolar 2.4 4
Unipolar 2.2 3
Bipolar 1.5 2.5
Unipolar 1.2 2.0
DD
4.75 5 5.25 V
0.1 1.4 MHz
0.8 V
0.2 V
-10 +10 µA
15 pF
V
DD
- 0.5
-10 +10 µA
15 pF
510
2.4 V
µA
mA
µA
mA
µA
LSB
V
V
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
_______________________________________________________________________________________ 5
TIMING CHARACTERISTICS
(VDD= 4.75V to 5.25V, unipolar/bipolar input range, external reference mode, V
REF
= 4.096V, C
REF
= 1.0µF, f
SCLK
= 1.4MHz,
50% duty cycle, C
LOAD
= 50pF, TA= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at TA= +25°C.) (Figures 1 and 4)
Note 1: Accuracy specifications tested at VDD= 5V. Performance at power-supply tolerance limit is guaranteed by power-supply
rejection test.
Note 2: Offset error nulled. The ideal last-code transition is (FS - 1.5 LSB).
Note 3: PSRR measured at full scale. Tested at ±10V (MAX1272) and ±4.096V (MAX1273) input ranges.
Note 4: Acquisition and conversion times are dependent on the clock speed.
Typical Operating Characteristics
(Typical operating circuit, BIP = RNG = 1, VDD= 5V, external reference mode, V
REF
= 4.096V, C
REF
= 1.0µF, f
SCLK
= 1.4MHz,
50% duty cycle, 87ksps, T
A
= +25°C, unless otherwise noted.)
CONVERTING SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1272/73 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
5.205.155.05 5.104.85 4.90 4.95 5.004.80
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
4.75 5.25
INTERNAL
REFERENCE
EXTERNAL
REFERENCE
V
AIN
= 0
CONVERTING SUPPLY CURRENT
vs. TEMPERATURE
MAX1272/73 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
6035-15 10
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
-40 85
V
AIN
= 0
INTERNAL
REFERENCE
EXTERNAL
REFERENCE
STANDBY SUPPLY CURRENT
vs. TEMPERATURE
MAX1272/73 toc03
TEMPERATURE (°C)
STANDBY SUPPLY CURRENT (mA)
603510-15
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
-40 85
V
AIN
= 0
INTERNAL
REFERENCE
EXTERNAL
REFERENCE
PARAMETERS SYMBOL CONDITIONS MIN TYP MAX UNITS
DIN to SCLK Setup t
DIN to SCLK Hold t
SCLK Fall to Output Data Valid t
CS Fall to Output Enable t
CS Rise to Output Disable t
CS to SCLK Rise Setup t
CS to SCLK Rise Hold t
SCLK Pulse Width High t
SCLK Pulse Width Low t
DS
DH
DO
DV
TR
CSS
CSH
CH
CL
100 ns
0ns
20 250 ns
100 ns
100 ns
100 ns
0ns
200 ns
200 ns
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Typical operating circuit, BIP = RNG = 1, VDD= 5V, external reference mode, V
REF
= 4.096V, C
REF
= 1.0µF, f
SCLK
= 1.4MHz,
50% duty cycle, 87ksps, T
A
= +25°C, unless otherwise noted.)
STANDBY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1272/73 toc04
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
5.205.155.05 5.104.85 4.90 4.95 5.004.80
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
4.75 5.25
V
AIN
= 0
INTERNAL
REFERENCE
EXTERNAL
REFERENCE
FULL POWER-DOWN
SUPPLY CURRENT vs. TEMPERATURE
MAX1272/73 toc05
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
603510-15
1
2
3
4
5
6
7
8
9
10
0
-40 85
V
AIN
= 0
INTERNAL/EXTERNAL
REFERENCE
FULL POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1272/73 toc06
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (µA)
5.205.155.05 5.104.85 4.90 4.95 5.004.80
1
2
3
4
5
6
7
8
9
10
0
4.75 5.25
V
AIN
= 0
INTERNAL/EXTERNAL
REFERENCE
NORMALIZED INTERNAL REFERENCE
VOLTAGE vs. TEMPERATURE
MAX1272/73 toc07
TEMPERATURE (°C)
NORMALIZED INTERNAL REFERENCE VOLTAGE
6035-15 10
0.9970
0.9975
0.9980
0.9985
0.9990
0.9995
1.0000
1.0005
0.9960
0.9965
-40 85
NORMALIZED INTERNAL REFERENCE
VOLTAGE vs. SUPPLY VOLTAGE
MAX1272/73 toc08
SUPPLY VOLTAGE (V)
NORMALIZED INTERNAL REFERENCE VOLTAGE
5.205.155.05 5.104.85 4.90 4.95 5.004.80
0.9992
0.9994
0.9996
0.9998
1.0000
1.0002
1.0004
1.0006
1.0008
1.0010
0.9990
4.75 5.25
DNL vs. CODE
MAX1272/73 toc09
CODE
DNL (LSB)
358430722048 25601024 1536512
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 4096
INL vs. CODE
MAX1272/73 toc10
CODE
INL (LSB)
358430722048 25601024 1536512
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 4096
FFT PLOT
MAX1272/73 toc11
FREQUENCY (kHz)
AMPLITUDE (dB)
40302010
0
-160
050
-140
-120
-100
-80
-60
-40
-20
f
AIN
= 10kHz
SUPPLY CURRENT
vs. CONVERSION RATE
MAX1272/73 toc12
CONVERSION RATE (ksps)
SUPPLY CURRENT (µA)
10
1
500
1000
1500
2000
2500
0
0.1 100
V
AIN
= 0
STANDBY POWER-DOWN MODE
BETWEEN CONVERSIONS
EXTERNAL REFERENCE
INTERNAL REFERENCE
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(Typical operating circuit, BIP = RNG = 1, VDD= 5V, external reference mode, V
REF
= 4.096V, C
REF
= 1.0µF, f
SCLK
= 1.4MHz,
50% duty cycle, 87ksps, T
A
= +25°C, unless otherwise noted.)
10
8
6
4
2
0
-2
OFFSET ERROR (LSB)
-4
-6
-8
-10
-40 85
OFFSET ERROR vs. TEMPERATURE
RNG = 1, BIP = 1
RNG = 0, BIP = 1
RNG = 1, BIP = 0
TEMPERATURE (°C)
RNG = 0, BIP = 0
603510-15
MAX1272/73 toc13
10
8
6
4
2
0
-2
OFFSET ERROR (LSB)
-4
-6
-8
-10
4.50 5.50
OFFSET ERROR vs. SUPPLY VOLTAGE
RNG = 0, BIP = 1
RNG = 1, BIP = 0
SUPPLY VOLTAGE (V)
RNG = 1, BIP = 1
RNG = 0, BIP = 0
5.255.004.75
MAX1272/73 toc14
GAIN ERROR vs. TEMPERATURE
10
8
RNG = 0, BIP = 0
6
4
2
0
GAIN ERROR (LSB)
RNG = 1, BIP = 0
-2
-4
-6
-8
-10
-40 85
RNG = 0, BIP = 1
RNG = 1, BIP = 1
TEMPERATURE (°C)
GAIN ERROR vs. SUPPLY VOLTAGE
10
8
6
MAX1272/73 toc15
GAIN ERROR (LSB)
603510-15
RNG = 0, BIP = 1
4
2
0
-2
-4
-6
-8
-10
4.50 5.50
RNG = 1, BIP = 1
SUPPLY VOLTAGE (V)
RNG = 0, BIP = 0
RNG = 1, BIP = 0
5.255.004.75
MAX1272/73 toc16
MAX1272/MAX1273
Detailed Description
Converter Operation
The MAX1272/MAX1273 multirange ADCs use successive approximation and internal track/hold (T/H) circuitry
to convert an analog signal to a 12-bit digital output.
Figure 2 shows a block diagram of the MAX1272/
MAX1273.
Analog-Input Track/Hold
The T/H tracking/acquisition mode begins on the falling
edge of the fourth clock cycle in the 8-bit input control
word and enters hold/conversion mode on the falling
edge of the eighth clock cycle.
The MAX1272/MAX1273 input architecture includes a
resistor-divider and a T/H system (Figure 3). When
operating in bipolar or unipolar mode, the resistordivider network formed by R1, R2, and R3 scales the
signal applied at the input channel. Use a low source
impedance (<4Ω) to minimize gain error.
Input Bandwidth
The ADC’s small-signal input bandwidth depends on
the selected input range and varies from 1.25MHz to
5MHz (see the Electrical Characteristics). The maximum sampling rate for the MAX1272/MAX1273 is
87ksps (16 clocks per conversion). Use undersampling
techniques to digitize high-speed transient events and
measure periodic signals with bandwidths exceeding
the ADC’s sampling rate.
Use anti-alias filtering to avoid the aliasing of high-frequency signals into the frequency band of interest. An
anti-aliasing filter must limit the input bandwidth to no
more than one half of the sampling frequency.
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
8 _______________________________________________________________________________________
Pin Description
Figure 1. Output Load Circuit for Timing Characteristics
PIN NAME FUNCTION
1 SCLK Serial Clock Input. Clocks data in and out of serial interface. SCLK sets the conversion speed.
2 DIN Serial Data Input. Data clocks in on the rising edge of SCLK.
3VDD5V Supply. Bypass with a 0.1µF capacitor to GND.
4 GND Ground
5 AIN Analog Input
Reference Buffer Output/Reference Input. Bypass REF with a 1µF capacitor to GND. In internal
6 REF
7 CS
8 DOUT
reference mode, the reference buffer provides a 4.096V nominal output. For external reference mode,
disable the internal reference buffer through the serial interface and apply an external reference to REF.
Active-Low Chip-Select Input. Drive CS low to clock data into the MAX1272/MAX1273. See the Input
Data Format section.
Serial Data Output. Data clocks out on the falling edge of SCLK. DOUT is high impedance when CS is
high.
DOUT
C
LOAD
1kΩ
A) TEST CIRCUIT FOR V
DOUT
1kΩ
OH
C
LOAD
5V
B) TEST CIRCUIT FOR V
f
= 1.4MHz, C
SCLK
LOAD
OL
= 50pF
Input Range and Protection
The MAX1272/MAX1273 provide software-selectable
analog input voltage ranges. Program the analog input
to one of four ranges by setting the appropriate control
bits (RNG, BIP) in the control byte (Table 1). The
MAX1272 has selectable input voltage ranges extending to ±10V (±V
REF
✕
2.4414), while the MAX1273 has
selectable input voltage ranges extending to ±V
REF
.
Figure 3 shows the equivalent input circuit.
Overvoltage circuitry at the analog input provides ±12V
fault protection for the MAX1272. This circuit limits the
current going into or out of the device to less than 2mA,
providing an added layer of protection from momentary
over/undervoltages at the analog input. The overvoltage
protection activates when the device enters powerdown mode or if V
DD
= 0.
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
_______________________________________________________________________________________ 9
Figure 2. Simplified Block Diagram
Table 1. Control-Byte Format
V
DD
GND
AIN
REF
SIGNAL
CONDITIONING
4.096V
REFERENCE
MAX1272
MAX1273
T/H
DIN DOUT SCLK
SERIAL INTERFACE
IN
LOGIC
OUT
12-BIT
SAR ADC
REF
CS
CLK
BIT 7
(MSB)
START RNG BIP PD MODE1 MODE0 RESERVED REF
BIT 6 BIT 5 BIT 4 Bit 3 BIT 2 BIT 1
BIT 0
(LSB)
BIT NAME DESCRIPTION
7 (MSB) START Write a logic 1 (see the Input Data Format section)
6 RNG Selects the full-scale input voltage range (Tables 2, 3)
5 BIP Selects unipolar or bipolar conversion mode (Tables 2, 3)
4 PD Selects normal operation (PD = 1) or power-down (PD = 0) mode
3 MODE1 Selects standby power-down (STBYPD) or full power-down (FULLPD) mode (Table 4)
2 MODE0 Selects delayed or immediate power-down mode (Table 4)
1 RESERVED Write a logic 1
0 (LSB) REF Selects external (REF = 0, default) or internal (REF = 1) reference mode
MAX1272/MAX1273
Input Data Format
Input data (control byte) clocks in at DIN on the rising
edge of SCLK. CS enables communication with the
MAX1272/MAX1273. After CS falls, the first arriving 1
represents the start bit (MSB) of the input control byte.
The start bit is defined as follows:
1) The first high bit clocked into DIN with CS low any
time the converter is idle (e.g., after applying VDD).
2) The first high bit clocked into DIN after bit 4 (D4) of a
conversion in progress clocks out on DOUT.
See Table 1 for programming the control byte. Figure 4
shows the detailed serial interface timing.
Output Data Format
Output data (DOUT) clocks out MSB first on the falling
edge of SCLK. The unipolar mode provides a straight
binary output. The bipolar mode provides a two’s complement binary output. For output binary codes, see the
Transfer Function section.
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
10 ______________________________________________________________________________________
Table 2. Input Range and Polarity Selection for MAX1272
Table 3. Input Range and Polarity Selection for MAX1273
Table 4. Power-Down Selection
Figure 3. Equivalent Input Circuit
INPUT RANGE RNG BIP
NEGATIVE
FULL SCALE
0 to 5V 0 0 — 0V
±5V 0 1 -V
× 1.2207 0 V
REF
0 to 10V 1 0 — 0V
±10V 1 1 -V
INPUT RANGE RNG BIP
0 to V
/ 2 0 0 — 0V
REF
±V
/ 2 0 1 -V
REF
0 to V
±V
REF
REF
10 — 0V
11 -V
× 2.4414 0 V
REF
NEGATIVE
FULL SCALE
/ 2 0 V
REF
REF
PD MODE1 MODE0 MODE
1XX
0
0
1
0 Delayed standby power-down mode.
1 Immediate standby power-down mode.
0 Delayed full power-down mode.
1 Immediate full power-down mode.
Normal operation (ADCs always active). Automatically enters delayed
standby power-down mode between conversions.
ZERO SCALE FULL SCALE
× 1.2207
REF
× 1.2207
REF
× 2.4414
REF
× 2.4414
REF
ZERO SCALE FULL SCALE
/ 2
REF
/ 2
REF
REF
0V
REF
BIPOLAR
S1
R3
4.8kΩ
R1
AIN
UNIPOLAR
OFF
C
S2
ON
R2
HOLD
S3
TRACKHOLD
TRACK
VOLTAGE
REFERENCE
S4
T/H
OUT
HOLD
S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
R1 = 11.3kΩ (MAX1272)
or 4.8kΩ (MAX1273)
R2 = 7.8kΩ (MAX1272)
or ∞ (OPEN) (MAX1273)
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
______________________________________________________________________________________ 11
Figure 4. Detailed Serial Interface Timing
Figure 5. Conversion Timing, 21 Clocks/Conversion
CS
t
t
CSH
CSS
SCLK
t
DS
t
DH
DIN
t
DV
DOUT
CS
• • •
t
CL
t
CH
t
CSH
• • •
• • •
t
DO
t
TR
• • •
DOUT
SCLK
DIN
START
1
RNG
PD
BIP
MODE1
ACQUISITION
4 SCLKs
MODE0
RESERVED
REF
MSB LSBHI-Z HI-Z
D11
8
D7
D6
D5
D4
D3
D2
D1
D9
D8
D10
16
CONVERSION
12 SCLKs
D0
24
AUTO STANDBY
32
MAX1272/MAX1273
Starting a Conversion
The MAX1272/MAX1273 use the serial clock to complete
an acquisition. The falling edge of CS does not start a
conversion on the MAX1272/MAX1273. Each conversion
requires a control byte. Programming the fourth bit in the
control byte starts the acquisition sequence. Conversion
starts on the falling edge of the eighth clock cycle after
the start bit.
Keep CS low during successive conversions. If a start bit
is received after CS transitions from high to low, but before
the output bit 4 (D4) becomes available, the current conversion terminates and a new conversion begins. DOUT
enters high-impedance state when CS transitions high.
SCLK shifts data in and out of the MAX1272/MAX1273
and controls both acquisition and conversion timing.
Conversion begins immediately after the end of the
acquisition cycle. Successive-approximation bit decisions appear at DOUT on each of the following 12 clock
falling edges (Figure 5). Additional clock falling edges
result in trailing zeros at DOUT.
The maximum running rate of the MAX1272/MAX1273 is
16 clocks per conversion. A clock speed of 1.4MHz
allows for a maximum sampling rate of 87ksps (Figure 6).
To achieve the maximum throughput, keep CS low, and
start the control byte after bit 4 (D4) of the conversion in
progress clocks out on DOUT.
If CS is low and SCLK is continuous, guarantee a start
bit by first clocking in 16 zeros.
Applications Information
Power-On Reset
The MAX1272/MAX1273 power-up in normal operating
mode (all internal circuitry active), and external reference
mode. The MAX1272/MAX1273 require a start bit to initiate a conversion. The contents of the output data register
clear during power-up.
Internal or External Reference
Operate the MAX1272/MAX1273 with an internal or an
external reference. Configure REF as an internal reference output or an external reference input using the
serial interface. When changing from external reference
mode to internal reference mode, allow 2ms (C
REF
=
1µF) for the reference to stabilize before taking any
measurement.
Internal Reference
The internally trimmed reference provides 4.096V at REF.
Bypass REF to GND with a 1.0µF capacitor (Figure 7a).
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
12 ______________________________________________________________________________________
Figure 6. Conversion Timing, 16 Clocks/Conversion
CS
CONTROL BYTE 0 CONTROL BYTE 1
DOUT
SCLK
DIN
HI-Z
RNG
START
1
MODE1
PD
BIP
ACQUISITION
MODE0
4 SCLKs
REF
RESERVED
MSB LSB
D9
D10
D11
8
REF
RESERVED
MODE0
MODE1
PD
BIP
RNG
START
RESULT 0 RESULT 1
D0
D1
D2
D3
D8
D7
CONVERSION
12 SCLKs
D4
D5
D6
16
ACQUISITION
4 SCLKs
MSB LSB
D8
D9
D10
D11
24
CONTROL BYTE 2
RNG
START
D3
D4
D5
D6
D7
32
CONVERSION
12 SCLKs
MODE1
PD
BIP
D0
D1
D2
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
______________________________________________________________________________________ 13
External Reference
To use an external reference, disable the internal buffer
by setting the REF bit in the 8-bit control word to zero
(see Table 1), and apply a reference voltage to REF. Use
an external reference voltage ranging from 2.40V to
4.18V. External reference voltages less than 4.096V
increase the ratio of RMS noise to the LSB value (full
scale / 4096) resulting in performance degradation (loss
of effective bits—ENOB).
The REF input impedance is a minimum of 4.8kΩ for
DC currents; therefore, the external reference must be
able to source 850µA during conversions and have an
output impedance of less than 10Ω. Bypass REF with a
1µF capacitor to GND as close to REF as possible
(Figure 7b).
Power-Down Modes
To save power, configure the ADC for a low-current
shutdown mode by setting the PD bit in the control
byte. The MAX1272/MAX1273 features four programmable power-down modes: delayed standby powerdown, immediate standby power-down, delayed full
power-down, and immediate full power-down. Select
standby or full power-down by programming MODE1 in
the input control byte (Table 4). Select delayed or
immediate power-down by programming MODE0 in the
input control byte. Use the MODE0 bit to choose when
the part enters the power-down state. For example,
when MODE0 of the control byte is 0, the device
remains powered up until after the current conversion
ends (Figure 8). On the other hand, if MODE0 = 1, the
device powers down on the falling edge of the eighth
serial clock cycle and no conversion takes place
(Figure 9). In all power-down modes, the interface
remains active with the conversion results available at
DOUT. Additionally, the input overvoltage protection
remains active in all power-down modes (MAX1272).
The first high bit on DIN after CS falls (start condition)
powers up the MAX1272/MAX1273 from any softwareselected power-down condition. With external reference mode, device power-up time from full powerdown is typically 10µs. Send a control byte and allow
10µs for the device to wake up from full power-down.
The next received control byte initiates a conversion.
When in internal reference mode, full power-down
mode disables the internal reference and reference
buffer. Only the interface circuitry remains active for
reading conversion results. Send a control byte and
allow 2ms (C
REF
= 1µF) for the internal reference to settle and the MAX1272/MAX1273 to wake up from full
power-down mode. The next received control byte initiates a conversion.
AutoShutdown™
The MAX1272/MAX1273 automatically enter standby
power-down mode after each conversion without requiring any startup time on the next conversion.
Digital Interface
The MAX1272/MAX1273 feature a fully compatible
SPI/QSPI and MICROWIRE serial interface. For SPI and
QSPI, clear CPOL and CPHA in the microcontroller’s
SPI control registers.
Figure 7a. Internal Reference Configuration
Figure 7b. External Reference Configuration
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
REF
MAX1272
MAX1273
C
REF
1.0µF
5V
IN
MAX6064
C
OUT
1.0µF
REF
GND
REF
MAX1272
MAX1273
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
14 ______________________________________________________________________________________
SPI and MICROWIRE Interface
When using the SPI (Figure 10a) or MICROWIRE (Figure
10b) interfaces, set CPOL = 0 and CPHA = 0 in the SPI
master. Conversion begins with a falling edge on CS.
Three consecutive 8-bit readings are necessary to
obtain the entire 12-bit result from the ADC. DOUT data
transitions on the serial clock’s falling edge. The first 8-
bit data stream contains all leading zeros. The second
8-bit data stream contains a leading zero followed by
the MSB through D5. The third 8-bit data stream contains D4–D0 followed by trailing zeros.
Figure 8. Delayed Power-Down Timing
Figure 9. Immediate Power-Down Timing
CS
DOUT
SCLK
DIN
RNG
START
1
ODE1
BIP
M
0
ACQUISITION
4 SCLKs
RESERVED
REF
MSB LSBHI-Z HI-Z
D11
8
POWERED UP
0
CS
DIN
DOUT
START
RNG
BIP
HI-Z HI-Z
1
0
MODE1
RESERVED
REF
MODE1
POWERED UP
RESERVED
REF
MODE0
RESERVED
REF
32
PD
BIP
RNG
START
D8
D9
D10
D7
CONVERSION
12 SCLKs
D4
D5
D6
16
D1
D2
D3
D0
POWERED DOWN
24
START
RNG
BIP
MODE0
PD
MODE1
4 SCLKs
8
16
POWERED DOWN
24
POWERED UP
SCLK
1
ACQUISITION
POWERED UP
32
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
______________________________________________________________________________________ 15
Figure 10a. SPI Connections
Figure 10b. MICROWIRE Connections
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX1272/MAX1273 support a maximum f
SCLK
of 1.4MHz. Figure 11 shows the MAX1272/
MAX1273 connected to a QSPI master.
PIC16 with SSP Module and
PIC17 Interface
The MAX1272/MAX1273 are compatible with a
PIC16/PIC17 controller (µC) using the synchronous serial-port (SSP) module.
To establish SPI communication, connect the controller
as shown in Figure 12 and configure the PIC16/PIC17
as system master by initializing its synchronous serialport control register (SSPCON) and synchronous serialport status register (SSPSTAT) to the bit patterns shown
in Tables 5 and 6.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data
to be transmitted and received simultaneously. Three
consecutive 8-bit readings are necessary to obtain the
entire 12-bit result from the ADC. DOUT data transitions
on the serial clock’s falling edge and is clocked into the
µC on SCLK’s rising edge. The first 8-bit data stream
contains all zeros. The second 8-bit data stream contains a leading zero followed by the MSB through D5.
The third 8-bit data stream contains bits D4–D0 followed by trailing zeros.
Transfer Function
Output data coding for the MAX1272/MAX1273 is binary in unipolar mode with:
and two’s complement binary in bipolar mode with:
Code transitions occur halfway between successive
integer LSB values. Figures 13a and 13b show the
input/output transfer functions for uni-polar and bipolar
operations, respectively. For full-scale (FS) values, see
Tables 2 and 3.
1
2
4096
LSBFS=
× ||
1
4096
LSBFS=
Figure 11. QSPI Connections
Figure 12. SPI Interface Connection for a PIC16/PIC17
CS
SCLK
DOUT
MAX1272
MAX1273
SPI
I/O
SCK
MISO
SS
V
DD
CS
SCLK
DOUT
MAX1272
MAX1273
MICROWIRE
I/O
SCK
SI
CS
SCK
MISO
QSPI
SS
SCK
SDI
I/O
V
DD
PIC16/PIC17
V
DD
CS
SCLK
V
DD
DOUT
MAX1272
MAX1273
SCLK
DOUT
CS
MAX1272
MAX1273
GND
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
16 ______________________________________________________________________________________
X = Don’t care.
Table 6. Detailed SSPSTAT Register Contents—PIC16/PIC17
X = Don’t care.
Table 5. Detailed SSPCON Register Contents—PIC16/PIC17
Figure 13a. Unipolar Transfer Function
Figure 13b. Bipolar Transfer Function
CONTROL BIT SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL BIT7 X Write Collision Detection Bit
SSPOV BIT6 X Receive Overflow Detection Bit
Synchronous Serial-Port Enable Bit:
SSPEN BIT5 1
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.
CKP BIT4 0 Clock Polarity Select Bit. CKP = 0 for SPI master mode section.
SSPM3 BIT3 0
SSPM2 BIT2 0
SSPM1 BIT1 0
Synchronous Serial-Port Mode-Select Bit. Sets SPI master mode and selects f
SSPM0 BIT0 1
SMP BIT7 0
CONTROL BIT SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output
time.
CKE BIT6 1 SPI Clock Edge-Select Bit. Data is transmitted on the rising edge of the serial clock.
D/A BIT5 X Data Address Bit
P BIT4 X Stop Bit
S BIT3 X Start Bit
R/W BIT2 X Read/Write Bit Information
UA BIT1 X Update Address
BF BIT0 X Buffer Full Status Bit
CLK
= f
OSC
/ 16.
OUTPUT CODE
1…111
1…110
1…101
1…100
0…011
0…010
0…001
0…000
012
3
INPUT VOLTAGE (LSB)
4092 4094
FS
1 LSB =
4096
FS
OUTPUT CODE
(TWO’S COMPLEMENT)
0…111
0…110
0…101
0…100
0…001
0…000
1…111
1…011
1…010
1…001
1…000
-2048 -2046
-1 0 +1
INPUT VOLTAGE (LSB)
+2045
2FS
1 LSB =
4096
+2047
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
______________________________________________________________________________________ 17
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one star point (Figure 14), connecting the two ground
systems (analog and digital). For lowest-noise operation, ensure that the ground return to the star ground’s
power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog
and reference inputs.
High-frequency noise in the power supply (V
DD
) can
degrade the performance of the ADC’s fast comparator. Bypass VDDto the star ground with a 0.1µF capacitor located as close as possible to the MAX1272/
MAX1273’s power-supply input. Minimize capacitor lead
length for best supply-noise rejection. Add an attenuation resistor (5Ω) to extremely noisy power supplies.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1272/MAX1273
are measured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step-width and the ideal value of 1 LSB. A
DNL error specification of 1 LSB guarantees no missing
codes and a monotonic transfer function.
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between samples. Aperture delay (t
AD
) is the
time between the falling edge of the sampling clock
and the instant when the actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantization error (residual error).
The ideal, theoretical minimum analog-to-digital noise is
caused by quantization noise error only and results
directly from the ADC’s resolution (N-bits):
SNR = (6.02
✕ N + 1.76) dB
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals:
SINAD (dB) = 20
✕ log [Signal
RMS
/ (Noise +
Distortion)
RMS
]
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number
of bits as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V
1
is the fundamental amplitude and V2through
V5are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest frequency component, excluding DC offset.
THD
VVVV
V
=×
+++
20
2
2
3
2
4
2
5
2
1
log
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
18 ______________________________________________________________________________________
Typical Operating Circuit
Chip Information
TRANSISTOR COUNT: 6146
PROCESS: BiCMOS
Figure 14. Power-Supply Grounding Connections
5V
SUPPLIES
5V V
R* = 5Ω
0.1µF
V
DD
GND
MAX1272
MAX1273
= 5V GND
LOGIC
DGND5V
DIGITAL
CIRCUITRY
1.0µF
AIN
REF
V
DD
MAX1272
MAX1273
GND
0.1µF
SCLK
DIN
DOUT
CS
I/O
SCK
MOSI
MISO
µP
*OPTIONAL
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
______________________________________________________________________________________ 19
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
PDIPN.EPS
MAX1272/MAX1273
Fault-Protected, 12-Bit ADCs
with Software-Selectable Input Range
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages
.)
8
b
E H
A1
A
c
ÿ 0.50±0.1
0.6±0.1
0.6±0.1
1
D
TOP VIEW
A2
e
FRONT VIEW
4X S
L
BOTTOM VIEW
SIDE VIEW
8
1
DIM
A
A1
A2
b
c
D
e
E
H
L
α
S
INCHES
MIN
-
0.002
0.030
0.010
0.005
0.116
0.0256 BSC
0.116
0.188
0.016
0∞
0.0207 BSC
0.043
0.006
0.037
0.014
0.007
0.120
0.120
0.198
0.026
MAX
6∞
MILLIMETERS
MIN
0.05 0.15
0.25 0.36
0.13 0.18
2.95 3.05
2.95 3.05
4.78
0.41
MAX
- 1.10
0.950.75
0.65 BSC
5.03
0.66
0.5250 BSC
8LUMAXD.EPS
6∞0∞
α
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
REV.DOCUMENT CONTROL NO.APPROVAL
21-0036
1
J
1
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