Rainbow Electronics MAX1249 User Manual
_______________
General Description
The MAX1248/MAX1249 10-bit data-acquisition systems combine a 4-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and low power consumption. They operate from
a single +2.7V to +5.25V supply, and their analog
inputs are software configurable for unipolar/bipolar
and single-ended/differential operation.
The 4-wire serial interface connects directly to SPI™/
QSPI™ and MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection
to TMS320-family digital signal processors. The
MAX1248/MAX1249 use either the internal clock or an
external serial-interface clock to perform successiveapproximation analog-to-digital conversions.
The MAX1248 has an internal 2.5V reference, while the
MAX1249 requires an external reference. Both parts
have a reference-buffer amplifier with a ±1.5% voltage
adjustment range.
These devices provide a hard-wired SHDN pin and a
software-selectable power-down, and can be programmed to automatically shut down at the end of a
conversion. Accessing the serial interface automatically
powers up the MAX1248/MAX1249, and the quick
turn-on time allows them to be shut down between all
conversions. This technique can cut supply current to
under 60µA at reduced sampling rates.
The MAX1248/MAX1249 are available in a 16-pin DIP
and a very small QSOP that occupies the same board
area as an 8-pin SO.
For 8-channel versions of these devices, see the
MAX148/MAX149 data sheet.
________________________Applications
Portable Data Logging Data Acquisition
Medical Instruments Battery-Powered Instruments
Pen Digitizers System Supervision
____________________________Features
♦ 4-Channel Single-Ended or 2-Channel
Differential Inputs
♦ Single +2.7V to +5.25V Operation
♦ Internal 2.5V Reference (MAX1248)
♦ Low Power: 1.2mA (133ksps, +3V supply)
54µA (1ksps, +3V supply)
1µA (power-down mode)
♦ SPI/QSPI/MICROWIRE/TMS320-Compatible
4-Wire Serial Interface
♦ Software-Configurable Unipolar or Bipolar Inputs
♦ 16-Pin QSOP Package (same area as 8-pin SO)
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
________________________________________________________________
Maxim Integrated Products
1
19-1072; Rev 2; 5/98
PART
†
MAX1248ACPE
MAX1248BCPE
MAX1248ACEE 0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
16 Plastic DIP
16 Plastic DIP
16 QSOP
_____________
Ordering Information
Ordering Information continued at end of data sheet.
†
Contact factory for availability of alternate surface-mount
packages.
Pin Configuration appears at end of data sheet.
MAX1248BCEE 0°C to +70°C 16 QSOP
INL
(LSB)
±1/2
±1
±1/2
±1
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
V
DD
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
V
SS
SHDN
SSTRB
DOUT
DIN
SCLK
CS
COM
AGND
DGND
V
DD
CH3
C1
4.7µF
C2
0.01µF
C3
0.1µF
CH0
0V TO
+2.5V
ANALOG
INPUTS
MAX1248
CPU
+3V
VREF
REFADJ
__________Typical Operating Circuit
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD= +2.7V to +5.25V; COM = 0V; f
SCLK
= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX1248—4.7µF capacitor at VREF pin; MAX1249—external reference, VREF = 2.500V applied to VREF pin; T
A
= T
MIN
to T
MAX
,
unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDDto AGND, DGND..............................................-0.3V to +6V
AGND to DGND.................................................... -0.3V to +0.3V
CH0–CH3, COM to AGND, DGND............-0.3V to (V
DD
+ 0.3V)
VREF to AGND........................................... -0.3V to (V
DD
+ 0.3V)
Digital Inputs to DGND............................................ -0.3V to +6V
Digital Outputs to DGND...........................-0.3V to (V
DD
+ 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (T
A
= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ......... 842mW
QSOP (derate 8.30mW/°C above +70°C)...................667mW
CERDIP (derate 10.00mW/°C above +70°C)..............800mW
Operating Temperature Ranges
MAX1248_C_E/MAX1249_C_E.......................... 0°C to +70°C
MAX1248_E_E/MAX1249_E_E........................ -40°C to +85°C
MAX1248_MJE/MAX1249_MJE.................... -55°C to +125°C
Storage Temperature Range............................ -60°C to +150°C
Lead Temperature (soldering, 10sec)............................ +300°C
6
µs
35 65
t
CONV
Conversion Time (Note 5)
5.5 7.5
MHz1.0Full-Power Bandwidth
MHz2.25Small-Signal Bandwidth
dB-75Channel-to-Channel Crosstalk
dB70SFDRSpurious-Free Dynamic Range
dB-70THDTotal Harmonic Distortion
dB66SINADSignal-to-Noise + Distortion Ratio
LSB±0.05
Channel-to-Channel Offset
Matching
ppm/°C±0.25Gain Temperature Coefficient
±0.5
Bits10Resolution
±1
Offset Error
LSB
±1.0
INLRelative Accuracy (Note 2)
LSB±1DNL
±1
LSB
±2
UNITSMIN TYP MAXSYMBOLPARAMETER
External clock = 2MHz, 12 clocks/conversion
Internal clock, SHDN = V
DD
Internal clock, SHDN = FLOAT
MAX124_A
-3dB rolloff
65kHz, 2.500Vp-p (Note 4)
Up to the 5th harmonic
MAX124_A
MAX124_B
No missing codes over temperature
MAX124_A
MAX124_B
CONDITIONS
Differential Nonlinearity
ns30Aperture Delay
MHz
1.8
SHDN = FLOAT
ps<50Aperture Jitter
MHz
0.1 2.0
µs1.5t
ACQ
Track/Hold Acquisition Time
0.225
Internal Clock Frequency
SHDN = V
DD
0 2.0
External Clock Frequency
Data transfer only
LSBGain Error (Note 3)
±2MAX124_B
DC ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)
CONVERSION RATE
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
_______________________________________________________________________________________ 3
Multiplexer Leakage Current
pF15C
IN
DIN, SCLK, CS Input Capacitance
µA±0.01 ±1I
IN
DIN, SCLK, CS Input Leakage
V0.2V
HYST
DIN, SCLK, CS Input Hysteresis
V0.8V
IL
DIN, SCLK, CS Input Low Voltage
2.0
µA0.01 10Shutdown VREF Input Current
kΩ18 25VREF Input Resistance
µA100 150VREF Input Current
V
1.0
V
DD
+
50mV
VREF Input Voltage Range
(Note 9)
pF16Input Capacitance
0 to VREF
V
±VREF/ 2
Input Voltage Range, SingleEnded and Differential (Note 6)
µA±0.01 ±1
UNITSMIN TYP MAXSYMBOLPARAMETER
(Note 10)
VIN= 0V or V
DD
Unipolar, COM = 0V
V
DD
≤ 3.6V
VREF = 2.500V
Bipolar, COM = VREF / 2
On/off leakage current, V
CH_
= 0V or V
DD
CONDITIONS
µA±4.0I
S
SHDN Input Current
V0.4V
SL
SHDN Input Low Voltage
VVDD- 0.4V
SH
SHDN Input High Voltage
SHDN = 0V or V
DD
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +2.7V to +5.25V; COM = 0V; f
SCLK
= 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX1248—4.7µF capacitor at VREF pin; MAX1249—external reference, VREF = 2.500V applied to VREF pin; T
A
= T
MIN
to T
MAX
,
unless otherwise noted.)
V
3.0
V
IH
DIN, SCLK, CS Input High Voltage
VDD> 3.6V
V2.470 2.500 2.530VREF Output Voltage TA= +25°C (Note 7)
mA30VREF Short-Circuit Current
ppm/°C±30VREF Temperature Coefficient MAX1248
µF
0
Capacitive Bypass at VREF
Internal compensation mode
4.7External compensation mode
mV0.35Load Regulation (Note 8) 0mA to 0.2mA output load
µF0.01Capacitive Bypass at REFADJ
±1.5REFADJ Adjustment Range %
V
V
DD -
0.5
REFADJ Buffer-Disable Threshold
Capacitive Bypass at VREF
Internal compensation mode 0
µF
External compensation mode 4.7
Reference-Buffer Gain
MAX1248 2.06
V/V
MAX1249 2.00
REFADJ Input Current
MAX1248 ±50
µA
MAX1249 ±10
V1.1 VDD- 1.1V
SM
SHDN Input Mid Voltage
ANALOG/COM INPUTS
EXTERNAL REFERENCE AT VREF (Buffer disabled)
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
EXTERNAL REFERENCE AT REFADJ
INTERNAL REFERENCE (MAX1248 only, reference buffer enabled)
VDD= 5.25V
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
4 _______________________________________________________________________________________
1.2 2.0
3.5 15
Operating mode,
full-scale input (Note 11)
30 70Fast power-down (MAX1248)
nA±100
SHDN Maximum Allowed
Leakage, Mid Input
VV
DD
/ 2V
FLT
SHDN Voltage, Floating
SHDN = FLOAT
SHDN = FLOAT
UNITSMIN TYP MAXSYMBOLPARAMETER
µA
1.2 10
I
DD
CONDITIONS
Positive Supply Current
mA
1.6 3.0
µA±0.01 ±10I
L
Three-State Leakage Current
VVDD- 0.5V
OH
Output Voltage High
V
0.8
V
OL
Output Voltage Low
0.4
V2.70 5.25V
DD
Positive Supply Voltage
pF15C
OUT
Three-State Output Capacitance
Full power-down
CS = VDD(Note 10)
CS = V
DD
I
SOURCE
= 0.5mA
I
SINK
= 16mA
I
SINK
= 5mA
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +2.7V to +5.25V; COM = 0V; f
SCLK
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX1248—4.7µF capacitor at VREF pin; MAX1249—external reference; VREF = 2.500V applied to VREF pin, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.)
mV±0.3PSRSupply Rejection (Note 12)
VDD= 2.7V to 5.25V, full-scale input,
external reference = 2.500V
DIGITAL OUTPUTS (DOUT, SSTRB)
POWER REQUIREMENTS
I
DD
VDD= 5.25V
VDD= 3.6V
VDD= 5.25V
VDD= 3.6V
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
_______________________________________________________________________________________
5
TIMING CHARACTERISTICS
(VDD= +2.7V to +5.25V, TA= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1: Tested at V
DD
= 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX1248—internal reference, offset nulled; MAX1249—external reference (VREF = +2.500V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to V
DD
.
Note 7 Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 10 Guaranteed by design. Not subject to production testing.
Note 11: The MAX1249 typically draws 400µA less than the values shown.
Note 12: Measured as
|
VFS(2.7V) - VFS(5.25V)|.
DIN to SCLK Setup
ns240t
STR
CS Rise to SSTRB Output Disable
ns240t
SDV
CS Fall to SSTRB Output Enable
240t
SSTRB
SCLK Fall to SSTRB ns
200t
CL
SCLK Pulse Width Low
ns200SCLK Pulse Width High
ns0
CS to SCLK Rise Hold
ns100t
CSS
CS to SCLK Rise Setup
ns240t
TR
CS Rise to Output Disable
ns240t
DV
CS Fall to Output Enable
t
DO
SCLK Fall to Output Data Valid
ns0t
DH
DIN to SCLK Hold
ns
µs1.5t
ACQ
Acquisition Time
0t
SCK
SSTRB Rise to SCLK Rise
ns100t
DS
UNITSMIN TYP MAXSYMBOLPARAMETER
Internal clock mode only (Note 10)
External clock mode only, Figure 2
External clock mode only, Figure 1
Figure 1
Figure 2
Figure 1
CONDITIONS
ns
20 240
Figure 1
t
CSH
t
CH
ns
MAX124__C/E
MAX124__M
20 200
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
6 _______________________________________________________________________________________
2.00
0.50
2.25 2.75
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.75
1.25
1.50
1.00
0.75
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
3.75 5.253.25 4.25 4.75
MAX1248-01
RL = ∞
CODE = 10101010
MAX1249
MAX1248
C
LOAD
= 20pF
C
LOAD
= 50pF
C
LOAD
= 50pF
C
LOAD
= 20pF
4.0
3.5
0
2.25 2.75
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
3.0
2.5
1.5
2.0
1.0
0.5
V
DD
(V)
SHUTDOWN SUPPLY CURRENT (µA)
3.75 5.253.25 4.25 4.75
MAX1248/49-02
FULL POWER-DOWN
2.5025
2.4975
2.25 2.75
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
2.5000
SUPPLY VOLTAGE (V)
INTERNAL REFERENCE VOLTAGE (V)
3.75 5.253.25 4.25 4.75
MAX1248-09
0.8
0.9
1.0
1.1
1.2
1.3
-60 -20 20 60 100 140
SUPPLY CURRENT vs. TEMPERATURE
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX1247-04
MAX1249
MAX1248
R
LOAD
= ∞
CODE = 1010101000
00
0.10
0.05
0.20
0.15
0.25
0.30
2.25 3.25 3.752.75 4.25 4.75 5.25
INTERGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX1248-07
SUPPLY VOLTAGE (V)
INL (LSB)
MAX1248
MAX1249
0
0.4
0.8
1.2
1.6
2.0
-60 -20 20 60 100 140
SHUTDOWN CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
SHUTDOWN CURRENT (µA)
MAX1248-05
2.494
2.495
2.496
2.497
2.498
2.499
2.500
2.501
-60 -20-40 200 6040 100 12080 140
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE, VREF
MAX1248-06
VDD = 2.7V
VDD = 3.6V
VDD = 5.25V
0
0.15
0.10
0.05
0.20
0.25
0.30
-60 200-40 -20 40 60 80 100 120 140
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX1248-08
TEMPERATURE (°C)
INL (LSB)
VDD = 2.7V
MAX1248
MAX1249
0.100
INTEGRAL NONLINEARITY
vs. CODE
0.050
-0.100
0
-0.025
-0.050
-0.075
0.075
0.025
MAX1248-09
INL (LSB)
CODE
256 512 768 10240
__________________________________________Typical Operating Characteristics
(VDD= 3.0V, VREF = 2.500V, f
SCLK
= 2.0MHz, C
LOAD
= 20pF, TA= +25°C, unless otherwise noted.)
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
_______________________________________________________________________________________ 7
NAME FUNCTION
1 V
DD
Positive Supply Voltage
2–5 CH0–CH3 Sampling Analog Inputs
PIN
6 COM
Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to
±0.5LSB.
7
SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1248/MAX1249 down; otherwise, the
devices are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode.
12 DOUT
Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
11 DGND Digital Ground
9 REFADJ Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD.
8 VREF
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
internal reference mode (MAX1248 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to VDD.
16 SCLK
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
15
CS
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
14 DIN Serial Data Input. Data is clocked in at SCLK’s rising edge.
13 SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1248/MAX1249 begin the
A/D conversion and goes high when the conversion is completed. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high (external
clock mode).
______________________________________________________________Pin Description
V
DD
6k
DGND
DOUT
C
LOAD
50pF
C
LOAD
50pF
DGND
6k
DOUT
a) High-Z to V
OH
and VOL to V
OH
b) High-Z to VOL and VOH to V
OL
Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time
10 AGND Analog Ground
DOUT
6k
DGND
a) V
to High-Z b) VOL to High-Z
OH
C
50pF
LOAD
DOUT
V
DD
6k
C
LOAD
50pF
DGND
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
8 _______________________________________________________________________________________
_______________Detailed Description
The MAX1248/MAX1249 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 10-bit digital output. A flexible
serial interface provides easy interface to microprocessors (µPs). Figure 3 is a block diagram of the
MAX1248/MAX1249.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog comparator is illustrated in the equivalent input circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH3, and IN- is switched to COM. In
differential mode, IN+ and IN- are selected from two
pairs: CH0/CH1 and CH2/CH3. Configure the channels
with Tables 2 and 3. Please note that the codes for
CH0–CH3 in the MAX1248/MAX1249 correspond to
the codes for CH2–CH5 in the eight-channel
(MAX148/MAX149) versions.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain stable within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
HOLD
. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge
on C
HOLD
as a sample of the signal at IN+.
The conversion interval begins with the input multiplexer switching C
HOLD
from the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is simply COM. This unbalances node ZERO at the comparator’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 10-bit resolution. This
action is equivalent to transferring a charge of 16pF x
[(V
IN
+
) - (VIN-)] from C
HOLD
to the binary-weighted
capacitive DAC, which in turn forms a digital representation of the analog input signal.
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for differential inputs, IN- connects to the “-” input, and the
difference of |IN+ - IN-
| is sampled. At the end of the
conversion, the positive input connects back to IN+,
and C
HOLD
charges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
INPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+1.21V
REFERENCE
(MAX1248)
T/H
ANALOG
INPUT
MUX
SAR
ADC
IN
DOUT
SSTRB
V
DD
DGND
AGND
SCLK
DIN
COM
REFADJ
VREF
OUT
REF
CLOCK
+2.500V
20k
A ≈ 2.06*
*A ≈ 2.00 (MAX1249)
7
8
9
6
12
13
14
15
16
CH3
5
CH2
4
CH1
3
CH0
2
MAX1248
MAX1249
CS
SHDN
1
11
10
Figure 3. Block Diagram
CH0
CH1
CH2
CH3
COM
C
SWITCH
TRACK
T/H
SWITCH
R
IN
9k
C
HOLD
HOLD
CAPACITIVE DAC
VREF
ZERO
COMPARATOR
–
+
16pF
SINGLE-ENDED MODE: IN+ = CHO–CH3, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1 AND CH2/CH3.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 4. Equivalent Input Circuit
Loading...