Rainbow Electronics MAX1204 User Manual

19-1179; Rev 0; 1/97

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

_______________General Description

The MAX1204 is a 10-bit data-acquisition system
specifically designed for use in applications with mixed
+5V (analog) and +3V (digital) supply voltages. It oper­ates with a single +5V analog supply or dual ±5V ana­log supplies, and combines an 8-channel multiplexer,
internal track/hold, and serial interface with high con­version speed and low power consumption.

A 4-wire serial interface connects directly to
SPI™/Microwire™ devices without external logic, and a
serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1204
uses either the internal clock or an external serial­interface clock to perform successive-approximation
analog-to-digital conversions. The serial interface oper­ates at up to 2MHz.

The MAX1204 features an internal 4.096V reference and
a reference-buffer amplifier that simplifies gain trim. It
also has a VL pin that supplies power to the digital out­puts. Output logic levels (3V, 3.3V, or 5V) are determined
by the value of the voltage applied to this pin.

A hard-wired SHDN pin and two software-selectable
power-down modes are provided. Accessing the serial
interface automatically powers up the device. A quick
turn-on time allows the MAX1204 to be shut down
between conversions, enabling the user to optimize
supply currents. By customizing power-down between
conversions, supply current can drop below 10µA at
reduced sampling rates.

The MAX1204 is available in 20-pin SSOP and DIP
packages, and is specified for the commercial, extend­ed, and military temperature ranges.

____________________________Features

♦ 8-Channel Single-Ended or 4-Channel

Differential Inputs

♦ Operates from +5V Single or ±5V Dual Supplies
♦ User-Adjustable Output Logic Levels

(2.7V to 5.25V)

♦ Low Power: 1.5mA (operating mode)

2µA (power-down mode)

♦ Internal Track/Hold, 133kHz Sampling Rate
♦ Internal 4.096V Reference
♦ SPI/Microwire/TMS320-Compatible

4-Wire Serial Interface

♦ Software-Configurable Unipolar/Bipolar Inputs
♦ 20-Pin DIP/SSOP
♦ Pin-Compatible 12-Bit Upgrade: MAX1202

______________Ordering Information

PART

MAX1204ACPP
MAX1204BCPP
MAX1204ACAP 0°C to +70°C
MAX1204BCAP 0°C to +70°C 20 SSOP

Ordering Information continued at end of data sheet.

TEMP. RANGE PIN-PACKAGE

0°C to +70°C
0°C to +70°C

20 Plastic DIP
20 Plastic DIP
20 SSOP

INL

(LSB)

±1/2
±1
±1/2
±1

__________________Pin Configuration

MAX1204

________________________Applications

5V/3V Mixed-Supply Systems
Data Acquisition
Process Control
Battery-Powered Instruments
Medical Instruments

Typical Operating Circuit appears on last page.

SPI is a registered trademark of Motorola, Inc.
Microwire is a registered trademark of National Semiconductor Corp.

________________________________________________________________

TOP VIEW

CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7

V

20

1
2
3

MAX1204

4
5
6
7
8
9

SS

10

DIP/SSOP

Maxim Integrated Products

V

DD

SCLK

19

CS

18
17

DIN

16

SSTRB
DOUT

15



VL

14
13

GND

12

REFADJ

11

REFSHDN

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone]

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

ABSOLUTE MAXIMUM RATINGS

VDDto GND..............................................................-0.3V to +6V

VL ...............................................................-0.3V to (V

to GND...............................................................+0.3V to -6V

V

SS

to VSS..............................................................-0.3V to +12V

V

DD

CH0–CH7 to GND............................(V

CH0–CH7 Total Input Current...........................................±20mA

REF to GND................................................-0.3V to (V

REFADJ to GND.........................................-0.3V to (V

Digital Inputs to GND .................................-0.3V to (V

MAX1204

Digital Outputs to GND.................................-0.3V to (VL + 0.3V)

Digital Output Sink Current.................................................25mA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

- 0.3V) to (VDD+ 0.3V)

SS

DD

DD
DD
DD

+ 0.3V)

+ 0.3V)
+ 0.3V)
+ 0.3V)

ELECTRICAL CHARACTERISTICS

(VDD= +5V ±5%, VL = 2.7V to 3.6V; VSS= 0V or -5V ±5%; f
cycle (133ksps); 4.7µF capacitor at REF; T

= T

to T

A

MIN

; unless otherwise noted.)

MAX

Continuous Power Dissipation (T

Plastic DIP (derate 11.11mW/°C above +70°C) ...........889mW

SSOP (derate 8.00mW/°C above +70°C) .....................640mW

CERDIP (derate 11.11mW°C above +70°C).................889mW

Operating Temperature Ranges

MAX1204_C_P.....................................................0°C to +70°C

MAX1204_E_P ..................................................-40°C to +85°C

MAX1204BMJP...............................................-55°C to +125°C

Storage Temperature Range.............................-60°C to +150°C

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion

SCLK

= +70°C)

A

CONDITIONS

DC ACCURACY (Note 1)

INLRelative Accuracy (Note 2)

Offset Error

Gain Error (Note 3)

Channel-to-Channel
Offset Matching

DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 4.096Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)

Total Harmonic Distortion
(up to the 5th harmonic)

MAX1204A
MAX1204B
No missing codes over temperature
MAX1204A
MAX1204B
MAX1204A
MAX1204B
External reference, 4.096V

VIN= 4.096Vp-p, 65kHz (Note 4)

-3dB rolloff MHz4.5Small-Signal Bandwidth

±0.5
±1.0

±1.0
±2.0
±1.0
±2.0

UNITSMIN TYP MAXSYMBOLPARAMETER

Bits10Resolution
LSB
LSB±1.0DNLDifferential Nonlinearity
LSB

LSB

ppm/°C±0.8Gain Temperature Coefficient

LSB±0.1

dB66SINADSignal-to-Noise + Distortion Ratio
dB-70THD
dB70SFDRSpurious-Free Dynamic Range

dB-75Channel-to-Channel Crosstalk

kHz800Full-Power Bandwidth

2 _______________________________________________________________________________________

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±5%, VL = 2.7V to 3.6V; VSS= 0V or -5V ±5%; f
cycle (133ksps); 4.7µF capacitor at REF; T

CONVERSION RATE

Conversion Time (Note 5)
Track/Hold Acquisition Time

External Clock-Frequency Range

ANALOG INPUT

Input Voltage Range, Single­Ended and Differential (Note 7)

INTERNAL REFERENCE

V

Temperature Coefficient

REF

Capacitive Bypass at REF

EXTERNAL REFERENCE AT REF (Buffer disabled, V
Input Voltage Range

REFADJ Buffer Disable Threshold

t

CONV

ACQ

= T

A

to T

MIN

MAX

Internal clock
External clock, 2MHz, 12 clocks/conversion

External compensation mode, 4.7µF
Internal compensation mode (Note 6)
Used for data transfer only

Unipolar, VSS= 0V
Bipolar, VSS= -5V
On/off leakage current, V
(Note 6)

TA= +25°C

MAX1204AC
MAX1204AE ±30 ±60

0mA to 0.5mA output load mV2.5Load Regulation (Note 8)
Internal compensation mode
External compensation mode 4.7

REF

SHDN = 0V

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion

SCLK

; unless otherwise noted.)

CONDITIONS

= 4.096V)

CH_

= ±5V

5.5 10
6

0.1 2.0

0.1 0.4 MHz
0 2.0

V

REF

±V

/2

REF

±30 ±50

ppm/°C

±30MAX1204B

0

2.50 VDD+
50mV

12 20Input Resistance

VDD-

50mV

MAX1204

UNITSMIN TYP MAXSYMBOLPARAMETER

µs
µs1.5t

ns10Aperture Delay
ps<50Aperture Jitter

MHz1.7Internal Clock Frequency

V

µA±0.01 ±1Multiplexer Leakage Current
pF16Input Capacitance

V4.076 4.096 4.116REF Output Voltage

mA30REF Short-Circuit Current

µF
µF0.01Capacitive Bypass at REFADJ

%±1.5REFADJ Adjustment Range

V

µA200 350Input Current

kΩ

µA1.5 10REF Input Current in Shutdown

V

_______________________________________________________________________________________ 3

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

ELECTRICAL CHARACTERISTICS (continued)

VDD= +5V ±5%, VL = 2.7V to 3.6V; VSS= 0V or -5V ±5%; f
cycle (133ksps); 4.7µF capacitor at REF; T

EXTERNAL REFERENCE AT REFADJ

Capacitive Bypass at REF

= T

A

to T

MIN

MAX

Internal compensation mode
External compensation mode

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion

SCLK

; unless otherwise noted.)

CONDITIONS

MAX1204

POWER REQUIREMENTS

Positive Supply Voltage
Negative Supply Voltage

Positive Supply Current

Negative Supply Current

Logic Supply Current (Notes 6, 10)
Positive Supply Rejection

(Note 11)
Negative Supply Rejection

(Note 11)
Logic Supply Rejection

(Note 12)

I

DD

DD

SS

VL

SS

Operating mode mA1.5 2.5
Fast power-down (Note 9)
Full power-down (Note 9) 210
Operating mode and fast power-down
Full power-down 10

VL = VDD= 5V µA10I
VDD= 5V ±5%; external reference, 4.096V;

full-scale input
VSS= -5V ±5%; external reference, 4.096V;

full-scale input

External reference, 4.096V; full-scale input mV±0.06 ±0.5PSR

0

4.7

UNITSMIN TYP MAXSYMBOLPARAMETER

µF

V/V1.68Reference-Buffer Gain

µA±50REFADJ Input Current
µA

V5 ±5%V
V0 or -5 ±5%V

30 70I

50

µA

µA

V2.70 5.25VLLogic Supply Voltage

mV±0.06 ±0.5PSR

mV±0.01 ±0.5PSR

4 _______________________________________________________________________________________

5V, 8-Channel, Serial, 10-Bit ADC

SHDN

with 3V Digital Interface

ELECTRICAL CHARACTERISTICS

(VDD= +5V ±5%, VL = 2.7V to 5.25V; VSS= 0V or -5V ±5%; f
cycle (133ksps); 4.7µF capacitor at REF; T

DIGITAL INPUTS: DIN, SCLK, CS,

DIN, SCLK, CS Input High Voltage
DIN, SCLK, CS Input Low Voltage
DIN, SCLK, CS Input Hysteresis
DIN, SCLK, CS Input Leakage
DIN, SCLK, CS Input Capacitance

SHDN Input High Voltage
SHDN Input Mid-Voltage
SHDN Voltage, Floating
SHDN Input Low Voltage
SHDN Input Current, High
SHDN Input Current, Low

SHDN Maximum Allowed

Leakage, Mid-Input
DIGITAL OUTPUTS: DOUT, SSTRB (VL= 2.7V to 3.6V)

Output Voltage Low
Output Voltage High

Three-State Leakage Current
Three-State Output Capacitance
DIGITAL OUTPUTS: DOUT, SSTRB (VL= 4.75V to 5.25V)

Output Voltage Low
Output Voltage High

Three-State Leakage Current
Three-State Output Capacitance

A

IH

IL

HYST

IN

IN
SH
SM

FLT

SL

SH

SL

V

OL

OH

L

OUT

V

OL

OH

L

OUT

= T

to T

MIN

VIN= 0V or V
(Note 6)

SHDN = open

SHDN = V
SHDN = 0V

SHDN = open

I

SINK

I

SINK

I

SOURCE

CS = VL
CS = VL (Note 6)

I

SINK

I

SINK

I

SOURCE

CS = 5V
CS = 5V (Note 6)

; unless otherwise noted.)

MAX

= 3mA
= 6mA 0.3

= 1mA

= 5mA
= 8mA 0.3

= 1mA V4V

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion

SCLK

CONDITIONS

DD

- 0.5V

DD

DD

0.4

0.4

MAX1204

UNITSMIN TYP MAXSYMBOLPARAMETER

V2.0V
V0.8V

V0.15V
µA±1I
pF15C

VV

V1.5 VDD- 1.5V

V2.75V

V0.5V
µA4.0I
µA-4.0I

nA-100 100

V

VVL - 0.5V
µA±10I
pF15C

V

µA±10I
pF15C

_______________________________________________________________________________________ 5

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

TIMING CHARACTERISTICS

(VDD= +5V ±5%, VL = 2.7V to 3.6V, VSS= 0V or -5V ±5%, TA= T

Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid

MAX1204

CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold

SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB

CS Fall to SSTRB Output Enable
(Note 6)

CS Rise to SSTRB Output
Disable (Note 6)

SSTRB Rise to SCLK Rise
(Note 6)

ACQ

DS
DH

DO

DV

TR

CSS

CSH

CH
CL

SSTRB

t

SDV

STR

SCK

C

C

LOAD

LOAD

C

LOAD

C

LOAD

C

LOAD

External clock mode only, C

External clock mode only, C

Internal clock mode only ns0t

= 100pF

= 100pF
= 100pF ns
= 100pF ns240t

= 100pF ns240t

to T

MIN

MAX

CONDITIONS

, unless otherwise noted.)

LOAD

LOAD

UNITSMIN TYP MAXSYMBOLPARAMETER

µs1.5t
ns100t
ns0t
ns20 240t

240t

ns100t
ns0t
ns200t
ns200t

= 100pF ns240

= 100pF ns240t

Note 1: Tested at VDD= 5.0V; VSS= 0V; unipolar input mode.
Note 2: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is

calibrated.

Note 3: Internal reference, offset nulled.
Note 4: On-channel grounded; sine-wave applied to all off-channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Common-mode range for analog inputs is from V
Note 8: External load should not change during the conversion for specified accuracy.
Note 9: Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND (Figure 12c);

REFADJ = GND.

Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are

active (CS low), the logic supply current depends on f

Note 11: Measured at V
Note 12: Measured at VL = 2.7V and VL = 3.6V.

SUPPLY

+5% and V

SUPPLY

-5% only.

SS

to VDD.

, and on the static and capacitive load at DOUT and SSTRB.

SCLK

6 _______________________________________________________________________________________

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

__________________________________________Typical Operating Characteristics

(VDD= 5V ±5%; VL = 2.7V to 3.6V; f

4.7µF capacitor at REF; TA = +25°C; unless otherwise noted.)

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

2.0


1.8


1.6


1.4


SUPPLY CURRENT (mA)

1.2


1.0

4.5     
SUPPLY VOLTAGE (V)

5.34.7 5.1 5.54.9

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);

SCLK

SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE

6

REFADJ = GND

5

4

3

2

1

0

-60

-20 20
TEMPERATURE (°C)

2.0

MAX1204 TOC01

1.8

1.6

1.4

SUPPLY CURRENT (mA)

1.2

1.0

SUPPLY CURRENT

vs. TEMPERATURE

-60

-20 60 140

20

TEMPERATURE (°C)

MAX1204 TOC02

SHUTDOWN SUPPLY CURRENT (µA)

100

60

100

140

______________________________________________________________Pin Description

PIN

1–8 CH0–CH7 Sampling Analog Inputs

9 V

10

11 REF

12 REFADJ Input to the Reference-Buffer Amplifier. Tie REFADJ to V
13 GND Ground; IN- Input for Single-Ended Conversions

14 VL
15 DOUT

16 SSTRB

17 DIN Serial-Data Input. Data is clocked in at SCLK’s rising edge.
18

19 SCLK
20 V

NAME FUNCTION

SS

Negative Supply Voltage. Tie VSSto -5V ±5% or GND.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1204 down to 10µA (max) supply

SHDN

current; otherwise, the MAX1204 is fully operational. Pulling SHDN to V
amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in
external compensation mode.

Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer
provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode,
disable the internal buffer by pulling REFADJ to V

DD.

Supply Voltage for Digital Output Pins. Voltage applied to VL determines the positive output swing of
the Digital Outputs (DOUT, SSTRB).

Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1204 begins the analog-

to-digital conversion and goes high when the conversion is finished. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high (external
clock mode).

CS

Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.

Serial-Clock Input. SCLK clocks data in and out of serial interface. In external clock mode, SCLK also
sets the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)

DD

Positive Supply Voltage, +5V ±5%

puts the reference-buffer

DD

to disable the reference-buffer amplifier.

DD

MAX1204

MAX1204 TOC03

_______________________________________________________________________________________

7

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

+3.3V

DOUT

3k

MAX1204

a. High-Z to V

GND

and VOL to V

OH

DOUT

C

LOAD

OH

b. High-Z to VOL and VOH to V

3k

C

LOAD

GND

Figure 1. Load Circuits for Enable Time

+3.3V

DOUT

DOUT

3k

GND

a. VOH to High-Z b. VOL to High-Z

C

LOAD

3k

C

LOAD

GND

Figure 2. Load Circuits for Disable Time

_______________Detailed Description

The MAX1204 uses a successive-approximation con­version technique and input track/hold (T/H) circuitry to
convert an analog signal to a 10-bit digital output. A
flexible serial interface provides easy interface to 3V
microprocessors (µPs). Figure 3 is the MAX1204 block
diagram.

Pseudo-Differential Input

Figure 4 shows the analog-to-digital converter’s
(ADC’s) analog comparator’s sampling architecture. In
single-ended mode, IN+ is internally switched to
CH0–CH7 and IN- is switched to GND. In differential
mode, IN+ and IN- are selected from pairs of CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels using Tables 3 and 4.

In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential such that only the signal at IN+ is
sampled. The return side (IN-) must remain stable with­in ±0.5LSB (±0.1LSB for best results) with respect to

18

CS

19

SCLK

DIN

SHDN

OL

CH0
CH1
CH2

CH3
CH4

CH5
CH6
CH7

GND

REFADJ

REF

SHIFT

REGISTER

10

1
2
3
4

ANALOG

INPUT

5

MUX

6



7
8

13

12
11

CONTROL

+2.44V

REFERENCE

LOGIC

T/H

20k

INPUT

17

CLOCK

CLOCK

IN

A

≈ 1.68

+4.096V

INT

SAR
ADC

REF

OUTPUT

SHIFT

REGISTER

OUT

MAX1204

15

DOUT

16

SSTRB

20

V

DD

14

VL

9

V

SS



Figure 3. Block Diagram

GND during a conversion. To do this, connect a 0.1µF
capacitor from IN- (of the selected analog input) to
GND.

During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C

HOLD

. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit is entered. The T/H switch opens at the end of
the acquisition interval, retaining charge on C

HOLD

as a

sample of the signal at IN+.
The conversion interval begins with the input multiplex-

er switching C

from the positive input (IN+) to the

HOLD

negative input (IN-). In single-ended mode, IN- is sim­ply GND. This unbalances node ZERO at the compara­tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 10-bit resolution. This
action is equivalent to transferring a charge of 16pF x
[(VIN+) - (VIN-)] from C

to the binary-weighted

HOLD

capacitive DAC, which in turn forms a digital represen­tation of the analog input signal.

8 _______________________________________________________________________________________

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

Track/Hold

The T/H enters tracking mode on the falling clock edge
after the fifth bit of the 8-bit control word is shifted in. The
T/H enters hold mode on the falling clock edge after the
eighth bit of the control word is shifted in. IN- is connect­ed to GND if the converter is set up for single-ended
inputs, and the converter samples the “+” input. IN- con­nects to the “-” input if the converter is set up for differen­tial inputs, and the difference of |N+ - IN- is sampled.
The positive input connects back to IN+ at the end of
the conversion, and C

The time required for the T/H to acquire an input signal is
a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
acquisition time increases and more time must be
allowed between conversions. The acquisition time,
t

, is the maximum time the device takes to acquire

ACQ

the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following:

= 7 x (RS+ RIN) x 16pF

t

ACQ

where R
input signal, and t

= 9kΩ, RS= the source impedance of the

IN

ACQ

source impedances below 4kΩdo not significantly affect
the ADC’s AC performance. Higher source impedances

charges to the input signal.

HOLD

is never less than 1.5µs. Note that

can be used if an input capacitor is connected to the
analog inputs, as shown in Figure 5. Note that the input
capacitor forms an RC filter with the input source imped­ance, limiting the ADC’s signal bandwidth.

CAPACITIVE DAC

REF

C

INPUT

CH0
CH1

CH2
CH3
CH4
CH5
CH6
CH7

GND

SINGLE-ENDED MODE:
DIFFERENTIAL MODE:

HOLD

MUX

–

+

16pF

9k

C

SWITCH

TRACK

IN+ = CHO–CH7, IN- = GND.
IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.

R

T/H

SWITCH

Figure 4. Equivalent Input Circuit

IN

COMPARATOR

ZERO

HOLD

AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES 
FROM THE SELECTED IN+ 
CHANNEL TO THE SELECTED 
IN– CHANNEL.

MAX1204

+3V

0.1µF

0V TO

4.096V

ANALOG

0.01µF

INPUT

C2

0.01µF

FULL-SCALE ANALOG INPUT

C1

4.7µF

Figure 5. Quick-Look Circuit

_______________________________________________________________________________________ 9

VL

CH7

REFADJ

REF

MAX1204

V

GND

V

CS

SCLK

DIN

SSTRB

DOUT

SHDN

DD

SS

+3V

N.C.

+5V

0.1µF

2MHz

OSCILLATOR

OSCILLOSCOPE

CH1 CH2

CH3

SCLK

SSTRB
DOUT

CH4

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

Table 1a. Unipolar Full Scale
and Zero Scale

REFERENCE

Internal
External

MAX1204

at REFADJ
at REF

The ADC’s input tracking circuitry has a 4.5MHz
small-signal bandwidth. Therefore, it is possible to digi­tize high-speed transient events and measure periodic
signals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.

Analog Input Range and Input Protection

Internal protection diodes, which clamp the analog
inputs to VDDand VSS, allow the analog input pins to
swing from (VSS- 0.3V) to (VDD+ 0.3V) without dam­age. However, for accurate conversions near full scale,
the inputs must not exceed VDDby more than 50mV, or
be lower than VSSby 50mV.

If the analog input exceeds 50mV beyond the sup­plies, do not forward bias the protection diodes of
off-channels over 2mA, as excessive current
degrades on-channel conversion accuracy.

The full-scale input voltage depends on the voltage at
REF (Tables 1a and 1b).

Use the circuit of Figure 5 to quickly evaluate the
MAX1204’s analog performance. The MAX1204 requires
that a control byte be written to DIN before each conver­sion. Tying DIN to +3V feeds in control byte $FF hex,

ZERO

SCALE

0V
0V
0V

FULL SCALE

+4.096V

V

REFADJ

V

REF

Input Bandwidth

Quick Look

x 1.68

Table 1b. Bipolar Full Scale, Zero Scale,
and Negative Full Scale

REFERENCE

Internal

External

at
REFADJ

at REF

NEGATIVE

FULL SCALE

-4.096V/2

-1/2 V

REFADJ

1.68

-1/2 V

REF

which triggers single-ended unipolar conversions on
CH7 in external clock mode without powering down
between conversions. In external clock mode, the
SSTRB output pulses high for one clock period before
the most significant bit of the conversion result shifts out
of DOUT. Varying the analog input to CH7 alters the
sequence of bits from DOUT. A total of 15 clock cycles
per conversion is required. All SSTRB and DOUT output
transitions occur on SCLK’s falling edge.

How to Start a Conversion

Clocking a control byte into DIN starts conversion on
the MAX1204. With CS low, each rising edge on SCLK
clocks a bit from DIN into the MAX1204’s internal shift
register. After CS falls, the first logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with
no effect. Table 2 shows the control-byte format.

The MAX1204 is fully compatible with Microwire and SPI
devices. For SPI, select the correct clock polarity and
sampling edge in the SPI control registers: set CPOL =
0 and CPHA = 0. Microwire and SPI both transmit a byte
and receive a byte at the same time. Using the

Operating Circuit

requires only three 8-bit transfers to perform a con­version (one 8-bit transfer to configure the ADC, and two
more 8-bit transfers to clock out the conversion result).

, the simplest software interface

SCALE

x

ZERO

0V
0V
0V

FULL SCALE

+4.096V / 2

+1/2 V

REFADJ

x 1.68

+1/2 V

REF

Typical

10 ______________________________________________________________________________________

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

Table 2. Control-Byte Format

Bit 7

(MSB)

6
5
4

3

2

1

0 (LSB)

START7 (MSB)

SEL2
SEL1
SEL0

UNI/BIP

SGL/DIF

PD1
PD0

Bit 5Bit 6

SEL 1SEL 2START

The first logic 1 bit after CS goes low defines the beginning of the control byte.
These three bits select which of the eight channels is used for the conversion

(Tables 3 and 4).
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an

analog input signal from 0V to V
from -V

1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single­ended mode, input signal voltages are referred to GND. In differential mode, the voltage dif­ference between two channels is measured. (Tables 3 and 4.)

Selects clock and power-down modes.
PD1 PD0 Mode

00 Full power-down (IDD= 2µA, internal reference)
01 Fast power-down (I
10 Internal clock mode
11 External clock mode

REF

/ 2 to +V

Bit 4

SEL 0

REF

/ 2.

Bit 3

UNI/BIP

DescriptionNameBit

can be converted; in bipolar mode, the signal can range

REF

DD

Bit 2

SGL/DIF

= 30µA, internal reference)

Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)

Bit 1

PD1

MAX1204

Bit 0

(LSB)

PD0

SEL1 SEL0

0 0 0
1 0 0 –+
0 0 1 –+
1 0
0 1
1 1
0 1
1 1 1 + –

1 –+
0 + –
0 + –
1 + –

CH0

+

CH1

CH2

CH3

CH4 CH5SEL2 CH6 CH7 GND

Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)

SEL1 SEL0

0 0 0
0 0 1 –+
0 1 0 + –
0 1
1 0
1 0
1 1
1 1 1 – +

1 + –
0 – +
1 +–
0 – +

CH0

+

CH1

–

CH2

CH3

CH4 CH5SEL2 CH6 CH7

–

______________________________________________________________________________________ 11

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

Simple Software Interface

Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.

1) Set up the control byte for external clock mode and
call it TB1. TB1’s format should be: 1XXXXX11 binary,
where the Xs denote the particular channel and
conversion mode selected.

MAX1204

2) Use a general-purpose I/O line on the CPU to pull
CS on the MAX1204 low.

3) Transmit TB1 and simultaneously receive a byte
and call it RB1. Ignore RB1.

4) Transmit a byte of all zeros ($00 hex) and simulta­neously receive byte RB2.

5) Transmit a byte of all zeros ($00 hex) and simulta­neously receive byte RB3.

6) Pull CS on the MAX1204 high.

Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion padded
with one leading zero, two trailing sub-bits (S1 and S0),
and three trailing zeros. Total conversion time is a func­tion of the serial clock frequency and the amount of idle
time between 8-bit transfers. To avoid excessive T/H
droop, make sure that the total conversion time does
not exceed 120µs.

Digital Output

In unipolar input mode, the output is straight binary
(Figure 15); for bipolar inputs, the output is two’s­complement (Figure 16). Data is clocked out at SCLK’s
falling edge in MSB-first format. The digital output logic
level is adjusted with the VL pin. This allows DOUT and
SSTRB to interface with 3V logic without the risk of
overdrive. The MAX1204’s digital inputs are designed
to be compatible with 3V CMOS logic as well as 5V
logic.

Internal and External Clock Modes

The MAX1204 can use either an external serial clock
or the internal clock to perform the successive­approximation conversion. In both clock modes, the
external clock shifts data in and out of the MAX1204.
The T/H acquires the input signal as the last three bits
of the control byte are clocked into DIN. Bits PD1 and
PD0 of the control byte program the clock mode.
Figures 7–10 show the timing characteristics common
to both modes.

External Clock

In external clock mode, the external clock not only shifts
data in and out, but it also drives the A/D conversion
steps. SSTRB pulses high for one clock period after the
last bit of the control byte. Successive-approximation bit
decisions are made and appear at DOUT on each of the
next 12 SCLK falling edges (Figure 6). SSTRB and
DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic low. Figure 8 shows the SSTRB timing in external
clock mode.

The conversion must complete in some minimum time or
droop on the sample-and-hold can degrade conversion
results. Use internal clock mode if the clock period
exceeds 10µs or if serial-clock interruptions could cause
the conversion interval to exceed 120µs.

Internal Clock

In internal clock mode, the MAX1204 generates its own
conversion clock. This frees the µP from running the
SAR conversion clock, and allows the conversion
results to be read back at the processor’s convenience,
at any clock rate from zero to 2MHz. SSTRB goes low
at the start of the conversion, then goes high when the
conversion is complete. SSTRB is low for a maximum of
10µs, during which time SCLK should remain low for
best noise performance. An internal register stores data
while the conversion is in progress. SCLK clocks the
data out at this register at any time after the conversion
is complete. After SSTRB goes high, the next falling
clock edge produces the MSB of the conversion at
DOUT, followed by the remaining bits in MSB-first for­mat (Figure 9). CS does not need to be held low once a
conversion is started. Pulling CS high prevents data
from being clocked into the MAX1204 and three-states
DOUT, but it does not adversely affect an internal
clock-mode conversion already in progress. When
internal clock mode is selected, SSTRB does not go
high impedance when CS goes high.

Figure 10 shows the SSTRB timing in internal clock
mode. Data can be shifted in and out of the MAX1204 at
clock rates up to 2.0MHz if the acquisition time, t
kept above 1.5µs.

ACQ

, is

12 ______________________________________________________________________________________

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

CS

t

ACQ

SCLK

DIN

SSTRB

DOUT

ADC STATE

Figure 6. 24-Bit External-Clock-Mode Conversion Timing (Microwire/SPI Compatible)

14 8 12 16 20 24

UNI/

RB1

SGL/

BIP

DIF

ACQUISITION

(SCLK = 2MHz)

PD1 PD0




1.5µs 

RB2

B9

B8 B7 B6 B5 B4 B3 B2 B1

MSB

CONVERSION

SEL2 SEL1 SEL0

START

IDLE

B0

LSB

RB3

S1 S0

FILLED WITH 
ZEROS

IDLE

MAX1204

CS

t

CSS

t

DS

t

DH

t

DV

SCLK

DIN

DOUT

t

CSH

Figure 7. Detailed Serial-Interface Timing

CS

SSTRB

t

• • •

SDV

• • •

• • •

t

t

CL

CH

• • •

• • •

t

DO

• • •

• • •

• • •

t

SSTRB

t

SSTRB

t

CSH

t

TR

t

STR

SCLK

• • •

Figure 8. External Clock-Mode SSTRB Detailed Timing

______________________________________________________________________________________ 13

• • •

PD0 CLOCKED IN

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

CS

SCLK

DIN

MAX1204

SSTRB

DOUT

ADC STATE

14 8

2 3 5 6 7 9 10 11 19 21 22 23

SEL2 SEL1 SEL0

START

IDLE

Figure 9. Internal Clock Mode Timing

CS • • •

SSTRB • • •

SCLK • • •

UNI/

SGL/

DIP

DIF

ACQUISITION

(SCLK = 2MHz)

t

CSH

PD1 PD0

1.5µs 



CONVERSION

t

SSTRB

t

CONV

10µs MAX

t

CONV

B9

MSB

B8 B7

12

18

B0 
LSB

IDLE

t

SCK

S1

20

FILLED WITH 

S0

ZEROS

24

t

CSS

PD0 CLOCK IN

NOTE: KEEP SCLK LOW DURING CONVERSION FOR BEST NOISE PERFORMANCE.

Figure 10. Internal Clock Mode SSTRB Detailed Timing

Data Framing

CS’s falling edge does not start a conversion on the
MAX1204. The first logic high clocked into DIN is inter­preted as a start bit and defines the first bit of the control
byte. A conversion starts on SCLK’s falling edge after the
eighth bit of the control byte (the PD0 bit) is clocked into
DIN. The start bit is defined as:

The first high bit clocked into DIN with CS low any­time the converter is idle; (e.g., after VDDis applied).

or

MAX1204 can run is 15 clocks/conversion. Figure 11a
shows the serial-interface timing necessary to perform
a conversion every 15 SCLK cycles in external clock
mode. If CS is low and SCLK is continuous, guarantee
a start bit by first clocking in 16 zeros.

Most microcontrollers (µCs) require that conversions
occur in multiples of eight SCLK clocks; 16 clocks per
conversion is typically the fastest that a µC can drive
the MAX1204. Figure 11b shows the serial-interface
timing necessary to perform a conversion every 16

SCLK cycles in external clock mode.
The first high bit clocked into DIN after bit 3 (B3) of a
conversion in progress appears at DOUT.

If a falling edge on CS forces a start bit before B3
becomes available, the current conversion is termi­nated and a new one started. Thus, the fastest the

14 ______________________________________________________________________________________

CS

SCLK

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

MAX1204

1

8181

1515

DIN

DOUT

SSTRB

Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing

CS

SCLK

DIN

DOUT

Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing

S CONTROL BYTE 0

CONVERSION RESULT 0

S CONTROL BYTE 0

CONVERSION RESULT 0

CONTROL BYTE 1S

B2B3B4B5B6B7B8B9 B1 B0 S1 S0 B2B3B4B5B6B7B8B9 B1 B0 S1 S0

CONVERSION RESULT 1

CONTROL BYTE 1S

B2B3B4B5B6B7B8B9 B5B6B7B8B9B1B0S1 S0

CONTROL BYTE 2S

CONVERSION RESULT 1

• • •

• • •

• • •

• • •

__________ Applications Information

Power-On Reset

When power is first applied and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1204 in internal clock mode, ready to convert with
SSTRB = high. After the power supplies are stabilized,
the internal reset time is 100µs. No conversions should
be performed during this phase. SSTRB is high on
power-up, and if CS is low, the first logical 1 on DIN is
interpreted as a start bit. Until a conversion takes
place, DOUT shifts out zeros.

Reference-Buffer Compensation

In addition to its shutdown function, SHDN also selects
internal or external compensation. The compensation
affects both power-up time and maximum conversion
speed. Compensated or not, the minimum clock rate is
100kHz due to droop on the sample-and-hold.

______________________________________________________________________________________ 15

Float SHDN to select external compensation. The

Operating Circuit

uses a 4.7µF capacitor at REF. A value

Typical

of 4.7µF or greater ensures stability and allows converter
operation at the 2MHz full clock speed. External com­pensation increases power-up time (see the section

Choosing Power-Down Mode,

and Table 5).

Internal compensation requires no external capacitor at
REF, and is selected by pulling SHDN high. Internal com­pensation allows for the shortest power-up times, but is
only available using an external clock up to 400kHz.

Power-Down

Choosing Power-Down Mode

You can save power by placing the converter in a
low-current shutdown state between conversions.
Select full power-down or fast power-down mode via
bits 1 and 0 of the DIN control byte with SHDN high or
floating (Tables 2 and 6). Pull SHDN low at any time to

5V, 8-Channel, Serial, 10-Bit ADC

SHDN

with 3V Digital Interface

shut down the converter completely. SHDN overrides
bits 1 and 0 of the control byte.

Full power-down mode turns off all chip functions
that draw quiescent current, reducing IDDand ISStypi­cally to 2µA.

Fast power-down mode turns off all circuitry except the
bandgap reference. With fast power-down mode, the
supply current is 30µA. Power-up time can be shortened

MAX1204

to 5µs in internal compensation mode.
The IDDshutdown current can increase if any digital input

(DIN, SCLK, CS) is held high in either power-down mode.
The actual shutdown current depends on the state of the
digital inputs, the voltage applied to the digital inputs
(VIH), the supply voltage (VDD), and the operating temper­ature. Figure 12c shows the maximum IDDincrease for
each digital input held high in power-down mode for differ­ent operating conditions. This current is cumulative, so if
all three digital inputs are held high, the additional shut­down current is three times the value shown in Figure 12c.

In both software power-down modes, the serial interface
remains operational, but the ADC does not convert.
Table 5 shows how the choice of reference-buffer com­pensation and power-down mode affects both power-up
delay and maximum sample rate.

In external compensation mode, power-up time is 20ms
with a 4.7µF compensation capacitor (200ms with a 33µF

capacitor) when the capacitor is initially fully discharged.

From fast power-down, start-up time can be eliminated

by using low-leakage capacitors that do not discharge

more than 1/2LSB while shut down. In power-down, the

capacitor has to supply the current into the reference

(typically 1.5µA) and the transient currents at power-up.

Figures 12a and 12b show the various power-down

sequences in both external and internal clock modes.

Software Power-Down

Software power-down is activated using bits PD1 and

PD0 of the control byte. As shown in Table 6, PD1 and

PD0 also specify clock mode. When software power-

down is asserted, the ADC continues to operate in the

last specified clock mode until the conversion is com-

plete. The ADC then powers down into a low

quiescent-current state. In internal clock mode, the

interface remains active and conversion results can be

clocked out even though the MAX1204 has already

entered a software power-down.

The first logical 1 on DIN is interpreted as a start bit

and powers up the MAX1204. Following the start bit,

the control byte also determines clock and power-down

modes. For example, if the control byte contains PD1 =

1, the chip remains powered up. If PD1 = 0,

power-down resumes after one conversion.

Table 5. Typical Power-Up Delay Times

REFERENCE

BUFFER

REFERENCE-BUFFER

COMPENSATION MODE

InternalEnabled
InternalEnabled

ExternalEnabled

REFERENCE

CAPACITOR

(µF)

4.7

Table 6. Software Shutdown and
Clock Mode

PD1

External clock mode11
Internal clock mode01
Fast power-down mode10
Full power-down mode00

16 ______________________________________________________________________________________

DEVICE MODEPD0

POWER-DOWN

MODE

Fast

Full

Fast/Full

Table 7. Hard-Wired Shutdown and
Compensation Mode

STATE

DD

GND

POWER-UP
DELAY (µs)

300

See Figure 14c

DEVICE

MODE

Full
Power-Down

5

REFERENCE-BUFFER

COMPENSATION

Internal compensationEnabledV
External compensationEnabledFloating

N/A

MAXIMUM

SAMPLING RATE

(ksps)

26

26
133
1332FastDisabled
1332FullDisabled

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

MAX1204

CLOCK

MODE

SHDN

DOUT

MODE

DIN

INTERNAL

XXXX

SX

EXTERNAL

SETS EXTERNAL
CLOCK MODE

11 S 01

DATA VALID

(10 + 2 DATA BITS)

POWERED UP

XXXXX XXXXX

SETS FAST
POWER-DOWN 
MODE

(10 + 2 DATA BITS)

Figure 12a. Timing Diagram for Power-Down Modes (External Clock)

CLOCK

MODE

DIN

DOUT

SX

SETS INTERNAL
CLOCK MODE

XXXX

10 S 00

DATA VALID

INTERNAL CLOCK MODE

XXXXX 

DATA VALID

SETS EXTERNAL

CLOCK MODE

S11

FAST

POWER-DOWN

SETS FULL
POWER-DOWN

POWERED UP

DATA VALID



EXTERNAL

DATA 

INVALID

FULL

POWER-

DOWN

POWERED
UP

S

SSTRB

MODE

CONVERSION

POWERED UP

Figure 12b. Timing Diagram for Power-Down Modes (Internal Clock)

Hardware Power-Down

The SHDN pin places the converter into full
power-down mode. Unlike the software power-down
modes, conversion is not completed; it stops coinci­dentally with SHDN being brought low. There is no
power-up delay if an external reference, which is not
shut down, is used. SHDN also selects internal or
external reference compensation (Table 7).

Power-Down Sequencing

The MAX1204’s automatic power-down modes can
save considerable power when operating at less than
maximum sample rates. The following sections discuss
the various power-down sequences.

______________________________________________________________________________________ 17

CONVERSION

FULL

POWER-DOWN

POWERED
UP

Lowest Power at up to

500 Conversions per Channel per Second

Figure 14a depicts MAX1204’s power consumption for one
or eight channel conversions using full power-down mode
and internal reference compensation. A 0.01µF bypass
capacitor at REFADJ forms an RC filter with the internal
20kΩ reference resistor, with a 0.2ms time constant. To
achieve full 10-bit accuracy, 10 time constants (or 2ms in
this example) are required for the reference buffer to settle.
When exiting FULLPD, waiting this 2ms in FASTPD mode
(instead of just exiting FULLPD mode and returning to nor­mal operating mode) reduces power consumption by a
factor of 10 or more (Figure 13).

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

Lowest Power at Higher Throughputs

Figure 14b shows power consumption with external­reference compensation in fast power-down, with one and
eight channels converted. The external 4.7µF compensa­tion requires a 50µs wait after power-up. This circuit com­bines fast multichannel conversion with the lowest power
consumption possible. Full power-down mode can
increase power savings in applications where the
MAX1204 is inactive for long periods of time, but where

MAX1204

intermittent bursts of high-speed conversions are required.

External and Internal References

The MAX1204 can be used with an internal or external
reference. An external reference can be connected
directly at the REF terminal or at the REFADJ pin.

40
35
30
25
20
15
10

5

SUPPLY CURRENT PER INPUT (µA)

0

-60

Figure 12c. Additional IDDShutdown Supply Current vs. V
for Each Digital Input at a Logic 1

- VIH) = 2.55V

(V

DD

(V

- VIH) = 2.25V

DD

(VDD - VIH) = 1.95V

20

-20 60 140
TEMPERATURE (°C)

100

An internal buffer is designed to provide 4.096V at REF
for the MAX1204. Its internally trimmed 2.44V reference
is buffered with a 1.68 nominal gain.

Internal Reference

The MAX1204’s full-scale range with internal reference is

4.096V with unipolar inputs and ±2.048V with bipolar
inputs. The internal reference voltage is adjustable to
±1.5% with the circuit of Figure 17.

External Reference

An external reference can be placed at either the input
(REFADJ) or the output (REF) of the MAX1204’s internal
buffer amplifier. The REFADJ input impedance is typical­ly 20kΩ. At REF, the input impedance is a minimum of
12kΩ for DC currents. During conversion, an external
reference at REF must deliver up to 350µA DC load cur­rent and have an output impedance of 10Ω or less. If the
reference has higher output impedance or is noisy,
bypass it close to the REF pin with a 4.7µF capacitor.



Using the buffered REFADJ input makes buffering of
the external reference unnecessary. To use the direct
REF input, disable the internal buffer by tying REFADJ
to VDD. In power-down, the input bias current to
REFADJ can be as much as 25µA with REFADJ tied to
VDD. Pull REFADJ to GND to minimize the input bias
current in power-down.

Transfer Function and Gain Adjust

Figure 15 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 16 shows the bipolar
I/O transfer function. Code transitions occur halfway
between successive integer LSB values. Output coding
is binary with 1 LSB = 4mV (4.096V/1024) for

IH

unipolar operation and 1 LSB = 4mV [(4.096V/2 -

-4.096V/2)/1024] for bipolar operation.

COMPLETE CONVERSION SEQUENCE

DIN

100

FULLPD FASTPD NOPD FULLPD FASTPD

REFADJ

REF

Figure 13. MAX1204 FULLPD/FASTPD Power-Up Sequence

18 ______________________________________________________________________________________

2.5V

0V

4V

0V

(ZEROS)

2ms WAIT

101 1 11100 101

τ = RC = 20kΩ x C

REFADJ

CH1 CH7

t

≈ 15µs

BUFFEN

(ZEROS)

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface



FULL POWER-DOWN

1000

2ms FASTPD WAIT
400kHz EXTERNAL CLOCK
INTERNAL COMPENSATION

100

10

AVERAGE SUPPLY CURRENT (µA)

1

0 100 300 500

50 150 250 350 450

CONVERSIONS PER CHANNEL PER SECOND

Figure 14a. MAX1204 Supply Current vs. Sample Rate/Second,
FULLPD, 400kHz Clock

10,000

8 CHANNELS

1000

100

AVERAGE SUPPLY CURRENT (µA)

10

0

2k

CONVERSIONS PER CHANNEL PER SECOND

200 400



FAST POWER-DOWN

2MHz EXTERNAL CLOCK
EXTERNAL COMPENSATION
50µs WAIT

4k 6k 8k 10k 12k 14k 16k 18k

8 CHANNELS

1 CHANNEL

1 CHANNEL

MAX186-14A

MAX1204

3.0

2.5

2.0

1.5

1.0

POWER-UP DELAY (ms)

0.5

0

0.0001 0.001 0.01 0.1 1 10
TIME IN SHUTDOWN (sec)

Figure 14c. Typical Power-Up Delay vs. Time in Shutdown

(especially clock) lines parallel to one another, or digital
lines underneath the ADC package.

Figure 18 shows the recommended system-ground con­nections. Establish a single-point analog ground (star
ground point) at GND. Connect all other analog grounds
to this ground. No other digital system ground should be
connected to this single-point analog ground. The
ground return to the power supply should be low imped­ance and as short as possible for noise-free operation.

High-frequency noise in the VDDpower supply may affect
the high-speed comparator in the ADC. Bypass these
supplies to the single-point analog ground with 0.1µF and

4.7µF bypass capacitors close to the MAX1204. Minimize
capacitor lead lengths for best supply-noise rejection. If
the +5V power supply is very noisy, a 10Ω resistor can
be connected as a lowpass filter, as shown in Figure 18.

Figure 14b. MAX1204 Supply Current vs. Sample Rate/Second,
FASTPD, 2MHz Clock

Figure 17, the Reference-Adjust Circuit, shows how to
adjust ADC gain in applications that use the internal
reference. The circuit provides ±1.5% (±16LSBs) of
gain-adjustment range.

Layout, Grounding, Bypassing

For best performance, use printed circuit boards.
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital

______________________________________________________________________________________ 19

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

OUTPUT CODE

FULL-SCALE

11 . . . 111
11 . . . 110

11 . . . 101

TRANSITION

MAX1204

FS = +4.096V

1024

00 . . . 011
00 . . . 010

00 . . . 001
00 . . . 000

Figure 15. Unipolar Transfer Function, 4.096V = Full Scale

0

123

INPUT VOLTAGE (LSBs)

FS - 3/2LSB

1LSB =

FS

+5V

MAX1204

510k

100k

24k

FS



Figure 17. Reference-Adjust Circuit

+5V

R* = 10Ω

0.01µF

SUPPLIES

-5V +3V

REFADJ

12

GND

OUTPUT CODE

011 . . . 111
011 . . . 110

000 . . . 010
000 . . . 001
000 . . . 000

111 . . . 111
111 . . . 110
111 . . . 101

100 . . . 001
100 . . . 000

+4.096V

FS =

2

+4.096V

1LSB =

1024

-FS

0V

INPUT VOLTAGE (LSBs)

DD

*OPTIONAL

Figure 18. Power-Supply Grounding Connection

+FS - 1LSB

GNDV

MAX1204

SS

Figure 16. Bipolar Transfer Function, ±4.096V/2 = Full Scale

20 ______________________________________________________________________________________

DGND+3VVLV

DIGITAL

CIRCUITRY

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

TMS320CL3x to MAX1204 Interface

Figure 19 shows an application circuit to interface the
MAX1204 to the TMS320 in external clock mode. Figure
20 is the timing diagram for this interface circuit.

Use the following steps to initiate a conversion in the
MAX1204 and to read the results.

1) The TMS320 should be configured with CLKX (trans­mit clock) as an active-high output clock and CLKR
(TMS320 receive clock) as an active-high input clock.
The TMS320’s CLKX and CLKR are tied together with
the MAX1204’s SCLK input.

2) The MAX1204’s CS is driven low by the TMS320’s
XF_ I/O port to enable data to be clocked into the
MAX1204’s DIN.

3) Write an 8-bit word (1XXXXX11) to the MAX1204 to
initiate a conversion and place the device into exter­nal clock mode. Refer to Table 2 to select the proper
XXXXX bit values for your specific application.

4) The MAX1204’s SSTRB output is monitored via the
TMS320’s FSR input. A falling edge on the SSTRB
output indicates that the conversion is in progress
and data is ready to be received from the MAX1204.

5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits repre­sent the 10-bit conversion result followed by two
sub-bits and four trailing bits, which should be
ignored.

6) Pull CS high to disable the MAX1204 until the next
conversion is initiated.

XF

CLKX

TMS320LC3x

CLKR

DX

DR

FSR

Figure 19. MAX1204 to TMS320 Serial Interface

CS

SCLK



DIN

DOUT

SSTRB

MAX1204

MAX1204

CS

SCLK

DIN

SSTRB

DOUT

Figure 20. TMS320 Serial-Interface Timing Diagram

START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0

______________________________________________________________________________________ 21

MSB LSB

HIGH
IMPEDANCE

HIGH
IMPEDANCE

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

_Ordering Information (continued)

PART

MAX1204AEPP
MAX1204BEPP

-40°C to +85°C

-40°C to +85°C

-40°C to +85°CMAX1204AEAP

MAX1204

*

Contact factory for availability.

PIN-PACKAGETEMP. RANGE

20 Plastic DIP
20 Plastic DIP
20 SSOP
20 SSOP-40°C to +85°CMAX1204BEAP
20 CERDIP*-55°C to +125°CMAX1204BMJP

___________________Chip Information

TRANSISTOR COUNT: 2503
SUBSTRATE CONNECTED TO V

SS

INL

(LSB)

±1/2
±1
±1/2
±1
±1

__________Typical Operating Circuit

0V to

4.096V

ANALOG

INPUTS

C1

4.7µF

C2 

0.01µF

CH0

CH7

REF

REFADJ

MAX1204

V

VL

GND

V

CS

SCLK

DIN

DOUT

SSTRB

SHDN

+5V

DD

SS

C3

0.1µF

+3V

C4 

0.1µF

V

DD

CPU

I/O
SCK (SK)
MOSI (SO)

MISO (SI)

V

SS

22 ______________________________________________________________________________________

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

________________________________________________________Package Information

DIM

A

A1

B
C

α

HE

C

L

e

SSOP

A

SHRINK

SMALL-OUTLINE

B

A1

PACKAGE

D
E
e
H
L

α

DIM

D
D
D
D
D

INCHES



MIN

0.068

0.002

0.010

0.004

0.205

0.301

0.025

PINS



14
16
20
24
28

MAX

0.078

0.008

0.015

0.008

SEE VARIATIONS



0.209



0.311

0.037

0˚

INCHES

MIN



0.239

0.239

0.278

0.317

0.397

D





8˚

MAX

0.249

0.249

0.289

0.328

0.407

MILLIMETERS

MIN

1.73

0.05

0.25

0.09

5.20

7.65

0.63

MAX

1.99

0.21

0.38

0.20



0.65 BSC0.0256 BSC



0˚

MILLIMETERS

MIN

6.07

6.07

7.07

8.07

10.07



5.38


7.90

0.95

8˚

MAX

6.33

6.33

7.33

8.33

10.33

21-0056A

MAX1204

DIM

D1

E

E1

A2

A

D

A3

A1

α

L

e

B

B1

e

A

e

B

A1
A2
A3

B1

C
D

D1

E1

e
e

C

INCHES MILLIMETERS



MIN

A

0.015

0.125

0.055

B

0.016

0.050

0.008

1.015

0.040

E

0.300

0.240

e



A



B

L

0.115

α

MAX

0.200

–

0.150

0.080

0.022

0.065

0.012

1.045

0.070

0.325

0.280

0.100 BSC



0.300 BSC



0.400

–

0.150

0˚

–




15˚

20-PIN PLASTIC

DUAL-IN-LINE

PACKAGE

MIN

–

0.38

3.18

1.40

0.41

1.27

0.20

25.78

1.02

7.62

6.10

2.54 BSC



7.62 BSC



–

2.92
0˚

MAX

5.08
–

3.81

2.03

0.56

1.65

0.30

26.54

1.78

8.26

7.11




10.16

3.81

15˚

21-333A

______________________________________________________________________________________ 23

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

___________________________________________Package Information (continued)

S1

MAX1204

A

Q

L

DIM

S

B1

C
D

E1

E1

D

α

L1

e

B1

E

C

L1

Q

S1

B

INCHES MILLIMETERS



MIN

A
B

0.014

0.038

0.008

E

0.220

0.290
e
L

0.125

0.150

0.015
S

0.005

α

MAX

0.200

–

0.023

0.065

0.015

1.060

–

0.310

0.320



–

0˚



0.200
–

0.070

0.080
–

15˚

20-PIN CERAMIC

DUAL-IN-LINE

PACKAGE

MIN

–

0.36

0.97

0.20
–

5.59

7.37



3.18

3.81

0.38
–

0.13

0˚

MAX

5.08

0.58

1.65

0.38

26.92

7.87

8.13

2.54 BSC0.100 BSC



5.08
–

1.78

2.03
–

15˚

21-335C

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

24

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