Rainbow Electronics MAX1204 User Manual

19-1179; Rev 0; 1/97

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

_______________General Description

The MAX1204 is a 10-bit data-acquisition system
specifically designed for use in applications with mixed
+5V (analog) and +3V (digital) supply voltages. It oper­ates with a single +5V analog supply or dual ±5V ana­log supplies, and combines an 8-channel multiplexer,
internal track/hold, and serial interface with high con­version speed and low power consumption.

A 4-wire serial interface connects directly to
SPI™/Microwire™ devices without external logic, and a
serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1204
uses either the internal clock or an external serial­interface clock to perform successive-approximation
analog-to-digital conversions. The serial interface oper­ates at up to 2MHz.

The MAX1204 features an internal 4.096V reference and
a reference-buffer amplifier that simplifies gain trim. It
also has a VL pin that supplies power to the digital out­puts. Output logic levels (3V, 3.3V, or 5V) are determined
by the value of the voltage applied to this pin.

A hard-wired SHDN pin and two software-selectable
power-down modes are provided. Accessing the serial
interface automatically powers up the device. A quick
turn-on time allows the MAX1204 to be shut down
between conversions, enabling the user to optimize
supply currents. By customizing power-down between
conversions, supply current can drop below 10µA at
reduced sampling rates.

The MAX1204 is available in 20-pin SSOP and DIP
packages, and is specified for the commercial, extend­ed, and military temperature ranges.

____________________________Features

♦ 8-Channel Single-Ended or 4-Channel

Differential Inputs

♦ Operates from +5V Single or ±5V Dual Supplies
♦ User-Adjustable Output Logic Levels

(2.7V to 5.25V)

♦ Low Power: 1.5mA (operating mode)

2µA (power-down mode)

♦ Internal Track/Hold, 133kHz Sampling Rate
♦ Internal 4.096V Reference
♦ SPI/Microwire/TMS320-Compatible

4-Wire Serial Interface

♦ Software-Configurable Unipolar/Bipolar Inputs
♦ 20-Pin DIP/SSOP
♦ Pin-Compatible 12-Bit Upgrade: MAX1202

______________Ordering Information

PART

MAX1204ACPP
MAX1204BCPP
MAX1204ACAP 0°C to +70°C
MAX1204BCAP 0°C to +70°C 20 SSOP

Ordering Information continued at end of data sheet.

TEMP. RANGE PIN-PACKAGE

0°C to +70°C
0°C to +70°C

20 Plastic DIP
20 Plastic DIP
20 SSOP

INL

(LSB)

±1/2
±1
±1/2
±1

__________________Pin Configuration

MAX1204

________________________Applications

5V/3V Mixed-Supply Systems
Data Acquisition
Process Control
Battery-Powered Instruments
Medical Instruments

Typical Operating Circuit appears on last page.

SPI is a registered trademark of Motorola, Inc.
Microwire is a registered trademark of National Semiconductor Corp.

________________________________________________________________

TOP VIEW

CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7

V

20

1
2
3

MAX1204

4
5
6
7
8
9

SS

10

DIP/SSOP

Maxim Integrated Products

V

DD

SCLK

19

CS

18
17

DIN

16

SSTRB
DOUT

15



VL

14
13

GND

12

REFADJ

11

REFSHDN

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone [phone]

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

ABSOLUTE MAXIMUM RATINGS

VDDto GND..............................................................-0.3V to +6V

VL ...............................................................-0.3V to (V

to GND...............................................................+0.3V to -6V

V

SS

to VSS..............................................................-0.3V to +12V

V

DD

CH0–CH7 to GND............................(V

CH0–CH7 Total Input Current...........................................±20mA

REF to GND................................................-0.3V to (V

REFADJ to GND.........................................-0.3V to (V

Digital Inputs to GND .................................-0.3V to (V

MAX1204

Digital Outputs to GND.................................-0.3V to (VL + 0.3V)

Digital Output Sink Current.................................................25mA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

- 0.3V) to (VDD+ 0.3V)

SS

DD

DD
DD
DD

+ 0.3V)

+ 0.3V)
+ 0.3V)
+ 0.3V)

ELECTRICAL CHARACTERISTICS

(VDD= +5V ±5%, VL = 2.7V to 3.6V; VSS= 0V or -5V ±5%; f
cycle (133ksps); 4.7µF capacitor at REF; T

= T

to T

A

MIN

; unless otherwise noted.)

MAX

Continuous Power Dissipation (T

Plastic DIP (derate 11.11mW/°C above +70°C) ...........889mW

SSOP (derate 8.00mW/°C above +70°C) .....................640mW

CERDIP (derate 11.11mW°C above +70°C).................889mW

Operating Temperature Ranges

MAX1204_C_P.....................................................0°C to +70°C

MAX1204_E_P ..................................................-40°C to +85°C

MAX1204BMJP...............................................-55°C to +125°C

Storage Temperature Range.............................-60°C to +150°C

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion

SCLK

= +70°C)

A

CONDITIONS

DC ACCURACY (Note 1)

INLRelative Accuracy (Note 2)

Offset Error

Gain Error (Note 3)

Channel-to-Channel
Offset Matching

DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 4.096Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)

Total Harmonic Distortion
(up to the 5th harmonic)

MAX1204A
MAX1204B
No missing codes over temperature
MAX1204A
MAX1204B
MAX1204A
MAX1204B
External reference, 4.096V

VIN= 4.096Vp-p, 65kHz (Note 4)

-3dB rolloff MHz4.5Small-Signal Bandwidth

±0.5
±1.0

±1.0
±2.0
±1.0
±2.0

UNITSMIN TYP MAXSYMBOLPARAMETER

Bits10Resolution
LSB
LSB±1.0DNLDifferential Nonlinearity
LSB

LSB

ppm/°C±0.8Gain Temperature Coefficient

LSB±0.1

dB66SINADSignal-to-Noise + Distortion Ratio
dB-70THD
dB70SFDRSpurious-Free Dynamic Range

dB-75Channel-to-Channel Crosstalk

kHz800Full-Power Bandwidth

2 _______________________________________________________________________________________

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

ELECTRICAL CHARACTERISTICS (continued)

(VDD= +5V ±5%, VL = 2.7V to 3.6V; VSS= 0V or -5V ±5%; f
cycle (133ksps); 4.7µF capacitor at REF; T

CONVERSION RATE

Conversion Time (Note 5)
Track/Hold Acquisition Time

External Clock-Frequency Range

ANALOG INPUT

Input Voltage Range, Single­Ended and Differential (Note 7)

INTERNAL REFERENCE

V

Temperature Coefficient

REF

Capacitive Bypass at REF

EXTERNAL REFERENCE AT REF (Buffer disabled, V
Input Voltage Range

REFADJ Buffer Disable Threshold

t

CONV

ACQ

= T

A

to T

MIN

MAX

Internal clock
External clock, 2MHz, 12 clocks/conversion

External compensation mode, 4.7µF
Internal compensation mode (Note 6)
Used for data transfer only

Unipolar, VSS= 0V
Bipolar, VSS= -5V
On/off leakage current, V
(Note 6)

TA= +25°C

MAX1204AC
MAX1204AE ±30 ±60

0mA to 0.5mA output load mV2.5Load Regulation (Note 8)
Internal compensation mode
External compensation mode 4.7

REF

SHDN = 0V

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion

SCLK

; unless otherwise noted.)

CONDITIONS

= 4.096V)

CH_

= ±5V

5.5 10
6

0.1 2.0

0.1 0.4 MHz
0 2.0

V

REF

±V

/2

REF

±30 ±50

ppm/°C

±30MAX1204B

0

2.50 VDD+
50mV

12 20Input Resistance

VDD-

50mV

MAX1204

UNITSMIN TYP MAXSYMBOLPARAMETER

µs
µs1.5t

ns10Aperture Delay
ps<50Aperture Jitter

MHz1.7Internal Clock Frequency

V

µA±0.01 ±1Multiplexer Leakage Current
pF16Input Capacitance

V4.076 4.096 4.116REF Output Voltage

mA30REF Short-Circuit Current

µF
µF0.01Capacitive Bypass at REFADJ

%±1.5REFADJ Adjustment Range

V

µA200 350Input Current

kΩ

µA1.5 10REF Input Current in Shutdown

V

_______________________________________________________________________________________ 3

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

ELECTRICAL CHARACTERISTICS (continued)

VDD= +5V ±5%, VL = 2.7V to 3.6V; VSS= 0V or -5V ±5%; f
cycle (133ksps); 4.7µF capacitor at REF; T

EXTERNAL REFERENCE AT REFADJ

Capacitive Bypass at REF

= T

A

to T

MIN

MAX

Internal compensation mode
External compensation mode

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion

SCLK

; unless otherwise noted.)

CONDITIONS

MAX1204

POWER REQUIREMENTS

Positive Supply Voltage
Negative Supply Voltage

Positive Supply Current

Negative Supply Current

Logic Supply Current (Notes 6, 10)
Positive Supply Rejection

(Note 11)
Negative Supply Rejection

(Note 11)
Logic Supply Rejection

(Note 12)

I

DD

DD

SS

VL

SS

Operating mode mA1.5 2.5
Fast power-down (Note 9)
Full power-down (Note 9) 210
Operating mode and fast power-down
Full power-down 10

VL = VDD= 5V µA10I
VDD= 5V ±5%; external reference, 4.096V;

full-scale input
VSS= -5V ±5%; external reference, 4.096V;

full-scale input

External reference, 4.096V; full-scale input mV±0.06 ±0.5PSR

0

4.7

UNITSMIN TYP MAXSYMBOLPARAMETER

µF

V/V1.68Reference-Buffer Gain

µA±50REFADJ Input Current
µA

V5 ±5%V
V0 or -5 ±5%V

30 70I

50

µA

µA

V2.70 5.25VLLogic Supply Voltage

mV±0.06 ±0.5PSR

mV±0.01 ±0.5PSR

4 _______________________________________________________________________________________

5V, 8-Channel, Serial, 10-Bit ADC

SHDN

with 3V Digital Interface

ELECTRICAL CHARACTERISTICS

(VDD= +5V ±5%, VL = 2.7V to 5.25V; VSS= 0V or -5V ±5%; f
cycle (133ksps); 4.7µF capacitor at REF; T

DIGITAL INPUTS: DIN, SCLK, CS,

DIN, SCLK, CS Input High Voltage
DIN, SCLK, CS Input Low Voltage
DIN, SCLK, CS Input Hysteresis
DIN, SCLK, CS Input Leakage
DIN, SCLK, CS Input Capacitance

SHDN Input High Voltage
SHDN Input Mid-Voltage
SHDN Voltage, Floating
SHDN Input Low Voltage
SHDN Input Current, High
SHDN Input Current, Low

SHDN Maximum Allowed

Leakage, Mid-Input
DIGITAL OUTPUTS: DOUT, SSTRB (VL= 2.7V to 3.6V)

Output Voltage Low
Output Voltage High

Three-State Leakage Current
Three-State Output Capacitance
DIGITAL OUTPUTS: DOUT, SSTRB (VL= 4.75V to 5.25V)

Output Voltage Low
Output Voltage High

Three-State Leakage Current
Three-State Output Capacitance

A

IH

IL

HYST

IN

IN
SH
SM

FLT

SL

SH

SL

V

OL

OH

L

OUT

V

OL

OH

L

OUT

= T

to T

MIN

VIN= 0V or V
(Note 6)

SHDN = open

SHDN = V
SHDN = 0V

SHDN = open

I

SINK

I

SINK

I

SOURCE

CS = VL
CS = VL (Note 6)

I

SINK

I

SINK

I

SOURCE

CS = 5V
CS = 5V (Note 6)

; unless otherwise noted.)

MAX

= 3mA
= 6mA 0.3

= 1mA

= 5mA
= 8mA 0.3

= 1mA V4V

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion

SCLK

CONDITIONS

DD

- 0.5V

DD

DD

0.4

0.4

MAX1204

UNITSMIN TYP MAXSYMBOLPARAMETER

V2.0V
V0.8V

V0.15V
µA±1I
pF15C

VV

V1.5 VDD- 1.5V

V2.75V

V0.5V
µA4.0I
µA-4.0I

nA-100 100

V

VVL - 0.5V
µA±10I
pF15C

V

µA±10I
pF15C

_______________________________________________________________________________________ 5

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

TIMING CHARACTERISTICS

(VDD= +5V ±5%, VL = 2.7V to 3.6V, VSS= 0V or -5V ±5%, TA= T

Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid

MAX1204

CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold

SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB

CS Fall to SSTRB Output Enable
(Note 6)

CS Rise to SSTRB Output
Disable (Note 6)

SSTRB Rise to SCLK Rise
(Note 6)

ACQ

DS
DH

DO

DV

TR

CSS

CSH

CH
CL

SSTRB

t

SDV

STR

SCK

C

C

LOAD

LOAD

C

LOAD

C

LOAD

C

LOAD

External clock mode only, C

External clock mode only, C

Internal clock mode only ns0t

= 100pF

= 100pF
= 100pF ns
= 100pF ns240t

= 100pF ns240t

to T

MIN

MAX

CONDITIONS

, unless otherwise noted.)

LOAD

LOAD

UNITSMIN TYP MAXSYMBOLPARAMETER

µs1.5t
ns100t
ns0t
ns20 240t

240t

ns100t
ns0t
ns200t
ns200t

= 100pF ns240

= 100pF ns240t

Note 1: Tested at VDD= 5.0V; VSS= 0V; unipolar input mode.
Note 2: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is

calibrated.

Note 3: Internal reference, offset nulled.
Note 4: On-channel grounded; sine-wave applied to all off-channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Common-mode range for analog inputs is from V
Note 8: External load should not change during the conversion for specified accuracy.
Note 9: Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND (Figure 12c);

REFADJ = GND.

Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are

active (CS low), the logic supply current depends on f

Note 11: Measured at V
Note 12: Measured at VL = 2.7V and VL = 3.6V.

SUPPLY

+5% and V

SUPPLY

-5% only.

SS

to VDD.

, and on the static and capacitive load at DOUT and SSTRB.

SCLK

6 _______________________________________________________________________________________

5V, 8-Channel, Serial, 10-Bit ADC

with 3V Digital Interface

__________________________________________Typical Operating Characteristics

(VDD= 5V ±5%; VL = 2.7V to 3.6V; f

4.7µF capacitor at REF; TA = +25°C; unless otherwise noted.)

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

2.0


1.8


1.6


1.4


SUPPLY CURRENT (mA)

1.2


1.0

4.5     
SUPPLY VOLTAGE (V)

5.34.7 5.1 5.54.9

= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);

SCLK

SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE

6

REFADJ = GND

5

4

3

2

1

0

-60

-20 20
TEMPERATURE (°C)

2.0

MAX1204 TOC01

1.8

1.6

1.4

SUPPLY CURRENT (mA)

1.2

1.0

SUPPLY CURRENT

vs. TEMPERATURE

-60

-20 60 140

20

TEMPERATURE (°C)

MAX1204 TOC02

SHUTDOWN SUPPLY CURRENT (µA)

100

60

100

140

______________________________________________________________Pin Description

PIN

1–8 CH0–CH7 Sampling Analog Inputs

9 V

10

11 REF

12 REFADJ Input to the Reference-Buffer Amplifier. Tie REFADJ to V
13 GND Ground; IN- Input for Single-Ended Conversions

14 VL
15 DOUT

16 SSTRB

17 DIN Serial-Data Input. Data is clocked in at SCLK’s rising edge.
18

19 SCLK
20 V

NAME FUNCTION

SS

Negative Supply Voltage. Tie VSSto -5V ±5% or GND.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1204 down to 10µA (max) supply

SHDN

current; otherwise, the MAX1204 is fully operational. Pulling SHDN to V
amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in
external compensation mode.

Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer
provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode,
disable the internal buffer by pulling REFADJ to V

DD.

Supply Voltage for Digital Output Pins. Voltage applied to VL determines the positive output swing of
the Digital Outputs (DOUT, SSTRB).

Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1204 begins the analog-

to-digital conversion and goes high when the conversion is finished. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high (external
clock mode).

CS

Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.

Serial-Clock Input. SCLK clocks data in and out of serial interface. In external clock mode, SCLK also
sets the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)

DD

Positive Supply Voltage, +5V ±5%

puts the reference-buffer

DD

to disable the reference-buffer amplifier.

DD

MAX1204

MAX1204 TOC03

_______________________________________________________________________________________

7

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface

+3.3V

DOUT

3k

MAX1204

a. High-Z to V

GND

and VOL to V

OH

DOUT

C

LOAD

OH

b. High-Z to VOL and VOH to V

3k

C

LOAD

GND

Figure 1. Load Circuits for Enable Time

+3.3V

DOUT

DOUT

3k

GND

a. VOH to High-Z b. VOL to High-Z

C

LOAD

3k

C

LOAD

GND

Figure 2. Load Circuits for Disable Time

_______________Detailed Description

The MAX1204 uses a successive-approximation con­version technique and input track/hold (T/H) circuitry to
convert an analog signal to a 10-bit digital output. A
flexible serial interface provides easy interface to 3V
microprocessors (µPs). Figure 3 is the MAX1204 block
diagram.

Pseudo-Differential Input

Figure 4 shows the analog-to-digital converter’s
(ADC’s) analog comparator’s sampling architecture. In
single-ended mode, IN+ is internally switched to
CH0–CH7 and IN- is switched to GND. In differential
mode, IN+ and IN- are selected from pairs of CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels using Tables 3 and 4.

In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential such that only the signal at IN+ is
sampled. The return side (IN-) must remain stable with­in ±0.5LSB (±0.1LSB for best results) with respect to

18

CS

19

SCLK

DIN

SHDN

OL

CH0
CH1
CH2

CH3
CH4

CH5
CH6
CH7

GND

REFADJ

REF

SHIFT

REGISTER

10

1
2
3
4

ANALOG

INPUT

5

MUX

6



7
8

13

12
11

CONTROL

+2.44V

REFERENCE

LOGIC

T/H

20k

INPUT

17

CLOCK

CLOCK

IN

A

≈ 1.68

+4.096V

INT

SAR
ADC

REF

OUTPUT

SHIFT

REGISTER

OUT

MAX1204

15

DOUT

16

SSTRB

20

V

DD

14

VL

9

V

SS



Figure 3. Block Diagram

GND during a conversion. To do this, connect a 0.1µF
capacitor from IN- (of the selected analog input) to
GND.

During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C

HOLD

. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit is entered. The T/H switch opens at the end of
the acquisition interval, retaining charge on C

HOLD

as a

sample of the signal at IN+.
The conversion interval begins with the input multiplex-

er switching C

from the positive input (IN+) to the

HOLD

negative input (IN-). In single-ended mode, IN- is sim­ply GND. This unbalances node ZERO at the compara­tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 10-bit resolution. This
action is equivalent to transferring a charge of 16pF x
[(VIN+) - (VIN-)] from C

to the binary-weighted

HOLD

capacitive DAC, which in turn forms a digital represen­tation of the analog input signal.

8 _______________________________________________________________________________________